Conductive particle partition arrangement CoPoS packaging structure and preparation method

Abstract

This application relates to the field of semiconductor packaging technology, specifically disclosing a CoPoS packaging structure with conductive particles arranged in a partitioned pattern and its fabrication method. The packaging structure includes a chip, a conductive film layer, an interposer layer, and a substrate. The conductive film layer contains a thermosetting resin matrix and conductive particles, divided into two regions with different areal densities, corresponding to the chip's high-speed radio frequency signal area and power ground area, respectively, with a medium-density transition region between the two regions. The fabrication method involves sequentially performing pad activation, partitioned conductive film attachment, chip alignment, gradient thermopressing, controlled cooling and pressure relief, isothermal post-curing, and performance testing. This structure can be used in the manufacture of high-performance AI chips and high-frequency radio frequency modules, simultaneously achieving high frequency and low loss with high current and low impedance, resolving the performance contradiction of traditional uniform density conductive film layers. The fabrication method employs a low-temperature interconnect process, which can reduce the warpage of large-size glass panels and improve packaging process yield and long-term reliability.

Description

Technical Field

[0001] This application relates to the field of semiconductor packaging technology, and more specifically, it relates to a CoPoS packaging structure with conductive particles arranged in a partition and a method for its fabrication. Background Technology

[0002] CoPoS (Chip-on-Panel-on-Substrate) is one of the mainstream technologies in the field of advanced semiconductor heterogeneous integration, widely used in the packaging and manufacturing of high-performance AI chips, high-frequency RF modules, and display driver chips. Conductive films, as a low-temperature interconnect material, are gradually becoming an important alternative to traditional micro-bump reflow soldering due to their characteristics of not requiring high-temperature reflow, simple processing, and suitability for fine-pitch interconnects. They can effectively reduce thermal stress in the packaging process and improve the yield of large-size glass panel packaging. Currently, commercially available conductive films all adopt a uniform density conductive particle distribution structure, which has gradually revealed performance limitations in practical applications, failing to meet the comprehensive performance requirements of next-generation electronic devices for packaging interconnects.

[0003] In a uniform-density conductive film structure, the areal density of conductive particles is fixed. Increasing the particle density to meet the high current carrying capacity requirements of the power and ground areas leads to a significant increase in parasitic capacitance between adjacent pads in the RF and high-speed signal areas, exacerbating dielectric loss and electromagnetic coupling during high-frequency signal transmission and affecting the transmission quality of high-frequency signals. Conversely, reducing the particle density to decrease high-frequency loss results in increased interconnect resistance between the power and ground areas, increased IR voltage drop, and difficulty in providing a stable and sufficient power supply to the chip. This performance constraint creates an irreconcilable technical contradiction, becoming a key bottleneck limiting the further application of conductive films in high-performance CoPoS packaging. Summary of the Invention

[0004] To address the problem that uniform density conductive films in existing technologies cannot simultaneously achieve high frequency and low loss, as well as high current and low impedance, this application provides a CoPoS packaging structure with conductive particles arranged in a partition and a fabrication method.

[0005] In a first aspect, this application provides a CoPoS packaging structure with conductive particles arranged in a partitioned manner, employing the following technical solution:

[0006] A CoPoS packaging structure with conductive particles arranged in a partitioned manner includes a chip, a conductive film, an interposer, and a substrate. The conductive film is disposed between the chip and the interposer, and the chip and the interposer are electrically connected and mechanically fixed through the conductive film. The interposer is disposed between the conductive film and the substrate. The conductive film comprises a thermosetting resin matrix and conductive particles dispersed in the thermosetting resin matrix, and the conductive film includes at least a first region and a second region, wherein the areal density of conductive particles in the first region is lower than the areal density of conductive particles in the second region.

[0007] By employing the above technical solution, a differentiated particle density distribution is constructed within the conductive film layer, breaking the performance limitations of traditional uniform density structures. Utilizing the vertical conductivity and horizontal insulation characteristics of the conductive film, regions with different electrical requirements acquire suitable conductivity properties. Low-density regions reduce parasitic capacitance and electromagnetic coupling between adjacent pads, lowering dielectric loss during high-frequency signal transmission. High-density regions increase parallel conduction paths per unit area, reducing interconnect resistance and improving current carrying capacity. This structurally resolves the industry's technical contradiction of simultaneously achieving high-frequency, low-loss and high-current, low-impedance performance.

[0008] Preferably, the chip has a radio frequency (RF) signal area, a high-speed differential I / O signal area, a power supply area, and a ground return area; the first region of the conductive film layer corresponds to the RF signal area and the high-speed differential I / O signal area, and the second region corresponds to the power supply area and the ground return area; a medium-density transition region is provided between the first region and the second region, the medium-density transition region corresponding to the region on the chip located between the RF signal area, the high-speed differential I / O signal area, the power supply area, and the ground return area; the substrate is selected as a lower redistribution layer or a packaging substrate.

[0009] By adopting the above technical solution, a precise spatial correspondence between the chip's functional areas and the conductive film density areas is established, ensuring that each circuit module achieves optimized interconnect performance. The medium-density transition region achieves a smooth gradient change in particle density, avoiding abrupt changes in particle distribution caused by direct adjacency between high and low density areas, reducing signal reflection and resistance fluctuations in the boundary region, and improving the integrity and stability of overall signal transmission.

[0010] Preferably, the areal density of conductive particles in the first region ranges from 5000 to 8000 particles / mm², the areal density of conductive particles in the medium-density transition region ranges from 8000 to 15000 particles / mm², and the areal density of conductive particles in the second region ranges from 15000 to 20000 particles / mm²; the conductive particles are polymer core-metal shell elastic microspheres with a particle size range of 2μm-6μm; the polymer core material is polystyrene or polymethyl methacrylate, and the metal shell is a nickel-palladium-gold three-layer plating structure.

[0011] By adopting the above technical solution, the quantified density range balances conductivity reliability and high-frequency performance, ensuring that 2 to 5 conductive particles can be stably captured within a single pad to form multiple conductive paths. The polymer core provides good elastic deformation capability, and can generate 60% to 80% deformation during hot pressing to expand the contact area with the pad. The bottom nickel layer acts as a diffusion barrier layer to prevent metal atom migration, the middle palladium layer enhances oxidation resistance, and the top gold layer provides low contact resistance. The uniform particle size distribution effectively avoids bridging short circuits between fine-pitch pads, improving the yield of high-density interconnects.

[0012] Preferably, the interposer is a glass interposer or a silicon interposer, the glass interposer has a thickness of 80μm-120μm, a via diameter of 25μm-35μm, and an aspect ratio of 2.5-3.5; the conductive film has a thickness of 15μm-25μm; the thermosetting resin matrix is ​​a modified epoxy resin, phenolic epoxy, or a flexible acrylic epoxy copolymer, with a glass transition temperature of 120°C-180°C and a modulus of 1GPa-5GPa; and the distance between the chip and the pads on the interposer is 15μm-20μm.

[0013] By adopting the above technical solutions, the glass interposer possesses a low dielectric constant, which can further reduce high-frequency signal transmission loss, and the adapted structural parameters ensure the reliability of via interconnection. The optimized conductive film thickness balances insulation reliability and conductivity, and the thermosetting resin system has suitable glass transition temperature and modulus, providing sufficient mechanical support strength and interfacial bonding force, as well as a certain stress buffering capacity, which can absorb the thermal expansion differences between heterogeneous materials and improve the thermomechanical stability of the encapsulation structure during temperature cycling.

[0014] Secondly, this application provides a method for fabricating a CoPoS packaging structure with conductive particles arranged in a partitioned manner, using the following technical solution:

[0015] A method for fabricating a CoPoS encapsulation structure with conductive particles arranged in a partitioned manner includes the following steps:

[0016] S1. Surface activation of solder pads: Plasma cleaning or wet activation treatment is performed on the surface of the solder pads of the interposer and the chip to remove oxide layer, organic contaminants and particulate impurities.

[0017] S2, Zoned Conductive Film Application: The pre-made zoned conductive film is pre-applied to the surface of the interlayer to complete the initial positioning and internal air bubble removal;

[0018] S3. Precise chip alignment: Spatially match the chip with the interposer layer so that the density arrangement of the conductive film corresponds spatially to the functional areas of the chip.

[0019] S4. Gradient thermo-press bonding: The chip and the interposer are thermo-pressed to cause the conductive particles to undergo elastic deformation and form a vertical conductive path. The thermosetting resin flows to fill the gap and completes the initial curing.

[0020] S5. Controlled cooling and pressure relief: Cool to the set temperature while maintaining the pressure at the end of hot pressing, and then gradually relieve the pressure at a constant rate;

[0021] S6. Post-curing at constant temperature: The bonded encapsulation structure is heat-treated to fully cross-link the thermosetting resin and eliminate internal residual stress.

[0022] S7. Comprehensive performance testing: The cured packaging structure is inspected for appearance defects and tested for electrical performance to select qualified products.

[0023] By adopting the above technical solution, a complete low-temperature interconnect fabrication process is constructed, with the highest process temperature not exceeding 180℃, replacing the traditional 250℃ high-temperature reflow soldering process. This significantly reduces the accumulation of thermal stress during the process and minimizes the thermal expansion mismatch problem between dissimilar materials. Each process step is sequentially linked, achieving full-process control from surface pretreatment to final performance testing, ensuring batch consistency and long-term reliability of the packaging structure, while also meeting the mass production requirements of 310mm×310mm large-size panel-level packaging.

[0024] Preferably, in step S1, when the surface activation of the solder pad is carried out using an argon-oxygen mixed plasma cleaning process, the process parameters are: plasma power 200W-500W, processing time 30s-120s, and reaction chamber gas pressure 100mTorr-300mTorr; when wet activation is used, the processing method is as follows: the surface of the solder pad is immersed in an alcohol-water mixed solution containing a silane coupling agent, the processing temperature range is 20℃-40℃, the processing time range is 100s-300s, and then it is dried with a drying gas after removal.

[0025] By adopting the above technical solutions, argon-oxygen mixed plasma cleaning effectively removes organic contaminants, oxide layers, and particulate impurities from the surface of the solder pads through the synergistic effect of the physical bombardment of argon and the chemical reaction of oxygen, thereby improving the surface energy of the solder pads. Wet activation treatment utilizes silane coupling agents to form chemical bonds on the surface of the solder pads, enhancing the interfacial adhesion between the conductive film resin and the solder pad metal. Both activation methods can be flexibly selected according to different substrate characteristics and process conditions.

[0026] Preferably, in step S2, the process parameters for attaching the partitioned conductive film are: attachment temperature 70°C-90°C, attachment pressure 0.1MPa-0.3MPa, and attachment speed 5mm / s-15mm / s.

[0027] By adopting the above technical solution, the optimized bonding temperature allows the conductive film resin to reach a suitable viscous state. Combined with appropriate bonding pressure and speed, this ensures a tight bond between the film layer and the interposer surface. The bonding process utilizes a vacuum environment with a vacuum level of no less than -90 kPa, effectively eliminating residual air bubbles between the film layer and the substrate. This avoids poor conductivity and interface delamination defects caused by air bubbles, improving the reliability of subsequent thermosetting bonding.

[0028] Preferably, in step S4, the hot pressing adopts a three-stage slow-increase pressure process, with a pressure increase rate of 0.5MPa / s-1MPa / s and a total hot pressing time of 5s-20s; when the interlayer is a silicon interlayer, the peak hot pressing temperature is 180°C-200°C and the hot pressing pressure is 2MPa-4MPa; when the interlayer is a glass interlayer, it is combined with an elastic buffer pad to disperse the pressure, with a heating rate of less than or equal to 3°C / s, a peak hot pressing temperature of 170°C-180°C, and a hot pressing pressure of 2.2MPa-4.8MPa.

[0029] By adopting the above technical solution, the three-stage gradual pressure increase process sequentially completes the three stages of low-pressure pre-pressure venting, medium-pressure particle deformation, and high-pressure resin curing, avoiding glass interlayer cracking and lateral displacement of conductive particles caused by sudden pressure changes. Different temperature and pressure parameters are used for interlayer materials with different thermal expansion characteristics. Elastic buffer pads disperse local high stress points, and the increased conductive film thickness can absorb the thermal deformation difference between silicon and glass, effectively reducing the warpage and microcrack risk of large-size glass panels. When using a glass interlayer, the conductive film thickness selected in the range of 15μm-25μm is 2μm-5μm greater than the thickness used for silicon interlayers under the same conditions. The stress buffering effect of the resin itself absorbs the interface stress caused by the mismatch of thermal expansion coefficients between the chip and the glass.

[0030] Preferably, in step S5, during the controlled cooling and depressurization process, the pressure at the end of hot pressing is maintained until the structural temperature drops below 100°C, and then the pressure is gradually depressurized at a rate of 0.2MPa / s-0.5MPa / s, and finally cooled to below 80°C before discharge.

[0031] By employing the above technical solutions, maintaining pressure cooling prevents solder pad misalignment and interface separation caused by thermal stress rebound, while depressurizing at a constant rate avoids resin layer cracking caused by sudden pressure changes. Slow cooling using natural air cooling allows residual stress within the packaging structure to be released gradually, improving the dimensional stability of the packaging structure and reducing deformation issues in subsequent processes.

[0032] Preferably, in step S6, the heat treatment temperature is 150°C-170°C and the treatment time is 40min-60min.

[0033] By employing the above technical solution, the thermosetting resin undergoes a constant temperature and time post-curing process under a nitrogen protective atmosphere, enabling it to complete a full cross-linking reaction and improving its mechanical strength, temperature resistance, and moisture resistance. Simultaneously, the post-curing process further eliminates residual internal stress from the manufacturing process, improving the long-term reliability of the encapsulation structure in high-temperature and high-humidity environments and extending the product's lifespan.

[0034] In summary, this application has the following beneficial effects:

[0035] 1. This application adopts a differentiated partition density arrangement of conductive film layers, setting conductive particles with different areal densities corresponding to different functional areas of the chip, and setting a medium density transition zone in the high and low density range. This solves the technical contradiction that traditional uniform density conductive film layers cannot simultaneously take into account high frequency and low loss and high current and low impedance, and achieves a balanced optimization of the overall electrical performance of the packaging structure.

[0036] 2. In this application, elastic conductive microspheres with a polymer core and a metal shell three-layer coating are preferably used to control the particle size range of conductive particles, so that the particles can undergo sufficient elastic deformation during hot pressing, expand the contact area with the solder pads, improve the particle capture efficiency of fine-pitch interconnects, and reduce the short-circuit risk of adjacent solder pads.

[0037] 3. The packaging structure of this application, by adapting the structural parameters of the glass interlayer and the silicon interlayer, optimizes the thickness of the conductive film layer and the glass transfer temperature and modulus of the thermosetting resin matrix, thereby enhancing the interfacial bonding strength and improving the mechanical stability and thermal reliability of the packaging structure. (See claim 4.)

[0038] 4. The method of this application adopts a three-stage gradient hot-press bonding process with gradually increasing pressure and sets a differentiated temperature and pressure compensation strategy for the glass interlayer to disperse stress concentration during the hot-pressing process, reduce warping and microcracks in large-size glass panels, and improve the yield of the packaging process.

[0039] 5. The method of this application, through a combination of controlled cooling and pressure relief and constant temperature post-curing process, gradually cools down and fully cross-links the resin while maintaining pressure, eliminating residual thermal stress inside the encapsulation structure, avoiding interface peeling, and improving the long-term reliability of the product. Attached Figure Description

[0040] Figure 1 This is a flowchart of a method for fabricating a CoPoS encapsulation structure with conductive particle partitioning provided in this application;

[0041] Figure 2 This is a cross-sectional schematic diagram of a CoPoS packaging structure with conductive particle partitioning provided in this application;

[0042] Figure 3This is a schematic diagram of the alignment preparation stage in the CoPoS packaging structure with conductive particle partitioning provided in this application, in which the chip and the substrate are interconnected through a conductive film layer.

[0043] Figure 4 This is a schematic diagram of the conductive film attachment and preliminary pressing stage in the CoPoS packaging structure with conductive particle partitioning provided in this application, in which the chip and the substrate are interconnected through a conductive film layer;

[0044] Figure 5 This is a schematic diagram of the thermo-press bonding stage in the CoPoS packaging structure with conductive particle partitioning provided in this application, in which the chip and the substrate are interconnected through a conductive film layer;

[0045] The components are: 1. Chip; 2. Conductive film layer; 3. Intermediate layer; 4. Substrate. Detailed Implementation

[0046] The present application will be further described in detail below with reference to embodiments and comparative examples. Unless otherwise specified, the experimental methods used below are conventional methods. Unless otherwise specified, the materials, reagents, methods and instruments used are all conventional materials, reagents, methods and instruments in the art, which can be obtained by those skilled in the art through commercial channels or prepared according to literature methods.

[0047] Technical Concept: With the rapid development of high-performance chips, high-frequency RF modules, and large-size glass interposers, CoPoS packaging is gradually becoming the mainstream technology for advanced heterogeneous integration. However, existing interconnect technologies still face insurmountable systemic bottlenecks. Traditional tin-silver-copper micro-bump reflow soldering processes require temperatures above 250°C. The significant difference in thermal expansion coefficients between silicon chips and glass interposers leads to severe warping, microcracks, and interlayer delamination in large-size glass panels. Furthermore, solder bridging and short circuits are prone to occur at fine pitches of 15μm-20μm. While existing uniform-density conductive films can achieve low-temperature interconnects, their high density configuration, limited by single particle density, increases parasitic capacitance and dielectric loss in the RF region, while low density configuration increases interconnect resistance and IR voltage drop in the power region. This makes it impossible to simultaneously meet the dual requirements of high-frequency, low-loss and high-current, low-impedance.

[0048] This technical solution addresses the aforementioned technical challenges by constructing a zoned density conductive film structure that precisely corresponds to the functional areas of the chip. Low-density conductive particles are placed in the RF and high-speed signal areas, while high-density conductive particles are placed in the power and ground areas. A medium-density transition zone is introduced in between to achieve a smooth performance transition, thus structurally resolving the aforementioned technical contradictions. A polymer core-nickel-palladium-gold three-layer coating of elastic conductive particles, combined with a modified epoxy resin matrix, enhances the particle capture efficiency and contact stability of fine-pitch interconnects. To address the thermal differences between the glass and silicon interlayers, a differentiated three-stage gradually increasing pressure gradient hot-pressing process is designed, incorporating elastic buffer pads and film thickness compensation to disperse stress. Controlled cooling and pressure relief, followed by isothermal post-curing, eliminate residual internal stress, ultimately achieving low-temperature, low-warpage, and highly reliable large-size panel-level fine-pitch interconnects.

[0049] Preparation Example 1: This preparation example provides a method for preparing a pre-fabricated zoned density conductive film using a metal light-shielding selective deposition method. A roll-to-roll precision coating machine is used. First, a thermosetting resin primer with a thickness of 8-12 μm is coated onto a release PET substrate. The resin system is a mixture of modified epoxy resin and phenolic epoxy resin at a mass ratio of 7:3, with 0.5% latent curing agent and 0.2% coupling agent added. The coating speed is 10-15 m / min. After coating, the substrate is pre-baked at 60-70℃ for 3-5 min to allow the solvent to evaporate. Subsequently, a pre-fabricated metal light-shielding mask is placed over the primer surface. The light-transmitting area on the mask corresponds to the power ground functional area of ​​the chip, and the light-shielding area corresponds to the radio frequency high-speed signal functional area. Electrostatic spraying is used to deposit Ni-Pd-Au three-layer coated polystyrene conductive particles onto the surface of a base coat. The particle size is 3.5-5.0 μm. The spraying voltage is 8-12 kV, the particle feed concentration is 15-20 g / L, and the spraying time is 10-15 s. At this time, the particle deposition in the light-transmitting area is 18,000-23,000 particles / mm², and the particle deposition in the light-blocking area is 7,000-10,000 particles / mm². After removing the mask, a thermosetting resin topcoat with a thickness of 7-13 μm is applied to the surface and pre-baked at 50-60℃ for 2-3 min. Finally, the film is rolled, laminated, and slit to obtain a pre-fabricated zoned density conductive film with a thickness of 15-25 μm. The boundary accuracy between the low-density and high-density areas on the film is controlled within ±50 μm.

[0050] Preparation Example 2: This preparation example provides a method for preparing a pre-fabricated zoned density conductive film using a dual-tank multi-coating method combined with electrostatic assisted arrangement. A dual-coating head roll-to-roll device is used; the first coating head corresponds to the radio frequency high-speed signal functional area of ​​the chip, and the second coating head corresponds to the power ground functional area. First, a first layer of thermosetting resin with a thickness of 5-8 μm is coated on a release PET substrate. After pre-baking, a low-concentration conductive particle slurry (5-8 g / L) is introduced at the first coating head, while a weak electrostatic field of 3-5 kV is applied to uniformly disperse and deposit the particles, forming a low-density area with a particle density controlled at 5000-8000 particles / mm². Subsequently, a high-concentration conductive particle slurry (20-25 g / L) is introduced at the second coating head, while a strong electrostatic field of 8-10 kV is applied to directionally deposit the particles, forming a high-density area with a particle density controlled at 15000-20000 particles / mm². A transition zone is set between the two coating heads. By gradually adjusting the electric field intensity, the particle density smoothly transitions from a low-density area to a high-density area, forming a medium-density transition zone. Finally, a second layer of thermosetting resin is coated, with the total thickness controlled at 15-25μm. After pre-baking, rolling, and slitting, the finished product is obtained. This method can achieve continuous production, with batch-to-batch particle density deviations of less than 5%.

[0051] Example 1: As Figures 2-5 As shown, this embodiment provides a CoPoS packaging structure with conductive particle partitioning, including a chip 1, a conductive film layer 2, an interposer layer 3, and a substrate 4. The conductive film layer 2 is disposed between the chip 1 and the interposer layer 3, and the chip 1 and the interposer layer 3 are electrically connected and mechanically fixed through the conductive film layer 2. The interposer layer 3 is disposed between the conductive film layer 2 and the substrate 4. The conductive film layer 2 includes a thermosetting resin matrix and conductive particles dispersed in the thermosetting resin matrix, and the conductive film layer 2 includes at least a first region and a second region, wherein the areal density of conductive particles in the first region is lower than the areal density of conductive particles in the second region.

[0052] The substrate 4 can be a redistribution layer or a packaging substrate.

[0053] In this embodiment, a CoPoS packaging structure with conductive particle partitioning is provided. By setting a first region and a second region with different conductive particle surface densities in the conductive film layer 2, the conductive particle density can be configured differently according to the electrical requirements of different functional areas of the chip 1. In the first region (such as the RF signal region), low-density conductive particles are used to reduce parasitic parameters and meet the low signal loss requirements of high-frequency / RF applications. At the same time, in the second region (such as the power supply region), high-density conductive particles are used to reduce interconnect impedance and ensure power supply stability. This structure combines the dual advantages of high-density interconnection, low parasitic characteristics, and low power consumption / high reliability, adapting to the application requirements of AI, RF and other scenarios, and improving the overall electrical performance and scenario adaptability of the package.

[0054] Example 2: This example provides a CoPoS packaging structure with conductive particle partitioning, including a chip, a conductive film layer, a glass interposer, and a lower redistribution layer. The conductive film layer is disposed between the chip and the glass interposer, and the chip and the glass interposer are electrically connected and mechanically fixed through the conductive film layer. The glass interposer is disposed between the conductive film layer and the lower redistribution layer. The conductive film layer comprises a thermosetting resin matrix and conductive particles dispersed in the thermosetting resin matrix, and the conductive film layer includes a first region, a medium-density transition region, and a second region. The areal density of conductive particles in the first region is lower than the areal density of conductive particles in the second region.

[0055] The chip has an RF signal area, a high-speed differential I / O signal area, a power supply area, and a ground return area. The first region of the conductive film corresponds to the RF signal area and the high-speed differential I / O signal area, and the second region corresponds to the power supply area and the ground return area. The medium-density transition region corresponds to the area on the chip located between the RF signal area, the high-speed differential I / O signal area, and the power supply area and the ground return area.

[0056] The areal density of conductive particles is 6500 particles / mm² in the first region, 11500 particles / mm² in the medium-density transition region, and 17500 particles / mm² in the second region. The conductive particles are polymer core-metal shell elastic microspheres with a particle size of 4 μm. The polymer core is made of polystyrene, and the metal shell has a nickel-palladium-gold three-layer coating structure.

[0057] The glass interposer has a thickness of 100 μm, a via diameter of 30 μm, and an aspect ratio of 3. The conductive film has a thickness of 20 μm. The thermosetting resin matrix is ​​a modified epoxy resin with a glass transfer temperature of 150°C and a modulus of 3 GPa. The spacing between the chip and the bonding pads on the glass interposer is 17.5 μm.

[0058] like Figure 1 As shown, the fabrication method of the above-mentioned CoPoS packaging structure with conductive particle partitioning includes the following steps:

[0059] S1. Surface activation of solder pads: Argon-oxygen mixed plasma cleaning is performed on the surface of the solder pads of the glass interposer and the chip to remove oxide layer, organic contaminants and particulate impurities.

[0060] The plasma power is 350W, the processing time is 75s, the reaction chamber pressure is 200mTorr, and the volume ratio of argon to oxygen is 9:1. This gas ratio can effectively remove organic contaminants and thin oxide layers from the surface of the solder pads, while avoiding excessive etching of the solder pad metal.

[0061] S2, Zoned Conductive Film Application: The pre-made zoned conductive film is pre-applied to the surface of the glass interlayer to complete the initial positioning and internal air bubble removal.

[0062] The bonding temperature was 80°C, the bonding pressure was 0.2 MPa, and the bonding speed was 10 mm / s. The pre-formed zoned density conductive film was prepared using the metal-shielded selective deposition method described in Preparation Example 1, and the boundary accuracy between the low-density and high-density regions on the film was controlled within ±50 μm. During vacuum bonding, the vacuum level was controlled below -90 kPa to ensure that there were no residual air bubbles between the film layer and the interlayer.

[0063] S2-1, In-situ partitioned control: Density partitioning enhancement treatment is applied to the already attached conductive film.

[0064] In this embodiment, the in-situ partitioning control step is selectively performed, applying a spatially non-uniform electrostatic field with an electric field strength of 1.75 kV / cm to the attached conductive film, driving conductive particles to migrate and gather towards the power supply area and the ground return area, thereby further enhancing the boundary clarity of the density partitioning.

[0065] S3. Precise chip alignment: Spatially match the chip with the glass interposer to make the partition density arrangement of the conductive film correspond spatially with the functional areas of the chip.

[0066] The alignment accuracy is controlled within ±2μm to ensure complete overlap between the chip's RF signal area, high-speed differential I / O signal area, and the first region of the conductive film; complete overlap between the chip's power supply area, ground return area, and the second region of the conductive film; and complete overlap between the chip's transition area and the medium-density transition area of ​​the conductive film. An automated optical inspection system is used for real-time alignment calibration, and pre-fixing is performed after alignment to prevent misalignment.

[0067] S4. Gradient thermo-press bonding: The chip and the glass interlayer are thermo-pressed to cause the conductive particles to undergo elastic deformation and form a vertical conductive path. The thermosetting resin flows to fill the gap and completes the initial curing.

[0068] The hot pressing process employs a three-stage, gradual pressure increase process with a pressure increase rate of 0.75 MPa / s and a total hot pressing time of 12.5 s. An elastic buffer pad is used to disperse pressure, increasing the conductive film layer thickness by 3.5 μm. The heating rate is less than or equal to 3°C / s, the peak hot pressing temperature is 175°C, and the hot pressing pressure is 3.5 MPa. The three-stage, gradual pressure increase process sequentially and uniformly prevents sudden pressure changes that could cause microcracks in the glass interlayer.

[0069] S5. Controlled cooling and pressure relief: Cool to the set temperature while maintaining the pressure at the end of hot pressing, and then gradually relieve the pressure at a constant rate.

[0070] The process involves maintaining the pressure at the end of hot pressing until the structural temperature drops below 100°C, then gradually depressurizing at a rate of 0.35 MPa / s, and finally cooling the material to below 80°C before discharge. Natural air cooling is used during the cooling process to avoid thermal stress concentration caused by forced cooling.

[0071] S6. Post-curing at constant temperature: The bonded encapsulation structure is heat-treated to fully cross-link the thermosetting resin and eliminate internal residual stress.

[0072] The heat treatment was carried out at 160°C for 50 minutes, using a nitrogen-protected oven for constant-temperature curing. The nitrogen flow rate was controlled at 5L / min to effectively prevent the resin from oxidizing and discoloring at high temperatures.

[0073] S7. Comprehensive performance testing: The cured packaging structure is inspected for appearance defects and tested for electrical performance to select qualified products.

[0074] The comprehensive performance testing includes visual microscopic inspection, on-resistance testing, RF insertion loss testing, warpage measurement, and short-circuit screening.

[0075] Example 3: This example provides a CoPoS packaging structure with conductive particle partitioning, including a chip, a conductive film layer, a silicon interposer, and a lower packaging substrate. The conductive film layer is disposed between the chip and the silicon interposer, and the chip and the silicon interposer are electrically connected and mechanically fixed through the conductive film layer. The silicon interposer is disposed between the conductive film layer and the lower packaging substrate. The conductive film layer comprises a thermosetting resin matrix and conductive particles dispersed in the thermosetting resin matrix, and the conductive film layer includes a first region, a medium-density transition region, and a second region. The areal density of conductive particles in the first region is lower than the areal density of conductive particles in the second region.

[0076] The chip has an RF signal area, a high-speed differential I / O signal area, a power supply area, and a ground return area. The first region of the conductive film corresponds to the RF signal area and the high-speed differential I / O signal area, and the second region corresponds to the power supply area and the ground return area. The medium-density transition region corresponds to the area on the chip located between the RF signal area, the high-speed differential I / O signal area, and the power supply area and the ground return area.

[0077] The areal density of conductive particles is 5000 particles / mm² in the first region, 8000 particles / mm² in the medium-density transition region, and 15000 particles / mm² in the second region. The conductive particles are polymer core-metal shell elastic microspheres with a particle size of 2 μm. The polymer core is made of polymethyl methacrylate, and the metal shell has a nickel-palladium-gold three-layer coating structure.

[0078] The silicon interposer is 100 μm thick. The conductive film is 15 μm thick. The thermosetting resin matrix is ​​phenolic epoxy, with a glass transition temperature of 120°C and a modulus of 1 GPa. The spacing between the chip and the bonding pads on the silicon interposer is 15 μm.

[0079] like Figure 1 As shown, the fabrication method of the above-mentioned CoPoS packaging structure with conductive particle partitioning includes the following steps:

[0080] S1. Surface activation of solder pads: Wet activation treatment is performed on the surface of solder pads of silicon interposer and chip to remove oxide layer, organic contaminants and particulate impurities.

[0081] The solder pad surface was immersed in an ethanol-water mixed solution containing 0.5 wt% γ-aminopropyltriethoxysilane (ethanol:water volume ratio 9:1), at a treatment temperature of 20°C for 100 seconds, and then dried with high-purity nitrogen. The silane coupling agent can form organic functional groups on the solder pad surface, significantly improving the interfacial adhesion between the conductive film and the solder pad.

[0082] S2, Zoned Conductive Film Application: The pre-formed zoned conductive film is pre-applied to the surface of the silicon interposer to complete the initial positioning and internal air bubble removal.

[0083] The bonding temperature was 70°C, the bonding pressure was 0.1 MPa, and the bonding speed was 5 mm / s. The pre-formed conductive film with partitioned density was prepared using the dual-groove multi-coating method combined with electrostatic assisted arrangement as described in Preparation Example 2, with batch-to-batch particle density deviation less than 5%. During the bonding process, a heated roller was used to apply uniform pressure to ensure tight adhesion between the conductive film layer and the silicon interposer surface.

[0084] S2-1, In-situ partitioned control: Density partitioning enhancement treatment is applied to the already attached conductive film.

[0085] In this embodiment, the in-situ partitioning control step is selectively performed. By selectively removing particles with a local photomask, excess conductive particles in the radio frequency signal area are precisely removed, so that the particle density in this area is stably controlled at 5000 particles / mm², further reducing high-frequency parasitic capacitance.

[0086] S3. Precise chip alignment: Spatially match the chip with the silicon interposer so that the density arrangement of the conductive film corresponds spatially to the functional areas of the chip.

[0087] Specifically, the alignment accuracy is controlled within ±1μm, ensuring complete overlap between the chip's RF signal area, high-speed differential I / O signal area, and the first area of ​​the conductive film; complete overlap between the chip's power supply area, ground return area, and the second area of ​​the conductive film; and complete overlap between the chip's transition area and the medium-density transition area of ​​the conductive film. A high-precision visual recognition system is employed, achieving a marking point accuracy of up to 0.5μm, ensuring accurate alignment of fine-pitch solder pads.

[0088] S4. Gradient thermo-press bonding: The chip and silicon interlayer are thermo-pressed to cause the conductive particles to undergo elastic deformation and form a vertical conductive path. The thermosetting resin flows to fill the gap and completes the initial curing.

[0089] The hot pressing process employs a three-stage gradual pressure ramp-up process with a ramp-up rate of 0.5 MPa / s and a total hot pressing time of 5 seconds. The peak hot pressing temperature is 180°C, and the hot pressing pressure is 2 MPa. The silicon interposer has a high coefficient of thermal expansion matching with the chip, ensuring bonding reliability without the need for additional conductive film thickness.

[0090] S5. Controlled cooling and pressure relief: Cool to the set temperature while maintaining the pressure at the end of hot pressing, and then gradually relieve the pressure at a constant rate.

[0091] The process involves maintaining the pressure at the end of hot pressing until the structural temperature drops below 100°C, then gradually depressurizing at a rate of 0.2 MPa / s, and finally cooling the material to below 80°C before discharge. The depressurization process is carried out in three stages, each lasting 1 second, to avoid interface delamination caused by a sudden drop in pressure.

[0092] S6. Post-curing at constant temperature: The bonded encapsulation structure is heat-treated to fully cross-link the thermosetting resin and eliminate internal residual stress.

[0093] The heat treatment temperature was 150°C, the treatment time was 40 minutes, and a hot air circulating oven was used for constant temperature curing. The hot air circulation speed was controlled at 2 m / s to ensure that the temperature uniformity inside the oven was within ±2°C.

[0094] S7. Comprehensive performance testing: The cured packaging structure is inspected for appearance defects and tested for electrical performance to select qualified products.

[0095] The comprehensive performance testing includes visual microscopic inspection, on-resistance testing, RF insertion loss testing, warpage measurement, and short-circuit screening.

[0096] Example 4: This example provides a CoPoS packaging structure with conductive particle partitioning, including a chip, a conductive film layer, a glass interposer, and a lower redistribution layer. The conductive film layer is disposed between the chip and the glass interposer, and the chip and the glass interposer are electrically connected and mechanically fixed through the conductive film layer. The glass interposer is disposed between the conductive film layer and the lower redistribution layer. The conductive film layer comprises a thermosetting resin matrix and conductive particles dispersed in the thermosetting resin matrix, and the conductive film layer includes a first region, a medium-density transition region, and a second region. The areal density of conductive particles in the first region is lower than the areal density of conductive particles in the second region.

[0097] The chip has an RF signal area, a high-speed differential I / O signal area, a power supply area, and a ground return area. The first region of the conductive film corresponds to the RF signal area and the high-speed differential I / O signal area, and the second region corresponds to the power supply area and the ground return area. The medium-density transition region corresponds to the area on the chip located between the RF signal area, the high-speed differential I / O signal area, and the power supply area and the ground return area.

[0098] The areal density of conductive particles is 8000 particles / mm² in the first region, 15000 particles / mm² in the medium-density transition region, and 20000 particles / mm² in the second region. The conductive particles are polymer core-metal shell elastic microspheres with a particle size of 6 μm. The polymer core is made of polystyrene, and the metal shell has a nickel-palladium-gold three-layer coating structure.

[0099] The glass interposer has a thickness of 120 μm, a via diameter of 35 μm, and an aspect ratio of 3.5. The conductive film has a thickness of 25 μm. The thermosetting resin matrix is ​​a flexible acrylic-epoxy copolymer with a glass transition temperature of 180°C and a modulus of 5 GPa. The spacing between the chip and the solder pads on the glass interposer is 20 μm.

[0100] like Figure 1 As shown, the fabrication method of the above-mentioned CoPoS packaging structure with conductive particle partitioning includes the following steps:

[0101] S1. Surface activation of solder pads: Argon-oxygen mixed plasma cleaning is performed on the surface of the solder pads of the glass interposer and the chip to remove oxide layer, organic contaminants and particulate impurities.

[0102] The plasma power is 500W, the processing time is 120s, the reaction chamber pressure is 300mTorr, and the volume ratio of argon to oxygen is 8:2. The higher oxygen ratio enhances the oxide layer removal capability, making it suitable for glass interposer pads with severely oxidized surfaces.

[0103] S2, Zoned Conductive Film Application: The pre-made zoned conductive film is pre-applied to the surface of the glass interlayer to complete the initial positioning and internal air bubble removal.

[0104] The bonding temperature was 90°C, the bonding pressure was 0.3 MPa, and the bonding speed was 15 mm / s. The pre-formed zoned conductive film was prepared using the metal-shielded selective deposition method described in Preparation Example 1, with the boundary accuracy between low-density and high-density areas on the film controlled within ±50 μm. After bonding, the bonding position of the conductive film was inspected using an optical microscope; products with deviations exceeding ±100 μm underwent rework.

[0105] S2-1, In-situ partitioned control: Density partitioning enhancement treatment is applied to the already attached conductive film.

[0106] In this embodiment, the in-situ partition control step is selectively executed. The conductive particles are supplemented to the power supply area and the ground return area by local inkjet supplementation of particles, so that the particle density in the area reaches a stable 20,000 particles / mm², thereby improving the high current carrying capacity.

[0107] S3. Precise chip alignment: Spatially match the chip with the glass interposer to make the partition density arrangement of the conductive film correspond spatially with the functional areas of the chip.

[0108] Specifically, the alignment accuracy is controlled within ±3μm to ensure complete overlap between the chip's RF signal area, high-speed differential I / O signal area, and the first area of ​​the conductive film; complete overlap between the chip's power supply area, ground return area, and the second area of ​​the conductive film; and complete overlap between the chip's transition area and the medium-density transition area of ​​the conductive film. For the 20μm pad spacing, a submicron-level alignment system is employed to ensure no misalignment between adjacent pads.

[0109] S4. Gradient thermo-press bonding: The chip and the glass interlayer are thermo-pressed to cause the conductive particles to undergo elastic deformation and form a vertical conductive path. The thermosetting resin flows to fill the gap and completes the initial curing.

[0110] The hot pressing process employs a three-stage, gradual pressure increase process with a pressure increase rate of 1 MPa / s and a total hot pressing time of 20 seconds. An elastic buffer pad is used to disperse pressure, increasing the conductive film layer thickness by 5 μm. The heating rate is less than or equal to 3°C / s, the peak hot pressing temperature is 180°C, and the hot pressing pressure is 4.8 MPa. The elastic buffer pad is made of silicone with a Shore hardness of 50, effectively dispersing pressure and preventing excessive localized stress on the glass interlayer.

[0111] S5. Controlled cooling and pressure relief: Cool to the set temperature while maintaining the pressure at the end of hot pressing, and then gradually relieve the pressure at a constant rate.

[0112] The process involves maintaining the pressure at the end of hot pressing until the structural temperature drops below 100°C, then gradually depressurizing at a rate of 0.5 MPa / s, and finally cooling the material to below 80°C before discharge. During cooling, the oven door is kept closed to ensure a uniform temperature drop and reduce warping.

[0113] S6. Post-curing at constant temperature: The bonded encapsulation structure is heat-treated to fully cross-link the thermosetting resin and eliminate internal residual stress.

[0114] The heat treatment temperature was 170°C, the treatment time was 60 minutes, and constant temperature curing was carried out in a nitrogen-protected vacuum oven. The vacuum degree was controlled below -95 kPa to eliminate air bubbles generated during resin curing and improve the compactness of the encapsulation structure.

[0115] S7. Comprehensive performance testing: The cured packaging structure is inspected for appearance defects and tested for electrical performance to select qualified products.

[0116] The comprehensive performance testing includes visual microscopic inspection, on-resistance testing, RF insertion loss testing, warpage measurement, and short-circuit screening.

[0117] Comparative Example 1: The only difference between this comparative example and Example 2 is that the conductive film layer adopts a single uniform high-density conductive particle distribution with a particle surface density of 17,500 particles / mm². The rest of the structure, materials and process parameters are exactly the same.

[0118] Comparative Example 2: The only difference between this comparative example and Example 2 is that the conductive particles are replaced with solid pure nickel metal particles, with a particle size of 4 μm, and the polymer elastic core and nickel-palladium-gold three-layer plating structure are removed. The remaining structures, materials and process parameters are exactly the same.

[0119] Comparative Example 3: The only difference between this comparative example and Example 2 is that the gradient hot-press bonding in step S4 adopts the general standard process parameters of silicon interposer, the hot-press peak temperature is 190°C, the hot-press pressure is 3MPa, the conductive film thickness is not increased, the elastic buffer pad is not used, and the gradual heating rate control is cancelled. The other process parameters and raw materials are exactly the same.

[0120] Comparative Example 4: The only difference between this comparative example and Example 2 is that the medium-density transition region of the conductive film layer is removed, and only the low-density region and the high-density region are retained. The two regions are directly adjacent, and the rest of the structure, materials and process parameters are exactly the same.

[0121] Comparative Example 5: The only difference between this comparative example and Example 2 is that the conductive film layer and related process steps are omitted, and the chip and the glass interposer are interconnected by tin-silver-copper microbump reflow soldering with a bump height of 15μm and a reflow peak temperature of 250℃; step S2, partitioned conductive film attachment, and step S2-1, partitioned in-situ control are omitted, while the rest of the process flow and testing standards are exactly the same.

[0122] I. High-frequency RF insertion loss test: Referring to GB / T34963.12-3-2021 "Semiconductor devices - Part 12-3: Radio frequency and microwave devices - Measurement methods for radio frequency and microwave integrated circuits", this experiment uses a vector network analyzer to test the RF transmission performance of the packaged samples of Examples 2-4 and Comparative Examples 1-5. All test samples use the same 310mm×310mm panel size and the same RF test pattern. Before the test, the vector network analyzer is fully calibrated in a dual-port manner, with the calibration frequency range covering 1GHz to 100GHz. During the test, the ambient temperature is maintained at 25℃±2℃ and the relative humidity at 45%±5%. Five independent RF transmission channels of each sample are tested in two typical application frequency bands, 28GHz and 77GHz. The insertion loss value of each channel is recorded, and the average insertion loss and standard deviation of the 20 samples in each group are calculated.

[0123] II. Interconnect Resistance and Current Carrying Capacity Testing: Referring to the DC resistance test method specified in Appendix A of GB / T4937.12-2018 "Mechanical and Climatic Testing Methods for Semiconductor Devices - Part 12: Temperature Cycling", this experiment used a high-precision four-point probe tester to test the interconnect resistance and current carrying capacity of the packaged samples of Examples 2-4 and Comparative Examples 1-5. All test samples were prepared with the same size and number of power area pads and signal area pads. Before the test, the samples were placed in an environment of 25℃±2℃ for 24 hours to reach thermal equilibrium. First, the initial interconnect resistance of 10 power area pads and 10 signal area pads of each sample was tested. The resistance values ​​were recorded and the average value and standard deviation were calculated. Then, a stepped current loading test was performed on the power area pads. Starting from 10mA, the current was gradually increased in 5mA increments. Each current level was maintained for 10 minutes, and the change in interconnect resistance was monitored in real time. When the interconnect resistance increased by more than 20% of the initial value, it was determined to be a current carrying capacity failure. The current value at the time of failure was recorded. 20 samples were tested in each group, and the average failure current and failure distribution were statistically analyzed.

[0124] III. Warpage and Thermal Cycling Reliability Testing of Large-Size Glass Panels: Referring to SJ / T11638-2016 "Test Method for Warpage of Glass Substrates for Electronic Packaging" and GB / T4937.12-2018 "Mechanical and Climatic Testing Methods for Semiconductor Devices - Part 12: Temperature Cycling," this experiment uses a laser scanning warpage meter to test the warpage and verify the thermal cycling reliability of the 310mm×310mm large-size glass panel packaging samples from Examples 2-4 and Comparative Examples 1-5. First, the initial warpage of the sample after thermoforming bonding is tested, with the scanning range covering the entire glass panel and the center of the panel being sampled. The warpage values ​​at five test points (four corners, etc.) were used to determine the initial warpage of the sample. All samples were then placed in a temperature cycling test chamber for reliability testing. The temperature cycling range was set from -40℃ to 125℃, with each cycle lasting 30 minutes, including 10 minutes each at high and low temperatures. The heating and cooling rate was 10℃ / minute, and the number of cycles was 1000. After the cycle, the warpage of the samples was tested again. At the same time, visual inspection and electrical performance testing were performed. The number of samples with glass cracks, delamination, and electrical performance failures was counted. Twenty samples were tested in each group, and the average warpage and failure rate were calculated.

[0125] Table 1: High-Frequency RF Insertion Loss Test Results

[0126] Example 2 0.82 0.06 1.45 0.11 Example 3 0.76 0.05 1.32 0.09 Example 4 0.89 0.07 1.58 0.12 Comparative Example 1 1.63 0.14 2.97 0.23 Comparative Example 2 1.21 0.10 2.15 0.18 Comparative Example 3 0.95 0.08 1.72 0.14 Comparative Example 4 1.07 0.11 1.94 0.16 Comparative Example 5 1.85 0.17 3.42 0.28

[0127] Table 2: Test Results of Interconnection Resistance and Current Carrying Capacity

[0128] Example 2 12.6 0.8 18.3 1.2 245 18 Example 3 14.2 0.9 20.1 1.3 218 16 Example 4 11.3 0.7 16.7 1.1 272 21 Comparative Example 1 12.8 0.9 11.5 0.8 241 19 Comparative Example 2 28.7 2.3 35.2 2.8 126 14 Comparative Example 3 17.5 1.5 23.8 1.7 189 17 Comparative Example 4 13.9 1.6 19.7 1.9 233 22 Comparative Example 5 21.4 2.1 26.9 2.4 197 23

[0129] Table 3: Test Results of Warpage and Thermal Cycling Reliability of Large-Size Glass Panels

[0130] Example 2 1.23 0.15 1.47 0.18 5.0 Example 3 0.68 0.09 0.79 0.11 0.0 Example 4 1.36 0.17 1.62 0.20 7.5 Comparative Example 1 1.27 0.16 1.51 0.19 6.0 Comparative Example 2 1.25 0.16 1.49 0.19 5.5 Comparative Example 3 2.84 0.32 3.57 0.41 45.0 Comparative Example 4 1.24 0.15 1.48 0.18 5.5 Comparative Example 5 4.12 0.45 5.38 0.57 70.0

[0131] As can be seen from Examples 2-4 and Comparative Example 1, and Tables 1 and 2, when the conductive film adopts a single uniform high-density particle distribution, although the current carrying capacity is close to that of the partitioned design scheme, it will lead to a significant decrease in high-frequency transmission performance and cannot simultaneously meet the dual requirements of high frequency low loss and high current low impedance. However, by arranging the particle density differently according to the functional areas of the chip, the electrical performance of different areas can be optimized in a targeted manner, and the overall electrical performance can be improved in a balanced way.

[0132] As can be seen from Examples 2-4 and Comparative Example 2, and Tables 1 and 2, after replacing the conductive particles with solid pure nickel metal particles, the interconnect resistance increases significantly, the current carrying capacity decreases drastically, and the high-frequency insertion loss also increases. This is because solid metal particles lack elastic deformation ability, the contact area with the solder pad is small after hot pressing, the contact resistance is unstable, and the high-frequency loss characteristics of the metal particles themselves are not as good as those of the elastic microspheres with polymer core metal shell structure.

[0133] As can be seen from Examples 2-4 and Comparative Example 3 and Table 3, when using the general hot pressing process parameters of silicon interlayer for glass interlayer, the warpage of large-size glass panels will increase significantly, and the failure rate after thermal cycling will rise sharply. This is because the thermal expansion coefficients of glass and silicon are quite different. The lack of targeted temperature compensation, pressure buffering and film thickness adjustment measures will lead to thermal stress concentration during hot pressing, which in turn will cause reliability problems such as glass microcracks and interlayer delamination.

[0134] As can be seen from Examples 2-4 and Comparative Example 4, and from Tables 1 and 2, after removing the medium-density transition region of the conductive film layer, the high-frequency insertion loss will increase and the consistency of the interconnect resistance will decrease. This is because the direct adjacency between the low-density region and the high-density region will cause a sudden change in particle density, forming a discontinuity in electrical performance at the boundary region, which in turn affects the stability of signal transmission and the uniformity of overall resistance.

[0135] As can be seen from Examples 2-4 and Comparative Example 5, and Tables 1-3, the high-frequency transmission performance is the worst, the interconnect resistance is high, and the warping problem of large-size glass panels is the most serious. The thermal cycling reliability is the lowest. This is because the high-temperature reflow process generates huge thermal stress, which leads to severe warping and cracking of the glass panel. At the same time, the high-frequency parasitic parameters of the microbump structure are also greater than those of the conductive film interconnect structure with partitioned density design.

[0136] This specific embodiment is merely an explanation of this application and is not intended to limit it. After reading this specification, those skilled in the art can make modifications to this embodiment without contributing any inventive step, but such modifications are protected by patent law as long as they fall within the scope of the claims of this application.

Claims

1. A CoPoS packaging structure with partitioned arrangement of conductive particles, comprising a chip, a conductive film layer, an interposer, and a substrate, characterized in that, The conductive film layer is disposed between the chip and the interposer layer, and the chip and the interposer layer are electrically connected and mechanically fixed through the conductive film layer; the interposer layer is disposed between the conductive film layer and the substrate; the conductive film layer comprises a thermosetting resin matrix and conductive particles dispersed in the thermosetting resin matrix, and the conductive film layer includes at least a first region and a second region, wherein the areal density of conductive particles in the first region is lower than the areal density of conductive particles in the second region.

2. The CoPoS packaging structure with partitioned arrangement of conductive particles according to claim 1, characterized in that: The chip has an RF signal area, a high-speed differential I / O signal area, a power supply area, and a ground return area; the first region of the conductive film layer corresponds to the RF signal area and the high-speed differential I / O signal area, and the second region corresponds to the power supply area and the ground return area; a medium-density transition region is provided between the first region and the second region, and the medium-density transition region corresponds to the area on the chip located between the RF signal area, the high-speed differential I / O signal area, the power supply area, and the ground return area; the substrate is selected as a lower redistribution layer or a packaging substrate.

3. The CoPoS packaging structure with partitioned arrangement of conductive particles according to claim 2, characterized in that: The areal density of conductive particles in the first region ranges from 5000 to 8000 particles / mm², the areal density of conductive particles in the medium-density transition region ranges from 8000 to 15000 particles / mm², and the areal density of conductive particles in the second region ranges from 15000 to 20000 particles / mm². The conductive particles are polymer core-metal shell elastic microspheres with a particle size range of 2μm to 6μm. The polymer core is made of polystyrene or polymethyl methacrylate, and the metal shell is a nickel-palladium-gold three-layer plating structure.

4. The CoPoS packaging structure with conductive particle partitioning according to claim 1, characterized in that: The interposer is a glass interposer or a silicon interposer. The glass interposer has a thickness of 80μm-120μm, a via diameter of 25μm-35μm, and an aspect ratio of 2.5-3.

5. The conductive film has a thickness of 15μm-25μm. The thermosetting resin matrix is ​​a modified epoxy resin, phenolic epoxy, or a flexible acrylic epoxy copolymer, with a glass transition temperature of 120°C-180°C and a modulus of 1GPa-5GPa. The distance between the chip and the pads on the interposer is 15μm-20μm.

5. A method for fabricating a CoPoS package structure with conductive particle partitioning, used in any one of claims 1-4, characterized in that, include: S1. Surface activation of solder pads: Plasma cleaning or wet activation treatment is performed on the surface of the solder pads of the interposer and the chip to remove oxide layer, organic contaminants and particulate impurities. S2, Zoned Conductive Film Application: The pre-made zoned conductive film is pre-applied to the surface of the interlayer to complete the initial positioning and internal air bubble removal; S3. Precise chip alignment: Spatially match the chip with the interposer layer so that the density arrangement of the conductive film corresponds spatially to the functional areas of the chip. S4. Gradient thermo-press bonding: The chip and the interposer are thermo-pressed to cause the conductive particles to undergo elastic deformation and form a vertical conductive path. The thermosetting resin flows to fill the gap and completes the initial curing. S5. Controlled cooling and pressure relief: Cool to the set temperature while maintaining the pressure at the end of hot pressing, and then gradually relieve the pressure at a constant rate; S6. Post-curing at constant temperature: The bonded encapsulation structure is heat-treated to fully cross-link the thermosetting resin and eliminate internal residual stress. S7. Comprehensive performance testing: The cured packaging structure is inspected for appearance defects and tested for electrical performance to select qualified products.

6. The method for fabricating a CoPoS encapsulation structure with conductive particles arranged in a partitioned manner according to claim 5, characterized in that: In step S1, when the surface activation of the solder pad is carried out using an argon-oxygen mixed plasma cleaning process, the process parameters are: plasma power 200W-500W, processing time 30s-120s, and reaction chamber gas pressure 100mTorr-300mTorr. When wet activation is used, the processing method is as follows: the surface of the solder pad is immersed in an alcohol-water mixed solution containing silane coupling agent, the processing temperature range is 20℃-40℃, the processing time range is 100s-300s, and then it is dried with drying gas.

7. The method for fabricating a CoPoS encapsulation structure with conductive particle partitioning according to claim 5, characterized in that: In step S2, the process parameters for attaching the partitioned conductive film are: attachment temperature 70°C-90°C, attachment pressure 0.1MPa-0.3MPa, and attachment speed 5mm / s-15mm / s.

8. The method for fabricating a CoPoS encapsulation structure with conductive particles arranged in a partitioned manner according to claim 5, characterized in that: In step S4, the hot pressing adopts a three-stage slow-increase pressure process, with a pressure increase rate of 0.5MPa / s-1MPa / s and a total hot pressing time of 5s-20s. When the interlayer is a silicon interlayer, the peak hot pressing temperature is 180°C-200°C and the hot pressing pressure is 2MPa-4MPa. When the interlayer is a glass interlayer, it is combined with an elastic buffer pad to disperse the pressure, with a heating rate of less than or equal to 3°C / s, a peak hot pressing temperature of 170°C-180°C, and a hot pressing pressure of 2.2MPa-4.8MPa.

9. The method for fabricating a CoPoS encapsulation structure with conductive particles arranged in a partitioned manner according to claim 5, characterized in that: In step S5, during the controlled cooling and depressurization process, the pressure at the end of hot pressing is maintained until the structural temperature drops below 100°C, and then the pressure is gradually depressurized at a rate of 0.2MPa / s-0.5MPa / s, and finally cooled to below 80°C before discharge.

10. The method for fabricating a CoPoS encapsulation structure with conductive particles arranged in a partitioned manner according to claim 5, characterized in that: In step S6, the heat treatment temperature is 150°C-170°C and the treatment time is 40min-60min.

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