A VCSEL high-frequency wide flip-chip application chip based on a three-layer passivation protective layer design of a silicon heat dissipation substrate and PSPBO coating and a preparation method

Abstract

The application discloses a VCSEL high-frequency wide flip-chip application chip based on a three-layer passivation protective layer design of a silicon heat dissipation substrate and PSPBO coating and a preparation method thereof, which comprises, in sequence from top to bottom, a substrate, a first buffer layer, an N-DBR, an active layer, a P-DBR, a second buffer layer, a photoelectric action mesa sidewall passivation protective layer, a dielectric coating layer and an upper coating layer; the substrate comprises a silicon heat dissipation substrate and an undoped GaAs insulating substrate; the first buffer layer is an N+GaAs high-doped thinning substrate; the active layer is an AlGaAs / GaAa-based multi-quantum well; the second buffer layer is a P+GaAs high-doped electrode contact layer; the photoelectric action mesa sidewall passivation protective layer is a high-precision aluminum oxide AIOx outer wall passivation film; the dielectric coating layer is a photosensitive polybenzoxazole material; and the upper coating layer is a SixNy insulating layer grown at 150 DEG C through PECVD. The application can simplify the process of the VCSEL flip-chip, meet the practical demand of high-speed operation, and improve the overall performance and service life by combining the silicon heat dissipation substrate.

Description

Technical Field

[0001] This invention relates to a VCSEL high-bandwidth flip-chip design based on a silicon heat dissipation substrate and a three-layer passivation protection layer covered by PSPBO, and its fabrication method, belonging to the field of VCSEL flip-chip technology. Background Technology

[0002] Vertical-cavity surface-emitting lasers (VCSELs) have become core light sources in high-speed optical communication, 3D sensing, and other fields due to their advantages such as low threshold current, high modulation rate, and ease of two-dimensional integration. However, with the increasing demand for high-frequency applications, traditional VCSEL structures face multiple technical bottlenecks: The thermal expansion coefficient mismatch between traditional GaAs-based VCSELs and silicon-based circuits makes them prone to stress cracks during flip-chip bonding, affecting device reliability. High-temperature epitaxial growth and packaging processes can easily cause thermal degradation of the dielectric coating, leading to fluctuations in the dielectric constant and exacerbating high-frequency signal transmission losses. Summary of the Invention

[0003] The technical problem to be solved by the present invention is to overcome the defects of the prior art and provide a VCSEL high-bandwidth flip chip and its fabrication method based on a three-layer passivation protection layer design with silicon heat dissipation substrate and PSPBO coating. It can simplify the VCSEL flip chip manufacturing process, meet the practical needs of high-speed operation, and improve the overall performance and lifespan.

[0004] To solve the above-mentioned technical problems, the technical solution of the present invention is: a VCSEL high-bandwidth flip-chip design based on a silicon heat dissipation substrate and a three-layer passivation protection layer encapsulated by PSPBO, comprising: The following layers are stacked in sequence: substrate, first buffer layer, N-DBR, active layer, P-DBR, second buffer layer, photoelectric action platform side, outer wall passivation protection layer, dielectric coating layer and upper coating layer. The substrate includes a silicon heat dissipation substrate and an undoped GaAs insulating substrate. The first buffer layer is an N+GaAs highly doped thinned substrate; The active layer is an AlGaAs / GaAa-based multiple quantum well; The second buffer layer is a P+GaAs highly doped electrode contact layer; The photoelectric action platform side and the outer wall passivation protection layer are high-precision ALD dielectric films; The dielectric coating layer is a photosensitive polybenzoxazole material; The upper coating layer is a SixNy insulating layer grown by PECVD at 150°C.

[0005] Furthermore, in order to reduce signal loss and interference, the dielectric layer has a low dielectric constant of 2.9-3.1@10G.

[0006] Furthermore, to extend the device lifespan, the P-DBR light-emitting end face is provided with a low-reflection coating area, and the N-DBR light-emitting end face is provided with a high-reflection coating area.

[0007] Furthermore, to ensure subsequent stacking, the dielectric coating layer thickness is 0.5-15 μm.

[0008] Furthermore, an oxide layer is provided between the active layer and the P-DBR, and the oxide layer is a 25-40 nm thick Al0.98Ga0.02As high-alumina oxide layer.

[0009] Furthermore, the first buffer layer is thinned to 1-2 μm.

[0010] Furthermore, a VCSEL high-bandwidth flip-chip design based on a silicon heat dissipation substrate and a three-layer passivation protection layer covered by PSPBO also includes an electrode assembly, which includes an N-ohm electrode, a P-ohm electrode, and a P / N external electrode.

[0011] This invention also provides a method for fabricating a VCSEL high-bandwidth flip-chip based on a silicon heat dissipation substrate and a three-layer passivation protection layer coated with PSPBO, comprising the following steps: S1. An N+GaAs first buffer layer (1-2 μm thick), N-DBR, and GaAs-based multi-quantum well active layer are sequentially grown on the substrate by MOCVD. S2. A current-limiting structure with a pore size of 3.5-7.5 μm is formed by vapor deposition of an Al0.98Ga0.02As oxide layer (thickness 25-40 nm) on the active layer and wet oxidation. S3, epitaxial growth of P-DBR and P+GaAs second buffer layer; S4. The photoelectric action mesa structure is formed by ICP dry etching, which can reach the first buffer layer of N+GaAs, forming a deep photoelectric action mesa (MESA) of 7-16um. S5. High temperature and humidity are introduced under low pressure (0.1-0.7 atm) to generate high-quality Al2O3 oxide pores in the original Al0.98Ga0.02As oxide layer (thickness 25-40nm); S6. An aluminum oxide passivation protective layer is formed on the sidewall of the MESA photoelectric action platform and the outer wall of the insulation area of ​​the chip design using ALD atomic layer chemical vapor deposition technology. S7. Spin-coated PSPBO dielectric layer (thickness 0.5-15μm, dielectric constant 2.9-3.1@10GHz), followed by step-curing to form passivation coating; S8. A coating layer on SixNy was deposited using PECVD at low temperature. S9. After photolithography to open the holes, sputter metal stacking is performed to form N / P ohmic electrodes and flip-chip solder ball arrays through the process. S10, the wafer is ground to 90-125um; S11, Undoped GaAs insulating substrate, with a thin gold layer deposited on the back crystal; S12. A high-heat-dissipation insulating adhesive is used to bond the VCSEL back gold layer on the surface of the silicon heat-dissipation substrate. Alternatively, a 2-5µm (Sn0.8Au0.2) tin-gold alloy can be plated on the surface of the silicon heat-dissipation substrate to bond the VCSEL back gold layer with high-temperature metal eutectic bonding. These two methods form a high-intensity and high-heat-dissipation high-bandwidth VCSEL light source. Finally, the VCSEL die and VCSEL array are cut and shaped.

[0012] After adopting the above technical solution, the present invention has the following beneficial effects: 1. In this invention, by using PSPBO as the outer dielectric layer, and adding ALD high-precision deposition of AIOx and SixNy to form a multi-layer encapsulation for protection, the VCSEL flip chip manufacturing process is simplified, manufacturing costs are reduced, and production efficiency is improved. Utilizing the low dielectric constant of PSPBO, the signal loss problem under high-frequency operation is improved, thereby improving the frequency response of the device and meeting the application requirements of high-speed data transmission. In addition, the ALD high-precision deposition of AIOx and SixNy outer coating layers on the outer wall of the optoelectronic platform reduces the leakage current in the photoelectric reaction region. The multi-layer passivation insulating layer can also protect the isolation region from the effects of moisture and oxidation in the air, greatly improving the reliability of the product. PSPBO's excellent mechanical strength and heat resistance enhance the stability of the wafer during the packaging process, reduce stress cracks caused by temperature fluctuations, and improve the reliability and lifespan of the device. PSPBO's low water absorption and low coefficient of thermal expansion ensure the stability of the P / N electrodes under temperature changes, further improving the long-term operational reliability of the device.

[0013] 2. In this invention, the VCSEL flip-chip structure design combines the insulating properties of the silicon heat dissipation substrate with the photosensitive molding performance of PSPBO, realizing a high-speed flip-chip structure, which improves data transmission speed and overall system performance. 3. In this invention, the precise and uniform coating of AIOx thin film on the entire photoelectric platform using ALD atomic layer chemical vapor deposition technology can completely insulate the protective crystal, increase the surface adhesion between VCSEL and PSPBO and SiNx, and improve the reliability of the product. Attached Figure Description

[0014] Figure 1 This is a schematic diagram of the structure of a VCSEL high-bandwidth flip-chip designed based on a silicon heat dissipation substrate and a three-layer passivation protection layer covered by PSPBO according to the present invention. Figure 2 This is a flowchart illustrating a method for fabricating a VCSEL high-bandwidth flip-chip based on a silicon heat dissipation substrate and a three-layer passivation protection layer encapsulated with PSPBO, according to the present invention. 1. P-Pad: P-type electrode pad; 2. N-Pad: N-type electrode pad; 3. SiNx: Silicon nitride passivation layer; 4. ALD: Atomic layer deposition thin film; 5. PSPBO: Photosensitive polybenzoxazole; 6. P-DBR: P-type distributed Bragg mirror; 7. MQW: Multiple quantum well active layer; 8. N-DBR: N-type distributed Bragg mirror; 9. N-GaAs: N-type gallium arsenide; 10. SI GaAs Substrate: Semi-insulating gallium arsenide substrate; 11. Silicon Heat Sink Substrate: Silicon heat sink substrate; 12. Bonding: Bonding layer; 13. Oxide protective layer. Detailed Implementation

[0015] To make the content of this invention easier to understand, the invention will be further described in detail below with reference to specific embodiments and accompanying drawings. Example

[0016] like Figure 1-2 As shown, a VCSEL high-bandwidth flip-chip design based on a silicon heat dissipation substrate and a three-layer passivation protection layer encapsulated by PSPBO includes: The following layers are stacked in sequence: substrate, first buffer layer, N-DBR, active layer, P-DBR, second buffer layer, photoelectric action platform side, outer wall passivation protection layer, dielectric coating layer and upper coating layer. The substrate includes a silicon heat dissipation substrate and an undoped GaAs insulating substrate. The first buffer layer is an N+GaAs highly doped thinned substrate; The active layer is an AlGaAs / GaAa basis multiple quantum well; The second buffer layer is a P+GaAs highly doped electrode contact layer, and the above layers are used to form a wafer; The photoelectric action platform side and the outer wall passivation protective layer are high-precision ALD dielectric films. In this embodiment, AlOx, Al2O3 and SiO2 can be used as materials to form the outer protective film of the first layer. The second dielectric coating layer is a photosensitive polybenzoxazole material; The top coating layer is a SixNy insulating layer grown by PECVD at 150°C to increase heat dissipation and form a third protective layer.

[0017] In this embodiment, the N-DBR (bottom n-type DBR) is composed of 32-37 periods of AlxGal-xAs / AlyGal-yAs (x=0.8-0.92; y=0.08-0.2); The active layer (MQW) is a 3-5 multi-quantum-well GaAs / AlxGal-xAs (x=0.2-0.88) covered by a lattice phase compensation layer; P-DBR (bottom P-type DBR) consists of 19-25 cycles of AlxGal-xAs / AlyGal-yAs (x=0.08-0.15; y=0.85-0.95), with the X and Y values ​​adjusted according to the photoelectric variations of VCSEL 760-880nm products. Specifically, such as Figure 1-2 As shown, the dielectric layer has a low dielectric constant of 2.9-3.1@10G, and the dielectric coating of the polybenzoxazole material has extremely low water absorption.

[0018] Specifically, such as Figure 1-2 As shown, the P-DBR light-emitting end face has a low-reflection coating area, and the N-DBR light-emitting end face has a high-reflection coating area.

[0019] In this embodiment, the reflectivity of the low-reflection coating area is 90-99%, and the reflectivity of the high-reflection coating area is greater than 99%.

[0020] Specifically, such as Figure 1-2 As shown, the dielectric coating thickness is 0.5-15μm.

[0021] Specifically, such as Figure 1-2 As shown, an oxide layer is provided between the active layer and the P-DBR. The oxide layer is a 25-40nm thick Al0.98Ga0.02As high-alumina oxide layer. In this embodiment, it is used in the process of placing the wafer into the low-pressure (0.1-0.7atm) semi-sealed gun body of the ICP etching optoelectronic platform. By introducing high-temperature (400-450℃) humid oxygen gas, the oxide pores are selectively oxidized to produce high-quality Al2O3, thereby limiting the lateral light field and electric field. The oxide pore size is 3.5-7.5μm.

[0022] In this embodiment, the oxide layer is a current-limiting oxide layer of Al2O3 at a pressure below ambient pressure, specifically AlxGal-xAs (x>9.95). The X and Y values ​​are adjusted based on the changes in photoelectric performance of the VCSEL 760-880nm product. Specifically, such as Figure 1-2 As shown, the first buffer layer is thinned to 1-2 μm. After the first buffer layer is thinned to 1-2 μm, MOCVD is started to carry out epitaxial growth at a growth temperature of 650-750℃.

[0023] Specifically, such as Figure 1-2 As shown, a VCSEL high-bandwidth flip-chip design based on a silicon heat dissipation substrate and a three-layer passivation protection layer covered by PSPBO also includes an electrode assembly, which includes an N-ohm electrode, a P-ohm electrode, and a P / N external electrode.

[0024] In this embodiment, the N-ohm electrode is an AuGeNi / Au P-type ohm contact electrode, the P-ohm electrode is a Ti / Au N-type ohm contact electrode, and the P / N external electrode is a TiW / Au electrode. After a second heating and annealing treatment at 225-260℃, a low-resistivity P / N conductive electrode is formed. Example

[0025] This embodiment describes a method for fabricating a VCSEL high-bandwidth flip-chip based on a silicon heat dissipation substrate and a three-layer passivation protection layer coated with PSPBO, as described in Embodiment 1. The method includes the following steps: S1. An N+GaAs first buffer layer (1-2 μm thick), N-DBR, and GaAs-based multi-quantum well active layer are sequentially grown on the substrate by MOCVD. S2. A current-limiting structure with a pore size of 3.5-7.5 μm is formed by vapor deposition of an Al0.98Ga0.02As oxide layer (thickness 25-40 nm) on the active layer and wet oxidation. S3, epitaxial growth of P-DBR and P+GaAs second buffer layer; S4. The photoelectric action mesa structure is formed by ICP dry etching, which can reach the first buffer layer of N+GaAs, forming a deep photoelectric action mesa (MESA) of 7-16um. S5. High temperature and humidity are introduced under low pressure (0.1-0.7 atm) to generate high-quality Al2O3 oxide pores in the original Al0.98Ga0.02As oxide layer (thickness 25-40nm); S6. An aluminum oxide passivation protective layer is formed on the sidewall of the MESA photoelectric action platform and the outer wall of the insulation area of ​​the chip design using ALD atomic layer chemical vapor deposition technology. S7. Spin-coated PSPBO dielectric layer (thickness 0.5-15μm, dielectric constant 2.9-3.1@10GHz), followed by step-curing to form passivation coating; S8. A coating layer on SixNy was deposited using PECVD at low temperature. S9. After photolithography to open the holes, sputter metal stacking is performed to form N / P ohmic electrodes and flip-chip solder ball arrays through the process. S10, the wafer is ground to 90-125um; S11, Undoped GaAs insulating substrate, with a thin gold layer deposited on the back crystal; S12. A high-heat-dissipation insulating adhesive is used to bond the VCSEL back gold layer on the surface of the silicon heat-dissipation substrate. Alternatively, a 2-5µm (Sn0.8Au0.2) tin-gold alloy can be plated on the surface of the silicon heat-dissipation substrate to bond the VCSEL back gold layer with high-temperature metal eutectic bonding. These two methods form a high-intensity and high-heat-dissipation high-bandwidth VCSEL light source. Finally, the VCSEL die and VCSEL array are cut and shaped.

[0026] In this embodiment, the VCSEL has a dual-mesa and coplanar electrode structure. Both mesa are dry-etched using inductively coupled plasma (ICP) with SiCl and CI as chemical agents. P-mesa etch depth: 7-9μm plus subsequent 1.5-2μm N-mesa etch to form a stepped structure, which makes the current evenly distributed to reduce impedance and capacitance.

[0027] In this embodiment, the dielectric coating layer of the photosensitive polybenzoxazole material has excellent photosensitive properties. It can be directly used for exposure and development to form pattern positioning, which can simplify the preparation process and reduce costs. After PBO is cured, the structure has high mechanical strength, heat resistance, insulation properties, low water absorption and low dielectric constant. It coats the non-metallic layer to form a protective layer. like Figure 2 As shown, in this embodiment, ADL coating is performed between steps S6 and S7. Specifically, a PECVD low-temperature (150°C) silicon nitride (SiNx) film is subsequently grown on the upper surface PSPBO layer. This film has high density and stability as well as excellent water vapor and oxygen isolation effect, forming the third passivation protection layer of VCSEL.

[0028] The above specific embodiments further illustrate the technical problems solved by the present invention, the technical solutions, and the beneficial effects. It should be understood that the above are only specific embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A VCSEL high-bandwidth flip-chip design based on a silicon heat dissipation substrate and a three-layer passivation protection layer encapsulated with PSPBO, characterized in that, include: The following layers are stacked in sequence: substrate, first buffer layer, N-DBR, active layer, P-DBR, second buffer layer, photoelectric action platform side, outer wall passivation protection layer, dielectric coating layer and upper coating layer. The substrate includes a silicon heat dissipation substrate and an undoped GaAs insulating substrate. The first buffer layer is an N+GaAs highly doped thinned substrate; The active layer is an AlGaAs / GaAa-based multiple quantum well; The second buffer layer is a P+GaAs highly doped electrode contact layer; The photoelectric action platform side and outer wall protective layer are high-precision aluminum oxide Al10x dielectric films; The dielectric coating layer is a photosensitive polybenzoxazole material; The upper coating layer is a SixNy insulating layer grown by PECVD at 150°C.

2. The VCSEL high-bandwidth flip-chip design based on a silicon heat dissipation substrate and a three-layer passivation protection layer encapsulated by PSPBO as described in claim 1, characterized in that: The dielectric layer has a low dielectric constant of 2.9-3.1@10G.

3. The VCSEL high-bandwidth flip-chip design based on a silicon heat dissipation substrate and a three-layer passivation protection layer encapsulated with PSPBO as described in claim 1, characterized in that: The P-DBR light-emitting end face is provided with a low-reflection coating area, and the N-DBR light-emitting end face is provided with a high-reflection coating area.

4. A VCSEL high-bandwidth flip-chip design based on a silicon heat dissipation substrate and a three-layer passivation protection layer encapsulated with PSPBO, as described in claim 1, is characterized in that: The dielectric coating layer has a thickness of 0.5-15 μm.

5. A VCSEL high-bandwidth flip-chip design based on a silicon heat dissipation substrate and a three-layer passivation protection layer encapsulated with PSPBO, as described in claim 1, is characterized in that: An oxide layer is provided between the active layer and the P-DBR, and the oxide layer is a 25-40 nm thick Al0.98Ga0.02As high-alumina oxide layer.

6. A VCSEL high-bandwidth flip-chip design based on a silicon heat dissipation substrate and a three-layer passivation protection layer encapsulated with PSPBO, as described in claim 1, is characterized in that: The first buffer layer is thinned to 1-2 μm.

7. A VCSEL high-bandwidth flip-chip design based on a silicon heat dissipation substrate and a three-layer passivation protection layer encapsulated with PSPBO, as described in claim 1, is characterized in that: It also includes an electrode assembly, which includes an N-ohm electrode, a P-ohm electrode, and a P / N external electrode.

8. A method for fabricating a VCSEL high-bandwidth flip-chip based on a silicon heat-dissipating substrate and a three-layer passivation protection layer encapsulated by PSPBO, as described in any one of claims 1 to 7, characterized in that, Includes the following steps: S1. An N+GaAs first buffer layer (1-2 μm thick), N-DBR, and GaAs-based multi-quantum well active layer are sequentially grown on the substrate by MOCVD. S2. A current-limiting structure with a pore size of 3.5-7.5 μm is formed by vapor deposition of an Al0.98Ga0.02As oxide layer (thickness 25-40 nm) on the active layer and wet oxidation. S3, epitaxial growth of P-DBR and P+GaAs second buffer layer; S4. The photoelectric action mesa structure is formed by ICP dry etching, which can reach the first buffer layer of N+GaAs, forming a deep photoelectric action mesa (MESA) of 7-16um. S5. High temperature and humidity are introduced under low pressure (0.1-0.7 atm) to generate high-quality Al2O3 oxide pores in the original Al0.98Ga0.02As oxide layer (thickness 25-40nm); S6. An aluminum oxide passivation protective layer is formed on the sidewall of the MESA photoelectric action platform and the outer wall of the insulation area of ​​the chip design using ALD atomic layer chemical vapor deposition technology. S7. Spin-coated PSPBO dielectric layer (thickness 0.5-15μm, dielectric constant 2.9-3.1@10GHz), followed by step-curing to form passivation coating; S8. A coating layer on SixNy was deposited using PECVD at low temperature. S9. After photolithography to open the holes, sputter metal stacking is performed to form N / P ohmic electrodes and flip-chip solder ball arrays through the process. S10, the wafer is ground to 90-125um; S11, Undoped GaAs insulating substrate, with a thin gold layer deposited on the back crystal; S12. A high-heat-dissipation insulating adhesive is used to bond the VCSEL back gold layer on the surface of the silicon heat-dissipation substrate. Alternatively, a 2-5µm (Sn0.8Au0.2) tin-gold alloy can be plated on the surface of the silicon heat-dissipation substrate to bond the VCSEL back gold with high-temperature metal eutectic bonding. These two methods form a high-intensity and high-heat-dissipation high-bandwidth VCSEL light source. Finally, the VCSEL die and VCSEL array are cut and shaped.

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