Array substrate and display device

Abstract

An array substrate includes a plurality of pixel driving circuits. Each pixel driving circuit includes a driving transistor having a gate connected to a first node, a first electrode configured to receive a first power signal, a second electrode connected to a second node; a second transistor having a gate connected to a second gate line, a first electrode connected to a corresponding data line, and a second electrode connected to the first node; a fifth transistor having a gate connected to a fifth gate line, a first electrode connected to the second node, and a second electrode coupled to an anode; a first storage capacitor having a first capacitor electrode connected to the second node and a second capacitor electrode connected to the first node; a second storage capacitor having a first capacitor electrode connected to the second node, and a second capacitor electrode.

Description

Technical Field

[0001] This invention relates to display technology, and more particularly to an array substrate and a display device. Background Technology

[0002] Silicon-based organic light-emitting diodes (OLEDs) are a novel display technology that combines semiconductor manufacturing processes with OLED display technology, using monocrystalline silicon driver circuit wafers as a substrate to fabricate OLED devices. By leveraging the advantages of both semiconductor manufacturing processes and OLED display technology, this method enables the production of microdisplays with smaller screen sizes (typically ranging from 0.2 to 1.8 inches) while maintaining a certain level of resolution. As a result, silicon-based OLEDs offer exceptionally high pixel densities (typically exceeding 3000 PPI). In addition to high pixel density, silicon-based OLEDs also feature characteristics such as high brightness, low power consumption, fast response time, wide color gamut, and excellent thermal stability. Summary of the Invention

[0003] On one hand, this disclosure provides an array substrate including a plurality of pixel driving circuits; wherein each pixel driving circuit in the plurality of pixel driving circuits includes: a driving transistor having a gate connected to a first node, a first electrode configured to receive a first power supply signal, and a second electrode connected to a second node; a second transistor having a gate connected to a second gate line, a first electrode connected to a corresponding data line for receiving pixel data signals, and a second electrode connected to the first node; a fifth transistor having a gate connected to a fifth gate line, a first electrode connected to the second node, and a second electrode coupled to the anode of a light-emitting element; a first storage capacitor having a first capacitor electrode connected to the second node and a second capacitor electrode connected to the first node; and a second storage capacitor having a first capacitor electrode connected to the second node and a second capacitor electrode connected to the first node. The array substrate further includes a first connecting line and a second connecting line; wherein the first connecting line is connected to the first capacitor electrode of the first storage capacitor and to the first electrode of the fifth transistor; the first capacitor electrode of the first storage capacitor is electrically connected to the second electrode of the driving transistor; and the first connecting line is located on a different layer from the first capacitor electrode of the first storage capacitor and on a different layer from the first electrode of the fifth transistor; wherein the second connecting line is connected to the second electrode of the fifth transistor and to the second electrode of the sixth transistor; and the second connecting line is located on a different layer from the second electrode of the fifth transistor and the second electrode of the sixth transistor; wherein the length of the first connecting line is less than the length of the second connecting line.

[0004] Optionally, the array substrate further includes a relay electrode; wherein the first capacitor electrode of the first storage capacitor is connected to the relay electrode; and the relay electrode is connected to the second electrode of the driving transistor and the second electrode of the fourth transistor.

[0005] Optionally, each pixel driving circuit further includes: a fourth transistor having a gate connected to a fourth gate line, a first electrode connected to a reset voltage line, and a second electrode connected to the second node; and a sixth transistor having a gate connected to a sixth gate line, a first electrode connected to an initialization voltage line, and a second electrode connected to the anode of the light-emitting element; wherein the second electrode of the driving transistor and the second electrode of the fourth transistor are directly connected to each other and are part of an integral structure; the first capacitor electrode of the first storage capacitor is electrically connected to the second electrode of the fourth transistor; and the second connection line is connected to the second electrode of the sixth transistor.

[0006] Optionally, the orthographic projection of the second connection line on the substrate does not overlap with the orthographic projection of any of the plurality of gate lines on the substrate.

[0007] Optionally, the gate of the fifth transistor in two adjacent columns of pixel driving circuits is part of the first integral structure; and the gate of the second transistor in the two adjacent columns of pixel driving circuits is part of the second integral structure; wherein, the array substrate further includes a fifth gate line and a second gate line; wherein, the first integral structure is connected to the fifth gate line; and the second integral structure is connected to the second gate line.

[0008] Optionally, the fifth transistors of two adjacent columns of pixel driving circuits have substantially mirror symmetry with respect to each other about a plane that is perpendicular to the main surface of the array substrate and substantially parallel to the second direction; and the second transistors of two adjacent columns of pixel driving circuits have substantially mirror symmetry with respect to each other about the plane that is perpendicular to the main surface of the array substrate and substantially parallel to the second direction.

[0009] Optionally, the array substrate further includes an initialization voltage line; wherein the orthographic projection of the initialization voltage line on the substrate spacers the orthographic projections of the active layers of the second transistors of two adjacent columns of pixel driving circuits on the substrate; and the orthographic projection of the initialization voltage line on the substrate spacers the orthographic projections of the active layers of the fifth transistors of two adjacent columns of pixel driving circuits on the substrate.

[0010] Optionally, the active layer of the fourth transistor and the driving transistor located in the same column of pixel driving circuits and in adjacent rows of pixel driving circuits is part of the overall structure.

[0011] Optionally, the array substrate further includes an N+ pickup active region, which is connected to the first electrode of the sixth transistor in the adjacent two columns of pixel driving circuits.

[0012] Optionally, the array substrate further includes a third connection line; wherein the third connection line is connected to the N+ pickup active region and to the first electrode of the sixth transistor in the two adjacent column pixel driving circuits; and the N+ pickup active region is configured to provide an initialization voltage signal to the first electrode of the sixth transistor in the two adjacent column pixel driving circuits.

[0013] Optionally, the array substrate further includes a P+ pickup active region, which is connected to the first electrode of the driving transistor in the adjacent two rows of pixel driving circuits.

[0014] Optionally, the array substrate further includes a fourth connection line; wherein the fourth connection line is connected to the P+ pickup active region and to the first electrode of the driving transistor in the adjacent two rows of pixel driving circuits; and the P+ pickup active region is configured to provide a first power signal to the first electrode of the driving transistor in the adjacent two rows of pixel driving circuits.

[0015] Optionally, the array substrate further includes a first node connection line; wherein the first node connection line is connected to the second electrode of the second transistor through one or more first vias, and connected to the gate of the driving transistor through one or more second vias; and the first node connection line is located on a different layer from the second electrode of the second transistor, and on a different layer from the gate of the driving transistor.

[0016] Optionally, the array substrate further includes an anti-interference block configured to receive a constant voltage signal; wherein the orthographic projection of the anti-interference block on the substrate spaced the orthographic projections of the one or more first vias on the substrate from the orthographic projections of the one or more second vias on the substrate; the orthographic projection of the anti-interference block on the substrate at least partially overlaps with the orthographic projection of the gate of the driving transistor on the substrate, and at least partially overlaps with the orthographic projection of the active layer of the driving transistor on the substrate; and the orthographic projection of the anti-interference block on the substrate does not overlap with the orthographic projections of the one or more first vias on the substrate, and does not overlap with the orthographic projections of the one or more second vias on the substrate.

[0017] Optionally, the anti-interference block is connected to the first electrode of the driving transistor and is configured to receive a first power signal.

[0018] Optionally, on all sides, the orthographic projection of each pixel driving circuit in the plurality of pixel driving circuits onto the substrate is at least partially surrounded by the orthographic projection of the signal lines onto the substrate.

[0019] Optionally, on a first side of each pixel driving circuit, the orthographic projection of the respective pixel driving circuit on the substrate is at least partially surrounded by the orthographic projection of one or more signal lines on the substrate; on a second side of each pixel driving circuit, the orthographic projection of the respective pixel driving circuit on the substrate is at least partially surrounded by the orthographic projection of one or more signal lines on the substrate; on a third side of each pixel driving circuit, the orthographic projection of the respective pixel driving circuit on the substrate is at least partially surrounded by the orthographic projection of one or more signal lines on the substrate; and on a fourth side of each pixel driving circuit, the orthographic projection of the respective pixel driving circuit on the substrate is at least partially surrounded by the orthographic projection of one or more signal lines on the substrate; wherein the first side is opposite to the second side, the third side is opposite to the fourth side, the third side connects the first side to the second side, and the fourth side connects the first side to the second side.

[0020] Optionally, the one or more signal lines located on the first side, the one or more signal lines located on the second side, the one or more signal lines located on the third side, and the one or more signal lines located on the fourth side are configured to provide one or more constant voltage signals.

[0021] Optionally, on a first side of each pixel driving circuit, the orthographic projection of each pixel driving circuit on the substrate is at least partially surrounded by the orthographic projection of at least a portion of the first power line on the substrate; on a second side of each pixel driving circuit, the orthographic projection of each pixel driving circuit on the substrate is at least partially surrounded by the orthographic projection of a reset voltage line on the substrate; on a third side of each pixel driving circuit, the orthographic projection of each pixel driving circuit on the substrate is at least partially surrounded by the orthographic projection of at least a portion of the first power line on the substrate; and on a fourth side of each pixel driving circuit, the orthographic projection of each pixel driving circuit on the substrate is at least partially surrounded by the orthographic projection of an initialization voltage line on the substrate; wherein the first side is opposite to the second side, the third side is opposite to the fourth side, the third side connects the first side to the second side, and the fourth side connects the first side to the second side.

[0022] Optionally, the second connection line includes: a first connection portion extending along a first direction; a second connection portion extending along a second direction toward a gate line connected to the gate of the sixth transistor; and a third connection portion extending along the first direction; wherein the second connection portion is connected to the first connection portion and to the third connection portion.

[0023] Optionally, the third connection portion is spaced apart from the gate of the fifth transistor by a first shortest distance; the first connection line is spaced apart from the gate of the fifth transistor by a second shortest distance; the second connection portion is spaced apart from the gate of the fifth transistor by a third shortest distance; and the first connection portion is spaced apart from the gate of the sixth transistor by a fourth shortest distance; wherein at least one of the first shortest distance, the third shortest distance, or the fourth shortest distance is greater than the second shortest distance.

[0024] On the other hand, this disclosure provides a display device including an array substrate described herein or manufactured by the methods described herein, and one or more integrated circuits connected to the array substrate. Attached Figure Description

[0025] The following figures are merely illustrative examples based on various disclosed embodiments and are not intended to limit the scope of the invention.

[0026] Figure 1 This is a schematic diagram illustrating the structure of a display panel according to some embodiments of the present disclosure.

[0027] Figure 2This is a schematic diagram illustrating the structure of a first portion of a display panel according to some embodiments of the present disclosure.

[0028] Figure 3 This is a schematic diagram illustrating the structure of a second portion of a display panel according to some embodiments of the present disclosure.

[0029] Figure 4 This illustrates a display panel formed by assembling a first part and a second part together.

[0030] Figure 5 It is the edge of the display panel Figure 4 A cross-sectional view of line A-A' in the diagram.

[0031] Figure 6 This is a schematic diagram illustrating the structure of a first portion of a display panel according to some embodiments of the present disclosure.

[0032] Figure 7 This is a circuit diagram of a pixel driving circuit according to some embodiments of the present disclosure.

[0033] Figure 8 This is a schematic diagram illustrating the structure of a display panel according to some embodiments of the present disclosure.

[0034] Figure 9 This is a schematic diagram illustrating the structure of a display panel according to some embodiments of the present disclosure.

[0035] Figure 10 This is a timing diagram illustrating the operation of a pixel driving circuit according to some embodiments of the present disclosure.

[0036] Figure 11 This is a circuit diagram of the pixel driving circuit in the first stage according to some embodiments of the present disclosure.

[0037] Figure 12 This is a circuit diagram of the pixel driving circuit in the second stage according to some embodiments of the present disclosure.

[0038] Figure 13 This is a circuit diagram of the pixel driving circuit in the third stage according to some embodiments of this disclosure.

[0039] Figure 14 This is a circuit diagram of the pixel driving circuit in the fourth stage according to some embodiments of this disclosure.

[0040] Figure 15 This is a schematic diagram illustrating the structure of a portion of an array substrate according to some embodiments of the present disclosure.

[0041] Figure 16 This is a schematic diagram illustrating the structure of an array substrate according to some embodiments of the present disclosure.

[0042] Figure 17 This is a cross-sectional view of an array substrate according to some embodiments of the present disclosure.

[0043] Figure 18 This is a cross-sectional view of an array substrate according to some embodiments of the present disclosure.

[0044] Figure 19 This is a schematic diagram illustrating the structure of each layer in the individual pixel driving circuitry of an array substrate according to some embodiments of the present disclosure.

[0045] Figure 20A This is a schematic diagram illustrating the structure of a portion of an array substrate according to some embodiments of the present disclosure.

[0046] Figure 20B Show Figure 20A The image depicts a portion of an array substrate containing multiple N-type well regions and multiple P-type well regions.

[0047] Figure 20C It is shown Figure 20A A schematic diagram of the structure of a semiconductor material layer in a portion of an array substrate.

[0048] Figure 20D It is shown Figure 20A A schematic diagram of the structure of the first conductive layer in a portion of the array substrate depicted in the figure.

[0049] Figure 20E It is shown Figure 20A A schematic diagram of an n-type implantation region in a portion of an array substrate depicted in the image.

[0050] Figure 20F It is shown Figure 20A A schematic diagram of a p-type implantation region in a portion of an array substrate depicted in the image.

[0051] Figure 20G It is shown Figure 20A A schematic diagram of contact holes in a portion of an array substrate, depicting electrodes connecting to a semiconductor material layer.

[0052] Figure 20H It is shown Figure 20A A schematic diagram of the structure of the first signal line layer in a portion of the array substrate depicted in the figure.

[0053] Figure 20I It is shown Figure 20A A schematic diagram of the structure of the first insulating layer in a portion of the array substrate depicted in the figure.

[0054] Figure 20J It is shown Figure 20AA schematic diagram of the structure of the second signal line layer in a portion of the array substrate depicted in the figure.

[0055] Figure 20K It is shown Figure 20A A schematic diagram of the structure of the second insulating layer in a portion of the array substrate depicted in the figure.

[0056] Figure 20L It is shown Figure 20A A schematic diagram of the structure of the third signal line layer in a portion of the array substrate depicted in the figure.

[0057] Figure 20M It is shown Figure 20A A schematic diagram of the structure of the third insulating layer in a portion of the array substrate depicted in the figure.

[0058] Figure 20N It is shown Figure 20A A schematic diagram of the structure of the fourth signal line layer in a portion of the array substrate depicted in the image.

[0059] Figure 200 It is shown Figure 20A A schematic diagram of the structure of the first electrode layer in a portion of the array substrate depicted in the figure.

[0060] Figure 20P It is shown Figure 20A A schematic diagram of the structure of the fourth insulating layer in a portion of the array substrate depicted in the figure.

[0061] Figure 20Q It is shown Figure 20A A schematic diagram of the structure of the second electrode layer in a portion of the array substrate depicted in the figure.

[0062] Figure 20R It is shown Figure 20A A schematic diagram of the structure of the third electrode layer in a portion of the array substrate depicted in the image.

[0063] Figure 20S It is shown Figure 20A A schematic diagram of the structure of the fifth insulating layer in a portion of the array substrate depicted in the diagram.

[0064] Figure 21 Show Figure 20A The arrangement of pixel driving circuits in a portion of the array substrate is depicted in the figure.

[0065] Figure 22 This is an enlarged view of a portion of an array substrate according to some embodiments of the present disclosure.

[0066] Figure 23 This is an enlarged view of a portion of an array substrate according to some embodiments of the present disclosure.

[0067] Figure 24 This is an enlarged view of a portion of an array substrate according to some embodiments of the present disclosure.

[0068] Figure 25 This is an enlarged view of a portion of an array substrate according to some embodiments of the present disclosure.

[0069] Figure 26 This is an enlarged view of a portion of a semiconductor material layer in an array substrate according to some embodiments of the present disclosure.

[0070] Figure 27 This is an enlarged view of a portion of an array substrate according to some embodiments of the present disclosure.

[0071] Figure 28 This is an enlarged view of a portion of an array substrate according to some embodiments of the present disclosure.

[0072] Figure 29 This is an enlarged view of a portion of an array substrate according to some embodiments of the present disclosure.

[0073] Figure 30 This is an enlarged view of a portion of an array substrate according to some embodiments of the present disclosure.

[0074] Figure 31 This is an enlarged view of a portion of an array substrate according to some embodiments of the present disclosure.

[0075] Figure 32 This is a schematic diagram illustrating a corresponding pixel driving circuit according to some embodiments of the present disclosure.

[0076] Figure 33 This is a schematic diagram showing a first connection line and a second connection line in an array substrate according to some embodiments of the present disclosure. Detailed Implementation

[0077] This disclosure will now be described in more detail with reference to the following embodiments. It should be noted that the following description of some embodiments presented herein is for illustrative and descriptive purposes only. It is not exhaustive or limited to the precise forms disclosed.

[0078] Silicon-based OLEDs primarily use a single-chip architecture. Figure 1 This is a schematic diagram illustrating the structure of a display panel according to some embodiments of the present disclosure. For example... Figure 1 As shown, the single-chip architecture integrates the display area (effective area) with complete display control and driving circuitry (including row and column driving units, image processing units, memory units, clock control units, etc.) into a single chip. (Refer to...) Figure 1In some embodiments, the display panel includes a display area DA, which represents a portion of the actual displayed image. This is where pixels are driven to display content. In some embodiments, the display panel includes one or more gate drivers GD, which are responsible for providing gate drive signals to the pixel array to control the timing of pixel updates during display operation. In some embodiments, the display panel also includes one or more source drivers SD and one or more source driver multiplexers SDM. The one or more source driver multiplexers SDM are configured to perform multiplexing of data signals for the pixel array. The one or more source drivers SD are configured to provide data signals to the pixels to control the image being displayed by adjusting pixel brightness. In some embodiments, the display panel also includes one or more memory RAMs configured to store frame buffers and display data for faster access. In some embodiments, the display panel also includes one or more bonding pad areas BPA for electrical connection and bonding to the remainder of external circuitry or devices. In some embodiments, the display panel further includes one or more image processing modules (IPBs) for processing input image data, one or more interfaces (MIPIs) for communicating between the display panel and other processors, a timing controller (TCON) configured to manage the timing of signals to control the display, and one or more one-time programmable memories (OTPs) configured to perform device calibration or configuration.

[0079] Single-chip display chips include both digital and analog components, thus classifying them as mixed-signal chips. In display control circuitry, modules such as image processing units and clock control units fall into the digital module category, requiring advanced semiconductor manufacturing processes (typically at the 55nm node) for production. Due to the complexity of digital module logic, more (generally at least six) metal layers are needed, significantly increasing the production cost of the single-crystal silicon driver substrate.

[0080] Furthermore, the yield of silicon-based OLED microdisplays can be divided into two parts: the display area and the display control and driving section. The yield of the display control and driving section is determined solely by the semiconductor process, while the yield of the display area depends on both the semiconductor process and the OLED device manufacturing process. In a single-chip architecture, any defect in any part will result in a defect in the entire module, leading to a significant loss in product yield and further increasing production costs.

[0081] In recent years, with the increasing demand for larger display sizes, the cost challenges associated with single-chip architectures have become more significant. To address these cost issues while also reducing power consumption, the industry has introduced a new dual-chip architecture. In a dual-chip architecture, the display area and a portion of the driving circuitry are independent display panels. In some embodiments, the display panel includes a first part and a second part. Figure 2This is a schematic diagram illustrating the structure of a first portion of a display panel according to some embodiments of the present disclosure. (Refer to...) Figure 2 In some embodiments, the first portion includes a display area DA, one or more gate drivers GD, one or more multiplexers DMX, and a cathode ring CR surrounding the display area DA. In some embodiments, the first portion also includes one or more bonding pad areas BPA, one or more integrated circuit bonding areas ICPA, and an integrated circuit IC for electrical connection and bonding to the remainder of external circuitry or devices. The one or more integrated circuit bonding areas ICPA are configured to handle input / output (I / O) operations of the integrated circuit IC, thereby facilitating communication between the integrated circuit IC and other components or external devices. In some embodiments, the integrated circuit IC includes portions configured to drive source lines of the display panel and portions configured to control one or more gate drivers GD.

[0082] Figure 3 This is a schematic diagram illustrating the structure of a second portion of a display panel according to some embodiments of the present disclosure. In some embodiments, the second portion is a display driver integrated circuit (DDIC) portion. (Refer to...) Figure 3 In some embodiments, the second part includes one or more source drivers SD, timing controller TCON, one or more memories RAM, and interface MIPI.

[0083] The first and second parts are manufactured using different process nodes: the second part is produced using advanced process nodes (typically 28nm or below), while the first part is manufactured using less advanced nodes (typically around 110nm). After the circuitry for the first part is fabricated, it is used in the production of the OLED device. Finally, the completed OLED panel is bonded to the second part using a chip-on-chip (COC) process, resulting in a complete display panel. Figure 4 This illustrates a display panel formed by assembling a first part and a second part together. Figure 5 It is the edge of the display panel Figure 4 The cross-sectional view of line A-A' in the diagram. (Refer to...) Figure 4 In some embodiments, the display panel includes a first portion P1 and a second portion P2 assembled together, and a flexible printed circuit FPC connected to the second portion P2.

[0084] Figure 6 This is a schematic diagram illustrating the structure of a first portion of a display panel according to some embodiments of the present disclosure. (Refer to...) Figure 6In some embodiments, at least a portion of one or more gate drivers GDs, one or more source drivers SDs, and a display area are integrated into a first portion. The display area includes a plurality of sub-pixels sp. The display area consists of an array of pixel driving circuitry that provides the current required to drive light-emitting diodes to emit light. One or more gate drivers GDs provide gate drive signals required to control line switching of the pixel circuitry, thereby enabling the display to perform progressive scanning. One or more source drivers SDs transmit data signals required by the pixel circuitry, enabling the switching and control of the displayed image.

[0085] Regardless of whether it's a single-chip or dual-chip architecture, the pixel driving circuit, as a crucial component of the display driver backplane, directly affects performance metrics such as the display's PPI (pixels per inch), maximum brightness, contrast ratio, crosstalk, and flicker. Compared to traditional TFT-based pixel driving circuits, MOS-based silicon microdisplay pixel driving circuits introduce new challenges.

[0086] The pixel driver circuit, as the core circuit of the display driver backplane, together with the gate driver and source driver, constitutes the basic display driver backplane. Under the control of the gate drive signal from one or more gate drivers, the pixel driver circuit uses a switch within each pixel to write the display data signal from one or more source drivers line by line into the storage capacitor of the pixel circuit. Then, the driving transistor in each pixel circuit accurately and continuously outputs the required voltage or current to the optoelectronic device of the display (e.g., OLED, LED, or LCD) based on the voltage stored in the capacitor. Driven by this current or voltage, the display device displays an image by active emission (OLED, LED) or passive emission (LCD).

[0087] Pixel circuits that provide a stable voltage output are generally called voltage-type pixel circuits, while pixel circuits with a stable current output are called current-type pixel circuits. The choice between these types depends on the photoelectric characteristics of the display device being driven.

[0088] Typically, pixel driving circuits require a data writing phase and an output (or emission) phase. Furthermore, considering the switching characteristics of optoelectronic devices and maintaining the consistency of the initial operating state of the pixel circuit, an initialization phase is needed. Additionally, to enhance the consistency of the output current or voltage, an extra threshold compensation phase is introduced to address variations in the threshold voltage and carrier mobility of the driving transistor.

[0089] In summary, standard pixel driver circuits operate in four phases: initialization, threshold compensation, data writing, and output / emission. Depending on the application and circuit design, these phases can be simplified or combined. For example, the threshold compensation and data writing phases can sometimes be combined to perform both functions within a single phase.

[0090] The main performance metrics for pixel driver circuits focus on three key aspects. First, a stable output voltage and / or current range is crucial. A wider range of stable output allows pixel driver circuits to be used in more diverse environments and enhances display brightness and contrast, thus indicating superior circuit performance. Second, the uniformity of output voltage and / or current is necessary. Greater uniformity results in consistent brightness across the entire display, thereby improving visual quality by maintaining uniform illumination. Finally, output stability is critical because displays refresh images frame by frame, requiring pixel driver circuits to maintain a stable output throughout each frame. Furthermore, because displayed images can vary in complexity, pixel driver circuits must provide stable output even for complex or specific image content, unaffected by interference from other data signals on the line. Therefore, the stability of the circuit output is a key indicator of the overall performance of the pixel circuit.

[0091] Pixel driver circuit design includes schematic design and layout design. To achieve optimal display performance, it is necessary to implement threshold compensation, grayscale segmentation, and expand the range of output voltage and / or current in the schematic design. This approach improves display quality. Simultaneously, the layout design should focus on simplifying the circuit layout, minimizing signal interference, and reducing signal attenuation and delay. These efforts collectively improve output stability and uniformity.

[0092] Pixel driving circuits for silicon-based microdisplays are built using CMOS technology, presenting greater design challenges in both principle and layout compared to traditional TFT-based pixel circuits. Silicon-based microdisplays are typically smaller than 2 inches, achieving 4K resolution and boasting ultra-high pixel densities (typically exceeding 3000 PPI). This results in pixel pitches of less than 8.5 μm and individual subpixel sizes of less than 8.5 μm × 2.8 μm, requiring pixel circuit layouts suitable for sizes smaller than 24 μm. 2 The area of ​​the subpixel is approximately 2580 μm. In contrast, traditional smartphone displays have a PPI of around 500 (or even lower for television screens), where the subpixel area is approximately 2580 μm. 2 This makes the space constraints of silicon-based microdisplays more pronounced.

[0093] Furthermore, compared to TFT technology, MOS transistors present challenges due to significant latch-up effects, back-gate effects, and channel length modulation. These effects must be carefully addressed during both the schematic and layout design phases of the pixel circuitry, thus increasing the overall design complexity.

[0094] This disclosure provides a silicon-based microdisplay pixel driving circuit and its variations constructed using semiconductor CMOS technology. The pixel driving circuit includes basic functions such as initialization, Vth (threshold voltage) readout, Vth compensation, data writing, and OLED emission. It is designed to have a wide anode dynamic range, high output uniformity, and excellent output stability, enabling OLED displays driven by this circuit to achieve higher brightness, higher contrast, and extended lifespan.

[0095] Furthermore, to reduce the number of MOS transistors in the pixel circuitry, the design was simplified and modified within the same process node, thereby enabling increased pixel density (PPI). This reduction in MOS transistors allows the circuitry to better meet the demands of higher PPI displays.

[0096] This disclosure provides, in particular, an array substrate and a display device that substantially overcomes one or more problems caused by the limitations and disadvantages of the prior art. In one aspect, this disclosure provides an array substrate. In some embodiments, the array substrate includes a plurality of pixel driving circuits. Optionally, each pixel driving circuit in the plurality of pixel driving circuits includes: a driving transistor having a gate connected to a first node, a first electrode configured to receive a first power supply signal, and a second electrode connected to a second node; a second transistor having a gate connected to a second gate line, a first electrode connected to a corresponding data line for receiving pixel data signals, and a second electrode connected to the first node; a fourth transistor having a gate connected to a fourth gate line, a first electrode connected to a reset voltage line, and a second electrode connected to the second node; a fifth transistor having a gate connected to a fifth gate line, a first electrode connected to the second node, and a second electrode coupled to the anode of a light-emitting element; a sixth transistor having a gate connected to a sixth gate line, a first electrode connected to an initialization voltage line, and a second electrode connected to the anode of a light-emitting element; and a first storage capacitor having a first capacitor electrode connected to the second node and a second capacitor electrode connected to the first node. Optionally, the second electrode of the driving transistor and the second electrode of the fourth transistor are directly connected to each other and are part of an integral structure. Optionally, the array substrate further includes a first interconnect line. Optionally, the first interconnect line is connected to a first capacitor electrode of a first storage capacitor and to a first electrode of a fifth transistor. Optionally, the first capacitor electrode of the first storage capacitor is electrically connected to a second electrode of a driving transistor and a second electrode of a fourth transistor. Optionally, the first interconnect line is located on a different layer from the first capacitor electrode of the first storage capacitor and on a different layer from the first electrode of the fifth transistor.

[0097] Figure 7 This is a circuit diagram of a pixel driving circuit according to some embodiments of this disclosure. (Refer to...) Figure 7In some embodiments, the pixel driving circuit includes: a driving transistor MD; a first storage capacitor C1 having a first capacitor electrode connected to a second node S and a second capacitor electrode connected to a first node G; and a second storage capacitor C2 having a first capacitor electrode connected to the second node S and a second capacitor electrode connected to a second power line ELVSS.

[0098] The driving transistor MD has a gate connected to a first node G, a first electrode connected to a second electrode of a first transistor M1, and a second electrode connected to a second node S. Optionally, the driving transistor MD uses an initialization voltage signal from the initialization voltage line VINI as the back gate voltage.

[0099] In some embodiments, the pixel driving circuit further includes: a first transistor M1 having a gate connected to a first gate line G1, a first electrode connected to a first power line ELVDD, and a second electrode connected to the first electrode of a driving transistor MD; and a second transistor M2 having a gate connected to a second gate line G2, a first electrode connected to a corresponding data line DL for receiving pixel data signals Vdata / VOFS, and a second electrode connected to a first node G. Optionally, the first transistor M1 uses a first power supply signal from the first power line ELVDD as its back gate voltage. Optionally, the second transistor M2 uses the first power supply signal from the first power line ELVDD as its back gate voltage.

[0100] In some embodiments, the pixel driving circuit further includes: a fourth transistor M4 having a gate connected to a fourth gate line G4, a first electrode connected to a reset voltage line VREF, and a second electrode connected to a second node S; and a fifth transistor M5 having a gate connected to a fifth gate line G5, a first electrode connected to a second node S, and a second electrode coupled to the anode of the light-emitting element LE. Optionally, the fourth transistor M4 uses an initialization voltage signal from the initialization voltage line VINI as the back gate voltage. Optionally, the fifth transistor M5 uses a first power supply signal from the first power supply line ELVDD as the back gate voltage.

[0101] In some embodiments, the pixel driving circuit further includes a sixth transistor M6 having a gate connected to a sixth gate line G6, a first electrode connected to an initialization voltage line VINI, and a second electrode connected to the anode of the light-emitting element LE. Optionally, the sixth transistor M6 uses an initialization voltage signal from the initialization voltage line VINI as a back gate voltage.

[0102] The light-emitting element LE has an anode connected to the second electrode of the fifth transistor M5 and a cathode connected to the second power line ELVSS.

[0103] In some embodiments, the pixel driving circuit includes a driving transistor MD, a first data writing transistor (e.g., a second transistor M2), a first light-emitting control transistor (e.g., a first transistor M1), a second light-emitting control transistor (e.g., a fifth transistor M5), a first reset transistor (e.g., a fourth transistor M4), and a second reset transistor (e.g., a sixth transistor M6).

[0104] The first node G is equivalent to the gate of the driving transistor MD. The second node S is equivalent to the second electrode of the driving transistor MD.

[0105] Figure 8 This is a schematic diagram illustrating the structure of a display panel according to some embodiments of the present disclosure. Figure 9 This is a schematic diagram illustrating the structure of a display panel according to some embodiments of the present disclosure. (Refer to...) Figure 8 and Figure 9 In some embodiments, the display panel includes multiple data lines (e.g., first data line DL1 and second data line DL2) for transmitting data signals (e.g., Vdata / VOFS) to multiple columns of sub-pixels. Figure 8 and Figure 9 Two pixel driving circuits are shown, located in the same row and in two adjacent columns. The pixel driving circuits are controlled by a set of gate driving signals provided by multiple gate lines (e.g., first gate line G1 to sixth gate line G6), which selectively activate or deactivate specific transistors in the pixel driving circuits.

[0106] In some embodiments, pixel driving circuits in the same row and multiple columns share the same first transistor. In some embodiments, the display panel includes multiple pixel driving circuits located in the same row and in multiple columns respectively. Each pixel driving circuit in the multiple pixel driving circuits in the same row and multiple columns includes: a driving transistor MD; a first storage capacitor C1 having a first capacitor electrode connected to a second node S and a second capacitor electrode connected to a first node G; a second storage capacitor C2 having a first capacitor electrode connected to a second node S and a second capacitor electrode connected to a second power supply line ELVSS; a second transistor M2 having a gate connected to a second gate line G2, a first electrode connected to a corresponding data line DL for receiving pixel data signals Vdata / VOFS, and a second electrode connected to the first node G; a fourth transistor M4 having a gate connected to a fourth gate line G4, a first electrode connected to a reset voltage line VREF, and a second electrode connected to the second node S; a fifth transistor M5 having a gate connected to a fifth gate line G5, a first electrode connected to the second node S, and a second electrode coupled to the anode of the light-emitting element LE; and a sixth transistor M6 having a gate connected to a sixth gate line G6, a first electrode connected to an initialization voltage line VINI, and a second electrode connected to the anode of the light-emitting element LE. The driving transistor MD has a gate connected to a first node G, a first electrode connected to a second electrode of a first transistor M1, and a second electrode connected to a second node S. Optionally, the driving transistor MD uses an initialization voltage signal from the initialization voltage line VINI as the back gate voltage.

[0107] In some embodiments, the display panel further includes a first transistor M1 having a gate connected to a first gate line G1, a first electrode connected to a first power line ELVDD, and a second electrode connected to the first electrode of a driving transistor in a plurality of pixel driving circuits in the same row and a plurality of columns.

[0108] Optionally, the first transistor M1 uses a first power signal from the first power line ELVDD as its back gate voltage. Optionally, the second transistor M2 uses a first power signal from the first power line ELVDD as its back gate voltage. Optionally, the fourth transistor M4 uses an initialization voltage signal from the initialization voltage line VINI as its back gate voltage. Optionally, the fifth transistor M5 uses a first power signal from the first power line ELVDD as its back gate voltage. Optionally, the sixth transistor M6 uses an initialization voltage signal from the initialization voltage line VINI as its back gate voltage.

[0109] The driving transistor MD is configured to operate in the subthreshold region by setting appropriate ranges for the source voltage, drain voltage, and gate voltage. At different gate voltages, the driving transistor MD outputs different levels of drive current, which controls the brightness of the light-emitting element LE to display information.

[0110] The fourth transistor M4 acts as the source reset switch for the driving transistor MD, controlling the input of the reset signal from the reset signal line VINI.

[0111] In one example, the fifth transistor M5 is a p-type transistor with two main functions. First, as a p-type transistor, the fifth transistor M5 prevents latch-up when an abnormal negative potential is present on the anode (typically caused by an anode-cathode short circuit). Because the substrate is an N-type well, the negative potential does not create a positive bias between the drain and the N-type well, thus avoiding latch-up. Without the fifth transistor M5, if the anode experiences a negative potential, the driving transistor MD (with a P-type well substrate) will have a positive bias between the drain and the P-type well, potentially leading to latch-up and display defects such as line defects.

[0112] Secondly, the fifth transistor M5 helps adjust the output current and voltage, improving display contrast. At low grayscale levels, the potential at the second node S is low. Under the same bias potential, the fifth transistor M5 operates at a lower on-level and acts as a large resistor, reducing the voltage supplied to the light-emitting element LE and further reducing the output current. At high grayscale levels, the potential at the second node S is higher. Under the same bias potential, the fifth transistor M5 has a higher on-level, effectively acting as a small resistor, increasing the voltage supplied to the light-emitting element LE and thus increasing the output current. This allows the fifth transistor M5 to increase the difference between high and low grayscale outputs, increasing contrast. With appropriate voltage settings, the fifth transistor M5 can be completely turned off at zero grayscale, thus achieving high contrast.

[0113] The sixth transistor, M6, is an anode reset switch that controls the input of the initialization voltage signal from the initialization voltage signal line VINI. This allows for a rapid reset of the anode potential, thereby improving dynamic contrast and ensuring a consistent initialization state throughout the pixel circuitry, thus enhancing pixel output uniformity.

[0114] Figure 10 This is a timing diagram illustrating the operation of a pixel driving circuit according to some embodiments of the present disclosure. (Refer to...) Figures 7 to 10 The operation of the pixel driving circuit includes the first stage t1, the second stage t2, the third stage t3, and the fourth stage t4.

[0115] In the first stage t1 (initialization stage), the gate and source potentials of the driving transistor MD and the anode potential of the light-emitting element LE are initialized. In the second stage t2 (threshold voltage sensing stage), the threshold voltage V of the driving transistor is... th Data is stored in the first storage capacitor C1 through self-discharge. In the third stage t3 (data writing stage), data is written to the first storage capacitor C1 and the second storage capacitor C2. Threshold voltage compensation is achieved due to the specific relationship between the capacitance ratio of the first storage capacitor C1 and the second storage capacitor C2 and the back gate coefficient of the driving transistor MD. In the fourth stage t4 (emission stage), after threshold compensation, the driving transistor operates in the subthreshold region under the control of the voltage stored in the first storage capacitor C1. The driving current flows through the OLED, causing it to emit light for display.

[0116] Figure 11 This is a circuit diagram of the pixel driving circuit in the first stage according to some embodiments of this disclosure. (Refer to...) Figure 10 and Figure 11 In the first stage t1, the second gate line G2 is configured to provide an effective voltage signal (e.g., a low voltage signal), and the second transistor M2 is turned on, allowing the offset voltage signal VOFS to be written through the first transistor M1 to the gate of the driving transistor MD (or the first capacitor electrode of the first storage capacitor C1). The potential at the first node G becomes V. G =VOFS. Simultaneously, the fourth gate line G4 is configured to provide an effective voltage signal (e.g., a high voltage signal), thereby turning on the fourth transistor M4. This allows the reset signal from the reset signal line VREF to be written through the fourth transistor M4 to the first electrode of the driving transistor MD (or to the second capacitor electrode of the first storage capacitor C1), thereby setting the potential of the second node S to V. S =VREF. Furthermore, the sixth gate line G6 is configured to provide an effective voltage signal (e.g., a high voltage signal) that turns on the sixth transistor M6, causing an initialization signal from the initialization signal line VINI to be written into the anode of the light-emitting element LE, thereby setting the anode potential to V. Anode =VINI.

[0117] Simultaneously, the first gate line G1 is configured to provide an invalid voltage signal (e.g., a high voltage signal), thereby turning off the first transistor M1; and the fifth gate line G5 is configured to provide an invalid voltage signal (e.g., a high voltage signal), thereby turning off the fifth transistor M5, preventing current caused by the voltage difference between the reset signal from the reset signal line VREF and the initialization signal from the initialization signal line VINI. The storage voltage across the first storage capacitor C1 becomes V. C1 =V GS=VOFS-VREF. The threshold voltage for driving transistor MD is V. th VOFS-VREF>V th This provides the threshold voltage V for driving transistor MD. th Prepare for reading.

[0118] Figure 12 This is a circuit diagram of the pixel driving circuit in the second stage according to some embodiments of this disclosure. (Refer to...) Figure 10 and Figure 12 In the second stage t2, the gate drive signal provided by the first gate line G1 changes from an invalid voltage signal (e.g., a high voltage signal) to an effective voltage signal (e.g., a low voltage signal), and the first transistor M1 turns on, thereby setting the drain potential of the driving transistor MD to V. D =ELVDD. The gate drive signal provided by the second gate line G2 changes from an effective voltage signal (e.g., a low voltage signal) to an ineffective voltage signal (e.g., a high voltage signal), thereby turning off the second transistor M2 and causing the gate of the driving transistor MD to float. The gate drive signal provided by the fourth gate line G4 also changes from an effective voltage signal (e.g., a high voltage signal) to an ineffective voltage signal (e.g., a low voltage signal), causing the second electrode of the driving transistor MD to float. The gate drive signals provided by the fifth gate line G5 and the sixth gate line G6 remain unchanged, causing the fifth transistor M5 and the sixth transistor M6 to remain in the same state as in the first stage t1.

[0119] The gate-source voltage of the driving transistor MD is V GS =V C1 =VOFS-VREF>V th Due to the drain voltage V DS =ELVDD-VREF, therefore, the driving transistor MD turns on and begins to discharge. Since the gate and source of the driving transistor MD are floating, the voltage across the first storage capacitor C1 remains constant during discharge; therefore, V C1 =V GS =VOFS-VREF. Simultaneously, the source potential of the driving transistor MD rises at the second node S, and due to the back-gate effect, the equivalent threshold voltage V... th_eq Change to V th_eq =V th +α×V SB =V th +α×(V s -V B ).

[0120] Discharge continues until V th_eq Increase to equal V th_eq =V C1 =V GS=VOFS-VREF, at which point the driving transistor MD is cut off, marking the end of the threshold reading phase. At this time, V th +α×(V s -V B ) = VOFS - VREF, where the back gate potential V B =VINI. Therefore, and

[0121] Figure 13 This is a circuit diagram of the pixel driving circuit in the third stage according to some embodiments of this disclosure. (Refer to...) Figure 10 and Figure 13 In the third stage t3, the gate drive signal provided by the first gate line G1 changes from an effective voltage signal (e.g., a low voltage signal) to an ineffective voltage signal (e.g., a high voltage signal), and the first transistor M1 is turned off, causing the first electrode of the driving transistor MD to float. The gate drive signal provided by the second gate line G2 changes from an ineffective voltage signal (e.g., a high voltage signal) to an effective voltage signal (e.g., a low voltage signal), thereby turning on the second transistor M2, allowing Vdata to be written to the gate of the driving transistor MD through the second transistor M2. The gate potential at the first node G becomes V G =VDATA. The gate drive signals provided by the fourth gate line G4, the fifth gate line G5, and the sixth gate line G6 remain unchanged, and the fourth transistor M4, the fifth transistor M5, and the sixth transistor M6 remain in the same state as in the second stage t2.

[0122] With the fourth transistor M4 and the fifth transistor M5 turned off and the second electrode of the driving transistor MD floating, the gate of the driving transistor MD also floats. Before the second transistor M2 is turned on, the voltage across the first storage capacitor C1 is V. C1 =V GS =VOFS-VREF. The source potential at the second node S is The gate potential at the first node G is

[0123] The voltage change (ΔV) at the second node S before and after the second transistor M2 is turned on. S ) and the voltage change (ΔV) at the first node G G Satisfying the relationship when At that time, ΔV S = (1-b)ΔV G .

[0124] After the second transistor M2 is turned on, the new source potential V' at the second node S S Depend on

[0125] Given the gate-source voltage V' of the driving transistor MD. GS Depend on Provided.

[0126] Figure 14 This is a circuit diagram of the pixel driving circuit in the fourth stage according to some embodiments of this disclosure. (Refer to...) Figure 10 and Figure 14 In the fourth stage t4, the gate drive signal provided by the first gate line G1 changes from an invalid voltage signal (e.g., a high voltage signal) to an effective voltage signal (e.g., a low voltage signal), and the first transistor M1 turns on, allowing the first power supply signal from the first power supply line ELVDD to flow through the first transistor M1 to the first electrode of the driving transistor MD. The gate drive signal provided by the second gate line G2 remains invalid (e.g., high), thus keeping the second transistor M2 off. The gate drive signal provided by the fourth gate line G4 remains invalid (e.g., low), thus keeping the fourth transistor M4 off. The gate drive signal provided by the fifth gate line G5 changes from an invalid voltage signal (e.g., a high voltage signal) to an effective voltage signal (e.g., a low voltage signal), thus turning on the fifth transistor M5, while the gate drive signal provided by the sixth gate line G6 changes from an effective voltage signal (e.g., a high voltage signal) to an invalid voltage signal (e.g., a low voltage signal), thus turning off the sixth transistor M6.

[0127] As the first capacitor electrode of the first storage capacitor C1 (at the first node G) becomes floating, the potential change at the second node S causes a corresponding change at the first node G, satisfying ΔV S =ΔV G Therefore, the gate-source voltage V' driving transistor MD GS It remains unchanged.

[0128] At this time, the current passing through the light-emitting element IOLED is... Given; where α represents the back-gate coefficient; b represents the capacitance ratio of the first storage capacitor C1 to the total capacitance of the first storage capacitor C1 and the second storage capacitor C2; C ox This represents the oxide capacitance per unit area.

[0129] This equation shows that when At that time, I OLED Becoming independent of V th Thus, threshold voltage compensation is achieved.

[0130] In some embodiments, when the driving transistor operates in the subthreshold region (or weak inversion region), the current I through the light-emitting element... OLED It is given by the following formula: When V ds When >100mV when hour,

[0131] Figure 15 This is a schematic diagram illustrating the structure of a portion of an array substrate according to some embodiments of the present disclosure. (Refer to...) Figure 15 A portion of the array substrate includes 16 pixel driving circuits arranged in four columns and four rows. Figure 15 The corresponding pixel drive circuit (PDC) is shown in the diagram. (Refer to...) Figure 15 , Figure 8 and Figure 9 In some embodiments, pixel driving circuits in the same row and multiple columns share the same first transistor. In some embodiments, the display panel includes multiple pixel driving circuits located in the same row and in multiple columns respectively. Each pixel driving circuit in the multiple pixel driving circuits in the same row and multiple columns includes: a driving transistor MD; a first storage capacitor C1 having a first capacitor electrode connected to a second node S and a second capacitor electrode connected to a first node G; a second storage capacitor C2 having a first capacitor electrode connected to a second node S and a second capacitor electrode connected to a second power supply line ELVSS; a second transistor M2 having a gate connected to a second gate line G2, a first electrode connected to a corresponding data line DL for receiving pixel data signals Vdata / VOFS, and a second electrode connected to the first node G; a fourth transistor M4 having a gate connected to a fourth gate line G4, a first electrode connected to a reset voltage line VREF, and a second electrode connected to the second node S; a fifth transistor M5 having a gate connected to a fifth gate line G5, a first electrode connected to the second node S, and a second electrode coupled to the anode of the light-emitting element LE; and a sixth transistor M6 having a gate connected to a sixth gate line G6, a first electrode connected to an initialization voltage line VINI, and a second electrode connected to the anode of the light-emitting element LE. The driving transistor MD has a gate connected to a first node G, a first electrode connected to a second electrode of a first transistor M1, and a second electrode connected to a second node S. Optionally, the driving transistor MD uses an initialization voltage signal from the initialization voltage line VINI as the back gate voltage.

[0132] In some embodiments, each pixel driving circuit includes two p-type transistors (second transistor M2 and fifth transistor M5), three n-type transistors (driving transistor MD, fourth transistor M4, and sixth transistor M6), and two capacitors. In some embodiments, the transistors are located in N-type wells with deep N-type wells. The deep N-type wells introduce a negative voltage (e.g., an initialization voltage signal from the initialization voltage line VINI) to extend the dynamic range of the anode, thereby enhancing the contrast of the display. Additionally, the deep N-type wells provide noise isolation for peripheral circuitry modules, thereby reducing their impact on the display area.

[0133] In some embodiments, the first storage capacitor C1 and the second storage capacitor C2 have a metal-insulator-metal (MIM) capacitor structure, which is formed by inserting additional metal plates into a conventional metal layer to create the MIM capacitor. By minimizing the distance between these plates, the capacitance density is increased, resulting in a high-density MIM capacitor. These capacitors can also be replaced with MOS capacitors or MOM capacitors if capacitance and area requirements are met.

[0134] In some embodiments, the array substrate includes an N+ pickup active region NAA and a P+ pickup active region PAA. The N+ pickup active region NAA is an active region connected to the N-type well, providing an initialization voltage signal (e.g., from the initialization voltage line VINI) to the N-type well. The substrates of the n-type transistors are interconnected. In some embodiments, the P+ pickup active region PAA is an active region connected to the P-type well, providing a first power supply signal (e.g., from the first power line ELVDD) to the P-type well. The substrates of the p-type transistors are interconnected.

[0135] In some embodiments, the N+ pickup active region NAA is configured as a contact point for connecting the N-type sink to a specific voltage, which is typically an initialization voltage signal (e.g., from the initialization voltage line VINI).

[0136] In some embodiments, the P+ pickup active region PAA is configured as a contact point that connects the P-type trap to a specified voltage, which is typically a first power supply signal (e.g., from a first power line ELVDD).

[0137] Figure 16 This is a schematic diagram illustrating the structure of an array substrate according to some embodiments of the present disclosure. (Refer to...) Figure 16 The array substrate includes a display area DA, one or more gate drive circuits GOA connected to the display area DA, and one or more demultiplexers DEMUX connected to the display area DA. Optionally, the array substrate also includes input / output pads and fan-out areas.

[0138] In some embodiments, in the display area DA, the initialization voltage signal from the initialization voltage line VINI is used as the anode reset voltage to expand the dynamic range of the anode of the pixel driving circuit. The input signals of one or more gate drive circuits GOA and one or more demultiplexers DEMUX are output by the display driver integrated circuit (DDIC) and fed to one or more gate drive circuits GOA and one or more demultiplexers DEMUX through input / output pads and fan-out areas within a voltage domain from ground voltage to a first power supply voltage.

[0139] To ensure isolation between the initialization voltage signal and the ground signal (to prevent short circuits between the second power line and ground), a deep N-well (DNW) is used. This DNW isolates the P-wells within display area DA from those outside DA, thus preventing short circuits between the second power line and ground. This isolation is achieved through junction isolation, where the cathode (N-side) of the parasitic diode is connected to a positive voltage (opposite), while the anode (P-side) is connected to a negative voltage, creating a non-conductive reverse-biased PN junction.

[0140] Figure 17 This is a cross-sectional view of an array substrate according to some embodiments of this disclosure. (Refer to...) Figure 17 Multiple transistors are arranged in a structured combination of P-type wells and N-type wells, and have deep N-type wells (DNWs) for enhanced isolation. In some embodiments, the array substrate includes a substrate BSP, deep N-type wells (DNWs) located on the substrate BSP, and multiple P-type wells (PWs) and multiple N-type wells (NWs) alternately arranged on the deep N-type wells (DNWs). The multiple P-type wells (PWs) include one or more p-type transistors. The multiple N-type wells (NWs) include one or more n-type transistors. The deep N-type wells (DNWs) are located within the display area (DA) of the array substrate and outside the peripheral area (PA) of the array substrate.

[0141] In some embodiments, each transistor in the array substrate includes a first electrode S, a second electrode D, a gate G, and a back gate B. Each p-type transistor includes a corresponding P-type well among a plurality of P-type wells PW. Each n-type transistor includes a corresponding N-type well among a plurality of N-type wells NW.

[0142] Figure 18 This is a cross-sectional view of an array substrate according to some embodiments of this disclosure. (Refer to...) Figure 18Multiple transistors are arranged in a structured combination of P-type wells and N-type wells, and have deep N-type wells (DNWs) for enhanced isolation. In some embodiments, the array substrate includes a substrate BSP, deep N-type wells (DNWs) located on the substrate BSP, and multiple P-type wells (PWs) and multiple N-type wells (NWs) alternately arranged on the deep N-type wells (DNWs). The multiple P-type wells (PWs) include one or more p-type transistors. The multiple N-type wells (NWs) include one or more n-type transistors. The deep N-type wells (DNWs) are located within the display area (DA) of the array substrate and outside the peripheral area (PA) of the array substrate.

[0143] In some embodiments, each transistor in the array substrate includes a first electrode S, a second electrode D, a gate G, and a back gate. Each p-type transistor includes a corresponding P-type well among a plurality of P-type wells PW. Each n-type transistor includes a corresponding N-type well among a plurality of N-type wells NW.

[0144] In some embodiments, the p-type transistors in the peripheral region PA use the ground voltage signal Gd as the back gate voltage. In some embodiments, the n-type transistors in the peripheral region PA use the first power supply signal Vdd as the back gate voltage.

[0145] In some embodiments, the p-type transistors in display area DA use a second power supply signal Vss as their back gate voltage. In some embodiments, the n-type transistors in display area DA use a first power supply signal Vdd as their back gate voltage.

[0146] Figure 19 This is a schematic diagram illustrating the structure of each layer in the individual pixel driving circuitry of an array substrate according to some embodiments of the present disclosure. (Refer to...) Figure 19 and Figure 7 In some embodiments, each pixel driving circuit includes a driving transistor MD, a second transistor M2, a fourth transistor M4, a fifth transistor M5, and a sixth transistor M6. Figure 19 The diagram shows a semiconductor material layer SML including an active layer of transistors and a first conductive layer including the gates of the transistors. The array substrate also includes a first gate line G1, a second gate line G2, a third gate line G3, a fourth gate line G4, and corresponding data lines DL for receiving pixel data signals Vdata / VOFS.

[0147] Figure 20A This is a schematic diagram illustrating the structure of a portion of an array substrate according to some embodiments of the present disclosure. Figure 20B Show Figure 20A The image depicts a portion of an array substrate containing multiple N-type well regions and multiple P-type well regions. Figure 20C It is shown Figure 20A A schematic diagram of the structure of a semiconductor material layer in a portion of an array substrate. Figure 20DIt is shown Figure 20A A schematic diagram of the structure of the first conductive layer in a portion of the array substrate depicted in the figure. Figure 20E It is shown Figure 20A A schematic diagram of an n-type implantation region in a portion of an array substrate depicted in the image. Figure 20F It is shown Figure 20A A schematic diagram of a p-type implantation region in a portion of an array substrate depicted in the image. Figure 20G It is shown Figure 20A A schematic diagram of contact holes in a portion of an array substrate, depicting electrodes connecting to a semiconductor material layer.

[0148] Reference Figure 15 , Figure 17 , Figure 18 , Figures 20A to 20G In some embodiments, the array substrate includes a plurality of N-type well regions (NWRs) and a plurality of P-type well regions (PWRs). In some embodiments, the plurality of NWRs and PWRs are arranged alternately. In some embodiments, the plurality of NWRs form a plurality of first columns, and the plurality of PWRs form a plurality of second columns. The plurality of first columns and the plurality of second columns are arranged alternately.

[0149] Each of the multiple N-type well regions (NWR) includes the active layer of the n-type transistor in the pixel driving circuit, and each of the multiple P-type well regions (PWR) includes the active layer of the p-type transistor in the pixel driving circuit.

[0150] Figure 21 Show Figure 20A The image depicts the arrangement of pixel driving circuitry in a portion of an array substrate. (Refer to...) Figures 20A to 20G and Figure 21In some embodiments, multiple pixel driving circuits are arranged in an array comprising multiple rows and multiple columns. In one depicted example, multiple pixel driving circuits are arranged in a first column C1, a second column C2, a third column C3, a fourth column C4, a first row R1, a second row R2, a third row R3, and a fourth row R4. The first row R1 includes a first pixel driving circuit PDC1, a second pixel driving circuit PDC2, a third pixel driving circuit PDC3, and a fourth pixel driving circuit PDC4. The second row R2 includes a fifth pixel driving circuit PDC5, a sixth pixel driving circuit PDC6, a seventh pixel driving circuit PDC7, and an eighth pixel driving circuit PDC8. The third row R3 includes a ninth pixel driving circuit PDC9, a tenth pixel driving circuit PDC10, an eleventh pixel driving circuit PDC11, and a twelfth pixel driving circuit PDC12. The fourth row R4 includes a thirteenth pixel driving circuit PDC13, a fourteenth pixel driving circuit PDC14, a fifteenth pixel driving circuit PDC15, and a sixteenth pixel driving circuit PDC16. The first column C1 includes a first pixel driving circuit PDC1, a fifth pixel driving circuit PDC5, a ninth pixel driving circuit PDC9, and a thirteenth pixel driving circuit PDC13. The second column C2 includes a second pixel driving circuit PDC2, a sixth pixel driving circuit PDC6, a tenth pixel driving circuit PDC10, and a fourteenth pixel driving circuit PDC14. The third column C3 includes a third pixel driving circuit PDC3, a seventh pixel driving circuit PDC7, an eleventh pixel driving circuit PDC11, and a fifteenth pixel driving circuit PDC15. The fourth column C4 includes a fourth pixel driving circuit PDC4, an eighth pixel driving circuit PDC8, a twelfth pixel driving circuit PDC12, and a sixteenth pixel driving circuit PDC16. In some embodiments, a row of pixel driving circuits is arranged along a first direction DR1, and a column of pixel driving circuits is arranged along a second direction DR2.

[0151] In some embodiments, the first pixel driving circuits that are directly adjacent to each other and in the same level (e.g., located in the same row) (e.g., Figure 21 The corresponding layer of PDC2 in the second pixel driving circuit (e.g., Figure 21 The corresponding layers of PDC3 in the array have, for example, a substantially mirror symmetry (e.g., at least 80%, at least 85%, at least 90%, at least 95%, at least 98%, at least 99%, or completely symmetrical) relative to each other, with respect to a plane perpendicular to the main surface of the array substrate and substantially parallel to the second direction DR2.

[0152] As used herein, the term “corresponding layer of the first pixel driving circuit and corresponding layer of the second pixel driving circuit” is not intended to include layers that are not part of the pixel driving circuit.

[0153] In one example, "the corresponding layer of the first pixel driving circuit and the corresponding layer of the second pixel driving circuit" refers to at least one conductive layer or at least one semiconductor material layer of the first pixel driving circuit and at least one conductive layer or at least one semiconductor material layer of the second pixel driving circuit. In a specific example, "corresponding layer" includes at least one of a semiconductor material layer and a first conductive layer.

[0154] In some embodiments, the p-type transistors of the pixel driving circuits in the first adjacent column and the pixel driving circuits in the second adjacent column are located in the same P-type well region among a plurality of P-type well regions (PWRs). For example, the p-type transistors of the first column C1 and the second column C2 are located in the same P-type well region among a plurality of P-type well regions (PWRs).

[0155] In some embodiments, the n-type transistors of the pixel driving circuits in the second adjacent column and the pixel driving circuits in the third adjacent column are located in the same N-type well region among a plurality of N-type well regions (NWRs). For example, the n-type transistors of the second column C2 and the third column C3 are located in the same N-type well region among a plurality of N-type well regions (NWRs).

[0156] In some embodiments, the active layers of the p-type transistors of the pixel driving circuits of the first adjacent column and the pixel driving circuits of the second adjacent column are located in the same P-type well region among a plurality of P-type well regions PWR. For example, the active layers of the p-type transistors of the first column C1 and the second column C2 are located in the same P-type well region among a plurality of P-type well regions PWR.

[0157] In some embodiments, the active layers of the n-type transistors of the pixel driving circuits in the second adjacent column and the pixel driving circuits in the third adjacent column are located in the same N-type well region among a plurality of N-type well regions (NWRs). For example, the active layers of the n-type transistors in the second column C2 and the third column C3 are located in the same N-type well region among a plurality of N-type well regions (NWRs).

[0158] In some embodiments, the gates of the p-type transistors of the pixel driving circuits in the first adjacent column and the second adjacent column are located in the same P-type well region among a plurality of P-type well regions PWR. For example, the gates of the p-type transistors in the first column C1 and the second column C2 are located in the same P-type well region among a plurality of P-type well regions PWR.

[0159] In some embodiments, the gates of the n-type transistors of the pixel driving circuits in the second adjacent column and the pixel driving circuits in the third adjacent column are located in the same N-type well region among a plurality of N-type well regions NWR. For example, the gates of the n-type transistors in the second column C2 and the third column C3 are located in the same N-type well region among a plurality of N-type well regions NWR.

[0160] In some embodiments, the fourth and sixth transistors of a row pixel driving circuit are arranged in the same row. In some embodiments, the fifth transistor of a row pixel driving circuit is arranged in the same row. In some embodiments, the second transistor of a row pixel driving circuit is arranged in the same row. In some embodiments, the driving transistors of a row pixel driving circuit are arranged in the same row.

[0161] In some embodiments, the active layers of the fourth and sixth transistors of a row pixel driving circuit are arranged in the same row. In some embodiments, the active layer of the fifth transistor of a row pixel driving circuit is arranged in the same row. In some embodiments, the active layers of the second transistor of a row pixel driving circuit are arranged in the same row. In some embodiments, the active layers of the driving transistors of a row pixel driving circuit are arranged in the same row.

[0162] In some embodiments, the gates of the fourth and sixth transistors of a row pixel driving circuit are arranged in the same row. In some embodiments, the gates of the fifth transistor of a row pixel driving circuit are arranged in the same row. In some embodiments, the gates of the second transistor of a row pixel driving circuit are arranged in the same row. In some embodiments, the gates of the driving transistors of a row pixel driving circuit are arranged in the same row.

[0163] Various suitable semiconductor materials can be used to fabricate semiconductor material layers. Examples of semiconductor materials used to fabricate semiconductor material layers include silicon-based semiconductor materials such as polycrystalline silicon, monocrystalline silicon, and amorphous silicon.

[0164] Various suitable semiconductor materials can be used to fabricate the first conductive layer. Examples of semiconductor materials used to fabricate the first conductive layer include silicon-based semiconductor materials such as polycrystalline silicon, monocrystalline silicon, and amorphous silicon.

[0165] The inventors of this disclosure have discovered that the spacing between gates is a key factor limiting the reduction of pixel pitch. To address this limitation, an interleaved arrangement of gates is implemented. This interleaved arrangement minimizes interference between gates and optimizes their spacing.

[0166] In some embodiments, at least two gates of at least two p-type transistors have different heights relative to the surface of the semiconductor material layer. In some embodiments, the gate GE2 of the second transistor M2 has a first height relative to the surface of the active layer ACT2 of the second transistor M2; the gate GE5 of the fifth transistor M5 has a first height relative to the surface of the active layer ACT5 of the fifth transistor M5; wherein the first height is greater than a second height. In a particular example, the gate GE2 of the second transistor M2 includes an upper polysilicon layer, and the gate GE5 of the fifth transistor M5 includes a lower polysilicon layer. The staggered design also reduces the total area required for polysilicon connections, especially when the contact points cause portions of the polysilicon to extend outward. By offsetting these extensions, the layout achieves better space efficiency. The inventors of this disclosure have found that this structure saves layout space and increases pixel density (PPI) by allowing for tighter packaging of components within the pixel circuitry. It ensures efficient use of space without compromising the functionality or connectivity of the gate structure.

[0167] Figure 20G The diagram shows contact holes for connecting electrodes (e.g., gate, first electrode, second electrode, and back gate electrode) to a semiconductor material layer in a portion of an array substrate.

[0168] Figure 20H It is shown Figure 20A A schematic diagram of the structure of the first signal line layer in a portion of the array substrate depicted in the figure. Figure 20I It is shown Figure 20A A schematic diagram of the structure of the first insulating layer in the array substrate portion depicted in the diagram. Figure 20J It is shown Figure 20A A schematic diagram of the structure of the second signal line layer in a portion of the array substrate depicted in the figure. Figure 20K It is shown Figure 20A A schematic diagram of the structure of the second insulating layer in a portion of the array substrate depicted in the figure. Figure 20L It is shown Figure 20A A schematic diagram of the structure of the third signal line layer in a portion of the array substrate depicted in the figure. Figure 20M It is shown Figure 20A A schematic diagram of the structure of the third insulating layer in the array substrate portion depicted in the diagram. Figure 20N It is shown Figure 20A A schematic diagram of the structure of the fourth signal line layer in a portion of the array substrate depicted in the image. Figure 200 It is shown Figure 20A A schematic diagram of the structure of the first electrode layer in a portion of the array substrate depicted in the figure. Figure 20P It is shown Figure 20A A schematic diagram of the structure of the fourth insulating layer in a portion of the array substrate depicted in the figure. Figure 20Q It is shown Figure 20AA schematic diagram of the structure of the second electrode layer in a portion of the array substrate depicted in the figure. Figure 20R It is shown Figure 20A A schematic diagram of the structure of the third electrode layer in a portion of the array substrate depicted in the image. Figure 20S It is shown Figure 20A A schematic diagram of the structure of the fifth insulating layer in a portion of the array substrate depicted in the diagram.

[0169] Reference Figure 20H In some embodiments, the first signal line layer includes multiple gate lines. In one example, the multiple gate lines include a second gate line G2. <1> It is configured to provide a gate drive signal to the second transistor in the first row pixel driving circuit; the fourth gate line G4 <1> It is configured to provide a gate drive signal to the fourth transistor in the first row pixel driving circuit; the fifth gate line G5 <1> It is configured to provide a gate drive signal to the fifth transistor in the first row pixel driving circuit; the sixth gate line G6 <1> It is configured to provide a gate drive signal to the sixth transistor in the first row pixel driving circuit; the second gate line G2 <2> It is configured to provide a gate drive signal to the second transistor in the second row pixel driving circuit; the fourth gate line G4 <2> It is configured to provide a gate drive signal to the fourth transistor in the second row pixel driving circuit; the fifth gate line G5 <2> It is configured to provide a gate drive signal to the fifth transistor in the second row pixel driving circuit; the sixth gate line G6 <2> It is configured to provide a gate drive signal to the sixth transistor in the second row pixel driving circuit; the second gate line G2 <3> It is configured to provide a gate drive signal to the second transistor in the third row pixel driving circuit; the fourth gate line G4 <3> It is configured to provide a gate drive signal to the fourth transistor in the third row pixel driving circuit; the fifth gate line G5 <3> It is configured to provide a gate drive signal to the fifth transistor in the third row pixel driving circuit; the sixth gate line G6 <3> It is configured to provide a gate drive signal to the sixth transistor in the third row pixel driving circuit; the second gate line G2 <4> It is configured to provide a gate drive signal to the second transistor in the fourth row pixel driving circuit; the fourth gate line G4 <4> It is configured to provide a gate drive signal to the fourth transistor in the fourth row pixel driving circuit; the fifth gate line G5 <4> It is configured to provide a gate drive signal to the fifth transistor in the fourth row pixel driving circuit; and the sixth gate line G6 <4> It is configured to provide a gate drive signal to the sixth transistor in the fourth row pixel drive circuit.

[0170] Figure 20I A via extending through the first insulating layer is shown. The second signal line layer is connected to the first signal line layer through the via extending through the first insulating layer.

[0171] Reference Figure 20JIn some embodiments, the second signal line layer includes at least one branch of the reset voltage line VREF, at least one branch of the initialization voltage line VINI, and at least one branch of the first power line ELVDD.

[0172] Figure 20K A via extending through the second insulating layer is shown. The third signal line layer is connected to the second signal line layer via the via extending through the second insulating layer.

[0173] Reference Figure 20L In some embodiments, the third signal line layer includes at least one branch of the reset voltage line VREF, at least one branch of the initialization voltage line VINI, and a plurality of data lines DL configured to provide pixel data signals (e.g., offset voltage signals or data signals) to a multi-column pixel driving circuit.

[0174] Figure 20M A via extending through the third insulating layer is shown. The fourth signal line layer is connected to the third signal line layer via a via extending through the third insulating layer.

[0175] Reference Figure 20N In some embodiments, the fourth signal line layer includes at least one branch of the reset voltage line VREF, at least one branch of the initialization voltage line VINI, at least one branch of the first power line ELVDD, and the first capacitor electrode Ce1-1 of the first capacitor.

[0176] Reference Figure 200 In some embodiments, the first electrode layer includes the second capacitor electrode Ce1-2 of the first capacitor.

[0177] Figure 20P A via extending through the fourth insulating layer is shown. The fifth signal layer is connected to the fourth signal layer via a via extending through the fourth insulating layer.

[0178] Reference Figure 20Q In some embodiments, the second electrode layer includes at least one branch of the first power line ELVDD and the first capacitor electrode Ce2-1 of the second capacitor.

[0179] Reference Figure 20R In some embodiments, the third electrode layer includes the second capacitor electrode Ce2-2 of the second capacitor.

[0180] Figure 20S The vias extending through the fifth insulating layer are shown. The fifth signal line layer is connected to the touch electrode layer vias extending through the fourth insulating layer.

[0181] Reference Figure 7 , Figure 8 , Figure 15 , Figures 20A to 20S and Figure 21 In some embodiments, the second electrode Dd of the driving transistor MD is electrically connected to the second electrode D4 of the fourth transistor M4. In some embodiments, the active layers of the fourth transistor and the driving transistor in the same column of pixel driving circuit are part of an integral structure. The second electrode Dd of the driving transistor MD and the second electrode D4 of the fourth transistor M4 are part of an integral structure, and are located between the active layer ACT4 of the fourth transistor M4 and the active layer ACTd of the driving transistor MD in the integral structure. Figure 22 This is an enlarged view of a portion of an array substrate according to some embodiments of the present disclosure. (Refer to...) Figure 22 The second electrode Dd of the driving transistor MD and the second electrode D4 of the fourth transistor M4 are directly connected to each other and are part of the overall structure.

[0182] In some embodiments, the second electrode Dd of the driving transistor MD is electrically connected to the first electrode S5 of the fifth transistor M5. In some embodiments, the second electrode Dd of the driving transistor MD is electrically connected to the first electrode S5 of the fifth transistor M5 through the first capacitor electrode Ce1-1 of the first storage capacitor C1. Figure 23 This is an enlarged view of a portion of an array substrate according to some embodiments of the present disclosure. (Refer to...) Figure 22 and Figure 23 The second electrode Dd of the driving transistor MD and the second electrode D4 of the fourth transistor M4 are electrically connected to the first electrode S5 of the fifth transistor M5 through the first capacitor electrode Ce1-1 of the first storage capacitor C1. In some embodiments, the array substrate further includes a first connection line Cl1. The first connection line Cl1 is connected to the first capacitor electrode Ce1-1 of the first storage capacitor C1 and to the first electrode S5 of the fifth transistor M5. Optionally, the first connection line Cl1 is located in the first signal line layer. In some embodiments, the array substrate further includes a relay electrode RE. The first capacitor electrode Ce1-1 of the first storage capacitor C1 is connected to the relay electrode RE, and the relay electrode RE is connected to the second electrode Dd of the driving transistor MD and the second electrode D4 of the fourth transistor M4. Optionally, the relay electrode RE is located in the first signal line layer.

[0183] The inventors of this disclosure have discovered that the structure of the array substrate of this disclosure minimizes the number of interconnections between the second electrode Dd of the driving transistor MD, the second electrode D4 of the fourth transistor M4, and the first electrode S5 of the fifth transistor M5, thereby reducing parasitic capacitance and interference resistance.

[0184] In some embodiments, the second electrode D5 of the fifth transistor M5 is electrically connected to the second electrode D6 of the sixth transistor M6. In some embodiments, the array substrate further includes a second connection line Cl2. The second connection line Cl2 is connected to the second electrode D5 of the fifth transistor M5 and to the second electrode D6 of the sixth transistor M6.

[0185] In some embodiments, the orthographic projection of the second connection line Cl2 on the substrate does not overlap with the orthographic projection of any of the plurality of gate lines on the substrate.

[0186] The inventors of this disclosure have discovered that the structure of the array substrate according to this disclosure minimizes the number of interconnections between the second electrode D5 of the fifth transistor M5 and the second electrode D6 of the sixth transistor M6, thereby reducing parasitic capacitance and interference resistance.

[0187] Figure 24 This is an enlarged view of a portion of an array substrate according to some embodiments of the present disclosure. (Refer to...) Figure 24 The gate of the fifth transistor in two adjacent pixel driving circuits is part of the first integrated structure; and the gate of the second transistor in two adjacent pixel driving circuits is part of the second integrated structure. The first integrated structure is connected to the fifth gate line G5. The second integrated structure is connected to the second gate line G2.

[0188] In some embodiments, the fifth transistors of two adjacent columns of pixel driving circuits have a substantially mirror-symmetric relationship with each other, for example, with respect to a plane perpendicular to the main surface of the array substrate and substantially parallel to the second direction DR2 (e.g., at least 80%, at least 85%, at least 90%, at least 95%, at least 98%, at least 99%, or completely symmetrical); and the second transistors of two adjacent columns of pixel driving circuits have a substantially mirror-symmetric relationship with each other, for example, with respect to a plane perpendicular to the main surface of the array substrate and substantially parallel to the second direction DR2 (e.g., at least 80%, at least 85%, at least 90%, at least 95%, at least 98%, at least 99%, or completely symmetrical).

[0189] The inventors of this disclosure have discovered that by placing the fifth transistor and the second transistor very close together, the number of N-well (NW) regions can be reduced, thereby minimizing the spacing constraints between the N-well and P-well regions and thus having a positive impact on pixel density (PPI).

[0190] Figure 25 This is an enlarged view of a portion of an array substrate according to some embodiments of the present disclosure. (Refer to...) Figure 24 and Figure 25In some embodiments, the orthographic projection of the initialization voltage line VINI onto the substrate spaced apart from the orthographic projections of the active layers of the second transistors of two adjacent columns of pixel driving circuits onto the substrate. In some embodiments, the orthographic projection of the initialization voltage line VINI onto the substrate spaced apart from the orthographic projections of the active layers of the fifth transistors of two adjacent columns of pixel driving circuits onto the substrate.

[0191] The inventors of this disclosure have discovered that by making the fifth transistors of two adjacent pixel driving circuits share the same gate, and by making the second transistors of two adjacent pixel driving circuits share the same gate, the two data lines configured to provide pixel data signals to the two adjacent pixel driving circuits are very close together, thereby increasing the risk of crosstalk between the data lines. Simply increasing the distance between them to reduce crosstalk results in uneven load and affects the first storage capacitor C1 and the second storage capacitor C2. The inventors of this disclosure have discovered that by setting an initialization voltage line VINI between the two data lines, crosstalk between the two data lines can be reduced, minimizing crosstalk without compromising layout efficiency.

[0192] In some embodiments, the active layers of the fourth transistor and the driving transistor in the same column of pixel driving circuits are part of the overall structure. The second electrode Dd of the driving transistor MD and the second electrode D4 of the fourth transistor M4 are part of the overall structure, and are located between the active layer ACT4 of the fourth transistor M4 and the active layer ACTd of the driving transistor MD in the overall structure. Figure 22 This is an enlarged view of a portion of an array substrate according to some embodiments of the present disclosure. (Refer to...) Figure 22 The second electrode Dd of the driving transistor MD and the second electrode D4 of the fourth transistor M4 are directly connected to each other and are part of the overall structure.

[0193] Figure 26 This is an enlarged view of a portion of a semiconductor material layer in an array substrate according to some embodiments of the present disclosure. (Refer to...) Figure 26 The fourth transistor, located in the same column of the pixel driving circuit and in two adjacent rows of the pixel driving circuit, is part of the active layer of the driving transistor as an integral structure.

[0194] Figure 27 This is an enlarged view of a portion of an array substrate according to some embodiments of the present disclosure. (Refer to...) Figure 27In some embodiments, the N+ pickup active region NAA is connected to the first electrode of the sixth transistor in two adjacent columns of pixel driving circuits. In some embodiments, the array substrate further includes a third connection line Cl3. The third connection line Cl3 is connected to the N+ pickup active region NAA and to the first electrode of the sixth transistor in two adjacent columns of pixel driving circuits. The N+ pickup active region NAA is configured to provide an initialization voltage signal (e.g., from the initialization voltage line VINI) to the first electrode of the sixth transistor in two adjacent columns of pixel driving circuits. The inventors of this disclosure have found that the structure of the array substrate reduces the complexity of the pickup voltage connection, making the layout more efficient and minimizing wiring difficulty.

[0195] Figure 28 This is an enlarged view of a portion of an array substrate according to some embodiments of the present disclosure. (Refer to...) Figure 28 In some embodiments, the P+ pickup active region PAA is connected to the first electrode of the driving transistor in the adjacent two rows of pixel driving circuits. In some embodiments, the array substrate further includes a fourth connection line Cl4. The fourth connection line Cl4 is connected to the P+ pickup active region PAA and to the first electrode of the driving transistor in the adjacent two rows of pixel driving circuits. The P+ pickup active region PAA is configured to provide a first power signal (e.g., from a first power line ELVDD) to the first electrode of the driving transistor in the adjacent two rows of pixel driving circuits. The inventors of this disclosure have found that the structure of the array substrate reduces the complexity of the pickup voltage connection, making the layout more efficient and minimizing the wiring difficulty.

[0196] Figure 29 This is an enlarged view of a portion of an array substrate according to some embodiments of the present disclosure. (Refer to...) Figure 29 In some embodiments, the array substrate further includes a first node connection line Cln1. In some embodiments, the first node connection line Cln1 is connected to the second electrode D2 of the second transistor and to the gate Gd of the driving transistor (which serves as the second capacitor electrode of the first capacitor).

[0197] In some embodiments, the first node connection line Cln1 is connected to the second electrode D2 of the second transistor through one or more first vias v1, and to the gate Gd of the driving transistor (which serves as the second capacitor electrode of the first capacitor) through one or more second vias v2. In some embodiments, the first node connection line Cln1 is located in the first signal line layer.

[0198] Figure 30 This is an enlarged view of a portion of an array substrate according to some embodiments of the present disclosure. (Refer to...) Figure 29 and Figure 30In some embodiments, the array substrate further includes an anti-interference block IPB. In some embodiments, the anti-interference block IPB is configured to receive a constant voltage signal. In one example, the anti-interference block IPB is configured to receive a first power signal, for example, from a first power line. In some embodiments, the anti-interference block IPB is connected to the first electrode Sd of the driving transistor.

[0199] In some embodiments, the orthographic projection of the anti-interference block IPB on the substrate spaced apart from the orthographic projections of one or more first vias v1 on the substrate and one or more second vias v2 on the substrate. The orthographic projection of the anti-interference block IPB on the substrate at least partially overlaps with the orthographic projection of the gate Gd of the driving transistor on the substrate. The orthographic projection of the anti-interference block IPB on the substrate at least partially overlaps with the orthographic projection of the active layer ACTd of the driving transistor on the substrate.

[0200] In some embodiments, the orthographic projection of the anti-interference block IPB on the substrate does not overlap with the orthographic projection of one or more second vias v2 on the substrate. The orthographic projection of the anti-interference block IPB on the substrate does not overlap with the orthographic projection of one or more first vias v1 on the substrate. In some embodiments, the anti-interference block IPB is located on a third signal line layer.

[0201] The inventors of this disclosure have discovered that, because the gate of the driving transistor is floating during the light-emitting phase, the potential at the gate of the driving transistor is easily affected by interference from other signals in the array substrate, leading to instability in the output current or voltage. In particular, crosstalk between the gate of the driving transistor and the data line is the main cause of vertical (V-direction) crosstalk.

[0202] The inventors of this disclosure have discovered that by spacing one or more first vias v1 and one or more second vias v2 as far apart as possible, crosstalk between the gate of the driving transistor and the first electrode S2 of the second transistor (connected to the data line) can be reduced. The anti-interference block IPB further reduces crosstalk between the gate of the driving transistor and the data line. This also increases the capacitance of the first storage capacitor C1, thereby improving stability.

[0203] Figure 31 This is an enlarged view of a portion of an array substrate according to some embodiments of the present disclosure. Figure 32This is a schematic diagram illustrating a corresponding pixel driving circuit according to some embodiments of the present disclosure. In some embodiments, on all sides, the orthographic projection of the corresponding pixel driving circuit RPDC on the substrate is at least partially surrounded by the orthographic projection of the signal line on the substrate. In some embodiments, on the first side S1 of the corresponding pixel driving circuit RPDC, the orthographic projection of the corresponding pixel driving circuit RPDC on the substrate is at least partially surrounded by the orthographic projections of one or more signal lines on the substrate; on the second side S2 of the corresponding pixel driving circuit RPDC, the orthographic projection of the corresponding pixel driving circuit RPDC on the substrate is at least partially surrounded by the orthographic projections of one or more signal lines on the substrate; on the third side S3 of the corresponding pixel driving circuit RPDC, the orthographic projection of the corresponding pixel driving circuit RPDC on the substrate is at least partially surrounded by the orthographic projections of one or more signal lines on the substrate; on the fourth side S4 of the corresponding pixel driving circuit RPDC, the orthographic projection of the corresponding pixel driving circuit RPDC on the substrate is at least partially surrounded by the orthographic projections of one or more signal lines on the substrate; wherein the first side S1 is opposite to the second side S2, the third side S3 is opposite to the fourth side S4, the third side S3 connects the first side S1 to the second side S2, and the fourth side S4 connects the first side S1 to the second side S2.

[0204] In some embodiments, one or more signal lines located on the first side S1, one or more signal lines located on the second side S2, one or more signal lines located on the third side S3, and one or more signal lines located on the fourth side S4 are configured to provide one or more constant voltage signals.

[0205] In a specific example, on the first side S1 of the corresponding pixel driving circuit RPDC, the orthographic projection of the corresponding pixel driving circuit RPDC on the substrate is at least partially surrounded by the orthographic projection of at least a portion of the first power line ELVDD on the substrate; on the second side S2 of the corresponding pixel driving circuit RPDC, the orthographic projection of the corresponding pixel driving circuit RPDC on the substrate is at least partially surrounded by the orthographic projection of the reset voltage line VREF on the substrate; on the third side S3 of the corresponding pixel driving circuit RPDC, the orthographic projection of the corresponding pixel driving circuit RPDC on the substrate is at least partially surrounded by the orthographic projection of at least a portion of the first power line ELVDD on the substrate; on the fourth side S4 of the corresponding pixel driving circuit RPDC, the orthographic projection of the corresponding pixel driving circuit RPDC on the substrate is at least partially surrounded by the orthographic projection of the initialization voltage line VINI on the substrate; wherein the first side S1 is opposite to the second side S2, the third side S3 is opposite to the fourth side S4, the third side S3 connects the first side S1 to the second side S2, and the fourth side S4 connects the first side S1 to the second side S2. In one example, the first power line ELVDD, the reset voltage line VREF, and the initialization voltage line VINI are located on the second signal line layer. The first power line ELVDD is configured to provide a first power signal. The reset voltage line VREF is configured to provide a reset voltage signal. The initialization voltage line VINI is configured to provide an initialization voltage signal.

[0206] The inventors of this disclosure have discovered that the structure of the array substrate disclosed herein can effectively prevent interference between adjacent pixel driving circuits.

[0207] In some embodiments, at least one of the first power line ELVDD, the reset voltage line VREF, and the initialization voltage line VINI includes a grid line. The inventors of this disclosure have discovered that by making the first power line ELVDD, the reset voltage line VREF, and the initialization voltage line VINI into grid lines, the impedance of these signal lines can be reduced.

[0208] In some embodiments, at least one of the first power line ELVDD, the reset voltage line VREF, and the initialization voltage line VINI includes a multi-layered grid line. The inventors of this disclosure have discovered that by providing a multi-layered grid line, the impedance of the signal lines can be further reduced, thereby ensuring stable power delivery and minimizing voltage drop.

[0209] Figure 33 This is a schematic diagram illustrating a first connection line and a second connection line in an array substrate according to some embodiments of the present disclosure. (Refer to...) Figure 23 and Figure 33In some embodiments, the length of the first connection line Cl1 is less than the length of the second connection line Cl2. In some embodiments, the second connection line Cl2 includes: a first connection portion CP1 extending along a first direction DR1; a second connection portion CP2 extending along a second direction DR2 toward a gate line connected to the gate G6 of the sixth transistor M6; and a third connection portion CP3 extending along the first direction DR1. Optionally, the second connection portion CP2 is connected to the first connection portion CP1 and to the third connection portion CP3.

[0210] In some embodiments, the third connection portion CP3 is spaced from the gate GE5 of the fifth transistor M5 by a first shortest distance d1; the first connection line Cl1 is spaced from the gate GE5 of the fifth transistor M5 by a second shortest distance d2; the second connection portion CP2 is spaced from the gate GE5 of the fifth transistor M5 by a third shortest distance d3; and the first connection portion CP1 is spaced from the gate GE6 of the sixth transistor M6 by a fourth shortest distance d4. Optionally, the first shortest distance d1 is greater than the second shortest distance d2. Optionally, the third shortest distance d3 is greater than the second shortest distance d2. Optionally, the fourth shortest distance d4 is greater than the second shortest distance d2.

[0211] In some embodiments, refer to Figure 15 The fourth transistor M4 and the sixth transistor M6 have approximately the same aspect ratio and are arranged side-by-side to save layout space. The second transistor M2 and the fifth transistor M5 have approximately the same aspect ratio and are also arranged side-by-side to save layout space. The arrangement direction of the fourth transistor M4 and the sixth transistor M6 intersects the arrangement direction of the second transistor M2 and the fifth transistor M5 at a 90° angle. The fifth transistor M5 is arranged side-by-side with the fifth transistor M5 of the adjacent sub-pixel, and its arrangement direction is the same as that of the fourth transistor M4 and the sixth transistor M6.

[0212] In some embodiments, refer to Figure 22 The gate GE4 of the fourth transistor is connected to the corresponding gate line through the first connection via cv1, and the gate G6 of the sixth transistor is connected to the corresponding gate line through the second connection via cv2. The positions of the first connection via cv1 and the second connection via cv2 relative to the corresponding gate are different from each other.

[0213] In some embodiments, refer to Figure 24 The gate GE5 of the fifth transistor is connected to the corresponding gate line through the third connection via cv3, and the gate GE2 of the second transistor is connected to the corresponding gate line through the fifth connection via cv5. The via positions of the third connection via cv3 and the fifth connection via cv5 relative to the corresponding gate are different from each other.

[0214] On the other hand, this disclosure provides a display device including a plurality of pixel driving circuits. The plurality of pixel driving circuits include pixel driving circuits described herein or manufactured using methods described herein. The display device also includes a plurality of light-emitting elements respectively connected to the plurality of pixel driving circuits. Examples of suitable display devices include, but are not limited to, electronic paper, mobile phones, tablet computers, televisions, monitors, laptop computers, digital photo albums, GPS, etc. Optionally, the display device is an organic light-emitting diode (OLED) display device. Optionally, the display device is a miniature OLED display device. Optionally, the display device is a miniature OLED display device. Optionally, the display device is a quantum dot display device.

[0215] In some embodiments, the plurality of pixel driving circuits include a plurality of pixel driving circuits located in the same row and respectively in a plurality of columns. Optionally, each pixel driving circuit in the plurality of pixel driving circuits in the same row and a plurality of columns includes a driving transistor, a first storage capacitor, a second storage capacitor, a second transistor, and a fifth transistor. Optionally, the display device further includes a first transistor having a second electrode connected to a first electrode of the driving transistor in the plurality of pixel driving circuits in the same row and a plurality of columns.

[0216] On the other hand, the present invention provides a method for manufacturing a pixel driving circuit. In some embodiments, the method includes: forming a plurality of pixel driving circuits. Optionally, forming each pixel driving circuit in the plurality of pixel driving circuits includes: forming a driving transistor having a gate connected to a first node, a first electrode configured to receive a first power supply signal, and a second electrode connected to a second node; forming a second transistor having a gate connected to a second gate line, a first electrode connected to a corresponding data line for receiving pixel data signals, and a second electrode connected to the first node; forming a fourth transistor having a gate connected to a fourth gate line, a first electrode connected to a reset voltage line, and a second electrode connected to the second node; forming a fifth transistor having a gate connected to a fifth gate line, a first electrode connected to the second node, and a second electrode coupled to the anode of a light-emitting element; forming a sixth transistor having a gate connected to a sixth gate line, a first electrode connected to an initialization voltage line, and a second electrode connected to the anode of a light-emitting element; and forming a first storage capacitor having a first capacitor electrode connected to the second node and a second capacitor electrode connected to the first node. Optionally, the second electrode of the driving transistor and the second electrode of the fourth transistor are directly connected to each other and are part of an overall structure. Optionally, the method further includes: forming a first interconnect line. Optionally, the first connection line is connected to the first capacitor electrode of the first storage capacitor and also to the first electrode of the fifth transistor. Optionally, the first capacitor electrode of the first storage capacitor is electrically connected to the second electrode of the driving transistor and the second electrode of the fourth transistor. Optionally, the first connection line is located on a different layer from the first capacitor electrode of the first storage capacitor and also on a different layer from the first electrode of the fifth transistor.

[0217] For illustrative and descriptive purposes, the foregoing description of embodiments of the invention has been provided. It is not exhaustive, nor is it intended to limit the invention to the precise forms or exemplary embodiments disclosed. Therefore, the foregoing description should be considered illustrative rather than restrictive. Clearly, many modifications and variations will be apparent to those skilled in the art. The embodiments were chosen and described to explain the principles of the invention and its best mode of practical application, thereby enabling those skilled in the art to understand the various embodiments of the invention and the various modifications suitable for the particular use or implementation contemplated. The scope of the invention is intended to be defined by the appended claims and their equivalents, wherein, unless otherwise stated, all terms are to be interpreted in their broadest reasonable sense. Therefore, the terms “the invention,” “the present invention,” etc., do not necessarily limit the scope of the claims to specific examples, and references to exemplary embodiments of the invention do not imply limitation of the invention, nor should such limitation be inferred. The invention is defined only by the spirit and scope of the appended claims. Furthermore, these claims may involve the use of “first,” “second,” etc., followed by nouns or elements. These terms should be understood as nomenclature and should not be construed as limiting the number of elements modified by these nomenclatures unless a specific number has been given. Any advantages and benefits described may not apply to all embodiments of the invention. It should be understood that changes to the described embodiments can be made by those skilled in the art without departing from the scope of the invention as defined by the appended claims. Furthermore, the elements and components in this disclosure are not intended for public distribution, whether or not they are expressly recited in the appended claims.

Claims

1. An array substrate comprising multiple pixel driving circuits; wherein Each pixel driving circuit in the plurality of pixel driving circuits includes: A driving transistor having a gate connected to a first node, a first electrode configured to receive a first power supply signal, and a second electrode connected to a second node; The second transistor has a gate connected to a second gate line, a first electrode connected to a corresponding data line for receiving pixel data signals, and a second electrode connected to the first node. The fifth transistor has a gate connected to the fifth gate line, a first electrode connected to the second node, and a second electrode coupled to the anode of the light-emitting element; A first storage capacitor having a first capacitor electrode connected to the second node and a second capacitor electrode connected to the first node; and The second storage capacitor has a first capacitor electrode connected to the second node and a second capacitor electrode connected to the second power line. The array substrate further includes a first connecting line and a second connecting line; The first connection line is connected to the first capacitor electrode of the first storage capacitor and to the first electrode of the fifth transistor. The first capacitor electrode of the first storage capacitor is electrically connected to the second electrode of the driving transistor; and The first connection line is located on a different layer from the first capacitor electrode of the first storage capacitor, and also on a different layer from the first electrode of the fifth transistor; The second connection line is connected to the second electrode of the fifth transistor and also to the second electrode of the sixth transistor; and The second connection line is located on a different layer from the second electrode of the fifth transistor and the second electrode of the sixth transistor; The length of the first connecting line is less than the length of the second connecting line.

2. The array substrate according to claim 1 further includes relay electrodes; wherein The first capacitor electrode of the first storage capacitor is connected to the relay electrode; and The relay electrode is connected to the second electrode of the driving transistor and the second electrode of the fourth transistor.

3. The array substrate according to claim 1, wherein, Each pixel driving circuit also includes: A fourth transistor has a gate connected to a fourth gate line, a first electrode connected to a reset voltage line, and a second electrode connected to the second node; and A sixth transistor having a gate connected to a sixth gate line, a first electrode connected to an initialization voltage line, and a second electrode connected to the anode of the light-emitting element; The second electrode of the driving transistor and the second electrode of the fourth transistor are directly connected to each other and are part of the overall structure. The first capacitor electrode of the first storage capacitor is electrically connected to the second electrode of the fourth transistor; and The second connection line is connected to the second electrode of the sixth transistor.

4. The array substrate according to claim 3, wherein, The orthographic projection of the second connecting line on the substrate does not overlap with the orthographic projection of any of the multiple gate lines on the substrate.

5. The array substrate according to any one of claims 1 to 4, wherein, The gate of the fifth transistor in two adjacent pixel driving circuits is part of the first integral structure; and the gate of the second transistor in the two adjacent pixel driving circuits is part of the second integral structure. The array substrate further includes a fifth gate line and a second gate line; Wherein, the first integral structure is connected to the fifth gate line; and The second integral structure is connected to the second gate line.

6. The array substrate according to claim 5, wherein, The fifth transistors of two adjacent pixel driving circuits have a substantially mirror symmetry with respect to each other about a plane that is perpendicular to the main surface of the array substrate and substantially parallel to the second direction. as well as The second transistors of two adjacent columns of pixel driving circuits have substantially mirror symmetry with respect to each other, about the plane that is perpendicular to the main surface of the array substrate and substantially parallel to the second direction.

7. The array substrate according to claim 5, further comprising an initialization voltage line; in, The orthographic projection of the initialization voltage line on the substrate will separate the orthographic projections of the active layers of the second transistors of the two adjacent pixel driving circuits on the substrate from each other. as well as The orthographic projection of the initialization voltage line onto the substrate spaced the orthographic projections of the active layers of the fifth transistors of two adjacent pixel driving circuits onto the substrate from each other.

8. The array substrate according to any one of claims 1 to 7, wherein, The active layer of the fourth transistor and the driving transistor, which are located in the same column of the pixel driving circuit and in two adjacent rows of the pixel driving circuit, is part of the overall structure.

9. The array substrate according to any one of claims 1 to 8, further comprising an N+ pickup active region, the N+ pickup active region being connected to the first electrode of the sixth transistor in two adjacent column pixel driving circuits.

10. The array substrate according to claim 9, further comprising a third connecting line; in, The third connection line is connected to the N+ pickup active region and to the first electrode of the sixth transistor in the two adjacent column pixel driving circuits; as well as The N+ pickup active region is configured to provide an initialization voltage signal to the first electrode of the sixth transistor in two adjacent column pixel driving circuits.

11. The array substrate according to any one of claims 1 to 8, further comprising a P+ pickup active region, the P+ pickup active region being connected to the first electrode of the driving transistor in the adjacent two rows of pixel driving circuits.

12. The array substrate according to claim 11, further comprising a fourth connecting line; in, The fourth connection line is connected to the P+ pickup active region and to the first electrode of the driving transistor in the adjacent two rows of pixel driving circuits; as well as The P+ pickup active region is configured to provide a first power signal to the first electrode of the driving transistor in the adjacent two rows of pixel driving circuits.

13. The array substrate according to any one of claims 1 to 12, further comprising a first node connection line; in, The first node connection line is connected to the second electrode of the second transistor through one or more first vias, and is connected to the gate of the driving transistor through one or more second vias; as well as The first node connection line is located on a different layer from the second electrode of the second transistor and on a different layer from the gate of the driving transistor.

14. The array substrate of claim 13, further comprising an anti-interference block configured to receive a constant voltage signal; in, The orthographic projection of the anti-interference block on the substrate separates the orthographic projection of the one or more first vias on the substrate from the orthographic projection of the one or more second vias on the substrate. The orthographic projection of the anti-interference block on the substrate at least partially overlaps with the orthographic projection of the gate of the driving transistor on the substrate, and at least partially overlaps with the orthographic projection of the active layer of the driving transistor on the substrate. as well as The orthographic projection of the anti-interference block on the substrate does not overlap with the orthographic projection of the one or more first vias on the substrate, and does not overlap with the orthographic projection of the one or more second vias on the substrate.

15. The array substrate according to claim 14, wherein, The anti-interference block is connected to the first electrode of the driving transistor and is configured to receive a first power signal.

16. The array substrate according to any one of claims 1 to 15, wherein, On all sides, the orthographic projection of each pixel driving circuit in the plurality of pixel driving circuits onto the substrate is at least partially surrounded by the orthographic projection of the signal lines onto the substrate.

17. The array substrate according to claim 16, wherein, On the first side of each pixel driving circuit, the orthographic projection of the corresponding pixel driving circuit on the substrate is at least partially surrounded by the orthographic projection of one or more signal lines on the substrate. On the second side of each pixel driving circuit, the orthographic projection of each pixel driving circuit on the substrate is at least partially surrounded by the orthographic projection of one or more signal lines on the substrate. On the third side of each pixel driving circuit, the orthographic projection of each pixel driving circuit on the substrate is at least partially surrounded by the orthographic projection of one or more signal lines on the substrate. as well as On the fourth side of each pixel driving circuit, the orthographic projection of each pixel driving circuit on the substrate is at least partially surrounded by the orthographic projection of one or more signal lines on the substrate. Wherein, the first side is opposite to the second side, the third side is opposite to the fourth side, the third side connects the first side to the second side, and the fourth side connects the first side to the second side.

18. The array substrate according to claim 17, wherein, The one or more signal lines located on the first side, the one or more signal lines located on the second side, the one or more signal lines located on the third side, and the one or more signal lines located on the fourth side are configured to provide one or more constant voltage signals.

19. The array substrate according to claim 16, wherein, On the first side of each pixel driving circuit, the orthographic projection of each pixel driving circuit on the substrate is at least partially surrounded by the orthographic projection of at least a portion of the first power line on the substrate. On the second side of each pixel driving circuit, the orthographic projection of each pixel driving circuit on the substrate is at least partially surrounded by the orthographic projection of the reset voltage line on the substrate. On the third side of each pixel driving circuit, the orthographic projection of each pixel driving circuit on the substrate is at least partially surrounded by the orthographic projection of at least a portion of the first power line on the substrate. as well as On the fourth side of each pixel driving circuit, the orthographic projection of each pixel driving circuit on the substrate is at least partially surrounded by the orthographic projection of the initialization voltage line on the substrate. Wherein, the first side is opposite to the second side, the third side is opposite to the fourth side, the third side connects the first side to the second side, and the fourth side connects the first side to the second side.

20. The array substrate according to claim 3, wherein, The second connecting line includes: A first connecting portion, which extends along a first direction; The second connection portion extends along a second direction toward the gate line connected to the gate of the sixth transistor; and The third connecting portion extends along the first direction; The second connecting part is connected to the first connecting part and also to the third connecting part.

21. The array substrate according to claim 20, wherein, The third connecting portion is spaced apart from the gate of the fifth transistor by a first minimum distance; The first connection line is spaced apart from the gate of the fifth transistor by a second shortest distance; The second connection portion is spaced from the gate of the fifth transistor by a third shortest distance; and The first connection portion is spaced apart from the gate of the sixth transistor by a fourth shortest distance; Wherein, at least one of the first shortest distance, the third shortest distance, or the fourth shortest distance is greater than the second shortest distance.

22. A display device comprising an array substrate according to any one of claims 1 to 21 and one or more integrated circuits connected to the array substrate.

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