Substrates including raised interconnects disposed on a die side surface to support increased interconnect density and related methods

Abstract

A plurality of surface interconnects are disposed in a surface interconnect layer on a first surface of a substrate. The surface interconnects extend between a first region and a second region. In some examples, the first region can be configured to be coupled to an integrated circuit die, and the second region can include package contacts. In the second region, a dielectric layer is disposed on the surface interconnect layer, a plurality of bump interconnects are disposed on the dielectric layer, and the bump interconnects are coupled to the surface interconnects through the dielectric layer. The bump interconnects can provide a parallel path for signals propagating through the surface interconnects between the first region and the second region. The bump interconnects can allow the surface interconnects to be narrowed and disposed on the substrate at an increased density without increasing the electrical resistance of signals propagating between the first region and the second region.

Description

[0001] Priority application

[0002] This application claims priority to U.S. Patent Application Serial No. 18 / 426,691, filed January 30, 2024, entitled “SUBSTRATES INCLUDING RAISED INTERCONNECTS DISPOSED ON A DIE-SIDE SURFACE TO SUPPORT INCREASED INTERCONNECT DENSITY AND RELATED METHODS,” the entire contents of which are incorporated herein by reference. background

[0003] I. Technical Field

[0004] The technology disclosed herein relates generally to packaging substrates, and more particularly to reducing the area occupied by interconnects on packaging substrates.

[0005] II. Background Technology

[0006] Integrated circuits (ICs) and other components provide the ubiquitous functionality of electronic devices in modern life. ICs and other components are mounted on a substrate in the form of packages to interconnect components in the circuitry and physically secure them within the electronic device. Efforts are underway to reduce the size of IC packages to increase the amount of functionality that can be assembled within electronic devices. This necessitates reducing not only the size of the ICs and other components but also the size of the package substrate on which they are mounted. However, challenges exist associated with reducing the size of the package substrate and / or the number of input / output signals on the package substrate without altering the level of functionality provided therein. For example, the peripheral area surrounding the IC on the surface of the substrate includes signal interconnects (“surface interconnects”) to couple the IC to other components and to package interconnects (e.g., solder ball / pillar interconnects) in the peripheral area. The package interconnects couple the substrate to external circuitry. As the size of the substrate decreases, the peripheral area decreases, leaving less space for the interconnects. To address this issue, the area of ​​the signal interconnects and package interconnects themselves can be reduced (e.g., made narrower), and the center-to-center spacing can also be reduced. However, making these features smaller may have consequences that also must be addressed. For example, a reduced wire width increases interconnect impedance. Summary of the Invention

[0007] The aspects disclosed in the detailed description include a substrate comprising raised interconnects disposed on a die-side surface to support increased interconnect density. A plurality of surface interconnects in a surface interconnect layer are disposed on a first surface of the substrate, which may be used in a package. The plurality of surface interconnects extend between a first region and a second region. In some examples, the first region may be configured to couple to an integrated circuit (IC) die, and the second region may include package contacts. In the second region, a dielectric layer is disposed on the surface interconnect layer, and the plurality of raised interconnects are disposed on the dielectric layer and coupled to the surface interconnects. In some examples, the plurality of raised interconnects provide parallel paths for signals propagating through the plurality of surface interconnects between the first and second regions. In some examples, the raised interconnects allow the surface interconnects to be narrowed and configured with increased interconnect density without increasing the resistance of signals propagating between the first and second regions.

[0008] In this regard, in one exemplary aspect, a substrate is disclosed. The substrate includes: a surface interconnect layer including a plurality of surface interconnects extending between a first region and a second region on a first surface; a dielectric layer disposed on the surface interconnect layer in the second region; and a raised interconnect layer disposed on the dielectric layer and including a plurality of raised interconnects coupled to the plurality of surface interconnects through the dielectric layer.

[0009] In another exemplary aspect, a package is disclosed. The package includes: a first IC die disposed in a first region of a first surface of a package substrate; a surface interconnect layer including a plurality of surface interconnects coupled to the first IC die and extending to a second region of the first surface of the package substrate; a dielectric layer disposed on the surface interconnect layer in the second region of the package substrate; and a raised interconnect layer disposed on the dielectric layer and including a plurality of raised interconnects coupled to the plurality of surface interconnects through the dielectric layer.

[0010] In another exemplary aspect, a method of manufacturing a package is disclosed. The method includes: forming a surface interconnect layer on a package substrate, the surface interconnect layer including a plurality of surface interconnects extending between a first region and a second region on a first surface of the package substrate; disposing a first IC die in the first region and coupled to the plurality of surface interconnects; forming a dielectric layer on the surface interconnect layer in the second region; and forming a raised interconnect layer on the dielectric layer and including a plurality of raised interconnects coupled to the plurality of surface interconnects through the dielectric layer. Attached Figure Description

[0011] Figure 1AIt is a plan view of a substrate, which includes a first region configured to be coupled to an integrated circuit (IC) die, a second region including surface interconnects, and a third region including package interconnects; Figure 1B It includes Figure 1A A close-up view of the second and third regions of the substrate, wherein the surface interconnects transition from a first larger size to a second smaller size; Figure 2 This is a cross-sectional side view of a first integrated circuit (IC) package, which includes an IC disposed on a package substrate and interconnects coupling the IC to a peripheral region. Figure 3 Is it like this? Figure 2 The image shows a cross-sectional side view of a packaging substrate, which includes a surface interconnect layer and a second interconnect layer coupled to the surface interconnect layer to reduce impedance; Figure 4 This is a cross-sectional side view of an exemplary IC package, which includes an IC disposed on a package substrate and a platform in a peripheral region, the platform including a raised interconnect layer coupled to the IC through a surface interconnect layer; Figure 5 This is a cross-sectional side view of an exemplary platform in the peripheral region of a package substrate, such as in... Figure 4 In this package substrate, a first raised interconnect is provided in the raised interconnect layer to provide another path parallel to the first surface interconnect, thereby reducing signal impedance; Figure 6 This is a flowchart of an exemplary manufacturing process for a substrate, which includes raised interconnect layers in a peripheral region to reduce the size of package interconnects, thereby reducing the peripheral region of the package substrate without increasing signal impedance. Figure 7 This is a cross-sectional side view of a second IC package, which includes a first IC on a first package substrate and a second substrate stacked on the first package substrate to couple the first IC to a second IC or another external circuit. Figure 8 This is a cross-sectional side view of a second exemplary IC package, which includes a second substrate for stacking a second IC on a first IC. The second substrate includes a platform in a peripheral region having (e.g., vertical) package interconnects extending from a raised interconnect layer to the second package substrate. Figure 9A and Figure 9BThese are a cross-sectional side view and a top plan view of an example IC package, which includes an IC disposed in a first region of a package substrate, a third region along the edge of the package substrate, and a raised interconnect layer in a second region between the first and third regions. Figure 10A and Figure 10B These are a cross-sectional side view and a top plan view of an example IC package, which includes a raised interconnect layer in a peripheral region extending from the edge of the IC package to the edge of the package substrate; Figure 11A and Figure 11B These are a cross-sectional side view and a top plan view of an example IC package, which includes a raised interconnect layer in a peripheral region, and a region excluding the raised interconnect layer that spaces the raised interconnect layer from the IC package. Figures 12A to 12F This is a flowchart illustrating another exemplary manufacturing process for an IC package, which includes a raised interconnect layer on a package substrate to reduce the size of the package interconnects and the area of ​​the signal interconnects without increasing impedance. The IC package includes, but is not limited to, [other examples of such processes]. Figure 4 and Figures 8 to 11B The packaging substrate and IC package in the process; Figures 13A to 13F It is based on Figures 12A to 12F An exemplary manufacturing stage during the manufacture of a package substrate, which includes a raised interconnect layer to reduce package interconnect size and signal interconnect area without increasing impedance; Figure 14 This is a block diagram of an exemplary processor-based system that may include an IC package, the IC package including a package substrate, the package substrate including a raised interconnect layer for... Figure 4 and Figures 8 to 11B And according to, but not limited to Figure 6 and Figures 12A to 12F Any exemplary manufacturing process in the exemplary manufacturing process reduces the size of the package interconnects and reduces the impedance of the signal interconnects; and Figure 15 This is a block diagram of an exemplary wireless communication device including radio frequency (RF) components. These RF components may include an IC package including a package substrate. The package substrate includes raised interconnect layers to reduce the size of package interconnects and reduce the impedance of signal interconnects coupled to the IC on the package substrate. The package substrate includes, but is not limited to, […]. Figure 4 and Figures 8 to 11B And according to, but not limited to Figure 6 and Figures 12A to 12F The packaging substrate of any exemplary manufacturing process in the exemplary manufacturing process. Detailed Implementation

[0012] Several exemplary aspects of this disclosure are described with reference to the accompanying drawings. The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any aspect described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects.

[0013] The aspects disclosed in the detailed description include a substrate comprising raised interconnects disposed on a die-side surface to support increased interconnect density. A plurality of surface interconnects in a surface interconnect layer are disposed on a first surface of the substrate, which may be used in a package. The plurality of surface interconnects extend between a first region and a second region. In some examples, the first region may be configured to couple to an integrated circuit (IC) die, and the second region may include package contacts. In the second region, a dielectric layer is disposed on the surface interconnect layer, and the plurality of raised interconnects are disposed on the dielectric layer and coupled to the surface interconnects. In some examples, the plurality of raised interconnects provide parallel paths for signals propagating through the plurality of surface interconnects between the first and second regions. In some examples, the raised interconnects allow the surface interconnects to be narrowed and configured with increased interconnect density without increasing the resistance of signals propagating between the first and second regions.

[0014] Figure 1A This is a plan view of a package substrate 100 (“substrate 100”), which includes a first region 102 configured to couple to an IC die 104 and a peripheral region including a second region 106 and a third region 107. The second region 106 includes surface interconnects 108 to electrically couple the IC die 104 to package contacts 110 in the third region 107. The second region 106 and the third region 107 may overlap each other. In this context, the term “surface interconnect” may refer to a conductive (e.g., metallic) wire or trace in an interconnect layer 112 on a surface 114 of a first side S1 of the package substrate 100, on which the IC die 104 may be attached. Surface 114 may be referred to herein as a “die-side surface” because surface 114 is configured to couple to the IC die 104. The package contact 110 may be a contact on which package interconnects (such as solder balls or column interconnects (e.g., vertical interconnects) can be disposed to electrically couple the surface interconnect 108 to an interposer (not shown) or an outer substrate of another package, which may include another IC or other component configured to couple to the IC die 104. The surface interconnect 108 may also be referred to as signal interconnect 108.

[0015] The die interconnects (not shown) (e.g., ball grid array) that couple the IC die 104 to the surface interconnects 108 in the first region 102 of the substrate 100 have a first conductor width WW1 and are arranged with a first conductor pitch WP1 (center-to-center distance), such as Figure 1B As can be seen. In contrast, different interconnect densities may exist in the peripheral region of the substrate 100 (including the second region 106) on or outside the IC die 104 to accommodate multiple surface interconnects 108 extending through the second region 106 to the third region 107. To achieve a greater interconnect density, the width of the surface interconnects 108 is reduced (narrowed) to a second conductor width WW2, and these surface interconnects are positioned closer together with a second conductor pitch (center-to-center distance) WP2. The need for increased interconnect density is exacerbated by the pressure to reduce the size of packages in electronic devices.

[0016] Figure 1B yes Figure 1A A close-up view of a portion of the packaging substrate 100, including a first region 102 and a second region 106, in which surface interconnects 108 have first dimensions (wire width WW1 and first wire pitch WP1), and in the second region, surface interconnects 108 transition to a second reduced wire width WW2 and a reduced wire pitch WP2 to achieve greater interconnect density and couple to package contacts 110 in a third region 107. That is, in order to assemble as many surface interconnects 108 and package contacts 110 as possible within a smaller area, the wire pitch and wire width are reduced in the second region 106.

[0017] The problem with reducing the conductor width without increasing the conductor height is that the cross-sectional area of ​​the conductor (e.g., surface interconnect 108) is reduced, which, in addition to increasing power consumption, may also increase impedance and slow down the speed at which signals propagate through surface interconnect 108.

[0018] Figure 2This is a cross-sectional side view of an IC package 200, which includes an IC die or chip 202 disposed on a surface 204 on a first side S1 of a package substrate 206 (“substrate 206”), and further includes a die interconnect 208 coupling the IC die 202 in a first region 210 of the package substrate 206 to a surface interconnect layer 212(1), the surface interconnect layer including a surface interconnect 214 extending from the first region 210 to a second region 216 outside the first region 210. The surface interconnect layer 212(1) is also coupled to interconnect layers 212(2)-212(3) below the surface 204, the surface including substrate interconnect 218. In this example, the surface interconnect 214 in the first interconnect layer 212(1) on the surface 204 is directly coupled to the IC die 202 by the die interconnect 208. A signal 220 generated or received in the IC die 202 propagates through the surface interconnect 214 in the interconnect layer 212(1). In addition, to reduce the impedance encountered by signal 220, surface interconnect 214 may be coupled to a corresponding substrate interconnect 218 in interconnect layer 212 (2). That is, in some examples, a substrate interconnect 218 corresponding to the surface interconnect 214 in interconnect layer 212 (1) may be present in interconnect layer 212 (2) to provide a parallel path between IC die 202 in first region 210 and second region 216, thereby reducing the resistance or impedance of signal 220.

[0019] In this example, insulating layer 222 is disposed on surface interconnect 214. Package contacts 224 are provided in interconnect layer 212(3) on the second side S2 of package substrate 206 to electrically couple IC die 202 to external circuitry.

[0020] Figure 3 This is a cross-sectional side view of a package substrate 300, which includes a surface interconnect 302 in a surface interconnect layer 304 coupled to a substrate interconnect 306 in another interconnect layer 308. The substrate interconnect 306 is used to provide a parallel path to conduct a signal 314 propagating from a first location L1 to a second location L2 through the surface interconnect 302. The package substrate 300 includes at least two vertical connections 310 and 312 (vertical interconnect vias) to electrically couple the surface interconnect 302 and the substrate interconnect 306. A first via 310 in the first location L1 and a second via 312 in the second location L2 of the package substrate 300 allow the signal 314 to propagate through both the surface interconnect 302 and the substrate interconnect 306 between the first location L1 and the second location L2, thereby increasing the conductive cross-section through which the signal 314 propagates, which reduces the impedance of the signal 314 between the first location L1 and the second location L2.

[0021] Figure 4This is a cross-sectional side view of an exemplary IC package 400, which includes an IC die 402 disposed on a surface interconnect layer 404 in a first region A1 of a first surface 406 of a package substrate 408 (“substrate 408”). The first surface 406 includes a first region A1 and a second region A2, the second region being external to and along the periphery of the first region A1. The surface interconnect layer 404 is among a plurality of interconnect layers of the package substrate 408 and includes a plurality of surface interconnects 412. The plurality of surface interconnects 412 includes a first surface interconnect 416, which is coupled to the IC die 402 and extends between the first region A1 and the second region A2 on the first surface 406 (not shown).

[0022] In an exemplary aspect, the IC package 400 further includes a dielectric layer 410 disposed on a surface interconnect layer 404 in a second region A2 of the first surface 406. The dielectric layer 410 is not disposed in the first region. A raised interconnect layer 414 including a plurality of raised interconnects 417 is disposed on the dielectric layer 410. The plurality of raised interconnects 417 are coupled to a plurality of surface interconnects 412 through the dielectric layer 410. A first surface interconnect 416 may extend from a first location LOC1 in the second region A2 to a second location LOC2 in the second region A2. The raised interconnect layer 414 includes a first raised interconnect 418, which is coupled to the first surface interconnect 416 in the first location LOC1 and also in the second location LOC2. For example, the package substrate 408 may include vias 420 and 422 in the first location LOC1 and the second location LOC2, respectively, wherein each of the vias 420 and 422 electrically couples the first raised interconnect 418 to the first surface interconnect 416.

[0023] The package substrate 408 includes substrate interconnect layers 424(1) and 424(2). Each of the surface interconnect layer 404, the raised interconnect layer 414, and the substrate interconnect layers 424(1) and 424(2) is a conductive layer that can be formed of a metal, such as copper or other suitable material. The substrate interconnect layer 424(1) may also include a substrate interconnect 426 corresponding to the first surface interconnect 416 to provide a parallel electrical path from a first location LOC1 to a second location LOC2. In this context, "parallel" does not mean that the paths take the same route, but that they are both connected to the first location LOC1 and the second location LOC2. The substrate interconnect 426 may provide a path for a signal 428 propagating from the first location LOC1 to the second location LOC2, wherein such a path is provided in addition to the first surface interconnect 416 to reduce signal impedance compared to the first surface interconnect 416 alone.

[0024] However, as manufacturers reduce package size, they reduce the area of ​​the package substrate 408, which may include reducing the size of the second region A2 without necessarily reducing the size of the first region A1. Therefore, the density of the plurality of surface interconnects 412 increases from the first region A1 to the second region A2. To achieve this increased density, the width of the plurality of surface interconnects 412 is reduced (making them narrower), and the plurality of surface interconnects are arranged in the second region A2 with a smaller center-to-center distance (e.g., ...). Figure 1B (As shown). For example, this reduction in width (without increasing height) results in an increase in the impedance of the signal 428 propagating through the first surface interconnect 416. In this example, the substrate interconnect 426 provides a first path parallel to the first surface interconnect 416 to reduce the impedance of the signal 428. Additionally, the first raised interconnect 418 in the raised interconnect layer 414 provides a second parallel path to achieve a further reduction in impedance, taking into account further reductions in interconnect dimensions (e.g., wire widths) in future generations of technology. Therefore, as referenced... Figure 1B As described, the first center-to-center distance or spacing WP1 between two adjacent surface interconnects 412 in the first region A1 is greater than the second center-to-center distance (spacing) WP2 between two adjacent surface interconnects 412 in the second region A2. Additionally, the first interconnect width (e.g., wire width) IW1 of the multiple surface interconnects 412 in the first region A1 is greater than the second width IW2 of the multiple surface interconnects 412 in the second region A2.

[0025] Figure 5 This is a cross-sectional side view of an exemplary package substrate 500 having a raised interconnect layer 504, which includes a first raised interconnect 506. In addition to the first substrate interconnect 508 in the substrate interconnect layer 510, the first raised interconnect 506 is provided for the purpose of reducing impedance by providing an alternative parallel path for signals propagating in the first surface interconnect 512 in the surface interconnect layer 514. The package substrate 500 includes vias 516(1)-516(2) between the surface interconnect layer 514 and the raised interconnect layer 504, and vias 516(3)-516(4) between the surface interconnect layer 514 and the substrate interconnect layer 510, to provide parallel paths. Coupled to both the raised interconnect layer 504 and the substrate interconnect layer 510 in a third direction (e.g., the Z-axis direction), the first surface interconnect 512 provides an alternative signal path parallel to the surface interconnect layer 514, thereby reducing signal impedance.

[0026] Figure 6 This is a flowchart of an exemplary manufacturing method 600 for manufacturing a packaging substrate. Manufacturing process or method 600 is about... Figure 4 The discussion focuses on the packaging substrate 408 in the IC package, but it should be noted that... Figure 6The manufacturing method 600 in the middle is not limited to manufacturing Figure 4 The packaging substrate 408 in the middle.

[0027] Method 600 includes: forming a package substrate 408, the package substrate including a surface interconnect layer 404, the surface interconnect layer including a plurality of surface interconnects 412 extending between a first region A1 and a second region A2 of a first surface 406 of the package substrate 408 (box 602). The method further includes: setting a first integrated circuit (IC) die 402 in the first region A1 and coupled to the plurality of surface interconnects 412 (box 604); and forming a dielectric layer 410 on the surface interconnect layer 404 in the second region A2 (box 606). The method further includes: forming a raised interconnect layer 414 on the dielectric layer 410 and including a plurality of raised interconnects coupled through the dielectric layer 410 to the plurality of surface interconnects 412 (box 608).

[0028] Figure 7This is a cross-sectional side view of an IC package 700, which includes a first IC die 702 on a first package substrate 704 and a second substrate 706 stacked on the first package substrate 704 to couple the first IC die 702 to a second IC (not shown) or another external circuit. The first IC die 702 is coupled to a surface interconnect layer 708 by die interconnects 710. The surface interconnect layer 708 includes surface interconnects 712(1)-712(3) that are coupled to substrate interconnect layers 714(1) and 714(2) to provide electrical paths parallel to the surface interconnects 712(1)-712(3). In this example, the surface interconnects 712(1)-712(3) are coupled to package contacts 716 and package interconnects 718(1)-718(3). Package interconnects 718(1)-718(3) are used to couple the first IC die 702 to the second substrate 706. The second substrate 706 is spaced apart from the surface interconnect layer 708 by a distance L1 in the Z-axis direction, and the first IC die 702 is located between the first package substrate 704 and the second substrate 706. The first IC die 702 extends a height H1 above the surface interconnect layer 708, so the distance L1 must be equal to or greater than the height H1. Therefore, the package interconnects 718(1)-718(3) extend a distance L1 in the Z-axis direction and have corresponding diameters D1 in the X and Y directions. For example, the package interconnects 718(1)-718(3) can be solder balls or pillars with a specific aspect ratio between their height and diameter. Due to the diameter D1 and the spacing considerations, there is a limitation on the center-to-center distance or pitch P1 of the package interconnects 718(1)-718(3), which limits the density of the package interconnects 718(1)-718(3) between the first package substrate 704 and the second substrate 706. Limiting the density of the package interconnects 718(1)-718(3) prevents further reduction in the area of ​​the IC package 700.

[0029] Figure 8This is a cross-sectional side view of a second exemplary IC package 800, which includes a first IC die 802 in a first region A1 on a first package substrate 804 and a second substrate 806 stacked on the first package substrate 804 to couple the first IC die 802 to a second IC (not shown) or another external circuit. The IC package 800 includes a surface interconnect layer 808 coupled to the first IC die 802, and substrate interconnect layers 810(1) and 810(2). The IC package 800 includes a raised interconnect layer 812 disposed on a dielectric layer 814 disposed on the surface interconnect layer 808 in the second region A2. The raised interconnect layer 812 includes raised interconnects 816(1)-816(3), which may include package contacts 817(1)-817(3). In this example, package contacts 817(1) and 817(2) on dielectric layer 814 are coupled to second substrate 806 via package interconnects 818(1)-818(2). It should be understood that... Figure 8 The number of package contacts 817(1)-817(3) shown is not intended to limit or necessarily represent the number that may be provided in region A2 or between the edges of the first IC die 802 and the first package substrate 804.

[0030] As previously discussed, the raised interconnects 816(1)-816(3) are provided for the purpose of reducing impedance by providing an alternative path for signal propagation parallel to the surface interconnects 820 in the surface interconnect layer 808. However, in an additional exemplary aspect, the distance L2 between the raised interconnect layer 812 and the second substrate 806 may be less than the height H1 of the first IC die 802 above the surface interconnect layer 808. Therefore, with Figure 7 Compared to the package interconnects 718(1)-718(3) in the package, the height of package interconnects 818(1) and 818(2) can be reduced. Since the height of package interconnects 818(1) and 818(2) can be reduced, their diameter can also be reduced while maintaining the same aspect ratio. This allows for smaller spacing or intervals in the X and Y axes, thereby further allowing for a greater density of package interconnects 818(1) and 818(2) between the first package substrate 804 and the second substrate 806. In this way, the raised interconnect layer 812 in the second region A2 helps to reduce the size of IC packages (such as IC package 800) by reducing the impedance in signal paths that are narrowed to achieve greater density in the package substrate and by reducing the size of the (vertical) package interconnects to increase the package interconnect density.

[0031] Figure 9AThis is a cross-sectional side view of another example of an IC package 900, which includes an IC die 902 disposed in a first region A1 of a package substrate 904. The package substrate 904 includes a raised interconnect layer 906 disposed on a dielectric layer 907 in a second peripheral region A2. The second region A2 is located on the periphery of the first region A1 (e.g., around it) and between the first region A1 and a third region A3, which is located along an edge E1 of the package substrate 904. The third region A3 does not include the raised interconnect layer 906 or the dielectric layer 907. Figure 9B yes Figure 9A A plan view of IC package 900.

[0032] In this example, the dielectric layer 907 and the raised interconnect layer 906 are disposed on the surface interconnect layer 908 and can be used to reduce the impedance of the signal S1 propagating through the surface interconnect 910 in the surface interconnect layer 908. However, in this example, the package contact 912 is formed on the surface interconnect 910 in the third region A3, and not on the dielectric layer 907. Therefore, in this example, the package interconnect density is not reduced in the third region A3.

[0033] Figure 10A This is a cross-sectional side view of another example of an IC package 1000, which includes an IC die 1002 disposed in a first region A1 of a package substrate 1004. The package substrate 1004 includes a raised interconnect layer 1006 in a second region A2, the raised interconnect layer including a third region A3 extending along an edge E1 of the package substrate 1004. In this example, the second region A2 is located between the first region A1 and the edge E1. Figure 10B yes Figure 10A A plan view of IC package 1000.

[0034] In this example, a raised interconnect layer 1006 is disposed on a surface interconnect layer 1008 that extends from a first region A1 to an edge E1. The raised interconnect layer 1006 can be used to reduce the impedance of a signal S2 propagating through surface interconnects 1010 in the surface interconnect layer 1008 in the second region A2, as discussed above. Signal S2 represents any number of signals that can propagate through the surface interconnect layer 1008. Additionally, the raised interconnect layer 1006 in this example includes a package contact 1012 in a third region A3, on which package interconnects (not shown) with reduced height can be formed for coupling another substrate to the IC package 1000. The package contact 1012 can be included among a plurality of package contacts provided in the third region A3 of the package substrate 1004 for coupling to another substrate. In this example, the raised interconnect layer 1006 provides the benefits of increasing the density of package interconnects (not shown) and reducing the impedance of signals in the surface interconnect layer 1008.

[0035] Figure 11A This is a cross-sectional side view of another example of an IC package 1100, which includes an IC die 1102 disposed in a first region A1 of a package substrate 1104. The package substrate 1104 includes a raised interconnect layer 1106 disposed along an edge E1 of the package substrate 1104 on a dielectric layer 1108 in a third peripheral region A3. The package substrate 1104 includes a second region A2 between region A1 and peripheral region A3. Figure 11B yes Figure 11A A plan view of IC package 1100.

[0036] In this example, a raised interconnect layer 1106 is disposed on a dielectric layer 1108. The dielectric layer 1108 is disposed on a surface interconnect layer 1110, which extends to edge E1 through a second region A2 and a third region A3. The raised interconnect layer 1106 may include package contacts (such as package contacts 1112), on which package contacts may be densely packed to form package interconnects (not shown) with a reduced height, and these package interconnects are used to couple another substrate to the IC package 1100. In this example, the raised interconnect layer 1106 is not provided in the second region A2.

[0037] Other manufacturing processes can also be used to manufacture IC packages, including packaging substrates (including but not limited to) Figures 8 to 11B The IC packages 800, 900, 1000, and 1100 in the example include raised interconnect layers that provide reduced impedance for signals in the surface interconnect layers of the package substrate and also provide reduced package interconnect size that allows for increased package interconnect density.

[0038] In this respect, Figures 12A to 12F This is a flowchart illustrating another exemplary manufacturing process 1200 for manufacturing an IC package 1300, which includes a raised interconnect layer on a package substrate to reduce the size of the package interconnects and reduce the impedance of the signal interconnects coupled to the IC in the IC package. The IC package includes, but is not limited to, Figures 8 to 11B IC packages 800-1100.

[0039] Figures 13A to 13F It is based on Figures 12A to 12F The exemplary manufacturing stages 1300A-1300F during the manufacturing of IC packages including packaging substrates in the manufacturing process 1200, the packaging substrates including raised interconnect layers, the raised interconnect layers providing reduced impedance for signals in the surface interconnect layers of the packaging substrates, and also providing reduced package interconnect size that allows for increased package interconnect density.

[0040] In this respect, such as Figure 13A As shown in manufacturing stage 1300A, the manufacturing process 1200 of the IC package 1300 begins with the formation of a package substrate 1302 comprising a plurality of interconnect layers 1304(1)-1304(X) (where X=3 in this example). For example, the plurality of interconnect layers 1304(1)-1304(X) may be disposed in a dielectric 1306. Step 1202 in the manufacturing process includes: forming a package substrate 1302, which is included on a first side S1 of the package substrate 1302 and in a first region A1 (where the IC die (see Figure 13D A surface interconnect layer 1304(1) extending between a package substrate 1302 and a second region A2 may be coupled to the first region A1, which may be outside or around the first region A1. Step 1202 may further include forming c surface interconnects 1308 in the surface interconnect layer 1304(1). In some examples, the package contacts 1308 may be coupled to interconnects in one or more surface interconnect layers 1304(2)-1304(X). Figure 13A The features marked in the middle can be Figures 13B to 13F Similar markings are used in the text, but will not be discussed further in this article.

[0041] exist Figure 13B Manufacturing step 1204 in manufacturing process 1200 is illustrated in manufacturing stage 1300B. Manufacturing step 1204 includes forming a dielectric layer 1310 on a first side S1 of the package substrate 1302 in the second region A2, and patterning the dielectric layer 1310 to form openings 1312 above surface interconnects 1308, in which vias (not shown) may be formed.

[0042] exist Figure 13C Manufacturing step 1206 in manufacturing process 1200 is illustrated in manufacturing stage 1300C. Manufacturing step 1206 includes forming a raised interconnect layer 1314 on dielectric layer 1310, including a filled opening 1312 to form a via 1316, and forming package contacts 1318 and die contacts 1320. Manufacturing step 1206 also includes forming a resist layer 1322 on a first side S1 of package substrate 1302, and patterning the resist layer 1322 in a second region A2 to form an opening 1324 thereby exposing the package contacts 1318. The resist layer 1322 may also be patterned in the first region A1 to form contact positions 1326 for coupling to IC 1328 (see See). Figure 13D In an alternative example, an opening 1324 may be formed in the resist layer 1322 at a later stage (such as manufacturing stage 1300E).

[0043] exist Figure 13D Manufacturing step 1208 in manufacturing process 1200 is illustrated in manufacturing stage 1300D. Manufacturing step 1208 includes: forming a die interconnect 1330 on a die contact 1320 in a first region A1, and coupling a first IC 1328 to the die interconnect 1330.

[0044] Additional optional steps are provided in manufacturing process 1200 for forming an IC package 1300 including a second substrate (e.g., for IC stacking), as in a second embodiment. Figure 13E and Figure 13F As shown. In Figure 13E Manufacturing step 1210 in manufacturing process 1200 is illustrated in manufacturing stage 1300E. Manufacturing step 1210 includes forming package interconnect 1332 on package contacts 1318 in raised interconnect layer 1314. Optionally, manufacturing step 1210 further includes coupling a second substrate 1334 to package substrate 1302 through package interconnect 1332.

[0045] exist Figure 13F Manufacturing step 1212 in manufacturing process 1200 is illustrated in manufacturing stage 1300F. Optional manufacturing step 1212 includes providing molding compound 1336 in the space 1338 between the second substrate 1334 and the first side S1 of the package substrate 1302.

[0046] Electronic devices according to any aspect disclosed herein can be located in or integrated into any processor-based device. Examples, without limitation, include: set-top boxes, entertainment units, navigation devices, communication devices, fixed location data units, mobile location data units, Global Positioning System (GPS) devices, mobile phones, cellular phones, smartphones, Session Initiation Protocol (SIP) phones, tablet computers, phablets, servers, computers, portable computers, mobile computing devices, laptop computers, wearable computing devices (e.g., smartwatches, health or fitness trackers, glasses, etc.), desktop computers, personal digital assistants (PDAs), monitors, computer monitors, televisions, tuners, radios, satellite radios, music players, digital music players, portable music players, digital video players, video players, digital video disc (DVD) players, portable digital video players, automobiles, vehicle components, avionics systems, drones, and multirotor aircraft.

[0047] In this respect, Figure 14 A block diagram illustrating an exemplary wireless communication device 1400 including radio frequency (RF) components formed by one or more ICs 1402 is shown, wherein the communication device 1400 may include an IC package including a raised interconnect layer on a package substrate to reduce the size of package interconnects and reduce coupling to the IC package (such as... Figures 8 to 11B The impedance of the signal interconnects of the IC in the IC package (any one of IC packages 800, 900, 1000, and 1100). Wireless communication device 1400 may include any of the devices described above or is provided as an example of any of the devices described above. Figure 14 As shown, the wireless communication device 1400 includes a transceiver 1404 and a data processor 1406. The data processor 1406 may include memory for storing data and program code. The transceiver 1404 includes a transmitter 1408 and a receiver 1410 supporting bidirectional communication. Generally, the wireless communication device 1400 may include any number of transmitters 1408 and / or receivers 1410 for any number of communication systems and frequency bands. All or part of the transceiver 1404 may be implemented on one or more analog ICs, RF ICs (RFICs), mixed-signal ICs, etc.

[0048] Transmitter 1408 or receiver 1410 can be implemented using a superheterodyne or direct conversion architecture. In a superheterodyne architecture, the signal undergoes multi-stage frequency conversion between RF and baseband, for example, from RF to intermediate frequency (IF) in one stage and then from IF to baseband in another stage. In a direct conversion architecture, the signal is converted between RF and baseband in a single stage. Superheterodyne and direct conversion architectures can use different circuit blocks and / or have different requirements. Figure 14In the wireless communication device 1400, the transmitter 1408 and the receiver 1410 are implemented using a direct frequency conversion architecture.

[0049] In the transmission path, data processor 1406 processes the data to be transmitted and provides I and Q analog output signals to transmitter 1408. In the exemplary wireless communication device 1400, data processor 1406 includes digital-to-analog converters (DACs) 1412(1) and 1412(2) to convert digital signals generated by data processor 1406 into I and Q analog output signals (e.g., I and Q output currents) for further processing.

[0050] Within transmitter 1408, low-pass filters 1414(1) and 1414(2) filter the I and Q analog output signals, respectively, to remove unwanted signals caused by the previous digital-to-analog conversion. Amplifiers (AMPs) 1416(1) and 1416(2) amplify the signals from low-pass filters 1414(1) and 1414(2), respectively, and provide I and Q baseband signals. Upconverter 1418 upconverts the I and Q baseband signals using the I and Q TX LO signals from transmit (TX) local oscillator (LO) signal generator 1422 via mixers 1420(1) and 1420(2) to provide upconverted signal 1424. Filter 1426 filters the upconverted signal 1424 to remove unwanted signals caused by upconversion and noise in the receive band. Power amplifier (PA) 1428 amplifies the up-converted signal 1424 from filter 1426 to obtain the desired output power level and provide a transmit RF signal. The transmit RF signal is routed through duplexer or switch 1430 and transmitted via antenna 1432.

[0051] In the receiving path, antenna 1432 receives signals transmitted by the base station and provides the received RF signal, which is routed through duplexer or switch 1430 and provided to low-noise amplifier (LNA) 1434. Duplexer or switch 1430 is designed to operate using a specific receive (RX) to TX duplexer frequency separation, such that the RX signal is isolated from the TX signal. The received RF signal is amplified by LNA 1434 and filtered by filter 1436 to obtain the desired RF input signal. Downconversion mixers 1438(1) and 1438(2) mix the output of filter 1436 with the I and Q RXLO signals (i.e., LO_I and LO_Q) from RX LO signal generator 1440 to generate I and Q baseband signals. The I and Q baseband signals are amplified by AMPs 1442(1) and 1442(2) and further filtered by low-pass filters 1444(1) and 1444(2) to obtain I and Q analog input signals, which are provided to data processor 1406. In this example, data processor 1406 includes analog-to-digital converters (ADCs) 1446(1) and 1446(2) to convert the analog input signals into digital signals to be further processed by data processor 1406.

[0052] exist Figure 14 In the wireless communication device 1400, a TX LO signal generator 1422 generates I and Q TXLO signals for up-conversion, while an RX LO signal generator 1440 generates I and Q RX LO signals for down-conversion. Each LO signal is a periodic signal with a specific base frequency. A TX phase-locked loop (PLL) circuit 1448 receives timing information from a data processor 1406 and generates control signals for adjusting the frequency and / or phase of the TX LO signals from the TX LO signal generator 1422. Similarly, an RX PLL circuit 1450 receives timing information from a data processor 1406 and generates control signals for adjusting the frequency and / or phase of the RX LO signals from the RX LO signal generator 1440.

[0053] Figure 15 Examples can be found Figure 5 A block diagram of an example of a processor-based system 1500 implemented in a packaging substrate 500, the processor-based system including an IC package, the IC package including a raised interconnect layer on the packaging substrate to reduce the package interconnect size and reduce coupling to the IC package (such as... Figures 8 to 11BThe impedance of the signal interconnects of the IC in the IC package (any one of IC packages 800, 900, 1000, and 1100). In this example, the processor-based system 1500 includes a processor 1502, which includes an IC 1504, which includes one or more central processing units (CPUs) 1508, which may also be referred to as CPUs or processor cores, each CPU or processor core including one or more processors 1510. The CPU 1508 may have a cache memory 1512 coupled to the processor 1502 for fast access to temporarily stored data. The CPU 1508 is coupled to a system bus 1514 and can interactively couple to master and slave devices included in the processor-based system 1500. As is well known, the CPU 1508 communicates with these other devices by exchanging address, control, and data information on the system bus 1514. For example, the CPU 1508 may communicate a bus transaction request to a memory controller 1516, which is an example of a slave device. Although in Figure 15 Not illustrated, but multiple system buses 1514 may be provided, each of which constitutes a different architecture.

[0054] Other master and slave devices can be connected to system bus 1514. For example... Figure 15 As illustrated, these devices may include a memory system 1520 (which includes a memory controller 1516 and one or more memory arrays 1518), one or more input devices 1522, one or more output devices 1524, one or more network interface devices 1526, and one or more display controllers 1528. Input devices 1522 may include any type of input device, including but not limited to input keys, switches, voice processors, etc. Output devices 1524 may include any type of output device, including but not limited to audio, video, other visual indicators, etc. Network interface devices 1526 may be any device configured to allow data exchange to and from network 1530. Network 1530 may be any type of network, including but not limited to wired or wireless networks, private or public networks, local area networks (LANs), wireless local area networks (WLANs), wide area networks (WANs), and Bluetooth. ™ Networks and the Internet. The network interface device 1526 can be configured to support any type of communication protocol desired.

[0055] CPU 1508 can also be configured to access display controller 1528 via system bus 1514 to control information transmitted to one or more displays 1532. Display controller 1528 transmits information to be displayed to displays 1532 via one or more video processors 1534, which process the information to be displayed into a format suitable for displays 1532. Displays 1532 may include any type of display, including but not limited to cathode ray tube (CRT), liquid crystal display (LCD), plasma display, or light-emitting diode (LED) displays.

[0056] Those skilled in the art will further understand that the various exemplary logic blocks, modules, circuits, and algorithms described in connection with the aspects disclosed herein can be implemented as electronic hardware, instructions stored in memory, or in another computer-readable medium, wherein any such instructions are executed by a processor or other processing device or a combination of both. As an example, the devices and components described herein can be used in any circuit, hardware component, integrated circuit (IC), or IC chip. The memory disclosed herein can be of any type and size and can be configured to store any desired information. To clearly illustrate this interchangeability, the functionality of the various exemplary components, blocks, modules, circuits, and steps has been generally described above. How such functionality is implemented depends on the specific application, design choices, and / or design constraints imposed on the overall system. Those skilled in the art may implement the described functionality in different ways for each specific application, but such specific implementation decisions should not be construed as departing from the scope of this disclosure.

[0057] The various exemplary logic blocks, modules, and circuits described in conjunction with the aspects disclosed herein may be implemented or executed using a processor, digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic unit, discrete hardware component, or any combination thereof, designed to perform the functions described herein. The processor may be a microprocessor, but in alternative embodiments, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors cooperating with a DSP core, or any other such configuration).

[0058] The aspects disclosed herein may be embodied in hardware and instructions stored in the hardware, and may reside in, for example, random access memory (RAM), flash memory, read-only memory (ROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), registers, hard disks, removable disks, CD-ROMs, or any other form of computer-readable medium known in the art. An exemplary storage medium is coupled to a processor, enabling the processor to read information from and write information to the storage medium. Alternatively, the storage medium may be integral with the processor. The processor and storage medium may reside in an ASIC. The ASIC may reside in a remote station. Alternatively, the processor and storage medium may reside as discrete components in a remote station, base station, or server.

[0059] It should also be noted that the operational steps described in any of the exemplary aspects of this document are described for the purpose of providing examples and discussion. The described operations may be performed in many different orders other than the order illustrated. Furthermore, the operations described in a single operational step may actually be performed in multiple different steps. In addition, one or more operational steps discussed in the exemplary aspects may be combined. It will be understood that, as will be apparent to those skilled in the art, many different modifications may be made to the operational steps illustrated in the flowcharts. Those skilled in the art will also understand that various techniques and methods can be used to represent information and signals. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be mentioned throughout the above description may be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or optical particles, or any combination thereof.

[0060] The prior description of this disclosure is provided to enable any person skilled in the art to make or use this disclosure. Various modifications to this disclosure will be apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the spirit or scope of this disclosure. Therefore, this disclosure is not intended to be limited to the examples and designs described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

[0061] Specific implementation examples are described in the following numbered clauses: 1. A substrate, the substrate comprising: A surface interconnect layer comprising a plurality of surface interconnects extending between a first region and a second region on a first surface, the first region being configured to be coupled to an integrated circuit (IC) die; A dielectric layer, the dielectric layer being disposed on the surface interconnect layer in the second region; and A raised interconnect layer is disposed on the dielectric layer and includes a plurality of raised interconnects coupled to the plurality of surface interconnects through the dielectric layer.

[0062] 2. The substrate according to Clause 1, wherein: The plurality of surface interconnects includes a first surface interconnect extending from a first location in the second region to a second location in the second region; and The plurality of raised interconnects includes a first raised interconnect coupled to the first surface interconnect in the first location and in the second location.

[0063] 3. The substrate according to Clause 2, wherein the substrate further comprises: A first via, extending through the dielectric layer to couple the first surface interconnect to the first raised interconnect at the first location; and A second via extends through the dielectric layer to couple the first surface interconnect to the first raised interconnect at the second location.

[0064] 4. The substrate according to Clause 1, wherein the second region is on the periphery of the first region.

[0065] 5. The substrate according to any one of Clauses 1 to 3, wherein the first surface further includes a third region between the second region and the edge of the substrate, wherein the dielectric layer is not disposed in the third region.

[0066] 6. The substrate according to any one of Clauses 1 to 4, wherein the dielectric layer extends from the periphery of the first region to the edge of the substrate.

[0067] 7. The substrate according to any one of Clauses 1 to 6, wherein the raised interconnect layer further includes a package contact coupled to the plurality of raised interconnects and configured to be coupled to a package interconnect, the package interconnect being further coupled to a second substrate.

[0068] 8. The substrate according to any one of Clauses 2 to 7, wherein one of the encapsulation contacts is disposed in the second position.

[0069] 9. The substrate according to any one of Clauses 1 to 8, wherein a first center-to-center distance between two adjacent surface interconnects in the first region is greater than a second center-to-center distance between two adjacent surface interconnects in the second region.

[0070] 10. The substrate according to any one of Clauses 1 to 9, wherein the first width of the first surface interconnect in the first region is greater than the second width of the first surface interconnect in the second region.

[0071] 11. A package, the package comprising: A first integrated circuit (IC) die is disposed in a first region on a first surface of a packaging substrate; A surface interconnect layer, the surface interconnect layer including a plurality of surface interconnects coupled to a second region of the first IC die and extending to the first surface of the package substrate; A dielectric layer, the dielectric layer being disposed on the surface interconnect layer in the second region of the packaging substrate; and A raised interconnect layer is disposed on the dielectric layer and includes a plurality of raised interconnects coupled to the plurality of surface interconnects through the dielectric layer.

[0072] 12. The package as described in Clause 11, wherein: The plurality of surface interconnects includes a first surface interconnect extending from a first location in the second region to a second location in the second region; and The plurality of raised interconnects includes a first raised interconnect coupled to the first surface interconnect in the first location and in the second location.

[0073] 13. The package according to Clause 11 or Clause 12, wherein the bump interconnect layer further includes package contacts on the dielectric layer and electrically coupled to the plurality of bump interconnects, the plurality of bump interconnects being coupled to the first IC die.

[0074] 14. The package according to Clause 13, the package further comprising a second substrate coupled to the package contact on the dielectric layer, the first IC die disposed between the package substrate and the second substrate.

[0075] 15. The package as described in Clause 13 or Clause 14, wherein: The first distance from the package contact to the second substrate in the first direction is less than the second distance from the surface interconnect layer to the second substrate in the first direction.

[0076] 16. The package as described in Clause 11, integrated into a device selected from the group consisting of: set-top boxes; entertainment units; navigation devices; communication devices; fixed location data units; mobile location data units; global positioning system (GPS) devices; mobile phones; cellular phones; smartphones; session initiation protocol (SIP) phones; tablet computers; tablet phones; servers; computers; portable computers; mobile computing devices; wearable computing devices; desktop computers; personal digital assistants (PDAs); monitors; computer monitors; televisions; tuners; radios; satellite radios; music players; digital music players; portable music players; digital video players; video players; digital video disc (DVD) players; portable digital video players; automobiles; vehicle components; avionics systems; unmanned aerial vehicles; and multirotor aircraft.

[0077] 17. A method of manufacturing a package, the method comprising: A package substrate is formed including a surface interconnect layer, the surface interconnect layer including a plurality of surface interconnects extending between a first region and a second region on a first surface of the package substrate; A first integrated circuit (IC) die is provided, the first IC die being located in the first region and coupled to the plurality of surface interconnects; A dielectric layer is formed on the surface interconnect layer in the second region; and A raised interconnect layer is formed on the dielectric layer and includes a plurality of raised interconnects coupled to the plurality of surface interconnects through the dielectric layer.

[0078] 18. The method according to Clause 17, further comprising: Two adjacent surface interconnects are formed among the plurality of surface interconnects, the two adjacent surface interconnects having a first center-to-center distance in the first region and a second center-to-center distance between the two adjacent surface interconnects in the second region, the second center-to-center distance being less than the first center-to-center distance.

[0079] 19. The method described pursuant to Clause 17 or Clause 18, further comprising: Forming a first vertical interconnect via through the dielectric layer to couple one of the plurality of surface interconnects to one of the plurality of raised interconnects in a first location; and A second via is formed through the dielectric layer to couple one of the plurality of surface interconnects to one of the plurality of raised interconnects in a second location.

[0080] 20. The method according to any one of Clauses 17 to 19, wherein the method further comprises: Forming encapsulation contacts on the dielectric layer and coupled to the plurality of raised interconnects; Package interconnects are formed on the package contacts; and A second substrate is disposed on the interconnect of the package.

Claims

1. A substrate, the substrate comprising: A surface interconnect layer comprising a plurality of surface interconnects extending between a first region and a second region on a first surface, the first region being configured to be coupled to an integrated circuit (IC) die; A dielectric layer disposed on the surface interconnect layer in the second region; and A raised interconnect layer is disposed on the dielectric layer and includes a plurality of raised interconnects coupled to the plurality of surface interconnects through the dielectric layer.

2. The substrate according to claim 1, wherein: The plurality of surface interconnects includes a first surface interconnect extending from a first location in the second region to a second location in the second region; and The plurality of raised interconnects includes a first raised interconnect coupled to the first surface interconnect in the first location and in the second location.

3. The substrate according to claim 2, further comprising: A first via extends through the dielectric layer to couple the first surface interconnect to the first raised interconnect at the first location; and A second via extends through the dielectric layer to couple the first surface interconnect to the first raised interconnect at the second location.

4. The substrate according to claim 1, wherein the second region is on the periphery of the first region.

5. The substrate according to claim 1, wherein the first surface further includes a third region between the second region and the edge of the substrate, wherein the dielectric layer is not disposed in the third region.

6. The substrate of claim 4, wherein the dielectric layer extends from the periphery of the first region to the edge of the substrate.

7. The substrate of claim 2, wherein the raised interconnect layer further comprises a package contact coupled to the plurality of raised interconnects and configured to be coupled to a package interconnect, the package interconnect being further coupled to a second substrate.

8. The substrate according to claim 7, wherein one of the encapsulation contacts is disposed in the second position.

9. The substrate of claim 1, wherein a first center-to-center distance between two adjacent surface interconnects in the first region is greater than a second center-to-center distance between two adjacent surface interconnects in the second region.

10. The substrate of claim 2, wherein the first width of the first surface interconnect in the plurality of surface interconnects in the first region is greater than the second width of the first surface interconnect in the second region.

11. A package, the package comprising: A first integrated circuit (IC) die is disposed in a first region on a first surface of a packaging substrate; A surface interconnect layer, the surface interconnect layer including a plurality of surface interconnects coupled to a second region of the first IC die and extending to the first surface of the package substrate; A dielectric layer disposed on the surface interconnect layer in the second region of the packaging substrate; and A raised interconnect layer is disposed on the dielectric layer and includes a plurality of raised interconnects coupled to the plurality of surface interconnects through the dielectric layer.

12. The package according to claim 11, wherein: The plurality of surface interconnects includes a first surface interconnect extending from a first location in the second region to a second location in the second region; and The plurality of raised interconnects includes a first raised interconnect coupled to the first surface interconnect in the first location and in the second location.

13. The package of claim 11, wherein the bump interconnect layer further comprises a package contact on the dielectric layer and electrically coupled to the plurality of bump interconnects, the plurality of bump interconnects being coupled to the first IC die.

14. The package of claim 13, further comprising a second substrate coupled to the package contact on the dielectric layer, wherein the first IC die is disposed between the package substrate and the second substrate.

15. The package according to claim 14, wherein: The first distance from the package contact to the second substrate in the first direction is less than the second distance from the surface interconnect layer to the second substrate in the first direction.

16. The package of claim 11, wherein the package is integrated into a device selected from the group consisting of: set-top boxes; entertainment units; navigation devices; communication devices; fixed location data units; mobile location data units; global positioning system (GPS) devices; mobile phones; cellular phones; smartphones; session initiation protocol (SIP) phones; tablet computers; tablet phones; servers; computers; portable computers; mobile computing devices; wearable computing devices; desktop computers; personal digital assistants (PDAs); monitors; computer monitors; televisions; tuners; radios; satellite radios; music players; digital music players; portable music players; digital video players; video players; digital video disc (DVD) players; portable digital video players; automobiles; vehicle components; avionics systems; unmanned aerial vehicles; and multi-rotor aircraft.

17. A method of manufacturing a package, the method comprising: A package substrate is formed including a surface interconnect layer, the surface interconnect layer including a plurality of surface interconnects extending between a first region and a second region on a first surface of the package substrate; A first integrated circuit (IC) die is provided, the first IC die being located in the first region and coupled to the plurality of surface interconnects; A dielectric layer is formed on the surface interconnect layer in the second region; as well as A raised interconnect layer is formed on the dielectric layer and includes a plurality of raised interconnects coupled to the plurality of surface interconnects through the dielectric layer.

18. The method according to claim 17, further comprising: Two adjacent surface interconnects are formed among the plurality of surface interconnects, the two adjacent surface interconnects having a first center-to-center distance in the first region and a second center-to-center distance between the two adjacent surface interconnects in the second region, the second center-to-center distance being less than the first center-to-center distance.

19. The method of claim 17, further comprising: A first vertical interconnect path (via) is formed through the dielectric layer to couple one of the plurality of surface interconnects to one of the plurality of raised interconnects in a first location; as well as A second via is formed through the dielectric layer to couple one of the plurality of surface interconnects to one of the plurality of raised interconnects in a second location.

20. The method of claim 17, further comprising: Forming encapsulation contacts on the dielectric layer and coupled to the plurality of raised interconnects; Package interconnects are formed on the package contacts; as well as A second substrate is disposed on the interconnect of the package.

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