Hybrid boost for memory write assist

Abstract

A memory is provided that includes a negative bit line hybrid boost circuit to boost a discharged bit line to a negative voltage during a negative bit line boost period for a write operation to a selected column in the memory. The hybrid boost circuit uses a charged gate capacitance of a boost transistor and a charged capacitance of a metal line capacitor to provide the negative bit line boost. Similarly, the memory can include a word line hybrid boost circuit that uses another boost transistor and another metal line capacitor for boosting a word line above a word line supply voltage during a write operation.

Description

Cross-referencing

[0001] This application claims priority and benefit to U.S. nonprovisional patent application No. 18 / 428,482, filed January 31, 2024, the entire contents of which are incorporated herein by reference, as fully set forth below and for all applicable purposes. Technical Field

[0002] This application relates to memory, and more specifically to memory having a hybrid boost converter for memory write assistance. Background Technology

[0003] Static Random Access Memory (SRAM) bit cells include a pair of cross-coupled inverters. Depending on the binary state of the stored data bits, a p-type metal-oxide-semiconductor (PMOS) transistor in one of the inverters charges the data node to the memory supply voltage. During a write operation that changes the binary content of the bit cell, an n-type metal-oxide-semiconductor (NMOS) access transistor attempts to discharge the same data node, while the PMOS transistor continues to charge the data node. The resulting NMOS / PMOS contention slows down write operations and consumes power. Summary of the Invention

[0004] A memory is disclosed, comprising: a bit line; a negative bit line hybrid boost circuit including: a boost transistor; and a metal line capacitor including a first metal line and at least one second metal line extending adjacent to the first metal line, wherein the first metal line is coupled to the bit line and coupled to the gate of the boost transistor, and wherein at least one second metal line is coupled to the drain and source of the boost transistor.

[0005] Furthermore, the present invention provides a negative bit-line hybrid boost method for a memory, the method comprising the following actions: responding to a first binary state of a boost signal by grounding the gate of a boost transistor, simultaneously grounding a first metal line coupled to the gate of the boost transistor, and simultaneously charging the drain and source of the boost transistor to a power supply voltage, while simultaneously charging at least one second metal line coupled to the drain and source of the boost transistor to a power supply voltage; and responding to a second binary state of the boost signal by grounding the drain and source of the boost transistor and grounding at least one second metal line to boost the bit line coupled to the gate of the boost transistor to a negative voltage.

[0006] Finally, a memory is provided, comprising: a word line; a word line driver configured to charge the word line with a word line power supply voltage during a write operation; a word line hybrid boost circuit comprising: a boost transistor; and a metal line capacitor, wherein the word line hybrid boost circuit is configured to boost the word line power supply voltage using the gate capacitance of the boost transistor and the capacitance of the metal line capacitor during a word line boost cycle.

[0007] These advantageous features can be better understood by considering the following detailed description. Attached Figure Description

[0008] Figure 1 This is a diagram of a memory including a negative bit line hybrid boost circuit according to aspects of this disclosure.

[0009] Figure 2 Based on the aspects of this disclosure Figure 1 The circuit diagram of the negative bit line hybrid boost circuit and the write driver.

[0010] Figure 3 This is a diagram of a memory including a word-line hybrid boost circuit according to aspects of this disclosure.

[0011] Figure 4 This is a cross-sectional view of a semiconductor device including a metal wire capacitor for hybrid boosting of bit lines or word lines, according to aspects of this disclosure.

[0012] Figure 5 Examples of electronic systems incorporating memories with mixed bit-line and / or word-line boosting are illustrated according to aspects of this disclosure.

[0013] Figure 6 This is a flowchart of a method for negative line hybrid boost according to aspects of this disclosure.

[0014] The specific embodiments of this disclosure and its advantages can be best understood by referring to the following detailed description. It should be understood that the same reference numerals are used to identify the same elements illustrated in one or more of the figures. Detailed Implementation

[0015] One form of write assistance used in Static Random Access Memory (SRAM) is called negative bit-line boost. In this technique, a write operation may involve changing the binary content of a bit cell such that the data node charged by a PMOS transistor in one of the inverters of the cross-coupled inverter of the bit cell must be discharged to the ground line via an NMOS access transistor during the write operation. In a negative bit-line boost operation, the ground line is temporarily boosted to a negative voltage. This negative voltage on the bit line effectively increases the intensity of the NMOS access transistor's competition with the PMOS transistor, which would otherwise continue charging the data node to the memory supply voltage. The increased intensity of the NMOS access transistor allows it to discharge the data node more quickly, resulting in a corresponding increase in write operation speed. Without negative bit-line boost, the NMOS access transistor might need to be made larger, increasing the memory footprint on the semiconductor die and thus increasing manufacturing costs. However, with negative bit-line boost, the NMOS access transistor can be relatively small, reducing the amount of semiconductor die space occupied by the memory and thus lowering manufacturing costs.

[0016] To provide negative boost to the bit lines, the write driver may include a negative boost circuit comprising a boost node grounded when the boost signal is in a default (e.g., discharged) state. During a write operation, a column multiplexer selects the column of bit cells traversed by the bit line pair. Depending on the binary value of the bit being written, the boost node in the boost circuit is coupled to one bit line in the bit line pair of the selected column. The boost circuit includes a boost transistor having its gate coupled to the boost node and its source and drain coupled to the node controlled by the inverted and buffered version of the boost signal. When the boost signal is in its default / discharged state, the drain and source of the boost transistor are charged to the memory supply voltage, while its gate is grounded, which charges the gate capacitance of the boost transistor. During the negative bit line boost cycle, the boost signal is asserted as the memory supply voltage, which grounds the source and drain of the boost transistor. Since the gate capacitance of the boost transistor has already been charged, grounding the source and drain of the boost transistor causes the gate of the boost transistor to discharge below ground. In this way, the boost transistor acts as a boost capacitor to pull the boost node (and therefore the corresponding bit line) to a negative voltage during the negative bit line boost cycle.

[0017] The operation of negative bit-line boost circuits is complex due to the need to adapt to various memory sizes. For that matter, memory is typically sized according to its application, as some applications require more storage while others require less. Regarding the number of bit cells (and therefore the size of the memory), the bit cells are arranged in rows and columns. Each row is traversed by a corresponding word line. Similarly, corresponding bit-line pairs traverse each column. As the memory size increases, the number of bit cells in a given column will increase. However, custom-designing a memory for a given application is cumbersome. Therefore, a memory compiler that includes a fixed (uniformly sized) boost circuit that covers a certain range of column sizes is typically used (e.g., an example range could be 128 to 255 bit cells per column). The memory compiler generates a memory design based on the desired number of bit cells per column, but by reusing many common components (such as the boost circuit), this does not change the size for a given range of bit cells per column. When the number of bit cells per column increases beyond a given range, the memory compiler changes to a new design for subsequent ranges of column sizes. Therefore, input / output (I / O) breakpoints exist in the memory compiler. For example, when the number of bits per column increases to more than 255 bits, the memory compiler may switch to a new breakpoint and use a larger, fixed-size boost circuit. However, the boost circuit size will not change as long as a breakpoint for a given range of column sizes is not reached.

[0018] Since bit line capacitance increases with the number of bits per column, it is immediately apparent that the boost transistor should be sized to provide sufficient boost capacitance at the upper end of the column size range. For example, suppose the number of bits per column ranges from 65 to 128 bits. Since the bit cell size is fixed, the column length (and therefore the bit line capacitance) is at its maximum at the upper end of the bit cell range. Therefore, for a given range of column sizes between corresponding breakpoints in the memory compiler, the boost transistor is sized to provide sufficient negative boost at that maximum column size. The size of the boost transistor in a FinFET (Fin Field-Effect Transistor) implementation can be limited by the number of its fins. In such applications, the memory compiler can therefore implement the boost transistor using the same number of fins across the entire range of column sizes between breakpoints. However, this number of fins is sized to provide sufficient negative boost at the upper end of the column size range.

[0019] While such boost transistors will then provide sufficient negative boost at the upper end of the column size range, it's important to note that the bit line capacitance will be at its minimum at the lower end of the column size range. For example, if the column size range is from 65 to 128 bits, the minimum bit line capacitance will be when the column size is only 65 bits per column. Therefore, there is excessive negative boost capacitance at the lower end of the column size range because the boost transistors are sized to provide sufficient negative boost capacitance at the upper end of the column size range. This excessive negative boost capacitance causes power loss due to the resulting excessive negative boost on the bit lines and can also lead to reliability issues due to the excessive negative voltage on the bit lines.

[0020] One solution to the problem of excessive negative boost would be to drastically increase the number of breakpoints in the memory compiler to significantly reduce the column size range. However, this would significantly increase the complexity and cost of the memory compiler. This paper discloses a hybrid solution in which the memory compiler retains the traditional set of breakpoints but does not have excessive negative boost at the lower end of each column size range. As the name "hybrid" suggests, the negative boost is provided not only by traditional boost circuit capacitors (which are formed by boost transistors) but also by metal wire capacitors. Regarding metal wire capacitors, it should be noted that the active devices of the memory (such as transistors) are integrated into a semiconductor substrate. Adjacent to the semiconductor substrate are multiple metal layers separated by insulating dielectric layers. The metal layers are patterned, for example, by photolithography, into leads for various signals, power supplies, and grounds. For example, the metal layers (or more than one metal layer) can be patterned to form bit lines. At the lower end of the column size range between compiler breakpoints, the bit lines are relatively short, but grow longer and reach their maximum length at the upper end of the column size range. For example, if the column size ranges from 65 to 128 bits, the bit line will be shortest for a 65-bit column size and longest for a 128-bit column size. Advantageously, the metal-line capacitor is formed of a metal layer line that is substantially the same length as the bit line or has a length proportional to the bit line length. The capacitance of the metal-line capacitor will therefore scale proportionally with the column size, making the capacitance minimal for the smallest column size and maximum for the largest column size. Thus, there is sufficient negative bit-line boost for the largest column size, while excessive negative bit-line boost is not incurred for the smallest column size. Due to the benefits of the metal-line capacitor, the size of the boost transistor can be reduced to save semiconductor die space and reduce power consumption.

[0021] Figure 1 Example memory 100 is shown. For clarity, Figure 1Only a single input / output (IO) group of a column of bit cell 105 is shown. Write driver 120 receives a data input signal gdin to drive the write driver input signal (wdin) accordingly. Similarly, write driver 120 receives a complementary data input signal gdin_n to drive the complementary write driver input signal (wdin_n) accordingly. Column multiplexer 110 selects a column of bit cell 105 during a write operation to couple the write driver input signal to the bit line in the selected column. Similarly, column multiplexer 110 couples the complementary write driver input signal to the complementary bit line in the selected column. The number of columns multiplexed by column multiplexer 110 (and therefore the number of columns in a single IO group) depends on the specific memory implementation. In memory 100, column multiplexer 110 selects from four columns of bit cells 105 ranging from column zero (column 0) to column three (column 3), but it should be understood that different IO sizes, such as two columns or eight columns, may be used in alternative implementations.

[0022] The column multiplexer 110 responds to the column address signal WMWM<3:0> to select the appropriate column. Each column of the bit cell 105 is traversed by a pair of bit lines. For example, bit line BL <0> and complementary bit line BLB <0> They all traverse the length of the zeroth column. Similarly, the bit line BL... <1> and complementary bit line BLB <1> The length that crosses the first column, and the bit line BL <2> and complementary bit line BLB <2> The length across the second column. Finally, bit line BL. <3> and complementary bit line BLB <3> The length spans the third column. During a write operation, column multiplexer 110 couples the write driver input signal to the bit line in the selected column. Similarly, column multiplexer 110 couples the complementary write driver input signal to the complementary bit line in the selected column. Bit cells 105 are also arranged in rows, but for clarity, Figure 1 Only the first and last rows of bit cells 105 are shown in the image.

[0023] Depending on the binary value of the input data signal gdin, either the write driver input signal or the complementary write driver input signal is grounded during a write operation. As will be explained further herein, the negative bit-line hybrid boost circuit 115 operates during the negative bit-line boost cycle to provide a negative voltage to boost node 125. Boost node 125 is coupled to the grounded write driver input signal in the write driver input signal via write driver 120. For example, if the complementary write driver input signal is grounded during a write operation, the negative boost applied to boost node 125 will also provide a negative boost to the complementary write driver input signal. This negative boost is then coupled to the complementary bit line in the selected column via column multiplexer 110. If, conversely, the write driver input signal is grounded during a write operation, the bit line in the selected column will receive the negative bit-line boost.

[0024] To provide negative boost to boost node 125, negative bit line hybrid boost circuit 115 includes a boost transistor that acts as a boost capacitor. Figure 1 (Not illustrated herein, but discussed further herein). Without further examples, such boost capacitors would need to be sized to provide sufficient negative boost for the maximum desired column size. However, as previously discussed, such robust boost capacitors would then provide excessive negative boost for the minimum desired column size, which consumes power and can also cause reliability issues. However, the boost transistors in the negative bit-line hybrid boost circuit 115 can be sized to not even provide sufficient capacitance for the minimum desired column size, because the memory 100 also includes a metal line capacitor 101 formed by a boost metal line 145 and at least one aggressor metal line 140. The boost metal line 145 is also referred to herein as the first metal line. Similarly, at least one aggressor metal line is also referred to herein as at least one second metal line. The boost metal line 145 and the aggressor metal line 140 are patterned from the same metal layer and are sufficiently adjacent to each other to provide the desired boost capacitance. The boost metal line 145 is coupled to the boost node 125 and is therefore boosted to a negative voltage during the negative bit line boost cycle. Furthermore, the interfering metal line 140 and the boost metal line 145 may have lengths substantially similar to (or proportional to) the bit line length. In this way, the capacitance of the metal line capacitor 101 scales proportionally with the bit line length, ensuring that the resulting mixed negative bit line boost is sufficient and not excessive across the entire intended column size.

[0025] Figure 2The write driver 120 and the negative bit-line mixed boost circuit 115 are shown in more detail herein. As previously described, the boost signal to the negative bit-line mixed boost circuit 115 has a default grounded state, but in alternative embodiments a default charged state may be used. Inverter 205 inverts the boost signal to form an inverted boost signal (boost int), which drives the gate of an n-type metal-oxide-semiconductor (NMOS) transistor M1, which has a grounded source and a drain coupled to boost node 125. Transistor M1 is also referred to herein as a first transistor. Similarly, inverter 205 may also be referred to herein as a first inverter.

[0026] Because the discharged boost signal is inverted, the inverted boost signal is then asserted as the memory power supply voltage, which turns on transistor M1 to ground boost node 125. A pair of series inverters 210 and 215 form a buffered version of the inverted boost signal to drive boost capacitor node 230 formed by the drain and source of p-type metal-oxide-semiconductor (PMOS) transistor P1, which has a gate coupled to boost node 125. Transistor P1 is referred to herein as a boost transistor. Similarly, inverters 210 and 215 are also referred to as a second inverter and a third inverter, respectively. Thus, the gate capacitance of transistor P1 serves as the boost capacitor. When the boost signal is in its default discharged state, the drain and source of transistor P1 are charged to the memory power supply voltage, while the gate of transistor P1 is grounded.

[0027] During the negative bit-line boost cycle, the memory controller (not illustrated) asserts the boost signal as the memory power supply voltage. Therefore, the inverted boost signal is grounded during the negative bit-line boost cycle to turn off transistor M1. Due to the grounding of the inverted boost signal, boost capacitor node 230 (drain and source of transistor P1) is also grounded during the negative bit-line boost cycle. This discharge of the source / drain of transistor P1, due to the previously charged state of its gate capacitance, causes its gate (and therefore boost node 125) to be pulled to a negative voltage. It should be noted that transistor P1 may be too small relative to providing sufficient negative bit-line boost. For example, in a conventional (non-hybrid) FINFET implementation using boost capacitors in the column size range of 65 to 128 bit cells, 216 fins can be used to form transistor P1. However, in the negative bit-line hybrid boost circuit 115, only 52 fins can be used to form transistor P1 for the same column size range. Since each IO group in the column is associated with a corresponding boost circuit / boost capacitor combination, it can be understood that the use of the undersized transistor P1 in the resulting negative bit line hybrid boost circuit 115 advantageously reduces the occupied area (semiconductor die area) of the memory 100.

[0028] Transistor P1 may be sized too small because boost node 125 is also coupled to boost metal line 145, while intrusive metal lines are coupled to boost capacitor node 230. The resulting boost capacitance is a hybrid boost capacitance, as it is provided not only by transistor P1 but also by metal line capacitor 101. In one embodiment, intrusive metal lines may be formed by a first intrusive metal line 240 and a second intrusive metal line 241. The first intrusive metal line 240 is also referred to herein as a third metal line. Similarly, the second intrusive metal line 241 is also referred to herein as a fourth metal line. Both the first intrusive metal line 240 and the second intrusive metal line 241 may be formed in the same metal layer used to construct boost metal line 145. The first intrusive metal line 240 is adjacent to a first side of boost metal line 145, while the second intrusive metal line 241 is adjacent to a second side of boost metal line 145. Since the boost metal line 145 is coupled to the boost node 125 and the first interfering metal line 240 and the second interfering metal line 241 are coupled to the boost capacitor node 230, the metal line capacitor 101 functions similarly to the boost capacitor formed by the transistor P1 in providing a negative boost to the boost node 125. Specifically, the boost metal line 145 is grounded, while the first interfering metal line 240 and the second interfering metal line 241 are charged to the memory power supply voltage, while the boost signal is in its default grounded state. When the boost signal is asserted as the memory power supply voltage during a negative boost cycle, the first interfering metal line 240 and the second interfering metal line 241 are grounded so that the charged capacitance of the metal line capacitor 101 helps pull the boost node 125 to the desired negative voltage. Furthermore, although the size of the transistor P1 is fixed for a given column size range, the length of the metal line capacitor 101 is proportional to (or equal to) the bit line length. Therefore, the boost capacitance from the metal line capacitor 101 scales proportionally with the bit line length.

[0029] The write driver 120 can be implemented using an inverter 220 formed by PMOS transistor P2 and NMOS transistor M2, and an inverter 225 formed by PMOS transistor P3 and NMOS transistor M3. The sources of transistors M2 and M3 are coupled to the boost node 125. Similarly, the sources of transistors P2 and P3 are coupled to the node for the memory power supply voltage (VDD). Metal leads for the complementary write driver input signal (WDIN_N) are coupled to the drains of transistors P2 and M2. The data input signal (GDIN) drives the gates of transistors P2 and M2. If the data input signal is asserted, transistor M2 is turned on, grounding the complementary write driver input signal while the boost signal is in its default state. The complementary write driver input signal is then pulled to a negative boost voltage during the negative bit-line boost cycle (where the data input signal is asserted). See again. Figure 1The complementary write driver input signal is coupled to the complementary bit line in the selected column via column multiplexer 110. The complementary bit line in the selected column is then pulled to a negative boost voltage during the negative bit line boost cycle (where the data input signal is asserted).

[0030] Metal leads for the write driver input signal (wdin) are coupled to the drains of transistors P3 and M3. The complementary data input signal (gdin_n) drives the gates of transistors P3 and M3. If the complementary data input signal is asserted, transistor M3 is turned on, grounding the write driver input signal while the boost signal is in its default state. The write driver input signal is then pulled to a negative boost voltage during the negative bit-line boost cycle (where the complementary data input signal is asserted). See again. Figure 1 The write driver input signal is coupled to the bit line in the selected column via column multiplexer 110. Therefore, the bit line in the selected column is pulled to a negative boost voltage during the negative bit line boost cycle (where the complementary data input signal is asserted).

[0031] If the capacitance of transistor P1 is denoted as C1, and the capacitance of the boost capacitor extending across the length of one bit cell 105 is designated as C2, then the total boost capacitance is equal to C1 and N. The sum of C2, where N is the column size in the bit cell. Therefore, it is easy to understand that the total boost capacitor will scale proportionally with the column length.

[0032] The hybrid negative bit-line boost disclosed herein can be combined with hybrid word-line boost. For that matter, recall that bit cells 105 in memory 100 are arranged in rows. Corresponding word lines traverse each row to couple to a pair of NMOS access transistors (not illustrated) in each bit cell of that row. When the word line voltage is asserted as the memory supply voltage, the NMOS access transistors are turned on, allowing a write operation to change (if necessary) the binary content of the accessed bit cell 105. To assist with any resulting NMOS / PMOS contention (which can occur if the binary content of the accessed bit cell 105 is inverted), conventional word-line boost circuits include a boost transistor that acts as a word-line boost capacitor to boost the word line voltage above the memory supply voltage. However, for a given range of row sizes, as measured in the bit cells, memory compilers typically use fixed boost transistor sizes for word-line boost. The boost transistors are then sized to provide sufficient word-line boost at the upper end of the row size range. Then, at the lower end of the row size range, there may be excessive word line boosting, which increases power consumption and causes reliability issues. Regarding the row size, it can be scaled proportionally based on the same breakpoints used for the column size. For example, in one implementation, the breakpoint could start the row size range at 65 bits and extend to 128 bits. Starting from the breakpoint at 128 bits, another row size range could start at 129 bits and extend to 256 bits, and so on.

[0033] A word-line hybrid boost circuit is disclosed, which operates similarly to the one discussed for the negative bit-line hybrid boost circuit 115, as it includes a boost transistor serving as a boost capacitor, and also includes a metal line capacitor having a length proportional to (or the same as) the word line length. The metal line capacitor will thus scale proportionally according to the row size, such that the resulting word-line hybrid boost is sufficient and does not become excessive across the entire intended row size.

[0034] Figure 3An example memory 300 with a word-line hybrid boost circuit 301 is shown. A pair of series inverters 305 and 310 buffer the word-line boost signal to form a buffered word-line boost signal at node 355, coupled to the gate of a PMOS transistor P4. The word-line boost signal is grounded in its default state (although this can be inverted in an alternative embodiment), which turns on transistor P4. The source of transistor P4 is coupled to a node for the word-line supply voltage (Vdd). The drain of transistor P4 is coupled to a power input node for the word-line driver 330. The word-line driver 330 responds to the row address signal by charging the word line (WL) to the word-line supply voltage during a write operation. The word line is coupled to the access transistor (not illustrated) in the row of bit cell 335. For clarity, only a single row of bit cells 335 and the corresponding word-line driver 330 and word-line hybrid boost circuit 301 are shown for the memory 300. However, as discussed with respect to memory 100, memory 300 may include multiple rows of bit cells 335, each row having its own word line driver 330 and word line hybrid boost circuit 301.

[0035] When the word line is asserted to be the word line power supply voltage, the access transistor is turned on in the selected row, allowing a write operation to be performed on bit cell 335. To assist the write operation, the word line boost signal is charged to the word line power supply voltage during the word line boost cycle, which turns off transistor P4. The drain of transistor P4 is coupled to the drain and source of PMOS transistor P5, which serves as the word line boost capacitor. Node 355 is coupled to node 325 at the gate of transistor P5 via a pair of series inverters 315 and 320. With the word line boost signal in its default state, the gate of transistor P5 is therefore grounded, while the source and drain of transistor P5 are charged to the word line power supply voltage. Thus, the gate capacitance of transistor P5 is charged to the word line power supply voltage. The word line boost signal is then charged to the word line power supply voltage during the word line boost cycle, which can be substantially simultaneous with the negative bit line boost cycle. When the word line boost signal is asserted, transistor P4 is turned off after a propagation delay through inverters 305 and 310. After an additional propagation delay through inverters 315 and 320, the gate voltage of transistor P5 is charged to the word line supply voltage, which boosts the word line above the word line supply voltage.

[0036] Since the size of transistor P5 is fixed for a given compiler line size, the bit-line hybrid boost circuit also uses a metal line capacitor 340 formed by a boost metal line 345 and at least one interfering metal line 350. Similar to the word line, the boost metal line 345 and the interfering metal line 350 can be formed in a metal layer, for example, by photolithography. The boost metal line 345 is coupled to the source and drain of transistor P5 and thus connected to the word line voltage. The interfering metal line 350 is coupled to node 325 and thus connected to the gate voltage of transistor P5. When the word line boost signal is in its default state (discharged), the boost metal line 345 is charged to the word line supply voltage, while the interfering metal line 350 is grounded. After the word line boost signal is asserted as the word line power supply voltage, following a propagation delay through inverters 305, 310, 315, and 320, the charged capacitance of the metal line capacitor 340 boosts the boost metal line 345 (and therefore the word line voltage) above the word line power supply voltage. This boost is combined with a boost from the gate capacitance of transistor P5.

[0037] The metal line capacitor 340 extends across the word line to have a length substantially the same as or proportional to the word line length (the word line length can also be indicated as width, since the word line direction is orthogonal to the bit line direction). The capacitance of the metal line capacitor 340 scales proportionally with the word line size. Therefore, the word line boost from the metal line capacitor 340 will not be excessive at the lower end of the word line size range, nor insufficient at the higher end of the word line size range. In contrast to the metal line capacitor 340, the size of the transistor P5 is fixed across the word line size range. It should be understood that the negative bit line mixed boost discussed with respect to memory 100 can be combined with the word line mixed boost discussed with respect to memory 300. In other specific embodiments, only negative bit line boost or only word line mixed boost may be used in a given memory. For that matter, memory 100 and memory 300 may represent the same memory, or they may be different memories.

[0038] Now regarding Figure 4 The cross-sectional view discusses the metal line capacitors disclosed herein. Active devices for memory 400 (such as PMOS and NMOS transistors) are integrated into a semiconductor substrate 405. Above the semiconductor substrate 405 is a first metal layer 410, which has been etched away except for metal leads 416, which may be bit lines or word lines. Although the first metal layer 410 is shown as the metal layer closest to the substrate 405, it should be understood that the bit lines or word lines disclosed herein can be formed in any suitable metal layer. Furthermore, it should be understood that one or more other layers (e.g., the middle end of a line layer) may exist between the substrate 405 and the metal layer 410 (although in Figure 4(Not illustrated to avoid obscuring the figures). In addition to the boost metal line 425, the first interfering metal line 430, and the second interfering metal line 435, the second metal layer 420 is also etched away. The first interfering metal line 430 is adjacent to a first side of the boost metal line 425, while the second interfering metal line 435 is adjacent to a second side of the boost metal line 425. The combination of the boost metal line 425, the first interfering metal line 430, and the second interfering metal line 435 forms a metal line capacitor, such as for negative bit line mixed boost or word line mixed boost. Although the second metal layer 420 differs from the first metal layer 415, it should be understood that in alternative embodiments, the same metal layer can be used to form bit lines (or word lines) and corresponding metal line capacitors. An insulating dielectric layer separates the first metal layer 415 from the substrate 405 and the second metal layer 420. Note that metal layers 415 and 420 can be separated from each other by additional metal layers (not illustrated) and corresponding insulating dielectric layers.

[0039] Figure 5 A flowchart of a method for a negative bit-line hybrid boost converter is shown. The method includes the following action 500: responding to a first binary state of a boost signal by grounding the gate of a boost transistor, simultaneously grounding a first metal line coupled to the gate of the boost transistor, and simultaneously charging the drain and source of the boost transistor to a power supply voltage, while simultaneously charging at least one second metal line coupled to the drain and source of the boost transistor to a power supply voltage. An example of action 500 is the response of the negative bit-line hybrid boost circuit 115 to the grounding of the boost signal by charging the boost capacitor node 230 to the memory power supply and thus charging the drain and source of transistor P1 and the interfering metal lines 240 and 241. Similarly, the same example of action 500 also includes the simultaneous response of the negative bit-line hybrid boost circuit 115 to the grounding of the boost signal by grounding the gate of transistor P1 and the boost metal line 145.

[0040] The method also includes the following action 505: responding to a second binary state of a negative bit-line boost signal by grounding the drain and source of the boost transistor and grounding at least one second metal line to boost the bit line coupled to the gate of the boost transistor to a negative voltage. An example of action 505 is the response of a negative bit-line hybrid boost circuit 115 to charging a boost signal by grounding the boost capacitor node 230, and thus grounding the source and drain of transistor P1, and also grounding intrusion metal lines 240 and 241 to pull the bit line voltage below ground.

[0041] Memory systems with negative bit-line hybrid boost and / or word-line hybrid boost, as disclosed herein, can be incorporated into a wide variety of electronic systems. For example, such as Figure 6As shown, mobile phone 600, laptop computer 605, and tablet PC 610 may all include memory configured for mixed word line and / or bit line boosting. Other exemplary electronic systems such as music players, video players, communication devices, and personal computers may also be configured with memory constructed according to this disclosure.

[0042] This disclosure will now be outlined in the following exemplary terms: Clause 1. A memory comprising: Bit line; Negative line hybrid boost circuit, the negative line hybrid boost circuit includes: Boost transistor; and A metal wire capacitor comprising a first metal wire and at least one second metal wire extending adjacent to the first metal wire, wherein the first metal wire is coupled to the bit line and to the gate of the boost transistor, and wherein the at least one second metal wire is coupled to the drain and source of the boost transistor. Clause 2. The memory according to Clause 1, wherein the length of the metal wire capacitor is proportional to the length of the bit line. Clause 3. The memory according to Clause 2, wherein the length of the metal wire capacitor is substantially equal to the length of the bit line. Clause 4. The memory according to any one of Clauses 1 to 3, wherein the bit line is located within a first metal layer adjacent to a semiconductor substrate, and wherein the first metal line and the at least one second metal line are located within a second metal layer adjacent to the first metal layer. Clause 5. The memory according to Clause 4, wherein the at least one second metal line includes a third metal line extending adjacent to a first side of the first metal line, and includes a fourth metal line extending adjacent to a second side of the first metal line. Clause 6. The memory according to any one of Clauses 1 to 5, wherein the negative bit hybrid boost circuit further comprises: A first transistor, the first transistor having a drain coupled to the first metal line and a grounded source; and A first inverter, configured to invert a boost signal, and having an output terminal coupled to the gate of the first transistor. Clause 7. The memory according to Clause 6, wherein the negative bit hybrid boost circuit further comprises: A second inverter, which is connected in series with the first inverter; and A third inverter, connected in series with the second inverter, has an output terminal coupled to the at least one second metal line and to the source and drain of the boost transistor. Clause 8. The memory pursuant to Clause 7, wherein the boost transistor comprises a P-type metal-oxide-semiconductor (PMOS) transistor. Clause 9. The memory according to any one of Clauses 1 to 8, wherein the memory further comprises: Write to the drive; and A column multiplexer, wherein the bit lines are configured to be coupled to the negative bit line hybrid boost circuit via the column multiplexer and the write driver. Clause 10. The memory according to any one of Clauses 1 to 9, wherein the memory is static random access memory (SRAM). Clause 11. The memory according to any one of Clauses 1 to 10, wherein the memory further comprises: An array of bit cells arranged in columns and rows, wherein the bit lines are configured to extend across one of the columns. Clause 12. The memory according to any one of Clauses 1 to 11, wherein the memory is incorporated into a cellular phone. Clause 13. A negative line hybrid boost method, the negative line hybrid boost method comprising: The boost signal is responded to in a first binary state by grounding the gate of the boost transistor, grounding a first metal line coupled to the gate of the boost transistor, charging the drain and source of the boost transistor to the power supply voltage, and charging at least one second metal line coupled to the drain and source of the boost transistor to the power supply voltage; and The second binary state of the boost signal is responded to by grounding the drain and source of the boost transistor and grounding the at least one second metal line to boost the bit line coupled to the gate of the boost transistor to a negative voltage. Clause 14. The method according to Clause 13, wherein responding to the first binary state of the boost signal includes responding to grounding of the boost signal, and wherein responding to the second binary state of the boost signal includes responding to charging the boost signal to the power supply voltage. Clause 15. The method according to Clause 14, wherein responding to the grounding of the boost signal comprises: The boost signal is inverted to form an inverted boost signal at the gate of the first transistor coupled between the gate of the boost transistor and ground, and also coupled between the first metal line and ground, so as to turn on the first transistor, thereby grounding the gate of the boost transistor and also grounding the first metal line; and The inverted boost signal is buffered to form a buffered inverted boost signal, which is then charged to the power supply voltage to charge the drain and source of the boost transistor to the power supply voltage, and to charge the at least one second metal line to the power supply voltage. Clause 16. The method according to Clause 15, wherein responding to the charging of the boost signal comprises: Turn off the first transistor. Clause 17. A memory comprising: Word lines; A word line driver configured to charge the word line with a word line power supply voltage during a write operation; Word-line hybrid boost circuit, the word-line hybrid boost circuit comprising: Boost transistor; and A metal-line capacitor, wherein the word-line hybrid boost circuit is configured to boost the word-line power supply voltage using the gate capacitance of the boost transistor and the capacitance of the metal-line capacitor during a word-line boost cycle. Clause 18. The memory pursuant to Clause 17, the memory further includes: An array of bit cells arranged in rows and columns, wherein the word lines are configured to extend across rows, wherein the metal line capacitor includes a first metal line and at least one second metal line, the first metal line and the at least one second metal line each having a length proportional to the length of the word line. Clause 19. The memory according to Clause 18, wherein the length of the first metal line and the length of the at least one second metal line are both substantially equal to the length of the word line. Clause 20. The memory according to Clause 18, wherein a first boost metal line is coupled to the drain and source of the boost transistor and to the word line, and wherein the at least one second metal line is coupled to the gate of the boost transistor.

[0043] As those skilled in the art will understand to date and depending on the specific application at hand, many modifications, substitutions, and variations may be made to the materials, apparatus, configurations, and methods of using the devices disclosed herein without departing from the scope of this disclosure. Therefore, the scope of this disclosure should not be limited to the specific embodiments illustrated and described herein (as they are merely examples), but should be fully equivalent to the appended claims and their functional equivalents.

Claims

1. A memory, the memory comprising: Bit line; Negative line hybrid boost circuit, the negative line hybrid boost circuit includes: Boost transistor; and A metal wire capacitor comprising a first metal wire and at least one second metal wire extending adjacent to the first metal wire, wherein the first metal wire is coupled to the bit line and to the gate of the boost transistor, and wherein the at least one second metal wire is coupled to the drain and source of the boost transistor.

2. The memory according to claim 1, wherein, The length of the metal wire capacitor is proportional to the length of the bit line.

3. The memory according to claim 2, wherein, The length of the metal wire capacitor is substantially equal to the length of the bit line.

4. The memory according to claim 2, wherein, The bit line is located within a first metal layer adjacent to the semiconductor substrate, and wherein the first metal line and the at least one second metal line are located within a second metal layer adjacent to the first metal layer.

5. The memory according to claim 4, wherein, The at least one second metal wire includes a third metal wire extending adjacent to a first side of the first metal wire, and includes a fourth metal wire extending adjacent to a second side of the first metal wire.

6. The memory according to claim 1, wherein, The negative line hybrid boost circuit also includes: A first transistor, the first transistor having a drain coupled to the first metal line and a grounded source; and A first inverter, configured to invert a boost signal, and having an output terminal coupled to the gate of the first transistor.

7. The memory according to claim 6, wherein, The negative line hybrid boost circuit also includes: A second inverter, which is connected in series with the first inverter; and A third inverter, connected in series with the second inverter, has an output terminal coupled to the at least one second metal line and to the source and drain of the boost transistor.

8. The memory according to claim 7, wherein, The boost transistor includes a p-type metal-oxide-semiconductor (PMOS) transistor.

9. The memory according to claim 1, further comprising: Write to the drive; and A column multiplexer, wherein the bit lines are configured to be coupled to the negative bit line hybrid boost circuit via the column multiplexer and the write driver.

10. The memory according to claim 1, wherein, The memory is static random access memory (SRAM).

11. The memory according to claim 1, further comprising: An array of bit cells arranged in columns and rows, wherein the bit lines are configured to extend across one of the columns.

12. The memory according to claim 1, wherein, The memory is incorporated into the cellular phone.

13. A negative line hybrid boost method, the negative line hybrid boost method comprising: The first binary state of the boost signal is responded to by grounding the gate of the boost transistor, grounding the first metal line coupled to the gate of the boost transistor, charging the drain and source of the boost transistor to the power supply voltage, and charging at least one second metal line coupled to the drain and source of the boost transistor to the power supply voltage. as well as The second binary state of the boost signal is responded to by grounding the drain and source of the boost transistor and grounding the at least one second metal line to boost the bit line coupled to the gate of the boost transistor to a negative voltage.

14. The method according to claim 13, wherein, Responding to the first binary state of the boost signal includes responding to grounding of the boost signal, and wherein responding to the second binary state of the boost signal includes responding to charging the boost signal to the power supply voltage.

15. The method of claim 14, wherein, Responding to the grounding of the boost signal includes: The boost signal is inverted to form an inverted boost signal at the gate of the first transistor coupled between the gate of the boost transistor and ground, and also coupled between the first metal line and ground, so as to turn on the first transistor, thereby grounding the gate of the boost transistor and also grounding the first metal line; and The inverted boost signal is buffered to form a buffered inverted boost signal, which is then charged to the power supply voltage to charge the drain and source of the boost transistor to the power supply voltage, and to charge the at least one second metal line to the power supply voltage.

16. The method according to claim 15, wherein, Responding to the charging of the boost signal includes: Turn off the first transistor.

17. A memory, the memory comprising: Word lines; A word line driver configured to charge the word line with a word line power supply voltage during a write operation; Word-line hybrid boost circuit, the word-line hybrid boost circuit comprising: Boost transistor; and A metal-line capacitor, wherein the word-line hybrid boost circuit is configured to boost the word-line power supply voltage using the gate capacitance of the boost transistor and the capacitance of the metal-line capacitor during a word-line boost cycle.

18. The memory according to claim 17, further comprising: An array of bit cells arranged in rows and columns, wherein the word lines are configured to extend across rows, wherein the metal line capacitor includes a first metal line and at least one second metal line, the first metal line and the at least one second metal line each having a length proportional to the length of the word line.

19. The memory according to claim 18, wherein, The length of the first metal wire and the length of the at least one second metal wire are both substantially equal to the length of the word line.

20. The memory according to claim 18, wherein, The first metal line is coupled to the drain and source of the boost transistor and to the word line, and wherein the at least one second metal line is coupled to the gate of the boost transistor.

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