One-time programmable bitcell with thermal-enhanced breakdown

Abstract

Current can flow through a channel of an antifuse field effect transistor (FET) to raise a temperature of a gate dielectric of the antifuse FET and change a breakdown voltage of the gate dielectric of the antifuse FET from a first breakdown voltage to a second breakdown voltage. The gate dielectric can be broken down by applying a first voltage between the gate dielectric and the channel of the antifuse FET, where the first voltage is between the first breakdown voltage and the second breakdown voltage.

Description

Technical Field

[0001] This disclosure relates to electronic circuits. More specifically, this disclosure relates to a one-time programmable bit cell with thermally enhanced breakdown. Background Technology

[0002] One-time programmable (OTP) bit cells can be a type of non-volatile memory (NVM) that stores single-bit information and can be programmed so that the bit cell retains its state after the power is removed. Summary of the Invention

[0003] Current can flow through the channel of an antifuse field-effect transistor (FET) to raise the temperature of the gate dielectric of the antifuse FET and change the breakdown voltage of the gate dielectric of the antifuse FET from a first breakdown voltage to a second breakdown voltage. The gate dielectric can be broken down by applying a first voltage between the gate dielectric and the channel of the antifuse FET, wherein the first voltage is between the first breakdown voltage and the second breakdown voltage. A set of antifuse FETs can be selectively heated by allowing current to flow through the channel of the set to be broken down.

[0004] In some embodiments described herein, applying a first voltage between the gate dielectric and the channel of the antifuse FET can be performed simultaneously with allowing current to flow through the channel of the antifuse FET.

[0005] In some embodiments described herein, applying a first voltage between the gate dielectric and the channel of the antifuse FET can be performed after current has flowed through the channel of the antifuse FET.

[0006] In some embodiments described herein, the antifuse FET may be a p-channel metal-oxide-semiconductor (PMOS) FET. In some embodiments described herein, the antifuse FET may be an n-channel metal-oxide-semiconductor (NMOS) FET.

[0007] In some embodiments described herein, the antifuse FET may be a finned FET. In some embodiments described herein, the antifuse FET may be a gate-all-around (GAA) FET.

[0008] In some embodiments described herein, the antifuse FET may be part of a bit cell. The bit cell may include circuitry for: (1) allowing current to flow through the channel of the antifuse FET to raise the temperature of the gate dielectric of the antifuse FET and changing the breakdown voltage of the gate dielectric of the antifuse FET from a first breakdown voltage to a second breakdown voltage; and (2) breaking down the gate dielectric by applying a first voltage between the gate dielectric of the antifuse FET and the channel, wherein the first voltage is between the first breakdown voltage and the second breakdown voltage.

[0009] In some embodiments described herein, the circuit may include a first FET and a second FET. The source of the first FET may be electrically connected to the drain of the antifuse FET, and the source of the antifuse FET may be electrically connected to the drain of the second FET.

[0010] In some embodiments described herein, the antifuse FET may be a PMOS FET, and the circuit may include a first NMOS FET and a second NMOS FET. The gate of the antifuse FET may be electrically connected to the drain of the first NMOS FET, and the source of the antifuse FET may be electrically connected to the drain of the second NMOS FET.

[0011] In some embodiments described herein, the antifuse FET may be a PMOS FET, and the circuit may include a first PMOS FET, a first NMOS FET, and a second NMOS FET. The gate of the antifuse FET and the gate of the first PMOS FET may be electrically connected to the drain of the first NMOS FET, the source of the antifuse FET may be electrically connected to the drain of the first PMOS FET, and the source of the first PMOS FET may be electrically connected to the drain of the second NMOS FET.

[0012] In some embodiments described herein, the antifuse FET may be a PMOS FET, and the circuit may include a first NMOS FET, a second NMOS FET, and a third NMOS FET. The gate of the antifuse FET may be electrically connected to the drain of the first NMOS FET, the source of the antifuse FET may be electrically connected to the drain of the second NMOS FET, and the source of the second NMOS FET may be electrically connected to the drain of the third NMOS FET.

[0013] In some embodiments described herein, the antifuse FET may be an NMOS FET, and the circuit may include a first NMOS FET. The gate of the antifuse FET may be electrically connected to the drain of the antifuse FET, and the source of the antifuse FET may be electrically connected to the drain of the first NMOS FET.

[0014] In some embodiments described herein, the antifuse FET may be an NMOS FET, and the circuit may include a first PMOS FET and a second PMOS FET. The drain of the antifuse FET may be electrically connected to the source of the first PMOS FET, the gate of the antifuse FET may be electrically connected to the source of the second PMOS FET, the drain of the first PMOS FET may be electrically connected to the drain of the second PMOS FET, and the gate of the first PMOS FET may be electrically connected to the gate of the second PMOS FET. Attached Figure Description

[0015] This disclosure can be more fully understood from the detailed description given below and the accompanying drawings of embodiments thereof. The drawings are provided to give an understanding of the embodiments of this disclosure and are not intended to limit the scope of this disclosure to these specific embodiments. Furthermore, the drawings are not necessarily drawn to scale.

[0016] Figures 1A to 1B The implementation of bit cells according to some embodiments described herein is illustrated.

[0017] Figures 1C to 1F Cross-sectional views of FETs manufactured using different processes according to some embodiments described herein are shown.

[0018] Figures 2A to 2D A process for selective programming of antifuse FETs according to some embodiments described herein is illustrated.

[0019] Figure 3 An implementation of a bit cell array according to some embodiments described herein is shown.

[0020] Figures 4A to 4B The implementation of bit cells according to some embodiments described herein is illustrated.

[0021] Figures 5A to 5B The implementation of bit cells according to some embodiments described herein is illustrated.

[0022] Figures 6A to 6B The implementation of bit cells according to some embodiments described herein is illustrated.

[0023] Figures 7A to 7B The implementation of bit cells according to some embodiments described herein is illustrated.

[0024] Figures 8A to 8B The implementation of bit cells according to some embodiments described herein is illustrated.

[0025] Figure 9 The process of programming an antifuse FET according to some embodiments described herein is illustrated. Detailed Implementation

[0026] Various aspects of this disclosure relate to OTP bit cells with thermally enhanced breakdown. A bit cell may include one or more FETs, and each FET may include a source, a drain, and a gate. The FET may include a channel between the source and drain (the channel may be constructed of an n-type or p-type material). A dielectric material may separate the gate from the channel. The voltage difference between the gate and drain can be used to modulate the amount of current flowing through the channel.

[0027] OTP bit cells may include antifuse FETs. An antifuse FET may have: (1) a first state, wherein there is a high resistance between the gate and drain (or source or channel region); and (2) a second state, wherein there is a low resistance between the gate and drain (or source or channel region). The antifuse can transition from the first state to the second state when a voltage greater than the breakdown voltage is applied across the gate dielectric and the channel / source / drain. Specifically, when a sufficiently high voltage is applied across the dielectric, the dielectric can break down or break down (i.e., the physical properties of the dielectric material can change), causing the gate to be electrically connected to the channel through a low-resistance path in the dielectric material. In other words, when the dielectric material breaks down, a conductive filament is formed during the breakdown process, short-circuiting the gate to the channel, source, or drain.

[0028] If the semiconductor manufacturing process allows for various dielectric thicknesses, a thinner dielectric can be used in an antifuse FET, while a thicker dielectric can be used in other FETs. A voltage greater than the breakdown voltage of the antifuse FET can be used to break down the thinner dielectric in the antifuse FET.

[0029] Some semiconductor manufacturing processes (including, but not limited to, those used to manufacture nanowire transistors and / or nanosheet transistors) may allow only a single gate dielectric thickness. Furthermore, the smaller spacing between devices in such processes can result in circuits with poorer voltage tolerance. In such semiconductor manufacturing processes, it is difficult to protect other FETs (i.e., non-antifuse FETs) when the dielectric of an antifuse FET breaks down.

[0030] Input / output (I / O) devices can refer to FETs that can operate at higher voltages and currents compared to non-I / O devices (also known as core FETs). Ideally, I / O devices can be used to generate high voltages to break down the dielectric in an antifuse FET. However, some semiconductor manufacturing processes (which may include, but are not limited to, processes used to fabricate nanowire transistors and / or nanosheet transistors) do not allow I / O devices and non-I / O devices to be fabricated on the same die. In such cases, it may even be necessary to use more FETs in the peripheral circuitry to isolate the high voltage, ensuring that only the antifuse to be broken down withstands the full breakdown voltage. However, using multiple FETs increases the circuit area used to generate the breakdown voltage. In some processes, the breakdown voltage may be higher than the breakdown voltage of the source / drain-to-well diode. When the diode voltage is below the breakdown voltage, high leakage from previously programmed bits on the common line can lead to extremely large leakage currents, limiting the number of bits that can share the common line. This also necessitates the use of isolated wells to safely handle high voltages in the peripheral circuitry. All of the above issues increase the area required for memory circuit implementation.

[0031] Some embodiments described herein utilize the self-heating property of FETs to locally heat the dielectric in an antifuse FET, thereby reducing the voltage required to break down the dielectric. Thermal runaway can refer to a positive thermal feedback loop that occurs when the heat generated by the FET's self-heating exceeds the heat dissipated (e.g., through conduction). The term "self-heating" can refer to heat generated by the FET itself, rather than by other nearby devices. Thermal runaway in a FET can be triggered by a combination of factors, including: a large current flowing through the FET, a FET structure with good thermal insulation, and optional preheating of the FET. Some embodiments described herein induce thermal runaway in an antifuse FET, thereby increasing the temperature of the dielectric in the antifuse FET and reducing the breakdown voltage of the dielectric. A breakdown voltage V2 can be applied across the dielectric layer to break down the dielectric, wherein the breakdown voltage V2 is different from the breakdown voltage V1 required to break down the dielectric when it is not heated. Some embodiments described herein employ a single-step programming process: heating the dielectric in the antifuse FET while simultaneously applying the breakdown voltage to the heated dielectric. Some embodiments described herein employ a two-step programming process: in the first step, the dielectric in the antifuse FET is heated, and then in the second step, a breakdown voltage is applied across the dielectric.

[0032] The technical advantages of the embodiments described herein include, but are not limited to: (1) allowing the implementation of OTP bit cells in semiconductor manufacturing processes that allow only a single gate dielectric thickness; (2) allowing the implementation of OTP bit cells in semiconductor manufacturing processes that do not include I / O devices; (3) allowing the implementation of OTP bit cells in semiconductor manufacturing processes with smaller device pitch (and therefore less resistant to increased voltage); (4) reducing the circuit area required to generate the programming voltage for the OTP bit cells; and (5) allowing for simpler peripheral circuitry, as the low breakdown voltage does not require significant separation to prevent overstress in any peripheral devices.

[0033] Figures 1A to 1B The implementation of bit cells according to some embodiments described herein is illustrated.

[0034] Bit cell 100 may include FET 102, FET 104, and FET 106. FET 102 and FET 106 may be used as transfer transistors, and FET 104 may be used as an antifuse transistor. Signal 108 may be used to program and read the contents of bit cell 100. Specifically, signal 108 may include a word line read (WLR) signal, a fuse signal, a word line program (WLP) signal, a bit line read (BLR) signal, and a bit line program (BLP) signal. In this disclosure, solid dots indicate an electrical connection between two intersecting wires. For example, a wire carrying the WLP signal is electrically connected to the gate of FET 102, a wire carrying the fuse signal is electrically connected to the gate of FET 104, and a wire carrying the WLR signal is electrically connected to the gate of FET 106. Furthermore, a wire carrying the BLP signal is electrically connected to the source of FET 102, and a wire carrying the BLR signal is electrically connected to the drain of FET 106. The term "wire" generally refers to a conductive path in a circuit used to carry a signal. Examples of wires include, but are not limited to, structures made of doped polysilicon and metal traces in the metal layers of integrated circuits.

[0035] The WLR signal, BLR signal, and fuse signal can be used to read the state of bit cell 100 (i.e., programmed or unprogrammed), and the state of bit cell 100 can correspond to the bit value stored in the bit cell (e.g., 0 or 1). The WLR signal can be used to select a group of bit cells belonging to a word. The fuse signal can be maintained at a desired voltage (e.g., a voltage corresponding to 0 or 1). If the antifuse FET 104 is programmed (i.e., the dielectric of the antifuse FET 104 is broken down), path 110 has low resistance, meaning there is an electrical connection between the fuse lead and the BLR lead. On the other hand, if the antifuse FET 104 is not programmed (i.e., the dielectric of the antifuse FET 104 is not broken down), path 110 has high resistance, meaning there is no electrical connection between the fuse lead and the BLR lead. In other words, the voltage of the BLR signal will depend on whether the antifuse FET 104 is programmed. The WLP signal, BLP signal, and fuse signal can be used to program bit cell 100. References will follow below. Figures 2A to 2C A detailed explanation of the programming details for bit cell 100.

[0036] Figures 1C to 1F Cross-sectional views of FETs manufactured using different processes according to some embodiments described herein are shown. Figures 1C to 1F In the drawing, the X direction is from left to right, the Y direction is from bottom to top, and the Z direction is perpendicular to the drawing plane (i.e., the Z direction extends beyond the drawing plane).

[0037] Figure 1C A planar FET is shown, which includes a gate 124, a channel 122, and a dielectric 126 insulating the gate 124 from the channel 122. The channel 122 extends along the Z direction, and the source and drain terminals of the FET are located at the ends of the channel 122.

[0038] Figure 1D A finned FET is shown, which includes a gate 134, a channel fin 132, and a dielectric 136 insulating the gate 134 from the channel fin 132. The channel fin 132 extends along the Z direction, and the source and drain terminals of the finned FET are located at the ends of the channel fin 132.

[0039] Figure 1E A GAA FET is shown, which includes a gate 144, a channel 142, and a dielectric 146 insulating the gate 144 from the channel fin 142. The channel 142 extends along the Z-direction, and the source and drain terminals of the GAA FET are located at the ends of the channel 142. Figure 1E As shown, the gate 144 structure surrounds the channel 142 structure. Examples of GAA FET structures include, but are not limited to, nanowire-based FETs, nanoribbon-based FETs, and nanosheet-based FETs.

[0040] Figure 1F A stacked GAA FET is shown, comprising a gate 154, a channel 152, and a dielectric 156 insulating the gate 154 from the channel 152. The channel 152 extends along the Z-direction, and the source and drain terminals of the stacked GAA FET are located at the ends of the channel 152. Figure 1F As shown, p-channel GAA FETs and n-channel GAA FETs can be stacked one on top of the other.

[0041] The embodiments described herein are generally applicable to FETs manufactured using any process. When a voltage greater than the breakdown voltage is applied across the gate and channel of the FET, the dielectric material can break down. For example, in Figure 1E If a voltage greater than the breakdown voltage is applied across the gate 144 and the channel 142, the dielectric 146 may break down, and an electrical connection may be formed between the gate 144 and the channel 142.

[0042] Most of the heat can be dissipated through the source and drain electrodes, that is, along the... Figures 1C to 1F The heat is dissipated along the Z-direction through the channel. Some heat can also be dissipated along... Figure 1C Dissipation in the Y direction. However, in Figure 1D The finned FET structure shown and Figures 1E to 1F In the GAA FET structure shown, the heat dissipation along the Y direction is very small. Figures 1D to 1F Self-heating is a serious problem in the finned FET and GAA FET structures shown.

[0043] The embodiments described herein utilize the finding that self-heating in FETs can be advantageously used to reduce the breakdown voltage of antifuse FETs. Specifically, some embodiments described herein can selectively induce self-heating in the antifuse FET to be programmed.

[0044] Figures 2A to 2D A process for selective programming of antifuse FETs according to some embodiments described herein is illustrated.

[0045] exist Figure 2AIn this configuration, voltage 202 can be supplied to the signal conductors WLR, fuse, WLP, BLP, and BLR, allowing current to flow through the channels of FETs 102, FET 104, and FET 106, and causing self-heating in FETs 102, FET 104, and FET 106. Specifically, a Vinhibit V voltage can be supplied to the BLP conductor, a 0 V voltage to the BLR conductor, a (Vinhibit + VT:N) V voltage to the WLR conductor, a Vrupt V voltage to the fuse conductor, and a (Vinhibit + VT:N) V voltage to the BLP conductor. The value "VT:N" can refer to the threshold voltage of FETs 102 and FET 106 (i.e., FETs 102 and FET 106 are turned on when the gate-drain voltage is greater than or equal to VT:N). These voltage values ​​can turn on FETs 102, FET 104, and FET 106, allowing current to flow through their channels. The current can cause self-heating in FET 104, raising the temperature of the dielectric within it. Vrupt is the voltage difference that can cause the dielectric in FET 104 to break down when the temperature is sufficiently high (i.e., above the desired temperature). Vinhibit is a voltage less than Vrupt, for example, equal to half of Vrupt. Figure 2A In this context, the voltage difference between the gate and channel of FET 104 is less than Vrupt. Therefore, when an application such as Figure 2A At the voltage 202 shown, the dielectric of FET 104 will not break down. Furthermore, devices 102 and 106 can be optimized for higher current and lower resistance, outperforming device 104. Optimization can be achieved by using a wider channel width, a greater number of fins, or an increased number of fingers. Optimization can increase heat generation in antifuse device 104.

[0046] After the dielectric in FET 104 is heated to a temperature above the desired temperature, it can supply signal conductors WLR, fuse, WLP, BLP, and BLR. Figure 2BThe voltage 204 is shown. Voltage 204 can break down the dielectric in FET 104, but will not break down the dielectric in FET 102 and FET 106. Specifically, a voltage of 0 V can be applied to the BLP and BLR leads, a voltage of (Vinhibit + VT:N) V can be applied to the WLR lead, a voltage of Vrupt V can be applied to the fuse lead, and a voltage of (Vinhibit + VT:N) V can be applied to the BLP lead. These voltage values ​​can keep FET 102, FET 104, and FET 106 conducting, but since BLP and BLR are both 0 V, no current flows through FET 102, FET 104, and FET 106. Figure 2B In this context, the voltage difference between the gate and channel of FET 104 is equal to Vrupt. Therefore, when an application of... Figure 2B At the voltage of 204 shown, the dielectric of FET 104 can break down.

[0047] Figure 2C The diagram illustrates voltages that can be used to read bit cell contents, program bit cells, and disable bit cell programming. Column 252 specifies signal lines, column 254 specifies voltages that can be applied to signal lines to selected bit cells to read their contents, column 256 specifies voltages that can be applied to signal lines to selected bit cells to program them, and column 258 specifies voltages that can be applied to signal lines to unselected bit cells to disable their programming.

[0048] For example, to read a selected bit cell, column 254 specifies that for the selected bit cell, the BLR wire is pre-charged to 0 V (the term "pre-charge" can refer to gradually changing the voltage to the desired voltage using a pre-charge circuit, rather than suddenly setting the voltage to the desired value and causing a current spike), the BLP wire is set to 0 V, the WLR wire is set to VDD (the term "VDD" can refer to the positive supply voltage, for example, 5 V), the WLP wire is set to 0 V, and the fuse wire is set to VDD. Column 254 also specifies that for unselected bit cells (i.e., bit cells whose contents are not intended to be read), the BLR wire is pre-charged to 0 V, the BLP wire is set to 0 V, the WLR wire is set to 0 V, the WLP wire is set to 0 V, and the fuse wire is set to 0 V. Figure 2C The other columns can be interpreted in a similar way.

[0049] Figure 2D It shows the use of Figure 2CThe illustrated voltage represents the process of selectively programming bit cells in a bit cell array. Bit cell array 260 may include bit cells 262, 264, 266, and bit cell 100. A voltage of 0 V can be supplied to the WLR, fuse, and WLP wires of bit cells 262 and 264. Furthermore, a Vinhibit V voltage can be supplied to the BLP and BLR wires of bit cells 264 and 266. These voltages do not cause current to flow in the FETs in bit cells 262, 264, and 266. Therefore, the FETs in bit cells 262, 264, and 266 do not self-heat. Furthermore, these voltages ensure that the voltage difference between the gate and channel of the FETs in bit cells 262, 264, and 266 is less than Vrupt. Therefore, the dielectric of the FETs in bit cells 262, 264, and 266 does not break down. On the other hand, the dielectric of the antifuse FET in bit cell 100 can break down, as mentioned above. Figures 2A to 2B The explanation given.

[0050] Figure 3 An implementation of a bit cell array according to some embodiments described herein is shown.

[0051] Bit cell array 300 may include bit cells 302, 304, 306, and 308. In bit cell array 300, adjacent bit cells in the same row may share BLR wires. For example, bit cells 302 and 304 share the same BLR wire. Therefore, with... Figure 2D Compared to the implementation shown, Figure 3 The implementation shown can reduce the number of vertical wires. Specifically, Figure 2D The bit cell array 260 shown uses four vertical wires (two BLP wires and two BLR wires), while Figure 3 The bit cell array 300 shown employs three vertical conductors (two BLP conductors and one BLR conductor). However, Figure 3 The implementation shown may increase the number of horizontal wires. Specifically, Figure 2D Each row of bit cells in the bit cell array 260 shown uses a single WLR wire and a single WLP wire, while each row of bit cells in the bit cell array 300 uses two WLP wires (in Figure 3 (marked as WLP1 and WLP2) and two WLR conductors (in Figure 3 (These are labeled WLR1 and WLR2). Wires WLP1 and WLR1 can be used for bit cell 302, and wires WLP2 and WLR2 can be used for bit cell 304.

[0052] Figures 4A to 4BImplementations of bit cells according to some embodiments described herein are illustrated. Some embodiments may simultaneously heat the antifuse and apply stress to the gate dielectric. This avoids the need for stopping the heating operation and the potential temperature drop after applying gate stress. Furthermore, if the breakdown voltage after heating is approximately equal to the inhibit voltage of the unheated device, the antifuse to be broken down can be selected by heating. In this case, the same breakdown voltage can be applied to the bit cell to be programmed and the unprogrammed (inhibited) bit cell, the only difference being that the cell to be programmed is heated. Heating causes breakdown to occur even at the inhibit voltage (i.e., in some embodiments, heating can selectively cause breakdown to occur in the bit cell to be programmed). One advantage of this method is that it simplifies the peripheral circuitry, as the peripheral circuitry does not need to switch additional voltages (e.g., Vinhibit in addition to Vrupt). Peak electrical stress in the antifuse may occur between the gate and source, or between the gate and drain.

[0053] Bit cell 400 may include a PMOS antifuse FET 402, and NMOS FETs 404 and 406. The WLP wire may be electrically connected to the drain of the PMOS antifuse FET 402, the source of the PMOS antifuse FET 402 may be electrically connected to the drain of the NMOS FET 406, and the source of the NMOS FET 406 may be electrically connected to VSS (the term "VSS" may refer to ground (0V) or a negative supply voltage, such as -5V). The gate of the PMOS antifuse FET 402 may be electrically connected to the drain of the NMOS FET 404, and the source of the NMOS FET 404 may be electrically connected to the BLR wire. The gate of the NMOS FET 406 may be electrically connected to the BLP wire, and the gate of the NMOS FET 404 may be electrically connected to the WLR wire.

[0054] Figure 4B The voltages that can be used to read the contents of bit cell 400, program bit cell 400, and disable programming bit cell 400 (e.g., when programming other bit cells besides bit cell 400 is selected) are shown. Figure 4B The columns in can be ordered with Figure 2C The columns shown are interpreted in a similar manner. Specifically, column 452 specifies the signal wire, column 454 specifies the voltage that can be applied to the signal wire of the selected bit cell to read the contents of the selected bit cell, column 456 specifies the voltage that can be applied to the signal wire of the selected bit cell to program the selected bit cell, and column 458 specifies the voltage that can be applied to the signal wire of the unselected bit cell to prevent the programming of the unselected bit cell.

[0055] Bit cell 400 can be programmed in a single step (unlike the two-step programming process used in bit cell 100). Specifically, to program the selected bit cell, the voltages in column 456 can be used. The BLR wire is set to 0 V, the BLP wire to VDD, the WLR wire to VDD, and the WLP wire to Vrupt. NMOS FET 404 is turned on (i.e., the channel of NMOS FET 404 is conductive, and the voltage drop across the channel is very low) because the gate of NMOS FET 404 is at VDD and the source of NMOS FET 404 is at 0 V. Therefore, the gate voltage of PMOS antifuse FET 402 (electrically connected to the drain of NMOS FET 404) is close to 0 V. PMOS antifuse FET 402 is turned on because the gate of PMOS antifuse FET 402 is close to 0 V and the drain of PMOS antifuse FET 402 is at Vrupt. NMOS FET 406 is turned on because its gate is at VDD and its source is at VSS. Therefore, current flows from the WLP conductor to the VSS conductor, passing through the channel of the PMOS antifuse FET 402 and the channel of the NMOS FET 406.

[0056] When both the PMOS antifuse FET 402 and NMOS FET 406 are in the ON state, the drain-source impedance of the PMOS antifuse FET 402 may be greater than that of the NMOS FET 406. Therefore, a large portion of the voltage between Vrupt (the voltage across the WLP wire) and VSS drops across the channel of the PMOS antifuse FET 402. In some variations of this unit device 406, device 406 is designed to carry a larger current. For example, device 406 may be wider, have more fins, or more fingers. In other words, the voltage across the gate and channel of the PMOS antifuse FET 402 is close to or equal to Vrupt. On the other hand, the voltage across the gate and channel of the NMOS FET 406 is less than Vrupt. The current flowing through the channel of the PMOS antifuse FET 402 can cause self-heating in the PMOS antifuse FET 402, thereby raising the dielectric temperature of the PMOS antifuse FET 402. As the dielectric temperature of the PMOS antifuse FET 402 increases, the breakdown voltage of the dielectric changes. When the temperature is high enough, the voltage across the gate and channel of the PMOS antifuse FET 402 can cause the dielectric of the PMOS antifuse FET 402 to break down.

[0057] Figures 5A to 5BThe implementation of a bit cell according to some embodiments described herein is illustrated. The devices in this bit cell can be optimized to maximize heat generation. Heat is primarily conducted upwards through the source and drain via the metal stack. When two devices are coupled in series, heat that would otherwise be conducted away from one device will flow into the other connected in series. Heat generation can be maximized by connecting devices in series, in parallel, or both. Other layout modifications that can increase the antifuse temperature can also be employed.

[0058] Bit cell 500 may include PMOS antifuse FETs 502 and 508, and NMOS FETs 404 and 406. PMOS antifuse FETs 502 and 508 may be series coupled, meaning the source of PMOS antifuse FET 502 may be electrically connected to the drain of PMOS antifuse FET 508. The WLP wire may be electrically connected to the drain of PMOS antifuse FET 502, the source of PMOS antifuse FET 502 may be electrically connected to the drain of NMOS FET 506, and the source of NMOS FET 506 may be electrically connected to VSS. The gates of PMOS antifuse FETs 502 and 508 may be electrically connected to the drain of NMOS FET 504, and the source of NMOS FET 504 may be electrically connected to the BLR wire. The gate of NMOS FET 506 may be electrically connected to the BLP wire, and the gate of NMOS FET 504 may be electrically connected to the WLR wire.

[0059] Figure 5B The voltages that can be used to read the contents of bit cell 500, program bit cell 500, and disable programming bit cell 500 (e.g., when programming other bit cells besides bit cell 500 is selected) are shown. Figure 5B The columns in can be ordered with Figure 2C The columns shown are interpreted in a similar manner. Specifically, column 552 specifies the signal wire, column 554 specifies the voltage that can be applied to the signal wire of the selected bit cell to read the contents of the selected bit cell, column 556 specifies the voltage that can be applied to the signal wire of the selected bit cell to program the selected bit cell, and column 558 specifies the voltage that can be applied to the signal wire of the unselected bit cell to disable the programming of the unselected bit cell.

[0060] Bit cell 500 operates similarly to bit cell 400. Bit cell 500 includes two series-coupled PMOS antifuse FETs 502 and 508 (unlike the single PMOS antifuse FET 402 in bit cell 400). Using two series-coupled PMOS antifuse FETs 502 and 508 allows for self-heating with lower current and breakdown of at least one of the PMOS antifuse FETs 502 and 508. Bit cell 500 can be programmed by breaking down only the dielectric of PMOS antifuse FET 502, only the dielectric of PMOS antifuse FET 508, or both.

[0061] Figures 6A to 6B The implementation of a bit cell according to some embodiments described herein is illustrated. In some cases, stress on other devices besides the antifuse in the bit cell can become problematic. If the breakdown voltage is high enough, a programmed bit cell sharing a WLP line with the bit cell being programmed may damage one of the other devices. To reduce the voltage on the gate of any selected device, the device can be replaced with a pair of devices, with the voltage distributed between the two devices, which can prevent device overstress.

[0062] Bit cell 600 may include a PMOS antifuse FET 602 and NMOS FETs 604, 606, and 608. NMOS FETs 606 and 608 may be series-coupled, meaning the source of NMOS FET 606 may be electrically connected to the drain of NMOS FET 608. The WLP wire may be electrically connected to the drain of PMOS antifuse FET 602, the source of PMOS antifuse FET 602 may be electrically connected to the drain of NMOS FET 606, and the source of NMOS FET 608 may be electrically connected to VSS. The gate of PMOS antifuse FET 602 may be electrically connected to the drain of NMOS FET 604, and the source of NMOS FET 604 may be electrically connected to the BLR wire. The gate of NMOS FET 606 may be electrically connected to the BLP2 wire, the gate of NMOS FET 608 may be electrically connected to the BLP1 wire, and the gate of NMOS FET 604 may be electrically connected to the WLR wire.

[0063] Figure 6B The voltages that can be used to read the contents of bit cell 600, program bit cell 600, and disable programming bit cell 600 (e.g., when programming other bit cells besides bit cell 600 is selected) are shown. Figure 6B The columns in can be ordered with Figure 2CThe columns shown are interpreted in a similar manner. Specifically, column 652 specifies the signal wire, column 654 specifies the voltage that can be applied to the signal wire of the selected bit cell to read the contents of the selected bit cell, column 656 specifies the voltage that can be applied to the signal wire of the selected bit cell to program the selected bit cell, and column 658 specifies the voltage that can be applied to the signal wire of the unselected bit cell to prevent the programming of the unselected bit cell.

[0064] Bit cell 600 operates similarly to bit cell 400. Bit cell 600 includes two NMOS FETs 606 and 608, instead of the single NMOS FET 406 in bit cell 400. Using two NMOS FETs 606 and 608 connected in series reduces the gate-channel voltage in both NMOS FETs 606 and 608, thus preventing breakdown of the dielectric in the two NMOS FETs 606 and 608 during bit cell 600 programming. Bit cell 600 is programmed similarly to bit cell 400, for example, by allowing current to flow through the channel of PMOS antifuse FET 602 to heat the dielectric of PMOS antifuse FET 602, while simultaneously applying a gate-channel voltage greater than the breakdown voltage to PMOS antifuse FET 602.

[0065] Figures 7A to 7B The implementation of bit cells according to some embodiments described herein is illustrated.

[0066] Bit cell 700 may include an NMOS antifuse FET 702, and NMOS FETs 704 and 706. The WLP wire may be electrically connected to the drain and gate of the NMOS antifuse FET 702. The source of the NMOS antifuse FET 702 may be electrically connected to the drain of the NMOS FET 706, and the source of the NMOS FET 706 may be electrically connected to VSS. The drain of the NMOS FET 706 may also be electrically connected to the drain of the NMOS FET 704, and the source of the NMOS FET 704 may be electrically connected to the BLR wire. The gate of the NMOS FET 706 may be electrically connected to the BLP wire, and the gate of the NMOS FET 704 may be electrically connected to the WLR wire.

[0067] Figure 7B The voltages that can be used to read the contents of bit cell 700, program bit cell 700, and disable programming bit cell 700 (e.g., when programming other bit cells besides bit cell 700 is selected) are shown. Figure 7B The columns in can be ordered with Figure 2CThe columns shown are interpreted in a similar manner. Specifically, column 752 specifies signal wires, column 754 specifies the voltage that can be applied to the signal wires of selected bits to read the contents of the selected bits, column 756 specifies the voltage that can be applied to the signal wires of selected bits to program the selected bits, and column 758 specifies the voltage that can be applied to the signal wires of unselected bits to prevent programming of the unselected bits. Figure 7B In this context, voltage “X” refers to “don’t care” voltage, meaning that the voltage can be equal to 0 V, VDD, or any value in between.

[0068] The operation of bit cell 700 can be similar to that of bit cell 400. For example, bit cell 700 can be programmed using the voltage in column 756 by the following steps: (1) allowing a large current to flow through the channel of NMOS antifuse FET 702 to heat the dielectric of NMOS antifuse FET 702; and (2) simultaneously applying a gate-source voltage to NMOS antifuse FET 702, wherein the gate-source voltage is greater than or equal to the breakdown voltage.

[0069] Figures 8A to 8B The implementation of bit cells according to some embodiments described herein is illustrated.

[0070] Bit cell 800 may include an NMOS antifuse FET 802, an NMOS FET 804, and PMOS FETs 806 and 808. The WLP wire may be electrically connected to the drain of PMOS FETs 806 and 808. The gates of PMOS FETs 806 and 808 may be electrically connected to the BLP wire. The source of PMOS FET 806 may be electrically connected to the drain of NMOS antifuse FET 802, and the source of PMOSFET 808 may be electrically connected to the gate of NMOS antifuse FET 802. The source of NMOS antifuse FET 802 may be electrically connected to VSS. The gate of NMOS antifuse FET 802 may also be electrically connected to the drain of NMOS FET 804, and the source of NMOSFET 804 may be electrically connected to the BLR wire.

[0071] Figure 8B The voltages that can be used to read the contents of bit cell 800, program bit cell 800, and disable programming bit cell 800 (e.g., when programming other bit cells besides bit cell 800 is selected) are shown. Figure 8B The columns in can be ordered with Figure 2CThe columns shown are interpreted in a similar manner. Specifically, column 852 specifies signal wires, column 854 specifies the voltage that can be applied to the signal wires of selected bits to read the contents of the selected bits, column 856 specifies the voltage that can be applied to the signal wires of selected bits to program the selected bits, and column 858 specifies the voltage that can be applied to the signal wires of unselected bits to prevent programming of the unselected bits. Figure 8B In this context, voltage “X” refers to “irrelevant” voltage, meaning that the voltage can be equal to 0 V, VDD, or any value in between.

[0072] The operation of bit cell 800 can be similar to that of bit cell 400. For example, bit cell 800 can be programmed using the voltage in column 856 by the following steps: (1) allowing a large current to flow through the channel of NMOS antifuse FET 802 to heat the dielectric of NMOS antifuse FET 802; and (2) simultaneously applying a gate voltage to NMOS antifuse FET 802, wherein the gate voltage is greater than or equal to the breakdown voltage.

[0073] Figure 9 The process of programming an antifuse FET according to some embodiments described herein is illustrated.

[0074] Current is allowed to flow through the channel of the antifuse FET to raise the temperature of the gate dielectric of the antifuse FET and change the breakdown voltage of the gate dielectric of the antifuse FET from the first breakdown voltage to the second breakdown voltage (step 902).

[0075] The gate dielectric can be broken down by applying a first voltage between the gate dielectric and the channel of the antifuse FET, wherein the first voltage is between a first breakdown voltage and a second breakdown voltage (step 904). For example, the first breakdown voltage can be 10V, the second breakdown voltage can be 5V, and the first voltage can be 7V. The gate dielectric can be broken down by simultaneously or synchronously applying a large current to the channel of the device and applying a high voltage across a portion of the gate of the device. For a PMOS antifuse, the gate breakdown voltage is lower than the source voltage of the antifuse device. For an NMOS antifuse, the gate breakdown voltage is equal to or higher than the source voltage of the antifuse. In some embodiments, the channel current can be applied first, followed by the gate stress. In some embodiments described herein, a set of antifuse FETs can be selectively heated by allowing current to flow through the channel of the set of antifuse FETs to be broken down. Specifically, in some embodiments described herein, the same voltage can be applied to the antifuse FETs to be broken down and the antifuse FETs not intended to be broken down, and only the selectively heated antifuse FETs will break down.

[0076] In some embodiments described herein, applying a first voltage between the gate dielectric and the channel of the antifuse FET can be performed after current has flowed through the channel of the antifuse FET. For example, Figures 2A to 2B The antifuse FET 104 in the reference can be programmed using a two-step process, as shown in the reference. Figures 2A to 2C As described.

[0077] In some embodiments described herein, applying a first voltage between the gate dielectric and the channel of the antifuse FET can be performed simultaneously with allowing current to flow through the channel of the antifuse FET. For example, Figure 4A Bit unit 400 in the middle Figure 5A Bit unit 500 in the middle Figure 6A Bit unit 600 in the middle Figure 7A Bit unit 700 and Figure 8A The antifuse FETs in bit cell 800 can all be programmed using a single-step process, as shown in the reference. Figures 4A to 8B As described.

[0078] In some embodiments described herein, the antifuse FET may be a PMOS FET. For example, Figure 4A Bit unit 400 in the middle Figure 5A Bit unit 500 and Figure 6A The antifuse FETs in bit cell 600 are all PMOS FETs.

[0079] In some embodiments described herein, the antifuse FET may be an NMOS FET. For example, Figure 7A Bit unit 700 and Figure 8A The antifuse FETs in bit cell 800 are all NMOS FETs.

[0080] In some embodiments described herein, the antifuse FET can be as follows: Figure 1D The finned FET shown. In some embodiments described herein, the antifuse FET can be as follows: Figures 1E to 1F The example shown is a gate all around (GAA) FET.

[0081] In some embodiments described herein, and as such Figure 2A , Figure 4A , Figure 5A , Figure 6A , Figure 7A and Figure 8AAs shown, the antifuse FET can be part of a bit cell, and the bit cell can include circuitry to: (1) allow current to flow through the channel of the antifuse FET to raise the temperature of the gate dielectric of the antifuse FET and change the breakdown voltage of the gate dielectric of the antifuse FET from a first breakdown voltage to a second breakdown voltage; and (2) break down the gate dielectric by applying a first voltage between the gate dielectric and the channel of the antifuse FET, wherein the first voltage is between the first breakdown voltage and the second breakdown voltage.

[0082] In some embodiments described herein, the circuit may include a first FET (e.g., Figure 2A FET 102 in the middle) and the second FET (e.g., Figure 2A FET 106 in the example). The source of the first FET can be electrically connected to the antifuse FET (e.g., FET 106 in the example). Figure 2A The drain of the FET 104 in the second FET is connected to the source of the antifuse FET, and the source of the antifuse FET can be electrically connected to the drain of the second FET.

[0083] In some embodiments described herein, the antifuse FET may be a PMOS FET (e.g., Figure 4A The circuit may include a PMOS antifuse FET 402, and may include a first NMOS FET (e.g., Figure 4A The NMOS FET 404 in the middle) and the second NMOS FET (e.g., Figure 4A (NMOS FET 406 in the example). The gate of the antifuse FET can be electrically connected to the drain of the first NMOS FET, and the source of the antifuse FET can be electrically connected to the drain of the second NMOS FET.

[0084] In some embodiments described herein, the antifuse FET may be a PMOS FET (e.g., Figure 5A The circuit may include a first PMOS FET (e.g., PMOS antifuse FET 502), and the circuit may include a first PMOS FET (e.g., Figure 5A The PMOS FET 508 in the first NMOS FET (e.g., the first NMOS FET) Figure 5A The NMOS FET 504 in the middle) and the second NMOS FET (e.g., Figure 5A (NMOS FET 506 in the example). The gate of the antifuse FET and the gate of the first PMOS FET can be electrically connected to the drain of the first NMOS FET, the source of the antifuse FET can be electrically connected to the drain of the first PMOS FET, and the source of the first PMOS FET can be electrically connected to the drain of the second NMOS FET.

[0085] In some embodiments described herein, the antifuse FET may be a PMOS FET (e.g., Figure 6A The circuit may include a PMOS antifuse FET 602, and may include a first NMOS FET (e.g., Figure 6A NMOS FET 604 in the middle), and the second NMOS FET (e.g., Figure 6A The NMOS FET 606 and the third NMOS FET (e.g., Figure 6A (NMOS FET 608 in the example). The gate of the antifuse FET can be electrically connected to the drain of the first NMOS FET, the source of the antifuse FET can be electrically connected to the drain of the second NMOS FET, and the source of the second NMOS FET can be electrically connected to the drain of the third NMOS FET.

[0086] In some embodiments described herein, the antifuse FET may be an NMOS FET (e.g., Figure 7A The circuit may include a first NMOS FET (e.g., NMOS antifuse FET 702), and the circuit may include a first NMOS FET (e.g., NMOS antifuse FET 702). Figure 7A (NMOS FET 706 in the example). The gate of the antifuse FET can be electrically connected to the drain of the antifuse FET, and the source of the antifuse FET can be electrically connected to the drain of the first NMOSFET.

[0087] In some embodiments described herein, the antifuse FET may be an NMOS FET (e.g., Figure 8A The circuit may include an NMOS antifuse FET 802, and may include a first PMOS FET (e.g., Figure 8A The PMOS FET 806 in the middle) and the second PMOS FET (e.g., Figure 8A (PMOS FET 808 in the example). The drain of the antifuse FET can be electrically connected to the source of the first PMOS FET, the gate of the antifuse FET can be electrically connected to the source of the second PMOS FET, the drain of the first PMOS FET can be electrically connected to the drain of the second PMOS FET, and the gate of the first PMOS FET can be electrically connected to the gate of the second PMOS FET.

[0088] In some embodiments described herein, the stress (leading to breakdown) originates from the gate-to-source or gate-to-drain junction, rather than the gate-to-channel junction. In some embodiments described herein, the bit cell has parallel-arranged high-current metal traces. Some processes feature a back-side interconnect structure where one metal stack is optimized for power (low resistance) and another for signal transmission (low capacitance). When back-side metal is available, high-current signals can ideally be routed in parallel to utilize the optimized high-current metal layers, such as... Figures 4A to 4B , Figures 5A to 5B , Figures 6A to 6B , Figures 7A to 7B and Figures 8A to 8B As shown. In processes without two stacked metal layers, high-current lines can be routed vertically.

[0089] In some embodiments, device dimensions can be optimized to maximize the current flowing through the antifuse FET, thereby maximizing the heat generated in the antifuse FET and ensuring that other devices do not overheat. In some embodiments, additional devices can be added to the bit cell to reduce stress on the select device. The select device includes the device in the bit cell for connecting the antifuse. These additional devices can be used to implement a cascaded or common-source structure of the device.

[0090] In the foregoing disclosure, implementations of this disclosure have been described with reference to specific exemplary embodiments. It will be apparent that various modifications can be made to this disclosure without departing from the broader spirit and scope of the implementations set forth in the appended claims. When this disclosure refers to certain elements in a singular form, more than one element may be shown in the drawings, and the same element may be labeled with the same reference numerals. Therefore, this disclosure and the drawings should be considered illustrative rather than restrictive.

Claims

1. A method comprising: The current flows through the channel of the antifuse field-effect transistor (FET) to raise the temperature of the gate dielectric of the antifuse FET and change the breakdown voltage of the gate dielectric of the antifuse FET from a first breakdown voltage to a second breakdown voltage. as well as The gate dielectric is broken down by applying a first voltage between the gate dielectric and the channel of the antifuse FET, wherein the first voltage is between a first breakdown voltage and a second breakdown voltage.

2. The method of claim 1, wherein applying the first voltage between the gate dielectric and the channel of the antifuse FET is performed simultaneously with causing the current to flow through the channel of the antifuse FET.

3. The method of claim 1, wherein applying the first voltage between the gate dielectric and the channel of the antifuse FET is performed after the current flows through the channel of the antifuse FET.

4. The method according to claim 1, wherein the antifuse FET is a p-channel metal-oxide-semiconductor FET.

5. The method according to claim 1, wherein the antifuse FET is an n-channel metal-oxide-semiconductor FET.

6. The method of claim 1, wherein the antifuse FET is a full-around gate FET.

7. The method of claim 1, wherein the set of antifuse FETs is selectively heated by allowing current to flow through the channel of the set of antifuse FETs to be broken down.

8. A bit unit, comprising: Anti-fuse field-effect transistor (FET); as well as Circuit, used for: The current flows through the channel of the antifuse FET to raise the temperature of the gate dielectric of the antifuse FET and change the breakdown voltage of the gate dielectric of the antifuse FET from a first breakdown voltage to a second breakdown voltage. as well as The gate dielectric is broken down by applying a first voltage between the gate dielectric and the channel of the antifuse FET, wherein the first voltage is between a first breakdown voltage and a second breakdown voltage.

9. The bit cell of claim 8, wherein the circuit includes a first FET and a second FET, wherein the source of the first FET is electrically connected to the drain of the antifuse FET, and wherein the source of the antifuse FET is electrically connected to the drain of the second FET.

10. The bit cell of claim 8, wherein the antifuse FET is a p-channel metal-oxide-semiconductor (PMOS) FET, wherein the circuit includes a first n-channel metal-oxide-semiconductor (NMOS) FET and a second NMOS FET, wherein the gate of the antifuse FET is electrically connected to the drain of the first NMOS FET, and wherein the source of the antifuse FET is electrically connected to the drain of the second NMOS FET.

11. The bit cell of claim 8, wherein the antifuse FET is a p-channel metal-oxide-semiconductor (PMOS) FET, wherein the circuit includes a first PMOS FET, a first n-channel metal-oxide-semiconductor (NMOS) FET and a second NMOS FET, wherein the gate of the antifuse FET is electrically connected to the drain of the first NMOS FET and the gate of the first PMOS FET, wherein the source of the antifuse FET is electrically connected to the drain of the first PMOS FET, and wherein the source of the first PMOS FET is electrically connected to the drain of the second NMOS FET.

12. The bit cell of claim 8, wherein the antifuse FET is a p-channel metal-oxide-semiconductor (PMOS) FET, wherein the circuit includes a first n-channel metal-oxide-semiconductor (NMOS) FET, a second NMOS FET and a third NMOS FET, wherein the gate of the antifuse FET is electrically connected to the drain of the first NMOS FET, wherein the source of the antifuse FET is electrically connected to the drain of the second NMOS FET, and wherein the source of the second NMOS FET is electrically connected to the drain of the third NMOS FET.

13. The bit cell of claim 8, wherein the antifuse FET is an n-channel metal-oxide-semiconductor (NMOS) FET, wherein the circuit includes a first NMOS FET, wherein the gate of the antifuse FET is electrically connected to the drain of the antifuse FET, and wherein the source of the antifuse FET is electrically connected to the drain of the first NMOS FET.

14. The bit cell of claim 8, wherein the antifuse FET is an n-channel metal-oxide-semiconductor (NMOS) FET, wherein the circuit includes a first p-channel metal-oxide-semiconductor (PMOS) FET and a second PMOS FET, wherein the drain of the antifuse FET is electrically connected to the source of the first PMOS FET, wherein the gate of the antifuse FET is electrically connected to the source of the second PMOS FET, wherein the drain of the first PMOS FET is electrically connected to the drain of the second PMOS FET, and wherein the gate of the first PMOS FET is electrically connected to the gate of the second PMOS FET.

15. A non-volatile memory, comprising: Anti-fuse field-effect transistor (FET); as well as Circuit, used for: A current is allowed to flow through the channel of the antifuse FET, the current raising the temperature of the gate dielectric of the antifuse FET and changing the breakdown voltage of the gate dielectric of the antifuse FET from a first breakdown voltage to a second breakdown voltage; The gate dielectric is broken down by applying a first voltage between the gate dielectric and the channel of the antifuse FET, wherein the first voltage is between a first breakdown voltage and a second breakdown voltage; and The application of the first voltage between the gate dielectric and the channel of the antifuse FET is performed simultaneously with the flow of the current through the channel of the antifuse FET.

16. The non-volatile memory of claim 15, wherein the antifuse FET is a p-channel metal-oxide-semiconductor (PMOS) FET, wherein the circuit includes a first n-channel metal-oxide-semiconductor (NMOS) FET and a second NMOSFET, wherein the gate of the antifuse FET is electrically connected to the drain of the first NMOS FET, and wherein the source of the antifuse FET is electrically connected to the drain of the second NMOS FET.

17. The non-volatile memory of claim 15, wherein the antifuse FET is a p-channel metal-oxide-semiconductor (PMOS) FET, wherein the circuit includes a first PMOS FET, a first n-channel metal-oxide-semiconductor (NMOS) FET and a second NMOS FET, wherein the gate of the antifuse FET is electrically connected to the drain of the first NMOS FET along with the gate of the first PMOS FET, wherein the source of the antifuse FET is electrically connected to the drain of the first PMOS FET, and wherein the source of the first PMOS FET is electrically connected to the drain of the second NMOS FET.

18. The non-volatile memory of claim 15, wherein the antifuse FET is a p-channel metal-oxide-semiconductor (PMOS) FET, wherein the circuit includes a first n-channel metal-oxide-semiconductor (NMOS) FET, a second NMOSFET, and a third NMOS FET, wherein the gate of the antifuse FET is electrically connected to the drain of the first NMOS FET, wherein the source of the antifuse FET is electrically connected to the drain of the second NMOS FET, and wherein the source of the second NMOS FET is electrically connected to the drain of the third NMOS FET.

19. The non-volatile memory of claim 15, wherein the antifuse FET is an n-channel metal-oxide-semiconductor (NMOS) FET, wherein the circuit includes a first NMOS FET, wherein the gate of the antifuse FET is electrically connected to the drain of the antifuse FET, and wherein the source of the antifuse FET is electrically connected to the drain of the first NMOS FET.

20. The non-volatile memory of claim 15, wherein the antifuse FET is an n-channel metal-oxide-semiconductor (NMOS) FET, wherein the circuit includes a first p-channel metal-oxide-semiconductor (PMOS) FET and a second PMOSFET, wherein the drain of the antifuse FET is electrically connected to the source of the first PMOS FET, wherein the gate of the antifuse FET is electrically connected to the source of the second PMOS FET, wherein the drain of the first PMOS FET is electrically connected to the drain of the second PMOSFET, and wherein the gate of the first PMOS FET is electrically connected to the gate of the second PMOS FET.

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