Circuit board and semiconductor package comprising the same

Abstract

Embodiments of the present invention disclose a circuit board, comprising: a first insulating layer; a second insulating layer arranged on the first insulating layer; a first conductive part pad arranged between the first insulating layer and the second insulating layer; a second conductive part pad arranged between the first conductive part pad and an upper surface of the second insulating layer; a first conductive part electrode arranged between the first conductive part pad and the upper surface of the second insulating layer; a second conductive part electrode arranged between the second conductive part pad and the upper surface of the second insulating layer; and a third conductive part electrode arranged between a lower surface of the first insulating layer and the upper surface of the second insulating layer, wherein a thickness of the first conductive part electrode, a thickness of the second conductive part electrode and a thickness of the third conductive part electrode are different from each other.

Description

Technical Field

[0001] An embodiment of the present invention relates to a circuit board and a semiconductor package. Background Technology

[0002] With the improvement of the performance of electrical / electronic products, techniques for attaching a greater number of packages to substrates with limited dimensions have been proposed and studied. However, since a typical package is basically configured to mount a semiconductor chip on it, there are limitations in obtaining the desired performance.

[0003] A typical circuit board or packaging substrate has a processor package on which a processor chip is mounted and a memory package on which a memory chip is attached, connected as a single unit. By manufacturing the processor chip and memory chip into an integrated package, this type of packaging substrate has the advantages of reducing the chip mounting area and enabling high-speed signal transmission through short paths. Due to these advantages, the packaging substrate described above is widely used in mobile devices and the like.

[0004] On the other hand, recently, due to the higher specifications of electronic devices such as mobile devices and the adoption of high-bandwidth memory (HBM), package size has increased. Furthermore, as the required functions of application processors increase, a circuit board is needed that can mount processor chips configured individually for their respective functions. In this case, even when application processors are divided into two processor chips for their respective functions, the number of (input / output) terminals on each processor chip is increasing.

[0005] Furthermore, recently, due to factors such as 5G, the Internet of Things (IoT), improved image quality, and increased communication speeds, the number of terminals on processor chips has been gradually increasing along with the number of power lines and signal lines. Consequently, the area and thickness of circuit boards, as well as the density of circuit patterns, are also increasing. When the area and thickness of circuit boards increase, issues arise such as difficulties in product miniaturization, reliability problems like circuit board warping, and increased product costs. Therefore, in terms of product cost, reliability issues such as warping, and product miniaturization, increasing the density of circuit patterns is more advantageous than increasing the area and thickness of the circuit board. Therefore, miniaturization of circuit patterns or through electrodes is required.

[0006] In particular, there is a need to improve the reliability of the circuit board and the performance of the electrical connection with the die. Summary of the Invention

[0007] Technical issues

[0008] Embodiments of the present invention provide a circuit board that facilitates electrical connection with an upper die, and a semiconductor package including the circuit board.

[0009] Alternatively, embodiments may provide a circuit board that reduces capacitance variation by adjusting the area of ​​the conductive pads, and a semiconductor package including the circuit board.

[0010] Alternatively, embodiments may provide a circuit board that improves integration, increases input / output counts, and reduces signal loss through an embedded capacitor structure, as well as a semiconductor package including the circuit board.

[0011] Alternatively, embodiments may provide a circuit board and a semiconductor package including the circuit board, wherein the generation of voids or gaps at the interface between insulating layers is suppressed by additionally providing conductive pads instead of conductive electrodes that pass through multiple insulating layers.

[0012] Alternatively, embodiments may provide a circuit board that improves electrical connection reliability through additional conductive pads, and a semiconductor package including the circuit board.

[0013] The problems to be solved by the embodiments are not limited to those described herein, and may also include objects or effects that can be understood from the solutions or embodiments described below.

[0014] Technical solution

[0015] A circuit board according to an embodiment of the present invention includes: a first insulating layer; a second insulating layer disposed on the first insulating layer; a first conductive pad disposed between the first insulating layer and the second insulating layer; a second conductive pad disposed between the first conductive pad and the upper surface of the second insulating layer; a first conductive electrode disposed between the first conductive pad and the upper surface of the second insulating layer; a second conductive electrode disposed between the second conductive pad and the upper surface of the second insulating layer; a third conductive electrode disposed between the lower surface of the first insulating layer and the upper surface of the second insulating layer; and a dielectric layer disposed between the first conductive pad and the second conductive pad, wherein the dielectric layer overlaps the first and second insulating layers in the horizontal direction, and the thicknesses of the first conductive electrode, the second conductive electrode, and the third conductive electrode are different from each other.

[0016] The thickness of the first conductive electrode can be greater than the thickness of the second conductive electrode.

[0017] The thickness of the third conductive electrode can be greater than the thickness of the second conductive electrode.

[0018] The third conductive electrode can pass through the second insulating layer and extend into a portion of the first insulating layer.

[0019] The first conductive electrode can overlap with the second conductive electrode in the horizontal direction.

[0020] The third conductive electrode can overlap with the first and second conductive electrodes in the horizontal direction.

[0021] The area of ​​the upper surface of the first conductive pad can be larger than the area of ​​the upper surface of the second conductive pad.

[0022] The thickness of the first conductive pad can be different from the thickness of the second conductive pad.

[0023] The width of each of the first conductive electrode and the second conductive electrode can gradually decrease from the upper surface of the second insulating layer toward the lower surface of the second insulating layer.

[0024] The width of the third conductive electrode can gradually decrease from the upper surface of the second insulating layer toward the lower surface of the first insulating layer.

[0025] The first conductive electrode may have a minimum first width at the upper surface of the first insulating layer, the second conductive electrode may have a minimum second width at the lower surface of the second insulating layer, and the third conductive electrode may have a minimum third width in the region adjacent to the lower surface of the first insulating layer.

[0026] The first width can be smaller than the second width.

[0027] The third width can be smaller than the first width.

[0028] The circuit board may include a capacitor structure, which includes a first conductive pad, a dielectric layer, and a second conductive pad sequentially stacked on a first insulating layer.

[0029] The second conductive electrode can be disposed on the capacitor structure.

[0030] The first conductive electrode can pass through the capacitor structure.

[0031] Beneficial effects

[0032] Embodiments of the present invention may provide a circuit board that facilitates electrical connection with an upper die, and a semiconductor package including the circuit board.

[0033] Alternatively, embodiments may provide a circuit board that reduces capacitance variation by adjusting the area of ​​the conductive pads, and a semiconductor package including the circuit board.

[0034] Alternatively, embodiments may provide a circuit board that improves integration, increases input / output counts, and reduces signal loss through an embedded capacitor structure, as well as a semiconductor package including the circuit board.

[0035] Alternatively, embodiments may provide a circuit board and a semiconductor package including the circuit board, wherein the generation of voids or gaps at the interface between insulating layers is suppressed by providing additional conductive pads instead of conductive electrodes that pass through multiple insulating layers.

[0036] Alternatively, embodiments may provide a circuit board that improves electrical connection reliability through additional conductive pads, and a semiconductor package including the circuit board.

[0037] The various useful advantages and effects of the present invention are not limited to those described above, and will be more readily understood in the process of describing specific embodiments of the invention. Attached Figure Description

[0038] Figure 1 This is a cross-sectional view of a circuit board according to a first embodiment of the present invention.

[0039] Figure 2 yes Figure 1 A magnified view of part K1 in the image.

[0040] Figure 3 yes Figure 1 A magnified view of part K2 in the image.

[0041] Figure 4 This is a plan view of the first conductive electrode, the second conductive electrode, the first conductive pad, and the second conductive pad in the circuit board according to the embodiment.

[0042] Figure 5 This is a cross-sectional view of a circuit board according to a second embodiment of the present invention.

[0043] Figure 6 yes Figure 5 A magnified view of part K3 in the image.

[0044] Figure 7 This is a plan view of the first conductive electrode, the second conductive electrode, the first conductive pad, and the second conductive pad in the circuit board according to the second embodiment.

[0045] Figure 8 It is a cross-sectional view of the first conductive electrode, the second conductive electrode, the first conductive pad, and the second conductive pad in the circuit board according to the modified example.

[0046] Figure 9It is a plan view of the first conductive part electrode, the second conductive part electrode, the first conductive part pad, and the second conductive part pad in the circuit board according to the modified example.

[0047] Figure 10 This is a cross-sectional view of a circuit board according to a third embodiment of the present invention.

[0048] Figure 11 yes Figure 10 A magnified view of part K4 in the image.

[0049] Figures 12a to 12o This is a diagram illustrating a method for manufacturing a circuit board according to a third embodiment.

[0050] Figure 13 This is a schematic diagram of a semiconductor package according to an embodiment. Detailed Implementation

[0051] Since the present invention can have various modifications and several embodiments, specific embodiments are shown and described in the accompanying drawings. However, this is not intended to limit the invention to the specific embodiments, and it should be understood to include all modifications, equivalents, and substitutions contained within the spirit and scope of the invention.

[0052] Although terms including ordinal numbers (e.g., first and second) can be used to describe various components, these components are not limited by these terms. These terms are used only to distinguish one component from another. For example, without departing from the scope of the invention, a second component may be referred to as a first component, and similarly, a first component may be referred to as a second component. The term "and / or" includes any combination of multiple related descriptive terms, or any one of multiple related descriptive terms.

[0053] It should be understood that when a component is referred to as "connected" or "joined" to another component, the component can be directly connected or joined to the other component, or an intermediate component may exist between them. On the other hand, it should be understood that when a component is referred to as "directly connected" or "directly joined" to another component, there is no intermediate component between them.

[0054] The terminology used in this application is for describing specific embodiments only and is not intended to limit the invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. It should be understood in this application that the terms "comprising" or "having" are intended to indicate the presence of features, quantities, steps, operations, components, portions, or combinations thereof described in the specification, but do not preclude the possibility of the presence or addition of one or more other features, numbers, steps, operations, components, portions, or combinations thereof.

[0055] Unless otherwise defined, all terms used herein (including technical or scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. Terms as defined in common dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the relevant field, and shall not be interpreted in an idealized or overly formal sense unless otherwise expressly defined in this application.

[0056] In the following description, embodiments will be described in detail with reference to the accompanying drawings, in which the same reference numerals are used for the same or corresponding parts throughout the drawings, and redundant descriptions of these parts will be omitted.

[0057] Before describing the embodiments, an electronic device using a circuit board and semiconductor package according to the embodiments will be briefly described. The electronic device includes a motherboard (not shown). The motherboard may be physically and / or electrically connected to various components. For example, the motherboard may be connected to the semiconductor package of the embodiments. The semiconductor package may also include a circuit board, a plurality of semiconductor devices disposed on the circuit board, and connection members electrically connecting the plurality of semiconductor devices.

[0058] The circuit board may include multiple stacked insulating layers, a circuit pattern disposed in each of the multiple stacked insulating layers, and conductive electrodes for connecting the circuit pattern disposed in each insulating layer.

[0059] Semiconductor devices can be mounted on a circuit board and can be semiconductor chips in the form of integrated circuits (ICs), in which hundreds to millions or more active and / or passive devices are integrated into a single chip. For example, a semiconductor device can be a logic chip, a memory chip, etc. A logic chip can be a central processing unit (CPU), a graphics processing unit (GPU), etc. For example, a logic chip can be an application processor (AP) chip that includes at least one of a CPU, GPU, digital signal processor, encryption processor, microprocessor, and microcontroller; it can be an analog-to-digital converter, an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), etc.; or it can be a chipset that includes a specific combination of the items listed above. Additionally, a semiconductor device can be a memory device such as high-bandwidth memory (HBM).

[0060] Connectors are components designed to electrically connect multiple semiconductor devices and can be positioned between the semiconductor devices and a circuit board. For example, connectors can be embedded in or mounted on a circuit board. When embedded in a circuit board, they can have the advantage of reducing the thickness of the semiconductor package. Connectors can be made of silicon, but are not limited to it, and can also be made of organic materials. Because connectors are used to electrically interconnect multiple semiconductor devices, they can be referred to as "bridges."

[0061] Additionally, the connecting member can be disposed on the circuit board. When mounted on the circuit board, the connecting member can be covered by the molding member, and the circuit board, semiconductor device, and connecting member can be electrically interconnected through a through-mold via (TMV) passing through the molding member. Furthermore, a redistribution layer can be further disposed between the molding member and the semiconductor device.

[0062] On the other hand, the product group of semiconductor packaging using this embodiment can be any of chip scale package (CSP), flip chip-scale package (FC-CSP), flip chip ball grid array (FC-BGA), package on package (POP), and system in package (SIP), but the present invention is not limited thereto.

[0063] In addition, electronic devices can be smartphones, personal digital assistants, digital cameras, digital still cameras, vehicles, high-performance servers, network systems, computers, monitors, tablets, laptops, netbooks, televisions, video game consoles, smartwatches, automotive equipment, etc. However, electronic devices are not limited to these; they can certainly be any other electronic device that processes data, besides those listed above.

[0064] A circuit board according to an embodiment of the present invention may include a core layer, a first build-up layer disposed on one surface of the core layer, and a second build-up layer disposed on the other surface of the core layer. Furthermore, the first and second build-up layers may each include multiple stacked insulating layers. However, the circuit board is not limited thereto and may be configured without a core layer, and may include the first and / or second build-up layers. That is, the circuit board may consist of a first build-up layer, a core layer, and an insulating layer of the second and / or first and / or second build-up layers. Additionally, the first and second build-up layers may be distinguished from each other by a structure in which the expansion directions of the conductive portions in the layers are opposite to each other. For example, in the first build-up layer, the width or area of ​​the via may increase (or enlarge) upwards. Additionally, in the second build-up layer, the width or area of ​​the conductive portion may decrease (or increase) upwards. Furthermore, each build-up layer may correspond to an insulating layer other than the core layer. A detailed description will be given below.

[0065] Figure 1 This is a cross-sectional view of a circuit board according to a first embodiment of the present invention. Figure 2 yes Figure 1 A magnified view of part of K1, Figure 3 yes Figure 1 A magnified view of part of K2, Figure 4 This is a plan view of the first conductive electrode, the second conductive electrode, the first conductive pad, and the second conductive pad in the circuit board according to this embodiment.

[0066] Reference Figure 1 According to the first embodiment, the circuit board 100 may include an insulating layer 110, an electrode portion 120, and a capacitor structure CAS. Furthermore, the circuit board 100 may also include a protective layer disposed on the electrode portion 120 or a core layer serving as an insulating layer disposed in the insulating layer 110.

[0067] The insulating layer 110 may include multiple layers. The insulating layer 110 may include a first insulating layer 111, a second insulating layer 112, a third insulating layer 113, and a fourth insulating layer 114.

[0068] The fourth insulating layer 114, the third insulating layer 113, the first insulating layer 111, and the second insulating layer 112 can be arranged sequentially in the stacking direction or the vertical direction (X-axis direction). In other words, the fourth insulating layer 114, the third insulating layer 113, the first insulating layer 111, and the second insulating layer 112 can be stacked sequentially.

[0069] The insulation layer 110 may comprise a thermosetting resin such as epoxy resin or a thermoplastic resin such as polyimide. In addition to the resin, the insulation layer 110 may also comprise a reinforcing material. The reinforcing material may include, for example, fabric reinforcement materials, inorganic fillers, etc. The fabric reinforcement material may be glass fiber that can be impregnated with resin to form a prepreg (PPG).

[0070] For example, the insulating layer 110 can be formed of any insulating resin such as a thermosetting resin and / or a photocurable resin. As a thermosetting resin, Ajinomoto Build-up Film (ABF) (a product of Ajinomoto Co., Ltd.) can be used, and materials such as prepreg (PPG) including glass fibers can be used. As a photocurable resin, any insulating resin can be used, such as photoimageable dielectric (PID) resin. Any of the aforementioned insulating resins can be, for example, epoxy resin, bismaleimide triazine resin (BT resin), phenolic resin, etc., and can contain inorganic fillers such as silica. When the insulating resin is used as a core, the insulating resin can contain reinforcing materials such as glass fibers, aramid fibers, etc. For example, the insulating layer 110 can use ABF, a product of Ajinomoto Co., Ltd., and FR-4, BT, PID resin, BT, etc. can also be used. For example, the insulating layer 110 can include multiple layers composed of ABF.

[0071] Insulating layers can be formed from the same or different materials. For example, a second insulating layer can be formed from the same or different material as the other insulating layer.

[0072] Additionally, a protective layer may be provided on the uppermost or lowermost surface of the insulating layer 110. The protective layer (not shown) can be used to protect the pads from external moisture or contaminants, preventing short circuits when semiconductor devices and / or motherboards are bonded to the circuit board. As an example, the protective layer (not shown) may be formed of a solder resist. Specifically, the semiconductor device, motherboard, etc., includes multiple terminals for connection to the circuit board. Furthermore, the multiple terminals may be arranged in a high density. As an example, solder can be used when the multiple terminals are bonded to pads on the circuit board. When solder is used, short circuits may occur between the high-density terminals, and to address this problem, a solder resist with poor wetting properties relative to the solder can be provided. Additionally, the protective layer (not shown) may be formed of a material having insulating properties for electrical connection. Therefore, the protective layer (not shown) may be referred to as an "insulating layer" and may be one of the components of the aforementioned insulating layer. The protective layer (not shown) may contain resin, curing agent, photoinitiator, pigment, solvent, filler, additive, acrylic monomer, etc. Furthermore, the third insulating layer (not shown) may contain any one of a photoresist layer, a cover layer, and a polymer material.

[0073] Additionally, the insulating or protective layer (not shown) located in the outer stacked area of ​​the circuit board may include openings. These openings allow for electrical connections to other semiconductor devices or circuit boards.

[0074] The electrode section 120 may include a circuit pattern (or a circuit pattern layer), pads, and conductive electrodes. Wiring may correspond to "electrode pattern," "pattern," "line," etc.

[0075] In this embodiment, the electrode portion 120 may include wiring electrodes and conductive electrodes. The wiring electrodes may include wiring (or circuit patterns) and pads disposed on the insulating layer. The conductive electrodes may be located in vias or vertical interconnect access (VIA) holes formed in the insulating layer. Electrical connections can be achieved through conductive electrodes located within, above, or below the insulating layer.

[0076] The electrode section 120 may include a first electrode section 121, a second electrode section 122, a third electrode section 123, a fourth electrode section 124, a fifth electrode section 125, and a sixth electrode section 126. Each electrode section may include a wiring section and a conductive section electrode.

[0077] The first electrode portion 121 may be located on the second insulating layer 112. The second electrode portion 122 may be located on the second insulating layer 112. The third electrode portion 123 may be located on the first insulating layer 111 and the second insulating layer 112. Additionally, the fourth electrode portion 124 may be located on the third insulating layer 113. The fifth electrode portion 125 may be located on the fourth insulating layer 114. The sixth electrode portion 126 may be located on the first insulating layer 111. Furthermore, additional electrode portions may be further provided in each insulating layer. These will be described in detail below.

[0078] Furthermore, the first electrode portion 121 may include a first conductive electrode 121a and a first wiring portion 121b. Additionally, the second electrode portion 122 may include a second conductive electrode 122a and a second wiring portion 122b. The third electrode portion 123 may include a third conductive electrode 123a and a third wiring portion 123b. Furthermore, the fourth electrode portion 124 may include a fourth conductive electrode 124a and a fourth wiring portion 124b. Additionally, the fifth electrode portion 125 may include a fifth conductive electrode 125a and a fifth wiring portion 125b. The sixth electrode portion 126 may include a sixth conductive electrode 126a and a sixth wiring portion 126b.

[0079] Furthermore, the external pads of the electrode portion 120 can be bonded to semiconductor devices, substrates, boards, etc., using solder, wires, or conductive adhesive, and can be configured to have a width larger than the width of the circuit pattern to address issues such as ensuring yield. However, the external pads are not limited to this, and can have the same width as the circuit pattern depending on the technical limitations of the bonding process.

[0080] The pads located on the inner side are used to connect the conductive electrodes to the circuit pattern. When the width of the conductive electrode is set to be greater than the width of the circuit pattern, pads with a width greater than the width of the circuit pattern are provided to ensure positional alignment during the manufacturing process where conductive electrodes need to be placed on each circuit pattern. Therefore, each conductive electrode may have an upper surface coplanar with the lower surface of the upper pad and a lower surface coplanar with the upper surface of the lower pad, with the lower surface of the upper pad in direct contact with the conductive electrode and the upper surface of the lower pad in direct contact with the lower surface of the conductive electrode. Here, the lower surface of the upper pad and the upper surface of the lower pad do not necessarily refer to flat surfaces, but should be understood to include concave or convex surfaces depending on various processes.

[0081] In addition, semiconductor devices can be mounted in or on a circuit board. Semiconductor devices can be logic chips, memory chips, etc.

[0082] The capacitor structure CAS can be located on the first insulating layer 111. Alternatively, the capacitor structure CAS can be located between the first insulating layer 111 and the second insulating layer 112. In addition, the capacitor structure CAS can be covered by the second insulating layer 112.

[0083] According to an embodiment, the capacitor structure CAS may include a first conductive pad VL1, a dielectric layer DL, and a second conductive pad VL2. In the capacitor structure CAS, the first conductive pad VL1, the dielectric layer DL, and the second conductive pad VL2 may be stacked or arranged sequentially in the vertical direction (X-axis direction). The second conductive pad VL2 may be located above the first conductive pad VL1. For example, the second conductive pad VL2 may be located between the first conductive pad VL1 and the upper surface US2 of the second insulating layer 112. The first conductive pad VL1 and the second conductive pad VL2 may be directly connected to the conductive electrode. Through the first conductive pad VL1 and the second conductive pad VL2, functions such as ensuring the positional alignment of the conductive electrode and the function of circuits electrically connected to the conductive electrode can be realized. Furthermore, in this case, the "conductive pad" may be an electrode, such as one electrode (layer) and another electrode (layer) of a capacitor structure used as a capacitor. Furthermore, although a single conductive electrode is shown connected to each of the first and second conductive pads of the capacitor, one or more conductive electrodes may be connected thereto depending on the circuit connection.

[0084] Furthermore, as the processor in the electronic device or package substrate continues to draw more power, initial power droop and power transfer noise can pose challenges. Specifically, initial power droop can occur when circuitry in a die or semiconductor device pulls power. To mitigate this initial power droop, capacitors can be added to the circuit board on which the die or semiconductor device is mounted, as in the embodiment. In particular, it may be desirable to add capacitors near the die or semiconductor device, which is a source of power droop. In this case, when the capacitor is located on the die side or pad side of the board, the electrical path between the die and the capacitor on the pad side (or die side) becomes longer, and the additional effect of the capacitor may be reduced due to additional factors such as parasitic inductance. Additionally, pad-side capacitors can cause interference at the interface between the circuit board and the package substrate.

[0085] Therefore, by embedding the capacitor structure in the circuit board beneath the die, as in this embodiment, power drop and power transfer noise can be suppressed. Additionally, capacitance can be increased by applying a dielectric layer DL with a high dielectric constant. Furthermore, in this embodiment, the capacitor structure can have any suitable shape and size. For example, in a plan view, the capacitor structure can have a rectangular or circular shape. Furthermore, the capacitor structure can be positioned anywhere on the circuit board. For example, to reduce the electrical path length, the capacitor structure can be located on a layer adjacent to the upper die in the circuit board. In other words, by placing the capacitor structure in the region of the insulating layer adjacent to the die, electrical performance degradation can be reduced.

[0086] Further reference Figure 2 In the circuit board 100 according to this embodiment, the second insulating layer 112 may be disposed on the first insulating layer 111. Furthermore, the first conductive pad VL1 may be located between the first insulating layer 111 and the second insulating layer 112.

[0087] In this embodiment, the positions of the first conductive electrode 121a, the second conductive electrode 122a, and the third conductive electrode 123a in the vertical direction can also be different from each other. Furthermore, the first conductive electrode 121a, the second conductive electrode 122a, and the third conductive electrode 123a passing through the second insulating layer 112 can have different lengths in the vertical direction (X-axis direction). In this embodiment, the first conductive electrode 121a, the second conductive electrode 122a, and the third conductive electrode 123a can have different thicknesses. Additionally, the first conductive electrode 121a, the second conductive electrode 122a, and the third conductive electrode 123a can be arranged to be spaced apart in the horizontal direction (Y-axis direction).

[0088] In this embodiment, the first insulating layer 111 may include an upper surface US1 and a lower surface BS1. The second insulating layer 112 may include an upper surface US2 and a lower surface BS2. The upper surface US1 of the first insulating layer 111 may contact the lower surface BS2 of the second insulating layer 112. For example, the upper surface US1 of the first insulating layer 111 and the lower surface BS2 of the second insulating layer 112 may be coplanar with each other. However, the second insulating layer 112 may have a step relative to the upper surface US1 of the first insulating layer 111 in the region of its lower surface that contacts the upper surface of the third conductive pad VL3.

[0089] Furthermore, the first conductive electrode 121a can be disposed between the upper surface US2 of the second insulating layer 112 and the first conductive pad VL1. Alternatively, the first conductive electrode 121a can be located between the upper surface US2 of the second insulating layer 112 and the first insulating layer 111. The first conductive electrode 121a can pass through at least a portion of the second insulating layer 112.

[0090] The second conductive electrode 122a can be disposed between the first conductive pad VL1 and the upper surface US2 of the second insulating layer 112. Alternatively, the second conductive electrode 122a can be located between the upper surface US1 of the first insulating layer 111 (or the lower surface BS2 of the second insulating layer 112) and the upper surface US2 of the second insulating layer 112. The second conductive electrode 122a can pass through at least a portion of the second insulating layer 112.

[0091] The third conductive electrode 123a can be disposed between the lower surface BS1 of the first insulating layer 111 and the upper surface US2 of the second insulating layer 112. Alternatively, the third conductive electrode 123a can be disposed between the lower surface BS1 of the first insulating layer 111 and the upper surface US2 of the second insulating layer 112. Furthermore, the third conductive electrode 123a can be located between the sixth wiring portion 126b and the upper surface US2 of the second insulating layer 112. Additionally, the third conductive electrode 123a can pass through at least a portion of the first insulating layer 111 and the second insulating layer 112. In this embodiment, the third conductive electrode 123a can pass through the second insulating layer 112 and extend into a portion of the first insulating layer 111.

[0092] Furthermore, the third conductive electrode 123a can pass through the entire first insulating layer 111 and the second insulating layer 112 and contact the sixth wiring portion 126b. Additionally, the second conductive electrode 122a can contact the second conductive pad VL2 within the capacitor structure CAS. Furthermore, the first conductive electrode 121a can contact the first conductive pad VL1 within the capacitor structure CAS. In other words, since the first conductive electrode 121a is electrically connected to the first conductive pad VL1 via the capacitor structure, and the second conductive electrode 122a is electrically connected to the second conductive pad VL2, the electrical connection between the capacitor embedded in the circuit board 100 and the upper semiconductor device can be easily achieved.

[0093] Furthermore, the upper surface US1 of the first insulating layer 111 may not be coplanar with the upper surface of the first conductive pad VL1. For example, the upper surface US1 of the first insulating layer 111 may have a step relative to the upper surface of the first conductive pad VL1. The upper surface of the first conductive pad VL1 may be located closer to the first conductive electrode 121a than the upper surface US1 of the first insulating layer 111. This is because after separation from the carrier substrate in the embedded trace substate (ETS) process, the first conductive pad VL1 is partially removed from the first insulating layer 111 by a cleaning process. Therefore, a groove may be formed above the first conductive pad VL1 in the first insulating layer 111 or at a position corresponding to the first conductive pad VL1.

[0094] Furthermore, since the dielectric layer DL is disposed on the first conductive pad VL1, the dielectric layer DL can overlap with the upper surface US1 of the first insulating layer 111 in the horizontal direction. In other words, the dielectric layer DL can overlap with the first insulating layer 111 in the horizontal direction (Y-axis direction). Additionally, the dielectric layer DL can overlap with the second insulating layer 112 in the horizontal direction (Y-axis direction).

[0095] Therefore, fine conductive pads can be formed in the first insulating layer 111, and since both the first insulating layer 111 and the second insulating layer 112 overlap with the dielectric layer DL, which serves as an insulating layer, electrical insulation can be easily ensured.

[0096] In addition, in the modified example, in order to enable various parallel and series connections with the capacitor structure CAS, the sixth conductive electrode 126a of the sixth electrode section 126 can contact the first conductive pad VL1 of the capacitor structure CAS.

[0097] In this specification, the conductive electrode may be located in a through-hole formed in each insulating layer, etc. This corresponds to a conductive electrode passing through each insulating layer, etc. This specification is described based on this.

[0098] In this embodiment, the thickness T1 of the first conductive electrode 121a, the thickness T2 of the second conductive electrode 122a, and the thickness T3 of the third conductive electrode 123a can be different from each other.

[0099] For example, the thickness T1 of the first conductive electrode 121a can be greater than the thickness T2 of the second conductive electrode 122a. Furthermore, the thickness T2 of the third conductive electrode 123a can be greater than the thickness of at least one of the first conductive electrode 121a and the second conductive electrode 122a. For example, the thickness T3 of the third conductive electrode 123a can be greater than the thickness T1 of the first conductive electrode 121a and the thickness T2 of the second conductive electrode 122a. With this configuration, at least one die (or semiconductor device) disposed above the circuit board 100 can be easily connected to a capacitor. Additionally, by forming a space for connection to the upper die, the vertical overlap between the first conductive pad and the second conductive pad can be easily ensured. That is, this minimizes the capacitance variation caused by the overlap between the first conductive pad and the second conductive pad.

[0100] Furthermore, in this embodiment, the third conductive electrode 123a may overlap with the first conductive electrode 121a and the second conductive electrode 122a in the horizontal direction (Y-axis direction). Additionally, the third conductive electrode 123a may at least partially overlap with the capacitor structure CAS in the horizontal direction (Y-axis direction). Furthermore, at least a portion of the third conductive electrode 123a may not overlap with the first conductive electrode 121a and the second conductive electrode 122a in the horizontal direction (Y-axis direction). Additionally, a portion of the third conductive electrode 123a may overlap with the dielectric layer DL in the horizontal direction.

[0101] Furthermore, the third conductive electrode 123a can overlap with the entire capacitor structure CAS in the horizontal direction (Y-axis direction). On the other hand, the first conductive electrode 121a can also overlap with at least a portion of the capacitor structure CAS in the horizontal direction (Y-axis direction). The first conductive electrode 121a can overlap with the dielectric layer DL and the second conductive pad VL2 of the capacitor structure CAS in the horizontal direction (Y-axis direction).

[0102] Furthermore, the width W1 of the first conductive electrode 121a can gradually decrease from the upper surface US2 of the second insulating layer 112 toward the lower surface BS2 of the second insulating layer 112. For example, the width (or diameter, etc.) of the first conductive electrode 121a can be increased in the vertical direction.

[0103] Furthermore, the minimum width W1a of the first conductive electrode 121a can be smaller than the maximum width W1b of the first conductive electrode 121a. In this embodiment, the first width W1a, which is the minimum width of the first conductive electrode 121a, can correspond to the minimum width at the lower surface BS2 of the second insulating layer 112. Alternatively, the first width W1a, which is the minimum width of the first conductive electrode 121a, can correspond to the width in the region closest to the lower surface BS2 of the second insulating layer 112. Additionally, the maximum width W1b of the first conductive electrode 121a can correspond to the width at the upper surface US2 of the second insulating layer 112. Alternatively, the maximum width of the first conductive electrode 121a can correspond to the width in the region closest to the upper surface US2 of the second insulating layer 112.

[0104] Furthermore, the width W2 of the second conductive electrode 122a can gradually decrease from the upper surface US2 of the second insulating layer 112 toward the lower surface BS2 of the second insulating layer 112. Alternatively, the width W2 of the second conductive electrode 122a can gradually increase in the vertical direction.

[0105] The minimum width W2a of the second conductive electrode 122a can be smaller than the maximum width W2b of the second conductive electrode 122a. In this embodiment, the minimum width of the second conductive electrode 122a can correspond to the minimum width at the lower surface BS2 of the second insulating layer 112 (or the upper surface of the first insulating layer). Alternatively, the minimum width of the second conductive electrode 122a can correspond to the width in the region closest to the upper surface US1 of the first insulating layer 111 (or the lower surface BS2 of the second insulating layer). Furthermore, the maximum width W2b of the second conductive electrode 122a can correspond to the width at the upper surface US2 of the second insulating layer 112. Alternatively, the maximum width of the second conductive electrode 122a can correspond to the width in the region closest to the upper surface US2 of the second insulating layer 112.

[0106] Furthermore, the width W3 of the third conductive electrode 123a can gradually decrease from the upper surface US2 of the second insulating layer 112 toward the lower surface BS1 of the first insulating layer 111 (or from the upper surface (or lower surface) of the second insulating layer toward the upper surface (or lower surface) of the first insulating layer). Alternatively, the width W3 of the third conductive electrode 123a can gradually increase in the vertical direction.

[0107] The minimum width W3a of the third conductive electrode 123a can be smaller than the maximum width W3b of the third conductive electrode 123a. In this embodiment, the minimum width of the third conductive electrode 123a can correspond to the width at the lower surface BS1 of the first insulating layer 111. Alternatively, the minimum width of the third conductive electrode 123a can correspond to the width in the region closest to the lower surface BS1 of the first insulating layer 111. Furthermore, the maximum width W3b of the third conductive electrode 123a can correspond to the width at the upper surface US2 of the second insulating layer 112. Alternatively, the maximum width of the third conductive electrode 123a can correspond to the width in the region closest to the upper surface US2 of the second insulating layer 112.

[0108] The first width W1a (which is the minimum width of the first conductive electrode 121a) can be greater than the third width W3a (which is the minimum width of the third conductive electrode 123a). Furthermore, the second width W2a (which is the minimum width of the second conductive electrode 122a) can be greater than the first width W1a (which is the minimum width of the first conductive electrode 121a). In this case, the maximum widths of the first conductive electrode 121a, the second conductive electrode 122a, and the third conductive electrode 123a can be the same.

[0109] Further reference Figure 3 and Figure 4The capacitor structure CAS can be located within the first insulating layer 111. Additionally, the capacitor structure CAS can be located between the first insulating layer 111 and the second insulating layer 112. At least a portion of the capacitor structure CAS can be embedded in the first insulating layer 111. Furthermore, at least a portion of the capacitor structure CAS can be embedded in the second insulating layer 112.

[0110] The capacitor structure CAS may include a first conductive pad VL1, a dielectric layer DL, and a second conductive pad VL2. The first conductive pad VL1, the dielectric layer DL, and the second conductive pad VL2 may be stacked sequentially in the vertical direction.

[0111] A storage capacitor or a capacitor can be formed between the first conductive pad VL1 and the second conductive pad VL2, and a dielectric layer DL is inserted between the first conductive pad VL1 and the second conductive pad VL2. In other words, the capacitor structure CAS can be used as a "capacitor".

[0112] The capacitor structure or capacitor needs to be further miniaturized to meet the requirements of substrates and semiconductor devices that require increased integration density.

[0113] As a method to improve the storage capacity of such a capacitor, one can consider increasing the effective surface area of ​​the first and second conductive pads (electrodes), reducing the thickness of the dielectric film, and using a high dielectric constant material for the dielectric film. In particular, when a high dielectric constant material is used as the dielectric film, the leakage current frequently generated between the first via pad (which is the lower electrode) and the second via pad (which is the upper electrode) can be sufficiently reduced while maintaining a small equivalent oxide thickness. In this embodiment, a material with a high dielectric constant can be used as the dielectric film. For example, high dielectric constant materials may include tantalum oxide, aluminum oxide, zirconium oxide, hafnium oxide, titanium oxide, etc.

[0114] Furthermore, when high-capacity capacitors are installed, the circuit board according to the embodiment can solve the problems mentioned above, such as the reduction in circuit board integration density and the decrease in input / output (I / O) count due to the size of the capacitors. In other words, the capacitor structure according to the embodiment can simultaneously provide increased circuit board integration density, increased I / O count, and improved storage capacity.

[0115] In this embodiment, at least one of the first conductive electrode 121a and the second conductive electrode 122a may overlap with the capacitor structure CAS in the vertical direction (X-axis direction). Specifically, the first conductive electrode 121a and the second conductive electrode 122a may overlap with the first conductive pad VL1 in the vertical direction (X-axis direction). Furthermore, the first conductive electrode 121a and the second conductive electrode 122a may be located above the first conductive pad VL1. Additionally, the first conductive electrode 121a and the second conductive electrode 122a may be connected to the capacitor structure CAS.

[0116] For example, the second conductive electrode 122a can be electrically connected to the capacitor structure CAS. In this embodiment, the second conductive electrode 122a can be disposed on the second conductive pad VL2. Alternatively, the second conductive electrode 122a can be disposed on the capacitor structure CAS. Therefore, the second conductive electrode 122a can overlap with the capacitor structure CAS in the vertical direction (X-axis direction).

[0117] Additionally, the first conductive electrode 121a can be electrically connected to the capacitor structure CAS. In this embodiment, the first conductive electrode 121a can be disposed on the first conductive pad VL1. In other words, the first conductive electrode 121a can be disposed on a portion of the capacitor structure CAS. Therefore, the first conductive electrode 121a can overlap with the capacitor structure CAS in the vertical direction (X-axis direction). Furthermore, the first conductive electrode 121a can be offset from the second conductive electrode 122a or the dielectric layer DL in the vertical direction (X-axis direction). Moreover, the first conductive electrode 121a can be spaced apart from the second conductive electrode 122a in the horizontal direction (Y-axis direction) and can at least partially overlap with the second conductive electrode 122a in the horizontal direction (Y-axis direction). Therefore, the capacitor structure CAS can be located between the die or chip mounted on the upper part of the circuit board 100 and the main circuit board, thereby allowing the capacitor to be disposed between the die (or chip) and the main circuit board.

[0118] Alternatively, one or more capacitor structures CAS can be provided in the circuit board 100. In this embodiment, multiple capacitor structures CAS can be provided, and the multiple capacitor structures CAS may include a first capacitor structure CAS1 and a second capacitor structure CAS2. The first capacitor structure CAS1 and the second capacitor structure CAS2 can be configured to be spaced apart from each other.

[0119] The third conductive electrode 123a can be configured to be spaced apart from the first capacitor structure CAS1 and the second capacitor structure CAS2. Alternatively, the third conductive electrode 123a can be disposed between the first capacitor structure CAS1 and the second capacitor structure CAS2. The third conductive electrode 123a can pass through at least one of the first capacitor structure CAS1 and the second capacitor structure CAS2. Therefore, at least a portion of the third conductive electrode 123a can overlap with the first capacitor structure CAS1 and the second capacitor structure CAS2 in the horizontal direction (Y-axis direction).

[0120] Furthermore, as described above, at least a portion of the capacitor structure CAS can be embedded in the first insulating layer 111. A portion of the first conductive electrode 121a can contact the second insulating layer 112. Alternatively, a portion of the first conductive electrode 121a can overlap with the second insulating layer 112 in the horizontal direction. More specifically, the upper surface US1 of the first insulating layer 111 (or the lower surface BS2 of the second insulating layer) can be configured to offset from the upper or lower surface of the first conductive pad VL1. Additionally, the upper surface US1 of the first insulating layer 111 may not be coplanar with the upper surface of the first conductive pad VL1. For example, as... Figure 3 As shown, the upper surface US1 of the first insulating layer 111 may not be coplanar with the upper surface of the first conductive pad VL1. Therefore, the upper surface US1 of the first insulating layer 111 may also have a step relative to the lower surface of the dielectric layer DL. Therefore, the second insulating layer 112 may have its maximum thickness above the third conductive pad VL3 or in the region overlapping with the third conductive pad VL3 in the vertical direction (X-axis direction).

[0121] Furthermore, since the first capacitor structure CAS1 and the second capacitor structure CAS2, which are spaced apart from each other, overlap each other in the horizontal direction, the first conductive pad VL1 of the first capacitor CAS1 and the first conductive pad VL1 of the second capacitor structure CAS2 can at least partially overlap each other in the horizontal direction. For example, the upper surface of the first conductive pad VL1 in the first capacitor CAS1 and the upper surface of the first conductive pad VL1 in the second capacitor structure CAS2 can be coplanar. Alternatively, as another example, the upper surface of the first conductive pad VL1 in the first capacitor CAS1 can be offset from the upper surface of the first conductive pad VL1 in the second capacitor structure CAS2. For example, the upper surfaces of the first conductive pad VL1 in the first capacitor CAS1 and the upper surfaces of the first conductive pad VL1 in the second capacitor structure CAS2 can have a gap in the vertical direction.

[0122] In the circuit board according to the modified example, the first capacitor structure CAS1 and the second capacitor structure CAS2 of the capacitor structure CAS can be embedded in the upper surface US1 of the first insulating layer 111. Furthermore, the upper surface of the first conductive pad VL1 of at least one of the first capacitor structures CAS1 and CAS2 can be offset from the upper surface US1 of the first insulating layer 111. For example, the upper surface of the first conductive pad VL1 can have a gap in the vertical direction (X-axis direction) relative to the upper surface US1 of the first insulating layer 111.

[0123] Furthermore, the upper surface of the first conductive pad VL1 and the upper surface US1 of the first insulating layer 111 in the first capacitor CAS1 can be offset from each other.

[0124] Furthermore, in the second capacitor structure CAS2, the upper surface of the first conductive pad VL1 and the upper surface US1 of the first insulating layer 111 can be offset from each other.

[0125] In this embodiment, the area S1 of the first conductive pad VL1 can be larger than the area S2 of the second conductive pad VL2. For example, the area S1 of the upper surface of the first conductive pad VL1 can be larger than the area S2 of the upper surface of the second conductive pad VL2. Additionally, the area S1 of the lower surface of the first conductive pad VL1 can be larger than the area S2 of the lower surface of the second conductive pad VL2. Furthermore, the thickness of the first conductive pad VL1 can be different from the thickness of the second conductive pad VL2. Moreover, the area S1 of the first conductive pad VL1 can completely overlap with the area S2 of the second conductive pad VL2 in the vertical direction (X-axis direction). Using this configuration, capacitance variations and errors caused by differences in the overlapping area can be suppressed.

[0126] Furthermore, the area of ​​the dielectric layer DL in the planar view can be smaller than the area S1 of the first conductive pad VL1. Additionally, the area of ​​the dielectric layer DL can be larger than the area S2 of the second conductive pad VL2. Therefore, a decrease in capacitance due to the dielectric layer can be prevented.

[0127] Figure 5 This is a cross-sectional view of a circuit board according to a second embodiment of the present invention. Figure 6 yes Figure 5 A magnified view of part of K3 in the image. Figure 7 This is a plan view of the first conductive electrode, the second conductive electrode, the first conductive pad, and the second conductive pad in the circuit board according to the second embodiment.

[0128] Reference Figures 5 to 7The circuit board 100A according to the second embodiment may include an insulating layer 110, an electrode portion 120, and a capacitor structure CAS. Furthermore, the circuit board 100A may also include a protective layer disposed on the electrode portion 120, or a core layer serving as an insulating layer disposed in the insulating layer 110. In addition, the structures described in the embodiments of the present invention can be applied equivalently, except as described below.

[0129] In the circuit board 100A according to this embodiment, the first conductive electrode 121a can pass through at least a portion of the capacitor structure CAS. In other words, the first conductive electrode 121a can be surrounded by the capacitor structure CAS.

[0130] Furthermore, the spacing between the first conductive electrode 121a and the capacitor structures CAS through which it passes can be the same. For example, the spacing between the outer surface of the first conductive electrode 121a and the adjacent capacitor structures CAS can be maintained equally along the shape or edge of the first conductive electrode 121a.

[0131] Furthermore, the first conductive electrode 121a can pass through the second conductive pad VL2 and may not contact the second conductive pad VL2. Additionally, the second conductive pad VL2 can be spaced apart from the first conductive electrode 121a by a predetermined gap. The inner surface of the through-hole Hcas1 of the second conductive pad VL2 and the outer surface of the first conductive electrode 121a can be spaced apart from each other.

[0132] The first conductive electrode 121a can penetrate the dielectric layer DL. Furthermore, the first conductive electrode 121a can contact the upper surface of the first conductive pad VL1. The first conductive electrode 121a can also contact the inner surface of the via Hcas2 in the dielectric layer DL. Therefore, capacitance changes caused by a decrease in the area of ​​the dielectric layer DL can be suppressed. Additionally, the first conductive electrode 121a can be spaced apart from the inner surface of the via Hcas2 in the dielectric layer DL. For example, the first conductive electrode 121a can be spaced apart from the inner surface of the via Hcas2 in the dielectric layer DL by a predetermined gap.

[0133] Furthermore, the second insulating layer 112 can be located within the capacitor structure CAS. For example, the second insulating layer 112 can pass through the capacitor structure CAS. A portion of the second insulating layer 112 can pass through the second conductive pad VL2 of the capacitor structure CAS. A portion of the second insulating layer 112 can be located in the via Hcas1 of the second conductive pad VL2 of the capacitor structure CAS. Therefore, electrical insulation between the first conductive electrode 121a and the capacitor structure CAS can be maintained. Using this structure, a circuit board with improved integration density can be provided by forming a third conductive electrode through the first and second insulating layers constituting multiple layers and simultaneously forming the capacitor structure CAS.

[0134] Furthermore, when the first conductive electrode 121a is spaced apart from the inner surface of the via Hcas2 of the dielectric layer DL, the second insulating layer 112 may also be disposed in the via Hcas2 of the dielectric layer DL.

[0135] Furthermore, the second conductive electrode 122a and the first conductive electrode 121a can respectively contact the second conductive pad and the first conductive pad of the capacitor structure CAS. For example, the second conductive electrode 122a can contact the second conductive pad of the capacitor structure CAS, and the first conductive electrode 121a can contact the first conductive pad of the capacitor structure CAS. In this case, the area where the second conductive electrode 122a contacts the second conductive pad may not at least partially overlap with the area where the first conductive electrode 121a contacts the first conductive pad in the vertical direction. Therefore, the circuit board described according to the embodiment can be designed to facilitate electrical connection.

[0136] Figure 8 This is a cross-sectional view of the first conductive electrode, the second conductive electrode, the first conductive pad, and the second conductive pad in the circuit board according to the modified example. Figure 9 It is a plan view of the first conductive part electrode, the second conductive part electrode, the first conductive part pad, and the second conductive part pad in the circuit board according to the modified example.

[0137] Reference Figure 8 and Figure 9 The circuit board according to the modified example may include an insulating layer 110, an electrode portion 120, and a capacitor structure CAS. Furthermore, the circuit board may also include a protective layer disposed on the electrode portion 120, or a core layer serving as an insulating layer disposed in the insulating layer 110. In addition, the structures described in the embodiments of the present invention can be applied equivalently, except as described below.

[0138] Furthermore, the third conductive electrode 123a can pass through the capacitor structure CAS. The third conductive electrode 123a can pass through the first conductive pad VL1, the dielectric layer DL, and the second conductive pad VL2. In other words, the third conductive electrode 123a can be surrounded by the capacitor structure CAS. Similarly, the third conductive electrode 123a can be configured to be spaced apart from the first conductive electrode 121a and the second conductive electrode 122a.

[0139] Additionally, the capacitor structure CAS may include a via Hcas3. A third conductive electrode 123a may be located within the via Hcas3 of the capacitor structure CAS. The third conductive electrode may be configured to be spaced a predetermined distance from the inner surface of the via Hcas3 in the capacitor structure CAS. Therefore, the third conductive electrode 123a may be electrically connected to the lower sixth wiring portion 126b, etc., instead of being connected to the capacitor structure CAS. Furthermore, a second insulating layer 112 may be located within the via Hcas3 of the capacitor structure CAS. For example, the second insulating layer 112 may pass through the capacitor structure CAS. Therefore, electrical insulation between the third conductive electrode 123a and the capacitor structure CAS can be maintained. Using this configuration, a circuit board with improved integration density can be provided by forming a third conductive electrode passing through the first and second insulating layers constituting multiple layers while simultaneously forming the capacitor structure CAS.

[0140] Furthermore, as another example, the third conductive electrode 123a can also be electrically connected to the first conductive pad VL1 or the second conductive pad VL2 to be electrically connected to the first conductive pad VL1 or the second conductive pad VL2 of the capacitor structure CAS, and to achieve a series connection or parallel connection with the capacitor.

[0141] Figure 10 This is a cross-sectional view of a circuit board according to a third embodiment of the present invention. Figure 11 yes Figure 10 A magnified view of part K4 in the image.

[0142] Reference Figure 10 and Figure 11 According to the third embodiment, the circuit board 100B may include an insulating layer 110, an electrode portion 120, and a capacitor structure CAS. Furthermore, the circuit board 100B may also include a protective layer disposed on the electrode portion 120, or a core layer serving as an insulating layer disposed in the insulating layer 110. Additionally, the circuit board 100B may include a third conductive pad VL3. Moreover, the structures described in the embodiments of the present invention can be applied equivalently, except as described below.

[0143] The circuit board 100B may include a third conductive pad VL3, which is disposed at a position corresponding to the first conductive pad VL1 of the capacitor structure CAS. The third conductive pad VL3 may overlap with the first conductive pad VL1 in the horizontal direction (Y-axis direction). Furthermore, as described below, the first conductive pad VL1 and the third conductive pad VL3 may be formed in the same process.

[0144] Furthermore, in this embodiment, the first electrode portion 121 may include a first conductive portion electrode 121a and a first wiring portion 121b. The first electrode portion 121 may correspond to the sixth electrode portion described above. The first conductive portion electrode 121a may be disposed between the lower surface BS1 of the first insulating layer 111 and the first conductive portion pad VL1. Additionally, the first conductive portion electrode 121a may be located between the lower surface BS1 of the first insulating layer 111 and the first conductive portion pad VL1. The first conductive portion electrode 121a may pass through at least a portion of the first insulating layer 111.

[0145] The third conductive pad VL3 can be located between the first insulating layer 111 and the second insulating layer 112. For example, the third conductive pad VL3 can be located between the lower surface BS1 of the first insulating layer 111 and the upper surface US2 of the second insulating layer 112.

[0146] Furthermore, the third conductive electrode 123a can be located between the third conductive pad VL3 and the upper surface US2 of the second insulating layer 112. Additionally, the third conductive electrode 123a can contact the third conductive pad VL3. The third conductive electrode 123a can pass through the second insulating layer 112 and can contact the upper surface of the third conductive pad VL3. The upper surface of the third conductive pad VL3 can be coplanar with the upper surface of the first conductive pad VL1.

[0147] The third conductive electrode 123a can be disposed opposite to the first conductive electrode 121a based on the third conductive pad VL3. In contrast, the second conductive electrode 122a can be disposed opposite to the first conductive electrode 121a based on the capacitor structure CAS.

[0148] In this embodiment, the length or thickness of the third conductive electrode 123a passing through the second insulating layer 112 in the vertical direction (X-axis direction) may differ from the length or thickness of the second conductive electrode 122a passing through the second insulating layer 112 in the vertical direction (X-axis direction). For example, the thickness of the second insulating layer at the inner surface in contact with the third conductive electrode 123a may be greater than the thickness of the second insulating layer at the inner surface in contact with the second conductive electrode 122a. Therefore, the third conductive electrode 123a may have a greater thickness or a greater length in the second direction than the second conductive electrode 122a. With this configuration, when the first insulating layer 111 and the second insulating layer 112 are formed and the conductive electrode passing through the first insulating layer 111 and the second insulating layer 112 is formed, cracks or damage at the interface between the first insulating layer 111 and the second insulating layer 112 can be prevented during the formation of the third conductive electrode. For example, cracks at the interface between the insulating layers can be suppressed by having a conductive electrode passing through both the first insulating layer and the second insulating layer. In other words, vias or conductive electrodes penetrating multiple insulating layers can be avoided. Furthermore, the degradation in structural reliability during via formation can be suppressed by using a third conductive pad (VL3). Additionally, the degradation in electrical performance due to the reduction in the area or width of the conductive electrodes penetrating multiple insulating layers can also be suppressed. Moreover, the capacitor structure CAS can provide an electrical connection between one end located on the lower surface of the circuit board and the other end located on the upper surface of the circuit board.

[0149] Furthermore, the third conductive electrode 123a may not overlap with the first conductive electrode 121a in the horizontal direction (Y-axis direction). The third conductive electrode 123a may be configured to be offset from the first conductive electrode 121a in the horizontal direction (Y-axis direction).

[0150] Furthermore, the width of the first conductive electrode 121a can gradually increase from the upper surface US1 of the first insulating layer 111 toward the lower surface BS1 of the first insulating layer 111.

[0151] In an additional example, a fourth conductive pad (not shown) may be further disposed on the third conductive pad VL3. That is, the circuit board may further include a fourth conductive pad (not shown). The fourth conductive pad (not shown) may overlap with at least one of the second conductive pad VL2 and the dielectric layer DL in the horizontal direction (Y-axis direction). In addition, the third conductive electrode 123a may be located between the fourth conductive pad (not shown) and the upper surface US2 of the second insulating layer 112.

[0152] Figures 12a to 12o This is a diagram illustrating a method for manufacturing a circuit board according to a third embodiment.

[0153] Reference Figure 12a In this embodiment, a carrier board can be prepared. The carrier board may include a carrier insulating layer 310 and a carrier metal layer 320 disposed on at least one surface of the carrier insulating layer 310. Specifically, the carrier board may have a carrier insulating layer 310 and a carrier metal layer 320 disposed on at least one surface of the carrier insulating layer 310. In this case, the carrier metal layer 320 may be disposed on only one of the opposing surfaces of the carrier insulating layer 310, or alternatively, it may be disposed on both surfaces of the carrier insulating layer 310. For example, if the carrier metal layer 320 is disposed on only one surface of the carrier insulating layer 310, then the ETS process for manufacturing a circuit board can be performed only on that surface. Alternatively, the carrier metal layer 320 may be disposed on both surfaces of the carrier insulating layer 310, so that the ETS process for manufacturing a circuit board can be performed simultaneously on both surfaces of the carrier board. In this case, two circuit boards can be manufactured simultaneously.

[0154] The carrier metal layer 320 can be formed by plating onto the carrier insulating layer 310. Alternatively, the carrier insulating layer 310 and the carrier metal layer 320 can constitute a copper clad laminate (CCL). That is, the carrier metal layer 320 can be a copper foil layer. For example, the carrier metal layer 320 can be a copper foil. For example, the carrier metal layer 320 can be an electroless plating layer formed on the carrier insulating layer 310. In other words, the carrier metal layer 320 is the first metal layer formed in the process of manufacturing the circuit board.

[0155] Reference Figure 12b In this embodiment, a dry film 330 may be formed on the carrier metal layer 320. In this case, after the dry film 330 covers the entire carrier metal layer 320, an opening exposing the surface of the carrier metal layer 320 can be formed by exposure and development. The opening can be formed on the surface of the carrier metal layer 320 to correspond to the area where the first conductive pad VL1 will be formed. Alternatively, the first conductive pad VL1 can be formed in the aforementioned opening.

[0156] In one embodiment, the first conductive pad VL1 filling the opening of the dry film 330 can be formed by performing electroplating using a carrier metal layer 320 as a seed layer.

[0157] In this embodiment, a curing process involving heat treatment of the dry film 330 can be performed additionally before the electroplating process of the first conductive pad VL1. For example, in this embodiment, the dry film 330 can be cured after the exposure and development processes of the dry film 330. The curing of the dry film 330 can include curing using ultraviolet light and curing using infrared light. For example, in this embodiment, ultraviolet light in the range of 5mV to 100mV can be used to cure the dry film 330. Alternatively, in this embodiment, infrared heat can be used to cure the dry film 330. As described above, in this embodiment, by performing an additional curing process on the dry film 330, the adhesion between the carrier metal layer 320 and the dry film 330 can be improved. Therefore, in this embodiment, by improving the bonding strength between the dry film 330 and the carrier metal layer 320, the first conductive pad VL1 formed in the opening can be miniaturized. For example, in this embodiment, by performing an additional curing process on the dry film 330, the linewidth and spacing of the traces in the first conductive pad VL1 can be reduced.

[0158] Reference Figure 12c The first insulating layer 111 can be stacked. The first insulating layer 111 can cover the first conductive pad VL1.

[0159] Reference Figure 12d The first electrode portion 121 can be formed in the first insulating layer 111. The first electrode portion 121 can be formed by sequentially performing the formation of a mask (e.g., a dry film), the formation of a mask pattern, the partial etching of the first insulating layer (e.g., the formation of via holes), and the formation of an electrode.

[0160] Alternatively, a third insulating layer 113 may be formed on the first insulating layer 111 and the first electrode portion 121. The third insulating layer 113 may be located on the first insulating layer 111 and the first electrode portion 121.

[0161] Additionally, the formation of a mask (e.g., a dry film), the formation of a mask pattern, the partial etching of the third insulating layer 113 (e.g., the formation of vias), and the formation of electrodes can be performed sequentially. Therefore, a fourth electrode portion 124 can be formed on the third insulating layer 113.

[0162] Reference Figure 12e In this embodiment, a process of removing the carrier board can be performed. For example, a process of removing the carrier insulating layer 310 from the carrier board can be performed. For example, in this embodiment, a process of separating the carrier insulating layer 310 from the carrier metal layer 320 can be performed. Therefore, in the circuit board of this embodiment, the carrier metal layer 320 included in the carrier board remains on the outermost layer.

[0163] Reference Figure 12fIn this embodiment, an etching process of the carrier metal layer 320 can be performed. In this case, during the etching process of the carrier metal layer 320, a portion of the first conductive pad VL1 (or the third conductive pad) is also removed along with the carrier metal layer 320. Therefore, grooves can be formed in all patterned portions of the first conductive pad VL1 (or the third conductive pad). That is, the upper surface of the first insulating layer 111 may not be coplanar with the upper surfaces of the first conductive pad VL1 and the third conductive pad VL3.

[0164] Additionally, a mask 330' can be formed in areas other than the first conductive pad VL1 and the third conductive pad VL3. For example, the mask 330' can be a dry film. Furthermore, the opening area can be formed by performing exposure, development, or other processes on the mask 330'. In other words, patterning can be performed on the dry film. The mask 330' can be positioned corresponding to the first conductive pad. Moreover, a mask curing process can be performed after the opening area is formed by exposure or other processes. Such mask formation can be applied to the formation of other masks in the same manner.

[0165] Reference Figure 12g A dielectric layer DL can be formed on the first conductive pad VL1.

[0166] Similarly, refer to Figure 12h A second conductive pad VL2 can be formed on the dielectric layer DL. The dielectric layer DL and the second conductive pad VL2 can be formed on the first conductive pad VL1 by forming, etching, or the like. Therefore, the capacitor structure can be located on the first insulating layer 111.

[0167] Reference Figure 12i A second insulating layer 112 can be formed on the first insulating layer 111. The second insulating layer 112 can cover the capacitor structure CAS and the first insulating layer 111. In addition, a fourth insulating layer 114 can be formed below the third insulating layer 113.

[0168] Reference Figure 12j The first conductive portion V1 and the second conductive portion V2 can be formed by etching in the second insulating layer 112. The first conductive portion V1 and the second conductive portion V2 can have different lengths in the vertical direction. The first conductive portion V1 and the second conductive portion V2 can pass through the second insulating layer 112. Etching and drilling can also be performed on the fourth insulating layer 114. Alternatively, etching of the fourth insulating layer 114 can be performed previously.

[0169] Additionally, the first conductive portion V1 can be located on the capacitor structure. The second conductive portion V2 can be spaced apart from the capacitor structure. The capacitor structure can be exposed through the first conductive portion V1. The pads of the first conductive portion can be exposed through the second conductive portion V2.

[0170] Reference Figure 12k A plating layer 340 for plating can be formed on the second insulating layer 112. For example, a plating layer 340 for electroless plating can be formed. However, various other processes can be applied besides this plating process. Additionally, a plating layer 340 can be formed in the same manner below the fourth insulating layer 114.

[0171] Reference Figure 12l A mask 330'' can be formed on the second insulating layer 112 and the plating layer 340. For example, the mask 330'' can be a dry film. Furthermore, the opening region can be formed by performing exposure, development, or other processes on the mask 330''. In other words, the dry film can be patterned. The mask 330'' can be located in a region other than the first conductive portion V1 and the second conductive portion V2.

[0172] Furthermore, a mask curing process can be performed after the opening area is formed through exposure or other means. This method of mask formation can be applied to the formation of other masks in the same way.

[0173] Alternatively, the formation and patterning of mask 330'' can be applied in the same manner to the area beneath the fourth insulating layer 114. In other words, the formation and patterning of mask 330'' can also be performed in the same manner on or around the conductive portion formed in the fourth insulating layer 114.

[0174] Reference Figure 12m A second electrode portion 122 and a third electrode portion 123 can be formed. For example, the first conductive portion V1 and the second conductive portion V2 can be plated by an electroplating process. Therefore, the second electrode portion 122 can be formed in the first conductive portion V1, and the third electrode portion 123 can be formed in the second conductive portion V2.

[0175] Alternatively, the same process can be applied below the fourth insulating layer 114 by electroplating. Thus, the fifth electrode portion 125 can be formed.

[0176] Reference Figure 12n The mask 330'' can be removed. Various etching methods can be used to remove the mask 330''. For example, the mask 330'' on the second insulating layer 112 and the mask 330'' under the fourth insulating layer 114 can be removed.

[0177] Reference Figure 12oThe coating 340 can be etched (e.g., fast etching). That is, the coating 340 can be removed by etching. For example, the coating 340 at the position corresponding to the mask 330'' can be removed.

[0178] The plating 340 on the second insulating layer 112 and the plating 340 below the fourth insulating layer 114 can be removed.

[0179] Using this configuration, the second electrode portion 122 and the third electrode portion 123 can be electrically isolated from each other. Furthermore, electrical isolation can be achieved between multiple second electrode portions 122. Additionally, electrical isolation can be achieved between multiple third electrode portions 123. Similarly, electrical isolation can be achieved between multiple fifth electrode portions 125.

[0180] Additionally, as an example of modification, in Figure 5 Prior to the operation shown in I, a portion of the aforementioned circuit board can also be manufactured using the processes described below. Based on the above description and figures, a carrier board can be prepared, for example, in a modified example. Similarly, a substrate material for manufacturing a circuit board or a semiconductor package including the circuit board can be prepared using an ETS process.

[0181] The carrier plate may include a carrier insulating layer 310 and a carrier metal layer 320 disposed on at least one surface of the carrier insulating layer 310.

[0182] Furthermore, a second electrode layer, a dielectric layer, and a first electrode layer for forming the capacitor structure can be sequentially stacked on the carrier board. The first electrode layer may correspond to the first conductive pad described above. The second electrode layer may correspond to the second conductive pad described above. The dielectric layer may correspond to the dielectric layer described above.

[0183] Alternatively, the carrier metal layer 320 may be disposed on only one of the upper and lower surfaces of the carrier insulating layer 310, or alternatively, the carrier metal layer 320 may be disposed on both the upper and lower surfaces of the carrier insulating layer 310.

[0184] For example, the carrier metal layer 320 can be disposed on both the upper and lower surfaces of the carrier insulating layer 310. Furthermore, when the carrier metal layer 320 is disposed on both the upper and lower surfaces of the carrier insulating layer 310, a process of simultaneously fabricating two semiconductor packages on both surfaces of the carrier substrate can be performed. In this case, two semiconductor packages can be fabricated simultaneously.

[0185] The carrier metal layer 320 can be formed on the carrier insulating layer 310 by chemical plating. Alternatively, the carrier insulating layer 310 and the carrier metal layer 320 can constitute a CCL.

[0186] Next, the patterning of the first electrode layer on the outer side can be performed. For example, various methods can be used to etch the first electrode layer. Therefore, the first electrode layer can have a shape corresponding to the first conductive pad VL1 described above. In other words, the first electrode layer can be etched to control the position of the capacitor structure.

[0187] Next, a first insulating layer 111 can be stacked. The first insulating layer 111 can cover the first conductive pad VL1. In addition, the first insulating layer 111 can be located on the dielectric layer.

[0188] Next, a first electrode portion 121 can be formed on the first insulating layer 111. The first electrode portion 121 can be formed by sequentially performing the formation of a mask (e.g., a dry film), the formation of a mask pattern, the partial etching of the first insulating layer (e.g., the formation of vias), and the formation of an electrode.

[0189] Alternatively, a third insulating layer 113 may be formed on the first insulating layer 111 and the first electrode portion 121. The third insulating layer 113 may be located on the first insulating layer 111 and the first electrode portion 121.

[0190] Additionally, the formation of a mask (e.g., a dry film), the formation of a mask pattern, the partial etching of the third insulating layer 113 (e.g., the formation of vias), and the formation of electrodes can be performed sequentially. Therefore, a fourth electrode portion 124 can be formed on the third insulating layer 113.

[0191] Next, in this embodiment, a process of removing the carrier plate can be performed. For example, a process of removing the carrier insulating layer 310 from the carrier plate can be performed. For example, in this embodiment, a process of separating the carrier insulating layer 310 from the carrier metal layer 320 can be performed.

[0192] Next, a mask 330' can be formed on the second electrode layer. For example, the mask 330' can be a dry film. Furthermore, the opening region can be formed by performing exposure, development, or other processes on the mask 330'. In other words, the dry film can be patterned. The mask 330' can be positioned at a location corresponding to the pad of the first conductive portion. Furthermore, a mask curing process can be performed after the opening region is formed by exposure or other processes. The formation of such a mask can be applied in the same manner to the formation of other masks.

[0193] Next, etching can be performed on the opening region. In other words, etching can be performed on a portion of the second electrode layer. As a portion of the second electrode layer is removed, the second conductive pad VL2, which is the remaining portion of the second electrode layer, can be formed to correspond to the first conductive pad VL1.

[0194] Next, etching can be performed on the dielectric layer. In other words, etching can be performed on a portion of the dielectric layer. As a portion of the dielectric layer is removed, the remaining portion of the dielectric layer DL can be located between the first conductive pad VL1 and the second conductive pad VL2. Therefore, the capacitor structure can be located on the first insulating layer 111.

[0195] In addition, the mask 330'' can be removed. Various etching methods can be used to remove the mask 330''.

[0196] Figure 13 This is a schematic diagram of a semiconductor package according to an embodiment.

[0197] Reference Figure 13 The semiconductor package according to the embodiment may include a lower substrate 200, a circuit board 100, and a semiconductor device DI.

[0198] The lower substrate 200 may be a packaging substrate. For example, the lower substrate 200 may provide space for at least one external substrate to be bonded. The external substrate may be a circuit board 100 bonded to the lower substrate 200. Alternatively, the external substrate may be a motherboard included in an electronic device bonded to the lower portion of the lower substrate 200. Furthermore, although not shown in the figures, the lower substrate 200 may provide space for mounting at least one semiconductor device. The lower substrate 200 may include at least one insulating layer and electrode portions disposed on the at least one insulating layer.

[0199] The circuit board 100 may be disposed on the lower substrate 200. The circuit board 100 may include the circuit board according to the above embodiments.

[0200] Additionally, circuit board 100 can be an interposer. For example, circuit board 100 can provide space for mounting at least one semiconductor device. Circuit board 100 can be connected to at least one semiconductor device DI. For example, circuit board 100 can provide space for mounting first semiconductor device DI to third semiconductor device DI3. Circuit board 100 can electrically connect first semiconductor device DI to third semiconductor device DI3 to the lower substrate 200 while also electrically connecting first semiconductor device DI to third semiconductor device DI3 to each other. In other words, circuit board 100 can perform horizontal connection functions between multiple semiconductor devices and vertical connection functions between semiconductor devices and the package substrate.

[0201] Although three semiconductor devices DI are shown disposed on circuit board 100, the invention is not limited thereto. For example, one semiconductor device may be disposed on circuit board 100, or alternatively, multiple semiconductor devices may be disposed on circuit board 100. Circuit board 100 may be disposed between at least one semiconductor device DI and the lower substrate 200.

[0202] In one embodiment, the circuit board 100 may be an active interposer used as a semiconductor device. When the circuit board 100 is used as a semiconductor device, the semiconductor package of this embodiment may have a vertical stack-up structure on the lower substrate 200 and may have the functionality of multiple logic chips. Having the functionality of logic chips may mean having the functionality of both active and passive devices. In the case of active devices, unlike passive devices, the current-voltage characteristics may be non-linear, and in the case of an active interposer, the functionality of active devices can be provided. In addition, the active interposer may have the functionality of a corresponding logic chip, and signal transmission functions may be performed between a second logic chip disposed above the active interposer and the lower substrate 200.

[0203] In another embodiment, the circuit board 100 may be a passive interposer. For example, the circuit board 100 may perform a signal relay function between the semiconductor device DI and the lower substrate 200, and may have the functions of passive devices such as resistors, capacitors, and inductors. For example, due to factors such as 5G, the Internet of Things (IoT), improved image quality, and increased communication speeds, the number of terminals on the semiconductor device DI is gradually increasing. That is, the number of terminals disposed on the semiconductor device DI increases, and therefore, the width of each terminal or the spacing between multiple terminals decreases. In this case, the lower substrate 200 may be connected to the motherboard of an electronic device. Therefore, in order to make the electrodes disposed on the lower substrate 200 have the width and spacing for connecting to the semiconductor device DI and the motherboard, there is a problem of increasing the thickness of the lower substrate 200 or making the layer structure of the lower substrate 200 more complex. Therefore, in the first embodiment, the circuit board 100 may be disposed on the lower substrate 200 and the semiconductor device DI. In addition, the circuit board 100 may include electrodes having fine widths and spacings corresponding to the terminals of the semiconductor device DI.

[0204] Semiconductor devices (DI) can be logic chips, memory chips, etc. Logic chips can be CPUs, GPUs, etc.

[0205] Additionally, the semiconductor package in this embodiment may include a connector.

[0206] For example, a semiconductor package may include a first connection portion disposed between a lower substrate 200 and a circuit board 100. The first connection portion can electrically connect the circuit board 100 to the lower substrate 200 while simultaneously bonding the circuit board 100 to the lower substrate 200.

[0207] For example, a semiconductor package may include a second connection portion disposed between a circuit board 100 and a semiconductor device DI. The second connection portion may electrically connect the semiconductor device DI to the circuit board 100 while simultaneously bonding the semiconductor device DI to the circuit board 100.

[0208] The semiconductor package may include a third connection portion disposed on the lower surface of the lower substrate 200. The third connection portion can electrically connect the lower substrate 200 to the motherboard while bonding the lower substrate 200 to the motherboard.

[0209] In this configuration, the first, second, and third connection portions can electrically connect multiple components using at least one bonding method selected from wire bonding, solder bonding, and direct metal-to-metal bonding. That is, since the first, second, and third connection portions function to electrically connect multiple components, when using direct metal-to-metal bonding, the connections in the semiconductor package can be understood as electrically connected portions rather than solder or wires.

[0210] In at least one of the lower substrate 200 and the circuit board 100, the electrode on which the first connecting portion, the second connecting portion, and the third connecting portion are provided may include a protrusion protruding outward from the insulating layer of the corresponding substrate. The protrusion may protrude outward from either the lower substrate 200 or the circuit board 100.

[0211] The protrusion can be referred to as a bump, a post, or a pillar. Preferably, the protrusion can be an electrode of the circuit board 100 having a second connection portion thereon for bonding with a semiconductor device DI. In other words, as the spacing of the terminals of the semiconductor device DI becomes finer, short circuits may occur between multiple second connections that are connected to multiple terminals of the semiconductor device DI by a conductive adhesive (e.g., solder). Therefore, in this embodiment, thermoforming can be performed to reduce the volume of the second connection portion. Thus, this embodiment allows the electrodes of the circuit board 100 having the second connection portion to include the protrusion to ensure alignment, diffusion characteristics, and anti-diffusion capability to prevent the intermetallic compound (IMC) formed between the conductive adhesive (e.g., solder) and the protrusion from diffusing into the interlayer and / or substrate.

[0212] Additionally, semiconductor packages may include interconnect components. These interconnect components can be referred to as bridging layers. For example, an interconnect component may include a redistribution layer. Interconnect components can be used to electrically connect multiple semiconductor devices in the horizontal direction. For example, because semiconductor devices typically require a large area, interconnect components may include a redistribution layer. Since semiconductor packages and semiconductor devices differ significantly in aspects such as the width of their circuit patterns, buffering of the circuit patterns used for electrical connections is required. Buffering may refer to having an intermediate dimension between, for example, the width or width of the circuit pattern in a semiconductor package and, for example, the width or width of the circuit pattern in a semiconductor device, and the redistribution layer may have the function of performing this buffering effect.

[0213] In this embodiment, the connecting member can be an organic material bridge. For example, the connecting member can contain organic materials. For example, the connecting member can include an organic substrate that comprises organic materials instead of a silicon substrate. The connecting member can be embedded in the circuit board 100.

[0214] For this purpose, the circuit board 100 may include a cavity, and connecting members may be disposed in the cavity of the circuit board 100. The connecting members can horizontally connect multiple semiconductor devices disposed on the circuit board 100.

[0215] Furthermore, the circuit board according to the embodiment can be divided into a packaging substrate and an interposer corresponding to the lower substrate, based on the function of the circuit board, and can be applied thereto. The packaging substrate is used to mount semiconductor devices and / or the interposer. Due to the increase in data, the area of ​​the circuit board may increase, or the yield of the circuit board may decrease significantly with the increase in the number of stacked insulating layers. Therefore, in order to improve the yield of a circuit board with a large number of stacked layers, the circuit board can be divided into an interposer and a packaging substrate, thereby improving the yield of the circuit board. In addition, as the density of terminals on semiconductor devices increases, it may be difficult to realize a pad of the packaging substrate with an area corresponding to the terminals of the semiconductor devices. Therefore, the interposer can be used as a buffer between the pad size of the packaging substrate and the fine pattern size of the terminals of the semiconductor devices.

[0216] Based on the structure of the insulating layer, the aforementioned packaging substrate and interposer can be classified as core-based substrates and coreless substrates, respectively. In the case of a core-based substrate, the insulating layer may include a core layer, which may be a layer containing reinforcing material within the stacked insulating layers. The reinforcing material may refer to glass fiber. The core layer can be made thicker than other insulating layers to prevent circuit board warping during processing. However, the core layer may cause problems such as voltage drop and signal loss, or may make it difficult to achieve thinner designs. Therefore, depending on the application, the insulating layer of the circuit board may use a coreless substrate that does not include a core layer.

[0217] In various semiconductor packages, the circuit board according to the above embodiments may be located in a portion of the area or may correspond to a substrate.

[0218] On the other hand, when a circuit board having the features of the present invention described above is used in IT equipment or home appliances such as smartphones, servers, or televisions, it can stably perform functions such as signal transmission or power supply. For example, when a circuit board having the features of the present invention performs semiconductor packaging functions, the circuit board can safely protect the semiconductor chip from external moisture or contaminants, and can solve problems such as leakage current, electrical short circuits between terminals, and electrical open circuits at terminals supplying power to the semiconductor chip. Furthermore, when the circuit board is used for signal transmission, noise problems can be solved. Thus, a circuit board having the features of the present invention described above can maintain the stable operation of IT equipment or home appliances, enabling the entire product and circuit board applying the present invention to achieve mutual functional integrity or technical interoperability.

[0219] When a circuit board having the features of the present invention described above is used in a transportation device such as a vehicle, it can solve the problem of signal distortion transmitted to the transportation device, or can safely protect the semiconductor chip controlling the transportation device from external influences. Furthermore, by solving problems such as leakage current, electrical short circuits between terminals, or electrical open circuits at terminals supplying power to the semiconductor chip, the stability of the transportation device can be further improved. Therefore, the transportation device and circuit board using the present invention can achieve mutual functional integrity or technical interoperability.

[0220] In the foregoing, the features, structures, effects, etc., described in the embodiments are included in at least one embodiment, but are not necessarily limited to one embodiment. Furthermore, the features, structures, effects, etc., exemplified in each embodiment can be combined with or modified by those skilled in the art to which the embodiments pertain. Therefore, content related to such combinations and modifications should be interpreted as being included within the scope of the embodiments.

[0221] Although embodiments have been described above, they are merely examples and not limiting of the embodiments. Those skilled in the art will understand that various modifications and applications not illustrated above can be made without departing from the essential characteristics of the embodiments. For example, the various components specifically shown in the embodiments can be modified and implemented. Furthermore, differences relating to these modifications and applications should be interpreted as including within the scope of the embodiments as defined in the appended claims.

Claims

1. A circuit board, comprising: First insulating layer; A second insulating layer is disposed on the first insulating layer; The first conductive pad is disposed between the first insulating layer and the second insulating layer; The second conductive pad is disposed between the first conductive pad and the upper surface of the second insulating layer; The first conductive electrode is disposed between the first conductive pad and the upper surface of the second insulating layer. The second conductive electrode is disposed between the second conductive pad and the upper surface of the second insulating layer. The third conductive electrode is disposed between the lower surface of the first insulating layer and the upper surface of the second insulating layer; as well as A dielectric layer is disposed between the first conductive pad and the second conductive pad. Wherein, the dielectric layer overlaps with the first insulating layer and the second insulating layer in the horizontal direction, and The thicknesses of the first conductive electrode, the second conductive electrode, and the third conductive electrode are different from each other.

2. The circuit board of claim 1, wherein, The thickness of the first conductive electrode is greater than the thickness of the second conductive electrode.

3. The circuit board of claim 1, wherein, The thickness of the third conductive electrode is greater than the thickness of the second conductive electrode.

4. The circuit board of claim 1, wherein, The third conductive electrode passes through the second insulating layer and extends into a portion of the first insulating layer.

5. The circuit board according to claim 1, wherein, The first conductive electrode overlaps with the second conductive electrode in the horizontal direction.

6. The circuit board according to claim 1, wherein, The third conductive electrode overlaps with the first conductive electrode and the second conductive electrode in the horizontal direction.

7. The circuit board according to claim 1, wherein, The area of ​​the upper surface of the first conductive pad is greater than the area of ​​the upper surface of the second conductive pad.

8. The circuit board according to claim 1, wherein, The thickness of the first conductive pad is different from the thickness of the second conductive pad.

9. The circuit board according to claim 1, wherein, The width of each of the first conductive electrode and the second conductive electrode gradually decreases from the upper surface of the second insulating layer toward the lower surface of the second insulating layer.

10. The circuit board according to claim 1, wherein, The width of the third conductive electrode gradually decreases from the upper surface of the second insulating layer toward the lower surface of the first insulating layer.

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