Circuit board and electronic control device

Abstract

A circuit substrate (100) is provided with a first electronic component (2-1) at one surface of a dielectric layer (74), a second electronic component (2-2) at the other surface of the dielectric layer (74) and at least partially overlapping the first electronic component (2-1) in a direction orthogonal to the stacking direction of the conductor layers (73), and a plurality of conductor layers (73) including a removal portion (75-1, 75-2) in which a conductor pattern is removed in a range in which the first electronic component (2-1) and the second electronic component (2-2) overlap in the direction orthogonal to the stacking direction, and a plurality of hole portions (76) in which a plurality of holes are formed in a range in which the first electronic component (2-1) and the second electronic component (2-2) overlap in the direction orthogonal to the stacking direction.

Description

Technical Field

[0001] This invention relates to circuit boards such as printed circuit boards or flexible printed circuit boards, and electronic control devices having the circuit boards. Background Technology

[0002] In recent years, automotive autonomous driving assistance systems have been continuously becoming more advanced. Level 2+ autonomous driving, which is gradually becoming common in ordinary vehicles, achieves hands-free driving, while Level 3 achieves eyes-free driving. To achieve this functionality, the electronic control unit (ECU) for autonomous driving (AD-ECU) or the electronic control unit (ECU) for advanced driver-assistance systems (ADAS-ECU) is connected via cables to multiple sensors such as cameras, LiDAR, and sonar to acquire information from the outside world.

[0003] Furthermore, with the addition of new features such as connectivity, personalization, and infotainment, the electrical / electronic (E / E) architecture of automobiles is shifting towards a centralized "regional architecture" where the processing of the powertrain, body, and safety domains is integrated into the vehicle's central computer by ECUs. Therefore, the integrated ECUs, which act as the vehicle's central computer, are connected by multiple cables for backbone data transmission with the regional ECUs located throughout the vehicle.

[0004] AD / ADAS-ECUs and integrated ECUs are required to be miniaturized due to space constraints within the vehicle. On the other hand, if the number of cable connections to the ECU increases, the number of cable connectors located around the ECU housing also increases. Therefore, the increase in the number of cables leads to a larger ECU housing.

[0005] Cables used for this type of cable communication include, for example, coaxial cables, twisted-pair cables, and STP (Shielded Twist Pair) cables. Coaxial cables are cables in which a single signal line is surrounded by a grounded shield. Twisted-pair cables are cables in which differential pairs are twisted together, with a positive (P) and a negative (N) wire forming a pair. STP cables are twisted-pair cables in which a grounded shield is surrounded by a grounded shield.

[0006] Communication standards using coaxial cables include GMSL and MIPI A-Phy, used for communicating image data from camera sensors. In camera sensor communication, the cable for powering the camera is eliminated, thus reducing the weight of in-vehicle cabling. To achieve this weight reduction, the technology of Power over Coax (PoC) is commonly used, where signal and power are superimposed on the same coaxial cable.

[0007] In addition, representative communication standards using twisted-pair or STP cables include automotive Ethernet, represented by 100BASE-T1 (100Mbps transmission) and 1000BASE-T1 (1Gbps transmission). Within these standards, to achieve lightweight cabling within vehicles, the standardization of Powerover Data Line (PoDL) technology, which involves layering power onto the cable used for signal transmission, is underway.

[0008] Figure 1 An example of an ECU connecting multiple communication cables for various communication standards is shown. This example illustrates a configuration capable of connecting an 8-channel coaxial cable. Furthermore, in practice, configurations that combine coaxial cables with twisted-pair cables or STP cables are common. To connect the 8-channel coaxial cable 10 to the housing 7, Figure 1 The ECU housing 7 shown has eight housing-side connectors 8 on its side. Cable-side connectors 9 are inserted into these housing-side connectors 8, enabling cable communication between the ECU and external devices. Figure 1 As can be seen, the width of housing 7 is almost entirely occupied by connector through holes (mounting holes), and increasing the number of cable communication channels is a major challenge for the miniaturization of ECU.

[0009] To address this issue, the use of multi-pole connectors that can connect to multiple cables with a single connector is being promoted. Figure 2 An example of an ECU utilizing multi-pole connectors is shown. In this example, the configuration allows for the connection of a 12-channel coaxial cable by utilizing three 4-pole connectors located on the coaxial cable. Furthermore, in practice, configurations that combine coaxial cables with twisted-pair cables or STP cables are common.

[0010] exist Figure 2 In the ECU housing 7 shown, three housing-side 4-pole connectors 11 are provided on the side of the housing to connect the 12-channel coaxial cable 10. Cable communication between the ECU and external devices can be achieved by inserting the cable-side 4-pole connectors 12 into these housing-side 4-pole connectors 11. Figure 2 It can be seen that, although the number of channels is higher than Figure 1The example has been increased, but the width of housing 7 is greater than... Figure 1 The narrower, 4-pole connector contributes to the miniaturization of housing 7.

[0011] However, the use of such multi-pole connectors in the printed circuit board (PCB) within the ECU housing presents problems from a component mounting density perspective. The following uses... Figure 3 Explain this example.

[0012] Figure 3 This is a top view of an example of a printed circuit board 1 in which the filter components are mounted only on the surface when a 4-pole connector is used. Figure 3 The image shows an example of a configuration that utilizes a 4-pole connector to enable a 4-channel connection for a coaxial cable.

[0013] In the printed circuit board 1 inside the ECU, in order to transmit the signal from the 4-channel coaxial cable to the communication LSI 16 mounted on the printed circuit board 1, the 4 signal lines from the 4-pole connector 11 on the housing side are connected to the communication LSI 16 using the signal wiring 13-1 to 13-4 on the printed circuit board 1.

[0014] Furthermore, in the case of communication using the PoC method with power superposition via coaxial cable, component mounting is required to connect the signal line and the power line. Specifically, one terminal of the filter components 14-1 to 14-4, referred to as PoC filters, is connected to the signal line (signal wiring 13-1 to 13-4), and the other terminal is connected to the power line (power line connection vias 15-1 to 15-4). PoC filters utilize inductors (coils), capacitors, ESD protection components, etc. Filter components used in PoC filters are often relatively large, measuring only a few millimeters square. Therefore, when multiple filter components are mounted on the same substrate, the size of the area occupied by these filter components (the length in the direction orthogonal to the stacking direction) is larger than the width of the 4-pole connector, hindering high-density connector mounting and thus limiting the miniaturization of the ECU housing.

[0015] As a solution to this problem, there are methods such as Figure 4 The filter components are configured to be mounted overlapping each other on both sides of the substrate. Figure 4 This is a top view of an example of a printed circuit board 1 in which filter components are mounted on both the front and back sides when a 4-pole connector is used.

[0016] exist Figure 4In the printed circuit board 1 inside the ECU shown, in order to transmit the signal from the 4-channel coaxial cable to the communication LSI 16 mounted on the printed circuit board 1, the four signal wires 13-1 to 13-4 from the housing-side 4-pole connector 11 are connected to the communication LSI 16 using the surface signal wires 13-1 to 13-2 and the bottom signal wires 18-1 to 18-2 on the printed circuit board 1.

[0017] Furthermore, two of the four PoC filters (filter components 14-2 and 14-3) used for PoC communication via coaxial cable power supply are mounted on the surface layer, and the remaining two (filter components 14-1 and 14-4) are mounted on the bottom layer. Filter components 14-2 and 14-3, and filter components 14-1 and 14-4 are configured to overlap when viewed from the top surface of the printed circuit board 1. This configuration allows the size of the area occupied by the filter components to be controlled to be within the same range as the connector width.

[0018] However, mounting such filter components on both sides presents problems from the perspective of signal quality characteristics in high-speed communication signals. When installing filter components, impedance mismatch and crosstalk must be considered from a signal quality standpoint.

[0019] Regarding the first point about impedance mismatch, because the filter component is connected to the signal wiring, if parasitic capacitance is generated between the filter component and the conductor pattern of the printed circuit board, the impedance in high-frequency signals will decrease. The conductor pattern is a ground pattern or signal wiring pattern composed of conductor layers.

[0020] Regarding the second point about crosstalk, if electromagnetic coupling occurs between multiple filter components, noise from other signal lines will degrade waveform quality. Therefore, isolation needs to be ensured between the various signal lines.

[0021] Regarding the first point of impedance mismatch, in order to avoid capacitive coupling between the wiring such as coils in the filter component and the conductor pattern of the printed circuit board, there is a mounting method that opens a hole in the conductor pattern directly below the filter component (Prior Art (1)).

[0022] use Figure 5 This section discusses the existing technology for assembling two-sided components.

[0023] Figure 5 This is a cross-sectional view showing the printed circuit board involved in the prior art (1). Figure 5In this circuit, a filter component 2-1 is mounted on the surface of the dielectric layer 4 (substrate body) of the printed circuit board 1, and a filter component 2-2 is mounted on its back side. Multiple conductor layers 3 are formed inside the dielectric layer 4. The conductor layers 3 form ground patterns or signal wiring patterns. Generally, the conductor layers 3 use a metal with high conductivity. As mentioned earlier, to avoid coupling between the filter component, which is several millimeters square, and the conductor pattern, a distance on the order of millimeters is required between the filter component and the conductor pattern.

[0024] However, the printed circuit board 1 (dielectric layer 4) typically used in ECUs is thin, approximately 1.6mm to 2.0mm thick. Therefore, with filter components 2-1 and 2-2 mounted on both sides, if holes are drilled in the conductor pattern (conductor layer 3) from both sides, such as... Figure 5 As shown, the conductor pattern removal section 5 is formed to extend from the surface to the back side. The conductor pattern removal section 5 is constructed by removing a portion of the conductor layer 3 that constitutes the conductor pattern. In this case, although capacitive coupling between the filter components 2-1, 2-2 and the conductor pattern in the printed circuit board 1 can be reduced, electromagnetic coupling between the filter components 2-1, 2-2 occurs due to the lack of an electromagnetic barrier, resulting in crosstalk.

[0025] In response, use Figure 6 This describes the substrate configuration that takes crosstalk into account.

[0026] Figure 6 This is a cross-sectional view showing the printed circuit board involved in the prior art (2). Figure 6 In the example shown, a shielding layer 6 serving as electromagnetic shielding is disposed in the center of the dielectric layer 4 of the printed circuit board 1, between the filter component 2-1 mounted on the surface and the filter component 2-2 mounted on the back (Prior Art (2)). In this method, electromagnetic coupling between filter component 2-1 and filter component 2-2 can be avoided, and crosstalk can be suppressed to a sufficiently low level. However, the removal depth of the conductor pattern removal portion 5-1 directly below filter component 2-1 and the conductor pattern removal portion 5-2 directly above filter component 2-2 is shallower than that of the prior art (1). Therefore, the increased capacitive coupling between filter components 2-1, 2-2 and the conductor pattern is a problem.

[0027] As background technology related to this invention, the technology described in Patent Document 1 is known. In the printed wiring board described in Patent Document 1, in order to ensure isolation between passive components and their terminals in an array of passive components composed of multiple coils, a configuration is adopted in which the coils and terminals are staggered vertically and horizontally. This ensures isolation between the input / output terminals of adjacent coil components and between the coils.

[0028] Existing technical documents

[0029] Patent documents

[0030] Patent Document 1: International Publication No. 2017 / 179590 Summary of the Invention

[0031] The problem the invention aims to solve

[0032] In the technology of Patent Document 1, electromagnetic coupling is suppressed by offsetting the coil configuration or the coil electrode configuration in the left-right and up-down directions to reduce the relative area. However, by offsetting the coil configuration or the coil electrode configuration in the left-right and up-down directions (especially left-right), the substrate size of the printed wiring board becomes larger.

[0033] Based on the above situation, there is a need for a method that can balance the high-density mounting of filter components on the circuit board attached to cable communication with high-frequency electrical characteristics.

[0034] Methods for solving problems

[0035] To address the aforementioned issues, one embodiment of the present invention provides a circuit board in which multiple conductor layers with conductor patterns are stacked inside a dielectric layer, and multiple electronic components for connecting signal wiring for transmitting signals are disposed on the surface of the dielectric layer. In this circuit board, a first electronic component is disposed on one surface of the dielectric layer, and a second electronic component is disposed on another surface of the dielectric layer, at a position that at least partially overlaps with the first electronic component in a direction orthogonal to the stacking direction of the conductor layers. The multiple conductor layers include: a removed portion in the overlapping area of ​​the first and second electronic components in the direction orthogonal to the stacking direction where the conductor patterns have been removed, and a porous portion in the overlapping area of ​​the first and second electronic components in the direction orthogonal to the stacking direction where multiple holes are formed.

[0036] The effects of the invention

[0037] According to at least one aspect of the present invention, it is possible to balance the high-density mounting and high-frequency electrical characteristics of electronic components such as filter components mounted on the circuit board attached to the cable communication.

[0038] Other issues, structures, and effects not mentioned above will be explained through the following description of the forms of the invention. Attached Figure Description

[0039] Figure 1 This is a diagram showing an ECU housing that utilizes existing technology with a single-pole cable connector.

[0040] Figure 2 This is a diagram illustrating existing technology that utilizes multi-pole cable connectors.

[0041] Figure 3 This is a top view of an example of a printed circuit board in which the filter components are mounted only on the surface when a 4-pole connector is used.

[0042] Figure 4 This is a top view of an example of a printed circuit board with filter components mounted on both the front and back sides when a 4-pole connector is used.

[0043] Figure 5 This is a cross-sectional view of the printed circuit board involved in the prior art (1).

[0044] Figure 6 This is a cross-sectional view of the printed circuit board involved in the prior art (2).

[0045] Figure 7 This is a cross-sectional view showing an example of a printed circuit board according to a first embodiment of the present invention.

[0046] Figure 8 This is a diagram illustrating an example of the effect of the printed circuit board of the present invention.

[0047] Figure 9 This is a top view illustrating an example of a printed circuit board according to a second embodiment of the present invention.

[0048] Figure 10 This is a cross-sectional view showing an example of a printed circuit board according to a third embodiment of the present invention.

[0049] Figure 11 This is a cross-sectional view showing an example of a printed circuit board according to a fourth embodiment of the present invention.

[0050] Figure 12 This is a top view illustrating an example of a printed circuit board according to a fifth embodiment of the present invention.

[0051] Figure 13 This is a top view illustrating an example of a printed circuit board according to the sixth embodiment of the present invention.

[0052] Figure 14 This is a top view showing an example of a printed circuit board according to the seventh embodiment of the present invention and a diagram showing an example of the effect of the hole size.

[0053] Figure 15 This is a top view illustrating an example of a printed circuit board according to the eighth embodiment of the present invention. Detailed Implementation

[0054] Hereinafter, examples of methods for carrying out the present invention (hereinafter referred to as "implementation methods") will be described with reference to the accompanying drawings.

[0055] In this specification and accompanying drawings, identical or similar components are given the same symbols, and repetitive descriptions are omitted, or only descriptions focusing on the differences are provided. Furthermore, when there are multiple identical or similar components, different subscripts may be used above the same symbols for description. Additionally, when it is not necessary to distinguish these multiple components, subscripts may be omitted for description. Unless otherwise specified, the number of each component may be single or multiple.

[0056] <First Implementation>

[0057] First, use Figure 7 and Figure 8 The printed circuit board according to the first embodiment of the present invention will be described. The present invention relates to a printed circuit board for signal transmission devices and signal transmission systems. The printed circuit board is envisioned to be mounted on various ECUs such as electronic control units (AD-ECUs) for autonomous driving or advanced driver assistance systems (ADAS-ECUs). Hereinafter, examples of applying the present invention to printed circuit boards will be described, but the present invention can also be applied to flexible printed circuit boards (PCBs). This is also true in other embodiments.

[0058] Figure 7 This is a cross-sectional view showing an example of a printed circuit board 100 according to a first embodiment of the present invention. A filter component 2-1 is mounted on the surface of a dielectric layer 74 (substrate body), and a filter component 2-2 is mounted on its back side. Multiple conductor layers 73 are formed inside the dielectric layer 74. Ground patterns or signal wiring patterns are formed on the conductor layers 73 as conductor patterns. The conductor layers 73 use a metal with high conductivity. The filter components 2-1 and 2-2 on one surface and the other surface (back side) of the dielectric layer 74 are configured to partially or completely overlap when viewed from the top surface (stack direction). Furthermore, for filter components 2-1 and 2-2, conductor pattern removal portions 75-1 and 75-2 are provided in the conductor layers 73 of the inner layer of the printed circuit board 100 (dielectric layer 4) from the surface layer to the intermediate layer, such that the conductor patterns do not overlap directly below the filter components.

[0059] Furthermore, the feature is that a porous grounding pattern 76 is disposed in the intermediate layer, which has multiple holes in the conductor layer 73. Here, a grounding pattern typically used for shielding is referred to as a porous grounding pattern, but the same effect can be achieved even if a power supply pattern with low impedance electrical connection via a grounding pattern and decoupling capacitors is used instead.

[0060] Additionally, an example of a porous grounding pattern formed on two conductor layers 73 is shown here, but it can also be formed with a single layer. The effects of forming a single layer will be described in the description of another embodiment (the second embodiment).

[0061] Furthermore, this configuration describes a portion of the printed circuit board, and other components not described herein (e.g., LSI, capacitors, power ICs, etc.) can be added, and the number of conductor layers on the printed circuit board does not need to be the same. Additionally, examples of filter components include PoC filters, PoDL filters, ESD protection elements, common-mode choke coils, etc., but one or more of these can also be applied to. Furthermore, the present invention can also be applied to other components with similar functions.

[0062] Here, use Figure 8 The effects of the printed circuit board of the present invention are explained.

[0063] Figure 8 This is a diagram illustrating an example of the effect of the printed circuit board of the present invention. Figure 8 In the upper chart, the vertical axis represents impedance Zo [Ω], and the horizontal axis represents time [ns]. Additionally, in Figure 8 In the chart below, the vertical axis represents crosstalk S. 41 [dB], with the horizontal axis representing frequency [Hz].

[0064] exist Figure 8 On the upper side, an example of the results of measuring the impedance of the wiring section of a printed circuit board using the Time Domain Reflectometry (TDR) method is shown. Additionally, an example of the measurement results for a single-line signal wiring is shown here. The impedance of the "signal wiring section" is expected to be as close as possible to the reference impedance of 50Ω, but... Figure 8 As shown above, the impedance of the "filter mounting section" is generally reduced due to parasitic capacitance between its components and the substrate. If the impedance drops to a certain level and falls below the acceptable standard (specification value), it becomes a problem with signal quality.

[0065] The result of the prior art (1) (characteristic 85 represented by a single-dotted line in the figure) is the aforementioned Figure 5The results are shown in the case of a printed circuit board with a cross-section as illustrated. By extensively removing the conductor pattern directly beneath the filter components, the effect of impedance reduction is minimized.

[0066] On the other hand, the result of the prior art (2) (characteristic 86 represented by the dashed line in the figure) is the aforementioned Figure 6 The results are shown in the case of the substrate cross-section configuration. When removing the conductor pattern directly below the filter component, the impedance reduction effect is amplified because the conductor pattern is left in the intermediate layer, which has triggered the judgment criteria.

[0067] In contrast, the present invention (characteristic 80 indicated by solid lines in the figure) is the aforementioned Figure 7 The results are shown in the case of a printed circuit board with the cross-section shown. Although not as good as the prior art (1), the present invention reduces the relative area between the component and the metal surface by using a porous grounding pattern in the intermediate layer, resulting in a reduction of parasitic capacitance. Therefore, the present invention achieves an impedance improvement of about 1 to 2 Ω compared to the prior art (2), achieving an impedance exceeding the standard.

[0068] Next, in Figure 8 On the lower side, for crosstalk, the S-parameter (S) is shown. 41 This frequency parameter, expressed in decibels, is an example of the measurement results for coupling at angular frequency. Additionally, an example of measurement results for single-wire signal cabling is also shown here. In this figure, lower crosstalk is better. As an example, the crosstalk criterion in a certain communication standard is shown with a dashed line, but this standard requires it to be below -60dB within 1MHz. If crosstalk exceeding this criterion occurs at a specific frequency, it becomes a problem.

[0069] The result of the prior art (1) (characteristic 87 represented by a single-dotted line in the figure) is the aforementioned Figure 5 The results are shown in the case of a printed circuit board with a cross-section as illustrated. By extensively removing the conductor pattern directly beneath the filter components, the electromagnetic coupling between the inner and outer components increases. In this case, crosstalk exceeding the acceptable threshold at approximately 1 GHz becomes a problem for signal quality. On the other hand, although not in Figure 8 The prior art (2) is shown in the lower diagram, but because a conductor pattern is left in the middle layer directly below the filter component, which acts as a shielding layer, crosstalk of less than -200dB is achieved without any problem.

[0070] In contrast, the present invention (characteristic 81 represented by solid lines in the figure: the present invention (1), characteristic 82 represented by dashed lines: the present invention (2)) is the aforementioned Figure 7The results are shown in the case of a printed circuit board with the cross-section shown. By employing a porous grounding pattern 76 in the intermediate layer, a crosstalk reduction effect of -60dB to -100dB was achieved compared to the prior art (1), resulting in a crosstalk level below the judgment standard. Furthermore, the difference in effect between the present invention (1) and the present invention (2) is due to the difference in the formation method of the holes in the porous grounding pattern. This will be explained in detail later in the second embodiment. Figure 8 For characteristic 80 in the upper chart, both the present invention (1) and the present invention (2) can obtain similar results.

[0071] As described above, the circuit board (e.g., printed circuit board 100) according to the first embodiment is a circuit board in which multiple conductor layers (conductor layers 73) with conductor patterns are stacked inside the dielectric layer (dielectric layer 74), and multiple electronic components for connecting signal wiring to transmit signals are disposed on the surface of the dielectric layer, and has the following configuration.

[0072] The circuit board has a first electronic component (e.g., filter component 2-1) disposed on one surface layer of the dielectric layer, and a second electronic component (e.g., filter component 2-2) disposed on another surface layer of the dielectric layer, at a position that at least partially overlaps with the first electronic component in a direction orthogonal to the stacking direction of the conductor layers. The plurality of conductor layers include: removal portions (conductor pattern removal portions 75-1, 75-2) where conductor patterns have been removed from the overlapping area of ​​the first and second electronic components in a direction orthogonal to the stacking direction, and porous portions (porous grounding pattern 76) where a plurality of holes are formed in the overlapping area of ​​the first and second electronic components in a direction orthogonal to the stacking direction.

[0073] Thus, by employing the configuration described in this embodiment on the printed circuit board, even in a high-density substrate mounting configuration where filter components are mounted on both sides, the impedance and crosstalk specifications can be made close to appropriate values. Consequently, this embodiment improves the overall signal quality of the printed circuit board.

[0074] In this embodiment, by intentionally aligning the mounting positions of the filter components on both the surface and back of the printed circuit board (dielectric layer), the mounting density is increased. Therefore, this embodiment, for example, achieves signal transmission performance at the Gbps level via cable transmission while simultaneously increasing the board wiring density (e.g., see reference...). Figure 12 , Figure 13 This enables the miniaturization of printed circuit boards, thereby reducing the size of the ECU housing.

[0075] Furthermore, although this embodiment describes an example where a multi-hole grounding pattern with multiple holes in a conductor layer 73 used for grounding is disposed in the intermediate layer of the printed circuit board 100 (dielectric layer 4), it is not limited to this example. For example, the present invention does not exclude the possibility of improving impedance and crosstalk by disposing of a signal wiring pattern with multiple holes in a conductor layer 73 used for signal transmission in the intermediate layer of the dielectric layer 4.

[0076] Furthermore, although in this embodiment the holes that completely block the conductor layer 73 when viewed from directly above are blocked, the present invention is effective even if it only has conductor layers with holes that are not completely blocked when viewed from directly above. It is best to calculate, through experiments or simulations, how much of a hole remains when viewed from directly above the conductor layer 73 to still achieve the effect of the present invention.

[0077] <Second Implementation>

[0078] Next, use Figure 9 The porous grounding pattern of the printed circuit board according to the second embodiment of the present invention is described. The overall structure of the printed circuit board in this embodiment is the same as that in the first embodiment.

[0079] Figure 9 This is a top view illustrating an example of a printed circuit board according to a second embodiment of the present invention. Figure 9 The diagram shows an example of a porous grounding pattern portion cut out from the structure of a printed circuit board and viewed from directly above (in the stacking direction) the corresponding conductor layer 73. In this embodiment, the holes are circular in shape. Furthermore, it is characterized in that, in the porous grounding pattern, the holes 90 in the upper conductor layer 73 and the holes 91 in the lower conductor layer 73 are configured so that they do not overlap when viewed from the top surface. (The preceding text appears to be incomplete and requires further context.) Figure 8 In the crosstalk characteristics, characteristic 82 of the present invention (2) is obtained according to the second embodiment.

[0080] Furthermore, the characteristic of the present invention (1) is that the positions (lateral positions) of the holes in the upper conductor layer 73 and the lower conductor layer 73 completely overlap. In both of these porous grounding patterns, the impedance characteristics are approximately the same. That is, by making the positions of the holes in adjacent conductor layers 73 non-overlap, the shielding effect of the porous grounding pattern consisting of two layers is improved by -40dB.

[0081] As described above, in the circuit board (e.g., printed circuit board 100) according to the second embodiment, a plurality of conductor layers (conductor layers 73) have a first conductor layer (e.g., upper layer side) and a second conductor layer (e.g., lower layer side) adjacent to the first conductor layer in the stacking direction. The first conductor layer includes a first porous portion having a plurality of holes (holes 90). The second conductor layer includes a second porous portion having a plurality of holes (holes 91), and the positions of the plurality of holes (holes 90) in the second porous portion do not overlap with the plurality of holes (holes 90) formed in the first porous portion included in the first conductor layer in a direction orthogonal to the stacking direction.

[0082] Furthermore, when the multi-hole grounding pattern 76 is composed of only one conductor layer 73 instead of two conductor layers 73, the positions of the holes cannot be staggered, therefore... Figure 8 Only the effects of the present invention (1) (characteristic 81) can be obtained in the middle.

[0083] In this embodiment, although the shape of the hole formed on the conductor layer 73 is described as circular, the shape of the hole is arbitrary. However, a circular shape is preferred to minimize the path of eddy currents flowing around the hole in order to achieve shielding. In the case of a circular hole, a shielding effect can be obtained at a higher frequency.

[0084] <Third Implementation Method>

[0085] Next, use Figure 10 This invention describes the printed circuit board according to the third embodiment of the present invention.

[0086] Figure 10 This is a cross-sectional view showing an example of a printed circuit board 100A according to a third embodiment of the present invention. In the printed circuit board 100A, filter components 2-1 and 2-2 are respectively disposed on one surface and another surface of the dielectric layer 74 (substrate body) in a manner that partially or completely overlaps when viewed from the top surface. In addition, relative to filter components 2-1 and 2-2, in the conductor layer 73 of the inner layer of the printed circuit board 100A, conductor pattern removal portions 75-1 and 75-2 are provided from the interlayer to the intermediate layer in a manner that the conductor patterns (positions of holes in the upper and lower layers) do not overlap directly below the filter components.

[0087] The conductor layer 73 has a total of N layers. Furthermore, in the intermediate layer of the dielectric layer 74, a porous grounding pattern 76 with multiple holes formed on the conductor layer 73 is disposed. The feature of this embodiment is that the conductor layer 73 on which the porous grounding pattern 76 is formed is the N / 2th and N / 2+1th layers counting from the first layer on which the filter component 2-1 is mounted.

[0088] Thus, by setting the porous grounding pattern 76 in the two layers exactly in the middle of the dielectric layer 74, the impedance mismatch problem caused by the conventional uniform shielding layer can be solved for the filter components 2-1 and 2-2.

[0089] (In the case of forming a porous grounding pattern using two conductor layers)

[0090] As described above, in the circuit board according to the third embodiment (e.g., printed circuit board 100A), the plurality of conductor layers (conductor layers 73) are composed of N layers. The conductor layers located in the N / 2th and (N / 2+1)th layers from one surface layer of the dielectric layer (dielectric layer 74) are equivalent to the first conductor layer and the second conductor layer, and the other conductor layers include removal portions. For example, in the case where there are 6 conductor layers 73, the conductor layers 73 in the 3rd and 4th layers counting from one surface layer have porous portions (porous grounding pattern 76).

[0091] (The case of forming a multi-hole grounding pattern using a single conductor layer)

[0092] Furthermore, when only one conductor layer 73 is used to form the porous grounding pattern 76, it can be configured as follows: In the printed circuit board, multiple conductor layers (conductor layers 73) are composed of N layers. The conductor layer located at the N / 2th or (N / 2+1th)th layer from one surface layer of the dielectric layer (dielectric layer 74) contains porous portions (porous grounding pattern 76), and the other conductor layers contain removal portions (conductor pattern removal portions 75-1, 75-2). For example, when there are 6 conductor layers 73, only the conductor layer 73 counting from one surface layer has porous portions (porous grounding pattern 76).

[0093] <Fourth Implementation>

[0094] Next, use Figure 11 This invention describes the printed circuit board according to the fourth embodiment of the present invention.

[0095] Figure 11 This is a cross-sectional view showing an example of a printed circuit board 100B according to a fourth embodiment of the present invention. In the printed circuit board 100B, filter component 2-1 and filter component 2-2A are respectively disposed on one surface and another surface of the circuit board in a manner that partially or completely overlaps when viewed from the top surface. Here, the characteristic is that, comparing the dimensions of filter component 2-1 and filter component 2-2A, filter component 2-1 is larger. In the case of using multi-pole connectors that combine different transmission standards, since the specifications of the filter components are also different, there are cases where it is necessary to mount filter components of different sizes on both sides.

[0096] Furthermore, for filter components 2-1 and 2-2A, in the inner conductor layer 73 of the printed circuit board, conductor pattern removal portions 75-1A and 75-2A are provided from the surface layer to the middle layer in such a way that the conductor patterns do not overlap directly below the filter components. Additionally, the conductor layer 73 has a total of N layers.

[0097] Furthermore, a porous grounding pattern 76A with multiple holes in the conductor pattern is disposed in the intermediate layer. The key feature is that the conductor layer in which the porous grounding pattern 76A is disposed is located at least from the first layer, counting from the N / 2+1th layer onwards, where the larger filter component 2-1 is mounted. Generally, the larger the size of the filter component, the larger the area opposite the conductor layer 73, thus generating a larger parasitic capacitance. Therefore, it is desirable to make the conductor pattern removal section 75-1A deeper directly below the filter component with a large component size. This solves the impedance mismatch problem caused by the conventional uniform shielding layer for the filter components 2-1 and 2-2A.

[0098] (In the case of forming a multi-hole grounding pattern using two conductor layers)

[0099] As described above, in the circuit board (e.g., printed circuit board 100B) according to the fourth embodiment, a plurality of conductor layers (conductor layers 73) are composed of N layers. When the first electronic component (filter component 2-1) is larger than the second electronic component (filter component 2-2A) in a direction orthogonal to the stacking direction, the first conductor layer (e.g., upper layer side) and the second conductor layer (e.g., lower layer side) are located at the (N / 2+1)th layer or higher from the surface layer of the dielectric layer (dielectric layer 74) where the first electronic component is disposed. The other conductor layers include removal portions (conductor pattern removal portions 75-1A, 75-2A). For example, when there are 6 conductor layers 73, the 4th and 5th conductor layers 73 counting from one surface layer have porous portions (porous grounding pattern 76A).

[0100] (The case of forming a multi-hole grounding pattern using a single conductor layer)

[0101] Furthermore, when only one conductor layer 73 is used to form the porous grounding pattern 76, the configuration can be as follows: In the printed circuit board, multiple conductor layers (conductor layers 73) are composed of N layers. When the first electronic component (filter component 2-1) is larger than the second electronic component (filter component 2-2A) in a direction orthogonal to the stacking direction, the conductor layers located from the (N / 2+1)th layer above the surface layer of the dielectric layer (dielectric layer 74) where the first electronic component is disposed include porous portions (porous grounding pattern 76A), and the other conductor layers include removal portions (conductor pattern removal portions 75-1A, 75-2A). For example, when there are 6 conductor layers 73, only the 4th conductor layer 73 counting from one surface layer has porous portions (porous grounding pattern 76A).

[0102] <Fifth Implementation>

[0103] Next, use Figure 12 This invention describes the printed circuit board according to the fifth embodiment of the present invention.

[0104] Figure 12 This is a top view illustrating an example of a printed circuit board 100C according to a fifth embodiment of the present invention. The printed circuit board 100C within the ECU transmits signals from a 4-channel coaxial cable to a communication LSI 16 mounted on the printed circuit board 100C. For this purpose, in the printed circuit board 100C, regarding the four signal lines from the housing-side 4-pole connector 11, the surface signal wiring 13-1 to 13-2 and the bottom signal wiring 18-1 to 18-2 on the printed circuit board 100C are connected to the communication LSI 16.

[0105] Furthermore, two of the four PoC filters (filter components) used for PoC communication via coaxial cable overlay power supply (filter components 14-2 and 14-3) are mounted on the surface layer, and the remaining two (filter components 14-1 and 14-4) are mounted on the bottom layer. In this case, by configuring filter components 14-2 and 14-3 to overlap with their corresponding filter components 14-1 and 14-4 on both sides of the printed circuit board 100C, the size of the area occupied by the four filter components 14-1 to 14-4 can be controlled to be within a range equivalent to the width of the connector.

[0106] In this configuration, two sets of wiring adjacent to the pins of the 4-pole connector 11 on the housing side form a pair of surface wiring and back wiring, and a multi-hole grounding pattern shared by the filter components 14-1 to 14-4 connected to each other is formed in the inner layer.

[0107] As described above, in the circuit board (e.g., printed circuit board 100C) according to the fifth embodiment, a multi-pole connector (e.g., housing-side 4-pole connector 11) and a communication circuit (communication LSI 16) that can connect multiple coaxial cables are mounted on the circuit board.

[0108] In this circuit board, the number of poles M (e.g., 4 poles) of the multi-pole connector is a multiple of 2. The multi-pole connector and the communication circuit are connected by the same number of signal wirings (signal wirings 13-1 to 13-2, 18-1 to 18-2) as the number of poles M. Each signal wiring has one or more electronic components connected to it.

[0109] One electronic component (filter components 14-2, 14-3) connected to the adjacent signal wiring is mounted on the surface of the dielectric layer (dielectric layer 74), and the other electronic component (filter components 14-1, 14-4) connected to the adjacent signal wiring is mounted on the back side of the dielectric layer. The positions of the electronic components mounted on the surface and back side of the dielectric layer overlap in the direction orthogonal to the stacking direction of the conductor layer (conductor layer 73).

[0110] With this configuration, the printed circuit board 100C according to this embodiment can connect the housing-side 4-pole connector 11 and the communication LSI 16 while densely mounting the filter components 14-1 to 14-4. In this example, a porous grounding pattern 76-1 shared by filter components 14-1 and 14-2 is formed in the inner layer, and a porous grounding pattern 76-2 shared by filter components 14-3 and 14-4 is separately formed in the inner layer.

[0111] Furthermore, this embodiment uses a 4-pole connector as an example, but it is not limited to this example. The number of channels (poles) can also be 2, 3, or more than 4.

[0112] <Sixth Implementation Method>

[0113] Next, use Figure 13 This invention describes the printed circuit board according to the sixth embodiment of the present invention. Figure 13 This is a top view illustrating an example of a printed circuit board 100D according to a sixth embodiment of the present invention. The printed circuit board 100D within the ECU transmits signals from a 2-channel differential cable to a communication LSI 16 mounted on the printed circuit board 100D. For this purpose, regarding the two pairs of differential signal wirings from the housing-side 2-pole differential connector 130, the printed circuit board 100D within the ECU uses surface differential pair wiring 131 and bottom differential pair wiring 132 on the printed circuit board 100D to connect to the communication LSI 16.

[0114] Additionally, the connection from the surface layer to the bottom layer is switched using differential signal connection vias 133-1 and 133-2. In differential cable communication, to cut off the common-mode component, which is a factor contributing to noise radiation and Electromagnetic Susceptibility (EMS), a common-mode choke coil is typically inserted between the housing-side 2-pole differential connector 130 and the communication LSI 16. The common-mode choke coil is a 4-terminal component that houses two pairs of coils.

[0115] In this configuration, a filter component 134-1, consisting of a common-mode choke coil for the differential distribution lines on the surface layer, is mounted on the surface layer, and a filter component 134-2, consisting of a common-mode choke coil for the differential distribution lines on the bottom layer, is mounted on the bottom layer. Furthermore, by arranging these filter components 134-1 and 134-2 in a lateral overlapping manner on both sides of the printed circuit board 100D, the width can be controlled to be within a range equivalent to the connector width.

[0116] In this configuration, two pairs of differential wiring 131 and 132 adjacent to the pins of the housing-side two-pole differential connector 130 form a pair of surface wiring and back wiring, and a shared multi-hole grounding pattern is formed in the inner layer for the filter components 134-1 and 134-2, which are respectively connected. The surface filter component 134-1 is connected to the housing-side two-pole differential connector 130 and the communication LSI 16 via the differential wiring 131. In addition, the back filter component 134-2 is connected to the housing-side two-pole differential connector 130 via the differential signal connection via 133-1 and the differential wiring 132, and is connected to the communication LSI 16 via the differential signal connection via 133-2 and the differential wiring 132.

[0117] As described above, in the circuit board (e.g., printed circuit board 100D) according to the sixth embodiment, a multi-pole differential connector (e.g., housing-side 2-pole differential connector 130) and a communication circuit (communication LSI 16) that can connect multiple differential cables are mounted on the circuit board.

[0118] In this circuit board, the number of differential pairs M (e.g., 2 pairs) of the multi-pole differential connector is a multiple of 2. The multi-pole differential connector and the communication circuit are connected by the same number of differential pair wirings (differential pair wirings 131, 132) as the number of differential pairs M. Each differential pair wiring is connected to one or more electronic components.

[0119] One electronic component (filter component 134-1) connected to the adjacent differential pair wiring is mounted on the surface of the dielectric layer, and the other electronic component (filter component 134-2) connected to the adjacent differential pair wiring is mounted on the back side of the dielectric layer. The positions of the electronic components mounted on the surface and back side of the dielectric layer overlap in the direction orthogonal to the stacking direction of the conductor layer.

[0120] With this configuration, the printed circuit board 100D according to this embodiment can connect the housing-side two-pole differential connector 130 and the communication LSI 16 while densely mounting the filter components 134-1 and 134-2. In this example, a multi-hole grounding pattern 76 shared by the filter components 134-1 and 134-2 is formed in the inner layer.

[0121] [0t074] Furthermore, although an example of two differential pair wirings has been described in this embodiment, it is not limited to this example, and the number of differential pair wirings may also be three or more.

[0122] <Seventh Implementation>

[0123] Next, use Figure 14 The printed circuit board according to the seventh embodiment of the present invention will be described. In particular, a preferred example of the size of the holes formed in the via grounding pattern will be described.

[0124] Figure 14 This is a top view showing an example of a printed circuit board according to the seventh embodiment of the present invention and a diagram showing an example of the effect of the hole size. Figure 14 The image shows an example where only a portion of the porous grounding pattern is cut out from the structure of a printed circuit board, and viewed from directly above the corresponding conductor layer 73. In this embodiment, the holes are circular in shape. Furthermore, in the porous grounding pattern 76B, the holes 90 in the upper conductor layer 73 and the holes 91 in the lower conductor layer 73 are configured so that they do not overlap when viewed from the top surface.

[0125] Here, in Figure 14 Below, a graph showing the crosstalk characteristics when the diameters of holes 90 and 91 are varied, for example, within the range of 0.5 to 2.0 mm. (This is in contrast to the aforementioned...) Figure 8 Similarly, feature 87 is an example of the prior art (1). As can be seen from this chart, the smaller the aperture, the greater the crosstalk reduction effect. Figure 14 As can be seen from the chart below, when the aperture diameter is below 2.0 mm, a certain amount of crosstalk reduction effect is achieved compared to the prior art (1), and the aperture size becomes an indicator. For example, near 20 GHz, where crosstalk increases sharply, the aperture diameter is preferably below 1.0 mm, taking into account the margin.

[0126] <Eighth Implementation Method>

[0127] Next, use Figure 15 The printed circuit board according to the eighth embodiment of the present invention will be described. In particular, preferred examples of the porous grounding pattern and the size of the holes formed thereon will be described.

[0128] Figure 15 This is a top view illustrating an example of a printed circuit board according to the eighth embodiment of the present invention. Figure 15 The image shows an example where only a portion of the porous grounding pattern is cut out from the structure of the printed circuit board, and viewed from directly above the corresponding conductor layer 73. In this embodiment, the holes are circular in shape. Furthermore, in the porous grounding pattern, the holes 90-1 and 90-2 located in the upper layer and the holes 91-1 and 91-2 located in the lower layer are configured so that they do not overlap when viewed from the top surface.

[0129] Here, in Figure 15 In the diagram, the component mounting area 150 is indicated by a dashed line. For example... Figure 15 As shown, this embodiment is characterized in that the diameter of the porous grounding pattern directly below the component mounting area is different from the diameter of the porous grounding patterns disposed around it. The diameter Φ_1 of the holes 90-2 and 91-2 on the inner side of the component mounting area 150 is smaller than the diameter Φ_2 of the holes 90-1 and 91-1 on the outer side.

[0130] The effect of this configuration is that, while maintaining crosstalk reduction, it further suppresses impedance drop caused by parasitic capacitance. As previously shown, the smaller the aperture, the greater the crosstalk reduction effect; therefore, the smaller the aperture of the grounding aperture directly below the component, the better.

[0131] On the other hand, if the electric field coupling between the filter components and the conductor pattern is considered, the electric field lines extend outward due to the edge effect, thus effectively reducing the coupling caused by these outwardly extending electric field lines. Therefore, this embodiment has the effect of further reducing the parasitic capacitance component.

[0132] As described above, in the printed circuit board according to this embodiment, in the porous grounding pattern 76B, the diameter of the holes (holes 90-1, 91-1) located outside the area overlapping with the electronic component in the direction orthogonal to the stacking direction of the conductor layer 73 is larger than the diameter of the holes (holes 90-2, 91-2) located in the area overlapping with the electronic component.

[0133] While this specification describes the invention primarily in the context of an in-vehicle ECU (electronic control unit), it is applicable to other applications utilizing the same communication system. For example, the invention can also be used in communication between industrial robots and electronic cameras.

[0134] Furthermore, the present invention is not limited to the above-described embodiments. Various other modifications and applications are possible as long as they do not depart from the spirit of the invention as described in the claims. For example, the above embodiments have been described in detail and specifically for the purpose of easily understanding the present invention, and are not necessarily limited to having all the described constituent elements. Additionally, a portion of the composition of one embodiment may be replaced with constituent elements of other embodiments. Furthermore, constituent elements of other embodiments may be added to the composition of one embodiment. Moreover, regarding a portion of the composition of each embodiment, other constituent elements may be added, replaced, or deleted.

[0135] Furthermore, in the above embodiments, the control lines and information lines shown are only those deemed necessary for explanation, and not all control lines and information lines on the product are necessarily shown. In fact, it can be assumed that almost all components are interconnected.

[0136] To facilitate understanding of the invention, the positions, sizes, shapes, and extents of the constituent elements shown in the drawings may not represent their actual positions, sizes, shapes, and extents. Therefore, the present invention is not necessarily limited to the positions, sizes, shapes, and extents disclosed in the drawings.

[0137] Furthermore, although terms such as “parallel” and “orthogonal” are used in this specification, these terms do not refer only to strictly “parallel” and “orthogonal” terms, but rather to “parallel” and “orthogonal” in the strict sense, and also to “approximately parallel” and “approximately orthogonal” within the scope of their function.

[0138] Symbol Explanation

[0139] 100, 100A~100D… Printed circuit board, 2-1, 2-2… Filter components, 73… Conductor layer, 74… Dielectric layer, 75-1, 75-2… Conductor pattern removal section, 76… Multi-hole grounding pattern.

Claims

1. A circuit board comprising a plurality of conductor layers having conductor patterns formed thereon stacked inside a dielectric layer, and a plurality of electronic components disposed on the surface of the dielectric layer, the plurality of electronic components being connected to signal wiring for transmitting signals. The circuit board is characterized in that: A first electronic component is disposed on one surface layer of the dielectric layer. A second electronic component is disposed on another surface layer of the dielectric layer, in a direction orthogonal to the stacking direction of the conductor layer, at a position that at least partially overlaps with the first electronic component. The plurality of conductor layers comprises: A removal section that removes the conductor pattern within the overlapping area of ​​the first electronic component and the second electronic component in a direction orthogonal to the stacking direction; and A porous portion having multiple holes formed in the overlapping area of ​​the first electronic component and the second electronic component in a direction orthogonal to the stacking direction.

2. The circuit board according to claim 1, characterized in that: The plurality of conductor layers includes a first conductor layer and a second conductor layer, the first conductor layer comprising a first porous portion having a plurality of holes, and the second conductor layer being adjacent to the first conductor layer in the stacking direction. The second conductor layer includes a second porous portion, which is formed with a plurality of holes in such a way that the positions of the plurality of holes in a direction orthogonal to the stacking direction do not overlap with the plurality of holes formed in the first porous portion included in the first conductor layer.

3. The circuit board according to claim 1, characterized in that: The plurality of conductor layers consists of N layers. The conductor layer located in the N / 2 or (N / 2+1)th layer from one surface layer of the dielectric layer contains the porous portion, and the other conductor layers contain the removal portion.

4. The circuit board according to claim 2, characterized in that: The plurality of conductor layers consists of N layers. The conductor layers located in the N / 2 and (N / 2+1)th layers from one surface layer of the dielectric layer correspond to the first conductor layer and the second conductor layer, and the other conductor layers contain the removal portion.

5. The circuit board according to claim 1, characterized in that: The plurality of conductor layers consists of N layers. When the first electronic component is larger than the second electronic component in a direction orthogonal to the stacking direction, the conductor layers located above the (N / 2+1)th layer from the surface layer of the dielectric layer where the first electronic component is disposed include the porous portion, and the other conductor layers include the removal portion.

6. The circuit board according to claim 2, characterized in that: The plurality of conductor layers consists of N layers. When the first electronic component is larger than the second electronic component in a direction orthogonal to the stacking direction, the first conductor layer and the second conductor layer are located at the (N / 2+1)th layer or higher from the surface layer of the dielectric layer where the first electronic component is disposed, and the other conductor layers include the removal portion.

7. The circuit board according to claim 1, characterized in that: A multi-pole connector capable of connecting multiple coaxial cables and communication circuitry are mounted on the circuit board. The number of poles M of the multi-pole connector is a multiple of 2. The multi-pole connector and the communication circuit are connected by a signal wiring with the same number of poles M. One or more of the aforementioned electronic components are connected to the signal wiring. One of the electronic components connected to the adjacent signal wiring is mounted on the surface of the dielectric layer. Another electronic component connected to the adjacent signal wiring is mounted on the back side of the dielectric layer. The electronic components mounted on the surface and back of the dielectric layer overlap in a direction orthogonal to the stacking direction of the conductor layer.

8. The circuit board according to claim 1, characterized in that: A multi-pole differential connector capable of connecting multiple differential cables and communication circuitry are mounted on the circuit board. The number of differential pairs M of the multi-pole differential connector is a multiple of 2. The multi-pole differential connector and the communication circuit are connected by differential pair wiring with the same number of differential pairs M. Each of the differential pair wirings is connected to one or more of the aforementioned electronic components. One of the electronic components connected to the adjacent differential pair wiring is mounted on the surface of the dielectric layer. The other electronic component connected to the adjacent differential pair wiring is mounted on the back side of the dielectric layer. The electronic components mounted on the surface and back of the dielectric layer overlap in a direction orthogonal to the stacking direction of the conductor layer.

9. The circuit board according to claim 1, characterized in that: The holes in the porous section are circular in shape. The diameter of the hole is less than 2.0 mm.

10. The circuit board according to claim 2, characterized in that: The holes in the porous section are circular in shape. The diameter of the hole located outside the region overlapping with the electronic component in a direction orthogonal to the stacking direction is larger than the diameter of the hole located within the region overlapping with the electronic component.

11. An electronic control device comprising a circuit board having a plurality of conductor layers with conductor patterns stacked inside a dielectric layer, and a plurality of electronic components disposed on the surface of the dielectric layer, the plurality of electronic components being connected to signal wiring for transmitting signals. The electronic control device is characterized in that: A first electronic component is disposed on one surface layer of the dielectric layer. A second electronic component is disposed on another surface layer of the dielectric layer, in a direction orthogonal to the stacking direction of the conductor layer, at a position that at least partially overlaps with the first electronic component. The plurality of conductor layers comprises: A removal section that removes the conductor pattern within the overlapping area of ​​the first electronic component and the second electronic component in a direction orthogonal to the stacking direction; and A porous portion having multiple holes formed in the overlapping area of ​​the first electronic component and the second electronic component in a direction orthogonal to the stacking direction.

Images