Semiconductor memory device and method of manufacturing the same

Abstract

A DRAM composed of only MOSFETs and a manufacturing method thereof, which can be mass-produced, has a memory cell array structure in which a plurality of layers are stacked with a MOSFET group insulated from a substrate and horizontally arranged with respect to the substrate; each MOSFET forms one memory cell, each memory cell is provided with a silicon channel layer and a pair of source and drain diffusion layers; the two diffusion layers are respectively connected to different wiring lines; a pair of wiring lines extend in parallel; in each MOSFET, two gate conductor layers form a vertical column in a manner of sandwiching the silicon channel layer; a gate terminal of one of the gate conductor layers extends to the source and drain diffusion layers; the other gate conductor layer does not extend to the source and drain diffusion layers, and two insulating film columns different from the gate insulating film are respectively arranged between the gate and the two diffusion layers.

Description

Technical Field

[0001] This invention relates to a semiconductor memory device and the operation of a semiconductor memory device. Background Technology

[0002] In recent years, there has been a pursuit of high integration and high performance of memory elements in Large Scale Integration (LSI). DRAM (Dynamic Random Access Memory, e.g., Non-Patent Document 1), which is connected to capacitors, cannot stack memory cells in three dimensions, thus hindering high integration. On the other hand, previous proposals have suggested using a MOS transistor employing Silicon On Insulator (SOI) to fabricate capacitor-free DRAM cells (Non-Patent Documents 2, 3). However, these methods have encountered problems in data retention and have not been practically implemented.

[0003] Figure 12-1 This demonstrates the operation of writing a "1" to a DRAM cell that does not have a capacitor. Figure 12-2 This displays the state of the cell after a "1" has been written. Figure 12-3 This demonstrates the operation of writing "0". (Refer to Non-Patent Literature 2) Figure 12-1This demonstrates the operation of writing a "1". Here, the memory cell is composed of: a source N+ layer 303 (formed on the SOI substrate 300 and connected to the source line SL) (hereinafter, the semiconductor region including high-concentration donor impurities is referred to as the "N+ layer", and the semiconductor region including acceptor impurities is referred to as the "P layer"), a drain N+ layer 304 (connected to the bit line BL), a gate conductive layer 305 (connected to the word line WL), and a floating body 302 of the P layer of a MOS transistor 310-1. It does not include a capacitor, and the memory cell of the DRAM is composed of a single MOS transistor 310-1. Furthermore, the floating body 302 is in direct contact with the SiO2 layer 301 of the SOI substrate. When writing a "1", the memory cell composed of a single MOS transistor 310-1 operates in the saturation region. That is, the inversion layer 307 extending from the source N+ layer 303 does not reach the drain N+ layer 304 connecting the bit line. In this way, by operating the MOS transistor 310-1 with both the bit line BL connecting the drain N+ layer 304 and the word line WL connecting the gate conductive layer 305 at high voltages, and with the gate voltage being approximately 2 / 3 of the drain voltage, the electric field strength is maximized at the pinch point near the drain N+ layer 304 where there is no inversion layer. Therefore, electrons flowing from the source N+ layer 303 to the drain N+ layer 304 are accelerated and collide with the Si lattice, generating electron-hole pairs (collision ionization) due to the lost kinetic energy. Most of the generated electrons (not shown in the figure) reach the drain N+ layer 304. A small portion of the hot electrons cross the gate oxide film 309 and reach the gate conductive layer 305. Simultaneously, the generated holes 306 charge the float 302. Since the float 302 is P-type Si, the generated holes contribute to a greater increase in carriers. When the float 302 is filled with the generated holes 306, causing the voltage of the float 302 to be higher than Vb (built-in potential) than that of the source N+ layer 303, further generated holes will discharge the source N+ layer 303. Here, Vb is the built-in voltage of the PN junction between the source N+ layer 303 and the float 302 in the P layer, which is approximately 0.7V. Figure 12-2 The floating body 302 is shown to be saturated due to the generated electrical hole 306.

[0004] Next, through Figure 12-3 This describes the operation of writing "0" to memory cell 310. Relative to the shared select word line WL, there are randomly existing memory cells 310-1 that are written with "1" and 310-2 that are written with "0". Figure 12-3This presents a scenario where the state changes from writing "1" to writing "0". When writing "0", the voltage of bit line BL is set to -0.9V, the source line SL is set to 0V, and 1V is applied to word line WL, thereby making the PN junction between the drain N+ layer 304 and the float 302 of the P layer forward biased. Therefore, the hole 306 pre-generated in the float 302 during the current cycle will flow to the drain N+ layer 304 connected to the bit line BL. After the write operation is completed, a memory cell 310-1 filled with the generated hole 306 is obtained. Figure 12-2 ), and the memory unit 310-2 that discharged the generated holes ( Figure 12-3 These are the two states of memory cells. The potential of the float 302, which is filled with holes 306 in memory cell 310-1, is higher than that of the float 302-2, which does not have the generated holes. Therefore, the threshold voltage of memory cell 310-1 is lower than that of memory cell 310-2. Figure 12-4 This situation is presented.

[0005] Figure 13 illustrates the reading operation (refer to Non-Patent Document 2). Figure 13-1 It is in a state where "0" has been written. Figure 13-2 This presents a state where a "1" is written. The voltage of bit line BL is set to a positive voltage (e.g., 0.2V), the source N+ layer 303 is set to 0V, and a forward bias voltage (e.g., 0.8V) is applied to the gate conductive layer 305. Because the threshold values ​​for writing a "0" and writing a "1" are different, such as... Figure 13-3 As shown, the cell current (Icell) during the reading of the two is different, and this difference is detected to determine "1" or "0".

[0006] One problem with SOI memory cells is the short data retention time after data is written (see Non-Patent Document 2). As an example, Figure 14 illustrates the problem with the data retention characteristics of a memory cell in a "0" state. First... Figure 14-1The memory array consists of two memory cells sharing a common bit line. When a "0" is written to the lower cell, -0.9V is applied to the bit line BL, 0V to the source line, and 1V to the word line WL. Conversely, the upper cell is a non-selection cell for writing "0". Even though the bit line is -0.9V and the source line is 0V, -1.5V is still applied to the word line to keep the memory transistor off. To quickly apply -1.5V to all non-selection word lines when writing "0", the memory array sets the bit line and source line to 0V in standby mode (a state without write or read operations) and constantly applies -1.5V to the word line. By applying -1.5V to the word line in standby mode, holes accumulated in the channel portion of the memory cell in the "1" state will gather below the gate, suppressing the recombination of holes and electrons, thus allowing holes to remain in the channel portion for a longer period. Therefore, when reading a memory cell after a 1-second standby period following data writing, the I-cell in the "1" state remains almost unchanged compared to immediately after writing. On the other hand, the I-cells in the "0" state gradually increase during standby; for example, at a standby temperature of 85°C, they will become roughly the same as the "1" state in about 100ms. If the difference between I-cells ("1") and I-cells ("0") decreases, the possibility of data read errors increases, thus limiting the standby time to approximately 50ms. However, in large-scale LSIs, the distribution of memory cells must be considered, further reducing the upper limit of standby time. Short data retention necessitates frequent data rewriting, and standby current consumption also increases, making it unsuitable for mass production.

[0007] The reason why the read current of cell "0" increases during standby is as follows: Figure 14-2 As shown. If a negative voltage of -1.5V is applied to the gate 305, the silicon electric field under the gate insulating film increases at the boundary between the source 303 and the channel 302, and at the boundary between the drain 304 and the channel 302, causing silicon electrical breakdown and generating electron-hole pairs. The generated electrons are absorbed by the source and drain, while the holes accumulate in the channel portion, causing the Icell to gradually increase.

[0008] [Existing technical documents] [Non-patent literature] [Non-patent document 1] H. Ishiuchi, T. Yoshida, H. Takato, K. Tomioka, K.Matsuo, H. Momose, S. Sawada, K. Yamazaki aNd K. Maeguchi: INterNatioNalElectroN Devices MeetiNg, pp. 33-36 (1997) [Non-patent document 2] T. Ohsawa, K. Fujita, T. Higashi, Y. Iwata, T.Kajiyama, Y. Asao, aNd K. SuNouchi: "Memory DesigN UsiNg (a) ONe-TraNsistorGaiN Cell oN SOI," IEEE JourNal of Solid-State Circuits, Vol. 37, No. 11, pp.1510-1522 (2002) [Non-patent document 3] MG ErtosuN, K. Lim, C. Park, J. Oh, P. Kirsch, aNdK. C. Saraswat: "Novel Capacitorless SiNgle-TraNsistor Charge-Trap DRAM (1TCT DRAM) UtiliziNg ElectroNs," IEEE Device Letter, Vol. 31, No.5, pp. 405-407 (2010) Summary of the Invention

[0009] DRAM, which uses only MOS transistors and lacks capacitors, has a shorter data retention time compared to DRAM using capacitors, making it difficult to implement in practical applications. Furthermore, the MOS transistors on SOI result in a larger area per memory cell, limiting the possibility of large-capacity DRAM.

[0010] To address the aforementioned problems, this invention employs a method for manufacturing a memory device using semiconductor elements. Multiple horizontally arranged MOS transistor clusters, insulated from a substrate, are vertically stacked, with insulating films separating each transistor layer. Each horizontally arranged MOS transistor cluster has a thickness of several tens of nanometers. Each MOS transistor forms a memory cell, and each memory cell includes a silicon channel layer and a pair of source diffusion layers and drain diffusion layers. The source diffusion layers are connected to a metal layer (source line), and the drain diffusion layers are connected to a metal layer (bit line), both having the same thickness. Furthermore, the pair of source lines and bit lines extend parallel to each other and connect to the source diffusion layers and drain diffusion layers of multiple memory cells existing on the same horizontal plane. Viewed from above, the pair of elongated source lines and bit lines extend side-by-side, and multiple sets of the same source lines and bit lines exist in parallel, forming a cell array. Furthermore, the bit lines of the upper and lower segments are electrically insulated from each other, and each segment is independently supplied with voltage within the column decoder at the memory cell array end, while the source lines within a single cell array are all supplied with a common voltage. Moreover, the gate conductor layer is formed as a vertical column, allowing the topmost MOS transistor to be shared from the bottommost MOS transistor when viewed from above. Within a single MOS transistor, two gate conductor layers are disposed, separated by a gate insulating film, in a manner that sandwiches the silicon channel layer. That is, the channel layer of a memory cell is sandwiched between source and drain diffusion layers at both ends, and at the other two ends in a 90-degree direction, it is separated by a gate insulating film and surrounded by two gate conductor layers. The gate end of a single gate conductor layer extends to the source and drain diffusion layers separated by a gate insulating film, and is responsible for changing the MOS transistor between on and off states; this is called the "memory gate." The other gate conductor layer is shorter and does not extend to the source and drain diffusion layers at either end. It is responsible for retaining the accumulated holes within the channel and is named the "storage gate." Two insulating film pillars, different from the gate insulating film, are respectively positioned between the storage gate and the source diffusion layer, and between the storage gate and the drain diffusion layer, so that the storage gate does not directly contact the source and drain diffusion layers. The insulating film pillars are thicker than the gate insulating film when viewed from above. The width of the silicon channel layer perpendicular to the memory gate is narrower at the two locations where the insulating film pillars are present compared to the locations without them. These insulating film pillars, like the gate conductor layer, are formed so that the topmost to bottommost MOS transistors can share the same position when viewed from above. An interlayer insulating film is provided on top of the topmost MOS transistor layer. The memory gate extends to the top of this insulating film and is connected to a gate wiring called a word line. The storage gate also extends to the top of this insulating film and is connected to a gate wiring called a storage gate line. These two types of gate wirings extend in parallel and are connected to a column decoder located at one end of the memory cell array.The two types of gate wiring are perpendicular to the bit lines and source lines. The memory gate and storage gate in each memory cell are connected to the gate wiring above them. That is, multiple types of gate wiring extend in parallel and are connected to the column decoder. Each gate wiring is applied with an independent potential according to its operation.

[0011] In one embodiment, the source line is normally applied 0V. For the gate line, a negative voltage is applied except when the memory cell connected to the gate line is written with "0" data. Also, a positive voltage is applied to the gate line when the memory cell connected to the gate line is written with "0" data. For the word line, a positive voltage is applied when the memory cell connected to the word line is written with and read with "0" and "1" data respectively; otherwise, 0V is applied during standby. For the bit line, a positive voltage is applied when the memory cell connected to the bit line is written with "1" data or read with data respectively; otherwise, 0V is applied.

[0012] Because memory cells are stacked vertically in multiple layers, the number of memory cells in a given memory region when viewed from above is directly proportional to the number of stacked memory cell layers. Increasing the number of memory cell layers increases memory capacity, allowing for the fabrication of larger capacity memory chips.

[0013] Furthermore, if a memory cell is in a "1" state, holes accumulate within the silicon channel. When a negative voltage is applied to the memory cell connected to the gate line (except when writing "0" data), the holes remain near the memory gate within the silicon channel. On the other hand, no negative voltage is applied to the memory gate, so even if electrons remain in the silicon channel, they remain near the memory gate. Therefore, the chance of holes and electrons meeting within the silicon channel is extremely low, reducing the probability of hole-electron recombination. Thus, even if a memory cell is in a "1" state and holes accumulate within the silicon channel, the holes will not recombine with electrons for a long time, maintaining the "1" state for an extended period. Moreover, the memory gate is not in contact with the source and drain diffusion layers; instead, an insulating film pillar is sandwiched between the memory gate and the two diffusion layers. Therefore, even if a negative voltage is applied to the memory gate (except when writing "0" data), the silicon channel layer near the memory gate will not experience breakdown, thus preventing the formation of electron-hole pairs. Therefore, memory cells written with "0" data are less prone to hole accumulation and can remain in the "0" state for a long time. This allows the data retention time to increase. Attached Figure Description

[0014] [Figure 1] Figure 1-1 A three-dimensional diagram showing the memory cell array structure of the first embodiment. Figure 1-2 yes Figure 1-1 AA line cross section view, Figure 1-3 yes Figure 1-1 BB line cross-section.

[0015] [Figure 2] Figure 2-1 yes Figure 1-1 A top-down view, showing the area enclosed by a dashed line for one memory cell. Figure 2-2 It is its equivalent circuit diagram. Figure 2-3 This is a top view of the eight memory cells arranged together. Figure 2-4 This is its equivalent circuit diagram.

[0016] [Figure 3] Figure 3-1 A three-dimensional diagram showing the connections of the core circuitry surrounding the memory cell array and the driver cell array. Figure 3-2 yes Figure 3-1 AA-line cross-section view.

[0017] [Figure 4] Figure 4-1 A diagram illustrating the operation of memory units. Figure 4-2 Presentation corresponds to Figure 4-1 The state of the memory unit.

[0018] [Figure 5] Figure 5-1 A top view of the memory cell showing the method of writing "0". Figure 5-2 This is the timing diagram for writing "0".

[0019] [Figure 6] Figure 6-1 A top view of the memory cell showing the method of writing "1". Figure 6-2 This is the timing diagram for writing "1".

[0020] [Figure 7] Figure 7-1 This shows the structure of the cell array and the voltage of each node when a "0" is written. Figure 7-2 This shows the structure of the cell array and the voltage of each node when a "1" is written. Figure 7-3 This shows the structure of the cell array and the voltage of each node when reading data.

[0021] [ Figure 8 A diagram and table showing the dimensions of the components that make up a memory unit.

[0022] [ Figure 9-1 [Figure used to illustrate the manufacturing method of the semiconductor memory device of the first embodiment.]

[0023] [ Figure 9-2 [Figure used to illustrate the manufacturing method of the semiconductor memory device of the first embodiment.]

[0024] [Figure 9-3] Figure 9-3a[Figure used to illustrate the manufacturing method of the semiconductor memory device of the first embodiment.]

[0025] [ Figure 9-3b [Figure used to illustrate the manufacturing method of the semiconductor memory device of the first embodiment.]

[0026] [ Figure 9-4 [Figure used to illustrate the manufacturing method of the semiconductor memory device of the first embodiment.]

[0027] [ Figure 9-5 [Figure used to illustrate the manufacturing method of the semiconductor memory device of the first embodiment.]

[0028] [ Figure 9-6 [Figure used to illustrate the manufacturing method of the semiconductor memory device of the first embodiment.]

[0029] [ Figure 9-7 [Figure used to illustrate the manufacturing method of the semiconductor memory device of the first embodiment.]

[0030] [ Figure 9-8 [Figure used to illustrate the manufacturing method of the semiconductor memory device of the first embodiment.]

[0031] [ Figure 9-9 [Figure used to illustrate the manufacturing method of the semiconductor memory device of the first embodiment.]

[0032] [ Figure 9-10 [Figure used to illustrate the manufacturing method of the semiconductor memory device of the first embodiment.]

[0033] [ Figure 9-11 [Figure used to illustrate the manufacturing method of the semiconductor memory device of the first embodiment.]

[0034] [ Figure 9-12 [Figure used to illustrate the manufacturing method of the semiconductor memory device of the first embodiment.]

[0035] [ Figure 9-13 [Figure used to illustrate the manufacturing method of the semiconductor memory device of the first embodiment.]

[0036] [ Figure 9-14 [Figure used to illustrate the manufacturing method of the semiconductor memory device of the first embodiment.]

[0037] [ Figure 9-15 [Figure used to illustrate the manufacturing method of the semiconductor memory device of the first embodiment.]

[0038] [ Figure 9-16 [Figure used to illustrate the manufacturing method of the semiconductor memory device of the first embodiment.]

[0039] [ Figure 9-17 [Figure used to illustrate the manufacturing method of the semiconductor memory device of the first embodiment.]

[0040] [ Figure 9-18 [Figure used to illustrate the manufacturing method of the semiconductor memory device of the first embodiment.]

[0041] [ Figure 9-19 [Figure used to illustrate the manufacturing method of the semiconductor memory device of the first embodiment.]

[0042] [ Figure 9-20 [Figure used to illustrate the manufacturing method of the semiconductor memory device of the first embodiment.]

[0043] [ Figure 9-21 [Figure used to illustrate the manufacturing method of the semiconductor memory device of the first embodiment.]

[0044] [ Figure 9-22 [Figure used to illustrate the manufacturing method of the semiconductor memory device of the first embodiment.]

[0045] [ Figure 9-23 [Figure used to illustrate the manufacturing method of the semiconductor memory device of the first embodiment.]

[0046] [ Figure 9-24 [Figure used to illustrate the manufacturing method of the semiconductor memory device of the first embodiment.]

[0047] [ Figure 9-25 [Figure used to illustrate the manufacturing method of the semiconductor memory device of the first embodiment.]

[0048] [ Figure 9-26 [Figure used to illustrate the manufacturing method of the semiconductor memory device of the first embodiment.]

[0049] [ Figure 9-27 [Figure used to illustrate the manufacturing method of the semiconductor memory device of the first embodiment.]

[0050] [ Figure 9-28 [Figure used to illustrate the manufacturing method of the semiconductor memory device of the first embodiment.]

[0051] [Figure 10] Figure 10-1 A three-dimensional diagram showing the memory cell array structure of the second embodiment. Figure 10-2 yes Figure 10-1 AA line cross section view, Figure 10-3 yes Figure 10-1 A top-down view, showing the area enclosed by a dashed line for one memory cell. Figure 10-4It is its equivalent circuit diagram. Figure 10-5 This is a top view of the eight memory cells arranged together. Figure 10-6 It is its equivalent circuit diagram. Figure 10-7 It is a three-dimensional diagram showing the connection of the core circuitry surrounding the memory cell array and the driver cell array. Figure 10-8 yes Figure 10-7 AA line cross section view, Figure 10-9 This shows the structure of the cell array and the voltage of each node when a "0" is written. Figure 10-10 and Figure 10-11 A diagram illustrating the manufacturing method of the semiconductor memory device of the second embodiment.

[0052] [ Figure 11-1 [Figure used to illustrate the manufacturing method of the semiconductor memory device of the third embodiment.]

[0053] [ Figure 11-2 [Figure used to illustrate the manufacturing method of the semiconductor memory device of the third embodiment.]

[0054] [ Figure 11-3 [Figure used to illustrate the manufacturing method of the semiconductor memory device of the third embodiment.]

[0055] [ Figure 11-4 [Figure used to illustrate the manufacturing method of the semiconductor memory device of the third embodiment.]

[0056] [ Figure 11-5 [Figure used to illustrate the manufacturing method of the semiconductor memory device of the third embodiment.]

[0057] [ Figure 11-6 [Figure used to illustrate the manufacturing method of the semiconductor memory device of the third embodiment.]

[0058] [ Figure 11-7 [Figure used to illustrate the manufacturing method of the semiconductor memory device of the third embodiment.]

[0059] [Figure 12] Figure 12-1 [A diagram used to illustrate the operation of writing "1" into a memory cell as shown in the example.]

[0060] [ Figure 12-2 [A diagram used to illustrate the state of a memory cell in an existing example after writing "1".]

[0061] [ Figure 12-3 [A diagram used to illustrate the operation of writing "0" into a memory cell in an existing example.]

[0062] [ Figure 12-4 [A diagram used to illustrate the voltage-current characteristics of a memory cell in an existing example.]

[0063] [Figure 13] Figure 13-1 [A diagram used to illustrate the "0" state of a memory cell in an existing example.]

[0064] [ Figure 13-2 [A diagram used to illustrate the "1" state of a memory cell in an existing example.]

[0065] [ Figure 13-3 [A diagram used to illustrate the reading operation of an existing example.]

[0066] [Figure 14] Figure 14-1 This graph shows the voltage applied to the two memory cells when the current example reads "0".

[0067] [ Figure 14-2 A diagram showing existing problems in the operation of memory units.

[0068] Explanation of reference numerals in the attached figures: 1:Substrate 2: Insulating film 3: Intrinsic silicon semiconductor 4: Top layer insulating film 5: N-type or P-type silicon layer 6: The first etched section of the stack of silicon layer and insulating film layer 7: Second etched section of the stack of silicon layer and insulating film layer 8: The third etched section of the stack of silicon layer and insulating film layer 9: Gate insulating film 10: Gate material 11: Masking material for gate material etching 12: Etching area of ​​the first gate material 13: Etched area of ​​the second gate material 14: First gate material removal section 15: Second gate material removal section 16: Third gate material removal section 17: Residual portion of the first insulating film 18: Residual part of the second insulating film 19: Insulating film etching section 20: Local etching of N-type or P-type silicon layer 21: Metal layer formation section 22: Metal layer removal section 23: Metal wiring 24: Insulating film forming section 25: Interlayer insulating film 26:Contact Department 27: Storage gate wiring 28: Character line wiring 29: Interlayer insulating film 100: Silicon substrate 101: Silicon-germanium compound film 102: Intrinsic Silicon Film 103: Top layer insulating film 104: Masking Material 105: Etching section for multilayer film 106: Buffer membrane 107: Buffer membrane removal section 108: Silicon-germanium compound film removal unit 109: Insulating film deposition section 200: Storage gate 201: Memory gate 202: Gate insulating film 203: Passage Area 204: Drain Diffusion Layer 205: Source diffusion layer 206: Upper part of the element line 207: Lower part of the line 208: Common source pole line 209: First insulating film 210: Second insulating film 211:Substrate 212: Character Line (WL) 213: Storage Gate Line (SGL) 300:SOI substrate 301: SiO2 layer 302:Floating body 303: Source N+ layer 304: Drain N+ layers 305: Gate conductive layer 306: Electric Hole 307: Inverted Layer 309: Gate insulating film 310: Memory Unit 310-1: Memory unit in the "1" state 310-2: Memory unit in "0" state Detailed Implementation

[0069] The structure, driving method, and manufacturing method of the semiconductor memory device of the present invention will be described below with reference to the accompanying drawings.

[0070] [Example] First, the structure of the semiconductor memory device of the present invention will be described with reference to the drawings. Figures 1, 2, and 3 show the structure of the memory cell of the present invention and its equivalent circuit diagram. Figure 1-1 As shown, an insulating film 209 and a silicon layer 203 are sequentially stacked on the substrate. Figure 1 illustrates a two-segment stack, but three or more segments are also possible. The memory gate 201 (MG) and storage gate 200 (SG) are vertically arranged, extending from the uppermost silicon layer 203 to the lowermost silicon layer 203, and each gate is covered by a gate insulating film 202. An insulating film 210 is disposed at both ends of the storage gate 200, extending vertically from the uppermost silicon layer 203 to the lowermost silicon layer 203. Diffusion layers 204 and 205 containing N-type or P-type impurities are disposed at both ends of the silicon layer 203. The silicon layer 203 does not contain impurities, but N-type or P-type impurities diffuse thermally from a portion of the diffusion layer near the diffusion layer. A MOS transistor is formed from the memory gate 201, silicon layer 203, and diffusion layers 204 and 205. Silicon layer 203 forms the channel portion, diffusion layer 204 forms the drain of the MOS transistor, and diffusion layer 205 forms the source. Low-resistance bit lines 206 and 207 are disposed adjacent to diffusion layer 204. The uppermost bit line 206 and the lowermost bit line 207 are electrically independent. Low-resistance common source line 208 is disposed adjacent to diffusion layer 205. A common potential is applied to the plurality of source lines 208. On the other hand, silicon layer 203 contacts the storage gate 200 through gate insulating film 202. The memory gate 201 contacts diffusion layers 204 and 205 through gate insulating film 202, but does not contact the storage gate 200. Figure 1-2 Presentation Figure 1-1 The AA cross-sectional view shows the shape of the memory gate 201, the storage gate 200 and the gate insulating film 202 vertically penetrating to the middle of the bottom insulating film layer 209. Figure 1-3 Figure 1-1 The BB cross-sectional view shows the shape of the storage gate 200, gate insulating film 202, and insulating film 210 vertically penetrating to the middle of the bottom insulating film layer 209. It also shows the configuration of the source diffusion layer 205 and common source line 208, drain diffusion layer 204 and bit line 206 and bit line 207.

[0071] Figure 2-1 In the top view, two memory cells are arranged with the storage gate 200 as the inverse axis of symmetry, and the rectangular area shown by the dashed line constitutes one memory cell. That is, two memory cells share one storage gate 200. Furthermore, by vertically stacking n layers of silicon layer 203, source diffusion layer 205, and drain diffusion layer 204, the number of memory cells can be n times the number of cells seen in the top view. Figure 2-1The topmost silicon layer has 206 bit lines. The bottommost silicon layer has 207 bit lines. Figure 2-2 The equivalent circuit of a memory cell is presented. The memory cell has four terminals, including two gates: a memory gate 201 and a storage gate 200. The potential of the channel is determined by the voltage of the bit line 206 connected to the two gates and the drain 204, and the common source line 208 connected to the source 205.

[0072] Figure 2-3 Presentation Figure 2-1 The array structure shown has two sets of horizontally arranged memory cells in the top two layers, resulting in a total of eight memory cells. Figure 2-4 In its equivalent circuit diagram, the common source line 208 is shared by 8 memory cells. The two bit lines 206 are independent of each other. The memory gate 201 is connected to the metal wiring, i.e., the word line 212 (WL). Furthermore, the two word lines 212 are independent. The storage gate 200 is connected to the storage gate line 213 (SGL). Also, each storage gate line 213 is independent of each other.

[0073] Figure 3-1 The diagram illustrates the connection method of word line 212 and storage gate line 213 from the memory cell array section to the row decoder circuit, and the connection method of bit line (BL) 206 and bit line 207 and common source line (CSL) 208 from the memory cell array section to the row decoder circuit. Here, a case with three layers of memory transistor stack-up is presented. Furthermore, Figure 3-1 The AA section diagram is presented in Figure 3-2 The bit lines (BLs) are stacked independently in three layers, and each layer is subjected to a separate voltage in the line decoder.

[0074] Next, the source diffusion layer 205 and drain diffusion layer 204 are made of N-type silicon, and the dependence of the drain current (Icell) of the memory cell on the gate voltage 201 is shown in the figure. Figure 4-1 The storage gate 200 is, for example, subjected to a fixed negative voltage, the source diffusion layer 205 is set to 0V, and a certain positive voltage is applied to the drain diffusion layer 204. Figure 4-1 There are two curves with different threshold values ​​(Vt). This difference depends on whether there is a hole in the channel section 203. Curve (A) corresponds to the case with a hole, and curve (B) corresponds to the case without a hole. A cross-sectional diagram of the memory cell with a hole is shown in [figure missing]. Figure 4-2Because a negative voltage is applied to the memory gate 200, a hole exists near the memory gate. However, due to the presence of the hole, the potential of the channel portion 203 near the memory gate 201 is higher than when there is no hole. Therefore, the voltage of the memory gate required to form the inversion layer near the memory gate 201 is lower when there is a hole than when there is no hole. That is, the threshold value decreases when there is a hole. This difference results in differences (A) and (B) in the IV characteristics. Thus, whether the channel has a hole or not will cause the drain current (Icell) during reading to be different. Therefore, the difference in Icell when a positive voltage is applied to the memory gate is detected and it is set as "1" and "0" data. Here, when the channel has a hole, it is called a "1" cell, and when the channel does not have a hole, it is called a "0" cell. Furthermore, when the source diffusion layer and drain diffusion layer are P-type silicon, the threshold value will change depending on whether there are electrons in the silicon channel layer, and the difference in the threshold value will be set as data. Therefore, the voltage supplied to each node is the opposite of that in the case where the source and drain diffusion layers are P-type silicon. The same applies when reading and writing data of "1" and "0". The following explanation focuses on the operation when the source and drain diffusion layers are N-type silicon. Furthermore, during the explanation, the memory gate will be referred to as MG, and the storage gate as SG.

[0075] First, the method for writing "0" will be explained. The explanation will focus on the case where the memory cell is in a "1" state before writing "0" and the channel section 203 has a hole. For example, CSL and BL are provided at 0V, MG at 0.5V, and SG at 1V. Since the channel section is N-type or P-type intrinsic silicon without impurities, therefore... Figure 5-1 As shown, the channel potential is higher than the source and drain potentials, causing holes to move towards the source or drain diffusion layer. These moved holes then recombine with electrons in the source or drain, thus being annihilated. Therefore, after writing a "1", there are no holes in the channel, resulting in a neutral, charge-free state. If the memory cell was in a "0" state before writing a "0", then the channel will remain hole-free after writing a "0" without any change. Figure 5-2 The voltage timing diagram of MG, SG, and BL is presented when writing "0". Also, CSL is always fixed at 0V during both writing and reading.

[0076] Next, the method for writing "1" data will be explained. The explanation will focus on the "0" state where the memory cell is in a "0" state before writing the "1" data and the channel section 203 has no holes. For example, if BL is provided at 1V, MG at 1.1V, SG is fixed at -1V, and CSL is fixed at 0V, then... Figure 6-1As shown, since the MG voltage is higher than the threshold of the memory cell in the "0" state, an inversion layer 215 is formed in the channel near the MG, allowing electrons to flow from the source to the drain. However, since the drain of the channel has a high potential, depletion occurs. Therefore, the electric field in the lateral direction increases, causing electrons to undergo collisional ionization and generate electron-hole pairs. The generated holes remain in the channel, causing the state of the memory cell to change from "0" to "1". If the memory cell was in the "1" state before writing "1", the channel will still have holes after writing "1", and therefore no state change will occur. Figure 6-2 Presents the voltage timing diagram of MG, SG, and BL when writing "0".

[0077] Next, the reading method will be explained. For example, BL is provided as 0.2V, MG as 1V, SG is fixed at -1V, and CSL is fixed at 0V. Figure 4-1 As shown, the drain current differs between the "1" and "0" states, and this difference is detected by the sensing circuitry within the line decoder.

[0078] Figure 7-1 When writing "0", the potentials provided to the upper and lower eight memory cells are shown. Furthermore, there is an upper silicon layer (Layer 1) and a lower silicon layer (Layer 2), with eight memory cells configured on each of the upper silicon layers. Viewed from above, the upper and lower layers share the MG and SG, while the CSL is shared by the left and right, upper and lower memory cells. Regarding BL, BL (BL1,1, BL2,1) connected to the upper memory cells and BL (BL1,2, BL2,2) connected to the lower memory cells can have independent potentials. However, all memory cells in Layer 1 and Layer 2, enclosed by dashed lines and connected to SG1, simultaneously perform the "0" writing operation; memory cells not connected to SG1 do not write "0". Here, a group of memory cells connected to a certain SG line is called a block. The applied voltage of each node when writing "0" is shown in... Figure 7-1 The table on the right. A positive voltage between 0.2V and 0.8V is applied to the memory gates (MG1, MG2) connected to the selection block, and a positive voltage between 0.5V and 1.5V is applied to the memory gate (SG1). Furthermore, BL and CSL are set to 0V. Thus, as... Figure 5-1 As shown, the holes in the channel section move toward the source diffusion layer (205) or the drain diffusion layer (204). Furthermore, a negative voltage between -0.5V and -1.5V is applied to the storage gate (SG2) connected to the non-selection block. Thus, the holes in the channel section remain near the storage gate and do not perform the write-to-"0" operation.

[0079] Figure 7-2When a "1" is written, the potential is provided to the eight memory cells above and below. All memory cells in Layer 1 and Layer 2, enclosed by dashed lines and connected to MG1, simultaneously perform the "1" writing operation. Here, a group of memory cells connected to a certain MG line is called a page. That is, one block consists of two pages. For the selected page, a voltage between 0.8V and 1.5V is applied to MG. Whether a "1" is written to a memory cell is determined by the voltage applied to BL. In Layer 1, the left cell connected to MG1 is written with a "1", and in Layer 2, the right cell is written with a "1", while other cells are not written with a "1". In this case, as... Figure 7-2 As shown in the table on the right, a voltage between 0.8V and 1.5V is applied to BL1,1 and BL2,2, while 0V is applied to BL2,1,BL1,2 and CSL. Figure 6-1 As shown, by applying a positive voltage to BL and a voltage above the threshold of the memory cell to MG, collisional ionization of electrons occurs near the drain, generating electron-hole pairs. The generated holes remain in the channel, causing the state of the memory cell to change from "0" to "1". Furthermore, 0V is applied to the non-selected memory gates (MG2-MG4). Also, a voltage between -0.5V and -1.5V is applied to all memory gates (SG1 and SG2). Here, through... Figure 7-1 and Figure 7-2 To explain the operation of writing "0" and "1", when you want to rewrite the data in a memory cell of a page, the cell data of the block including that page is first temporarily stored in the latch circuit in the row decoder. First, the operation of writing "0" is performed. Then, the data stored in the latch circuit or the new data is sequentially rewritten into the two pages in the block.

[0080] Figure 7-3When reading data, potentials are provided to the eight memory cells above and below. In Layer 1 and Layer 2, all memory cells in a page surrounded by dashed lines and connected to MG1 are read simultaneously. In the selected page, a voltage between 0.6V and 1.3V is applied to MG1. A voltage between 0.2V and 0.6V is applied to all BLs (BL1,1, BL2,1, BL1,2, and BL2,2) connecting Layer 1 and Layer 2. A fixed voltage between -0.5V and -1.5V is applied to all storage gates SG (SG1 and SG2). The state of a memory cell ("1" or "0") causes a difference in the current flowing between CSL and BL; this difference is detected by a sensing amplifier circuit within the line decoder. Furthermore, if a block is in standby mode but not in write or read mode, a voltage between -0.5V and -1.5V is applied to SG, and WL, BL, and CSL are all set to 0V. Furthermore, the write and read voltages also depend on the work function of the memory gate and storage gate. Figure 7 shows the case when the numerical work function is approximately 5.2 eV. For example, if the work function is reduced, the voltages applied to MG and SG also need to be reduced accordingly in each operation.

[0081] Figure 8 The dimensions of the memory cell, such as the gate length and gate insulating film thickness, are presented. L MG L represents the length of the memory gate. SG L represents the length of the storage gate. Diff L represents the length from the drain diffusion layer 204 and the source diffusion layer 205 to the outer edge of the insulating film 210. Si L represents the length of channel region 203. OX This represents the length from the end edge of the channel to the inner edge of the insulating film 210. t Channel t represents the width of channel region 203. Storage t represents the width from the edge of the gate insulating film 202 to the edge of the insulating film 210. Insulator L represents the width of insulating film 209, and W represents the width of silicon 203. Preferably, L MG 40–90 nanometers, L SG 10–25 nanometers, L Diff 10–30 nanometers, L Si 36–80 nanometers, L OX 10–20 nanometers, t Channel 20–40 nanometers, t Storage The nanometers are 10–20 nanometers, and W and t InsulatorThe thickness is 20–60 nanometers. Furthermore, the gate insulating film 202 uses silicon dioxide (silicon dioxide) film or hafnium dioxide (HfO2), etc. Regarding the physical aspects of the gate insulating film thickness (t)... Gate-Ox When using HfO2, the preferred size is 3-7 nanometers.

[0082] Compare t Channel / t Storage The Icell values ​​are shown for three conditions: 10nm / 5nm, 30nm / 15nm, and 60nm / 30nm. Furthermore, as read conditions, a voltage between -0.5V and -1.5V is applied to SG, 1V to MG, and 0.2V to BL. The difference between Icell ("1") and Icell ("0") immediately after writing is approximately 0.01μA, 0.15μA, and 0.12μA for 10 / 5nm, 30 / 15nm, and 60 / 30nm, respectively. That is, at 10 / 5nm, the Icell value difference is too small to be easily read. On the other hand, at 15 / 30nm and 30 / 60nm, the Icell difference is large, making data readable. Because a negative voltage is applied to SG, even with 1V applied to MG at 10 / 5nm, a sufficient inversion layer will not form in the silicon channel layer near MG, resulting in a small Icell ("1"). However, if a high voltage is applied to SG, the holes cannot remain near SG and will diffuse to the vicinity of MG in the channel. Repeated readings under this state will result in the recombination of electrons and holes, reducing the number of holes. Therefore, the number of reads is reduced. Thus, t Channel / t Storage A size exceeding 10⁵ nanometers is required. Furthermore, if the SG voltage is increased during standby time, the recombination of electrons and holes becomes easier in the memory cells of the "1" state, reducing the number of holes in the channel. Therefore, Icell ("1") decreases over standby time. This phenomenon occurs regardless of t Channel / t Storage The same result will occur under any of the three conditions. However, if the applied voltage of SG is reduced to below -0.5V, the standby time variation of Icell ("1") will decrease. This is because during standby time, holes are only locally present near SG, thus reducing the probability of hole-electron recombination. Therefore, to improve data retention characteristics, it is better to apply a negative voltage below -0.5V to SG.

[0083] On the other hand, the Icell ("0") standby time increases with longer operation. This is because weak bonding collapse occurs in the silicon channels near the source and drain diffusion layers, generating electron-hole pairs. The generated holes gradually accumulate in the silicon channels, causing the Icell ("0") to rise. However, the increase in Icell ("0") is not highly dependent on the SG voltage. For example, even when a negative voltage between -0.5V and -1.5V is applied to the SG, after writing "0" at 85°C and waiting for about 3 seconds, the change in Icell ("0") is still small. This is because the SG does not directly contact the source and drain diffusion layers, and there is an insulating film 210 of more than 10 nanometers between the diffusion layers and the SG. Due to the presence of the insulating film 210, for example, even when a negative voltage is applied to the SG, the electric field in the silicon near the SG decreases, thus reducing the generation of electron-hole pairs. Therefore, compared to previous examples, the time dependence of Icell ("0") standby time is reduced, and data retention characteristics can be significantly improved. Furthermore, the data retains its characteristics in t Channel / t Storage There is no significant difference between 15 / 30 nm and 30 / 60 nm. On the other hand, considering the viewpoint of reducing cell size, t Channel It is best to minimize this. Therefore, in order to increase the read margin, the difference between Icell("1") and Icell("0") after writing data is increased, thereby increasing the standby time, and to reduce the cell size, t Channel The optimal setting is around 18–55 nanometers, t Storage The optimal setting is around 8–31 nanometers.

[0084] pass Figures 9-1 to 10-2 8. A method for manufacturing a memory device according to a first embodiment is described.

[0085] like Figure 9-1 As shown, an insulating film layer 2 and a silicon layer 3 are sequentially stacked on a substrate 1. This includes cases where the substrate 1 is silicon. Here, two sets (two segments) of silicon layer 3 and insulating film layer 2 are stacked. An insulating film layer 4 is deposited on the uppermost silicon layer 3. This also includes cases where the silicon layer 3 is free of impurities. Regarding the method of forming the silicon layer 3 on the insulating film 2, methods include first depositing an amorphous silicon or polycrystalline silicon film, and then crystallizing the silicon through annealing in a subsequent step.

[0086] Then, as Figure 9-2 As shown, insulating film layer 2, silicon layer 3 and insulating film layer 4 are divided into multiple long strips.

[0087] The following steps are shown in Figure 9-3a , Figure 9-3a for Figure 9-2A cross-sectional view AA along the short side of the elongated strip. Multiple silicon layers 3 are exposed in the space 6 between adjacent stacked films, and high-concentration N-type or P-type impurities are implanted into the exposed silicon layers 3. Furthermore, Figure 9-3a In the etching section 6, the bottommost insulating film layer 2 is completely removed, but only a portion may be removed. Furthermore, there are three methods for implanting high concentrations of N-type or P-type impurities. The first method involves embedding a silicon layer containing a high concentration of N-type or P-type impurities into the space between the stacked films to allow solid-phase diffusion, and then removing the silicon layer containing a high concentration of phosphorus. The second method involves ion implanting N-type or P-type impurities from space 6. Ion implantation is performed at an inclined angle so that the silicon layer 3 can be implanted with impurities. The third method... Figure 9-3b As shown, a portion of the silicon layer 3 is removed from the space 6 between the stacked films to create a void 5-1 for the silicon layer 3. Then, a silicon layer containing a high concentration of N-type or P-type impurities is deposited to fill the space 6 between the stacked films. Subsequently, the silicon layer containing a high concentration of N-type or P-type impurities in the space 6 between the stacked films is removed by reactive ion etching. At this point, a silicon layer containing a high concentration of N-type or P-type impurities remains in the void 5-1.

[0088] Next, as shown in the top view Figure 9-4 As shown, the insulating film layer 4 and the stacked silicon layer 3 and insulating film layer 2 at locations 7 and 8 are etched until the middle of the bottom insulating film layer 2 is reached. Alternatively, the etching continues until the substrate 1 is exposed. Either of these methods is acceptable. Here, Figure 9-4 The subsequent diagrams show the etching process up to the middle of the bottommost insulating film layer 2. Figure 9-4 The BB cross-section is shown in Figure 9-5. Also, [the following is a separate section:] Figure 9-5 The top view shown in the figure with insulating film layer 4 removed is shown below. Figure 9-6 Also, will Figure 9-4 The AA section diagram is shown in Figure 9-7 .again, Figure 9-7 The diagram shows that the bottommost insulating film 2 at space 6 has been completely etched away, but some residue is shown in subsequent diagrams. Then, the gate insulating film 9 and gate material 10 are deposited sequentially, and the deposited gate insulating film 9 and gate material 10 are planarized and ground to expose the top of the insulating film layer 4. The above steps are shown in... Figure 9-8 . Figure 9-8 The BB cross section diagram is shown in Figure 9-9 .

[0089] Next, the masking material 11 is deposited. Figure 9-10 This is a top view showing the patterned masking material. Here, areas where the gate material 10 is embedded but not covered by the masking material 11 are marked as 12 and 13. Figure 9-10 The BB cross section diagram is shown in Figure 9-11.

[0090] Then, using the masking material 11 and the insulating film 4 as etching-resistant materials, the gate material 10 is etched.

[0091] The gate insulating film 9 can also be etched at the same time as the gate material 10, but here the gate insulating film 9 is not etched. Figure 9-12 Presents a top view after etching and removal of masking material 11. Figure 9-12 The AA section diagram is shown in Figure 9-13 . Figure 9-13 The etching sections of the middle gate electrode are 15 and 16.

[0092] then, Figure 9-14 This is a top view showing the surface of insulating film 4 exposed after surface grinding following the deposition of the insulating film. Points 17 and 18 represent the remaining portions of the insulating film. Figure 9-14 The AA section diagram is as follows Figure 9-15 .

[0093] Then, Figure 9-14 Both the residual insulating film at point 18 and the gate insulating film 9 were etched until the bottom insulating film 4 was exposed. The top view after exposing the bottom insulating film 4 is shown below. Figure 9-16 Also, will Figure 9-16 The AA section diagram is shown in Figure 9-17 .

[0094] Then, Figure 9-17 In the process, in region 19 where the diffusion layer 5 is exposed, a portion of the diffusion layer 5 is etched. Figure 9-18 The shape is shown after a portion of the diffusion layer 5 has been etched.

[0095] Then, the deposited metal material 21 is planar ground to expose the surface of the insulating film 4, in order to form Figure 9-19 The shape.

[0096] Next, using insulating film 4 as an etch-resistant material, the metal material 21 at point 22 is removed by reactive ion etching. At this time, the metal portion covered by insulating film 4 and insulating film 2 on top is not etched, thus becoming... Figure 9-20 The shape. Also, Figure 9-20 23 will become a metal wiring.

[0097] Then, an insulating film 24 is deposited, and then the surface of the insulating film 4 is exposed by planar grinding of the deposited insulating film 24. This will result in the top view. Figure 9-21 As shown, only Figure 9-20 An insulating film 24 is left at position 22. Also, the gate material 10 (200) is equivalent to... Figure 1-1The storage gate 200. Also, the gate material 10 (201) is equivalent to... Figure 1-1 The memory gate 201. Figure 9-21 The AA section diagram will become Figure 9-22 The shape. Here, the top view when viewed from the CC section will become... Figure 9-23 The shape. Also, Figure 9-23 The BB cross-section diagram will become Figure 9-24 The shape.

[0098] Next, an interlayer insulating film 25 is deposited, and then an opening is made in the contact hole 26 to expose the gate portion 10. A top view showing the contact hole 26 is provided. Figure 9-26 . right, Figure 9-25 In order to show that the contact hole 26 is located on the storage gate 200 and the memory gate 201, the interlayer insulating film 25 is not shown.

[0099] Then, as in the top view Figure 9-26 As shown, a metallic material is deposited, and then the metallic material is patterned to form gate wiring 27 and gate wiring 28. Figure 9-26 The AA section diagram is shown in Figure 9-27 The gate wiring 27 enters the contact hole 26 and connects to the storage gate 200. For example... Figure 9-25 As shown, gate wiring 27 is connected to storage gate 200, and gate wiring 28 is connected to memory gate 201.

[0100] Then, as Figure 9-28 As shown, an interlayer insulating film 29 is deposited on gate wiring 27 and gate wiring 28 to complete the step of fabricating the memory cell array.

[0101] Through 10-1 to Figure 10-11 Other variations of the invention are presented. In the first embodiment, the SG is shared by two memory cells, but it is also possible for each of the two memory cells to have its own SG. Figure 10-1 The structure of the memory cell of the present invention is presented. Except that each memory cell has an individual SG, there are no other differences from the first embodiment. Figure 10-2 Presentation Figure 10-1 AA cross-sectional view. Two adjacent SGs are separated by insulating film 216. Figure 10-1 BB cross section diagram and Figure 1-3 They are identical.

[0102] Figure 10-3 This is a top view; the two memory cells are arranged vertically opposite each other, and the rectangular area shown by the dashed line represents one memory cell. Also, Figure 10-4 The equivalent circuit of a memory cell is presented, which is the same as that of the first embodiment. Figure 10-5 Presentation Figure 10-1 The array structure shown has two sets of two memory cells arranged horizontally, resulting in a total of eight memory cells. Figure 10-6 Its equivalent circuit diagram shows that the common source line 208 is shared by 8 memory cells.

[0103] Figure 10-7 The diagram illustrates the connection method of word line 212 (WL) and storage gate line 213 (SGL) from the memory cell array section to the column decoder circuit, and the connection method of bit line (BL) 206, bit line 207, and common source line (CSL) 208 from the memory cell array section to the row decoder circuit. Here, a case with three layers of memory transistor stack-up is presented. Furthermore, Figure 10-7 The AA section diagram is presented in Figure 10-8 .

[0104] Figure 10-9 When a "0" is written, the potential is provided to eight memory cells in the upper and lower layers respectively. Here, viewed from above, the upper silicon layer (Layer 1) and the lower silicon layer (Layer 2) are located in the same place and share the MG and SG. The CSL is shared by the left and right, upper and lower memory cells. All memory cells in Layer 1 and Layer 2, surrounded by dashed lines and connected to SG1, simultaneously perform the "0" writing operation. Memory cells not connected to SG1 do not write "0". Here, a group of memory cells connected to a certain SG line is called a block. The number of memory cells connected to one block is the same as the number of memory cells connected to one page of one MG. The applied voltage of each node is shown in... Figure 10-9 The table on the right is the same as the first implementation.

[0105] In the manufacturing steps of the second embodiment, only the differences from the manufacturing steps of the first embodiment are listed. Figure 10-10 Corresponding to Figure 9-10 The manufacturing step of the first embodiment includes a region 13-2 that divides the gate material 10, which will subsequently become the SG, into two parts. Figure 10-11 Equivalent to Figure 10-10 The BB cross-sectional view, and corresponding to the first embodiment. Figure 9-11 The manufacturing steps are the same as those in the first embodiment.

[0106] pass Figures 11-1 to 11-7 Other embodiments of the present invention are presented. In the first embodiment, an insulating film and a silicon layer are stacked on a substrate. Figure 9-1 The initial manufacturing steps, specifically the method of stacking an insulating film and a silicon layer on a substrate, are shown as the third embodiment.

[0107] Figure 11-1In this process, a silicon-germanium layer 101 and a silicon layer 102 are sequentially stacked on a silicon substrate 100. An insulating film 103 is deposited on the topmost silicon layer, and a masking material 104 is deposited on the insulating film 103.

[0108] Next, as Figure 11-2 As shown, the masking material 104 is patterned into multiple parallel strips. Using the masking material 104 as a mask, the insulating film 103 and the stacked silicon-germanium layer 101 and silicon layer 102 are etched, exposing the silicon substrate 100 at point 105. Then, a buffer film 106 is deposited, and the buffer film 106 is polished using surface grinding, exposing the surface of the masking material 104 and forming... Figure 11-3 The shape is then determined. Next, the even-numbered buffer layer from the left is etched to expose the silicon substrate surface, thus forming... Figure 11-4 The shape. Figure 11-4 The silicon-germanium layer 101 is etched at point 107. Then, the silicon-germanium layer 101 is etched through the gaps at 107. Figure 11-4 The AA section diagram will become Figure 11-5 The shape is as follows. Here, the silicon-germanium layer at 108 is removed. Then, an insulating film 109 is deposited from the gaps at 107. Then, using a masking material 104 as a mask, the insulating film at 107 is etched to expose the surface of the silicon substrate 100. Figure 11-6 The shape. Then, the buffer layer at position 106 is selectively etched to become Figure 11-7 The shape. Then, the masking material 104 is removed, resulting in a shape identical to that of the first embodiment sample 1. Figure 9-2 Same shape.

[0109] Alternatively, although not illustrated, each elongated stacked film is sandwiched between two buffer layers, and a masking material and the stacked film below it are patterned (etched) in the center of each elongated stacked film. The masking material and the stacked film are exposed at the patterned (etched) areas to expose the silicon substrate. The silicon-germanium compound layer is selectively removed from the etched area, and then an insulating film is buried in the gaps between the elongated portions of the stacked film where the silicon-germanium compound layer has been removed. The insulating film outside the gaps in the elongated portions of the stacked film is then removed by reactive ion etching. Then, by removing the residual buffer layer, multiple elongated stacked films of insulating film and silicon film are formed on the silicon substrate. Subsequently, the aforementioned source diffusion layer, the aforementioned drain diffusion layer, the gate insulating film, the memory gate, the storage gate, the source line, the bit line, the word line, and the storage gate line are sequentially formed on the stacked film to manufacture a memory cell array.

Claims

1. A semiconductor memory device, wherein the semiconductor memory device has two or more MOS transistors stacked in multiple layers, the MOS transistors are insulated from a substrate and arranged horizontally with respect to the substrate, and an insulating film is provided between each MOS transistor layer to insulate them from each other; Each MOS transistor forms a memory cell, and each memory cell has: a silicon channel layer, and a pair of source diffusion layers and drain diffusion layers made of N-type or P-type silicon that enclose the silicon channel layer. The silicon channel layer, the source diffusion layer and the drain diffusion layer are formed to have the same thickness with no difference in thickness. The semiconductor memory device has a vertically columnar gate insulating film and a gate conductor layer. The gate insulating film and the gate conductor layer extend from the uppermost MOS transistor layer to the lowermost MOS transistor layer, so as to be shared by the stacked MOS transistor layers. The gate conductor layer is in contact with the side of the silicon channel layer of each layer through the gate insulating film layer; In this semiconductor memory device, the threshold of the MOS transistor can be changed depending on whether there is charge accumulation in each silicon channel layer, and data can be read by detecting the value of the threshold.

2. The semiconductor memory device as claimed in claim 1, characterized in that, Each layer of source diffusion layer is connected to the source line, and each layer of drain diffusion layer is connected to the bit line. In each layer, the source line and the bit line of a pair extend in parallel. The bit lines of the multilayer stack are insulated from each other; The source line and the bit line are respectively connected to the source diffusion layer and the drain diffusion layer of the multiple memory cell groups; At one end of the array of memory cells, the source line and the bit line are connected to the row decoder that controls the bit line and the source line of each layer.

3. The semiconductor memory device as claimed in claim 2, characterized in that, The silicon channel layer of this MOS transistor does not have the source diffusion layer and the drain diffusion layer on both sides, and is sandwiched by two vertical columnar, different gate conductor layers. An interlayer insulating film is provided on the topmost MOS transistor. The two vertically columnar, dissimilar gate conductor layers extend to the top surface of the interlayer insulating film and are respectively connected to two dissimilar gate wiring layers. The two gate wiring layers are arranged as a group and extend parallel to the bit line at an angle of 60 to 90 degrees. The two gate wiring layers are connected to the gates of the multiple memory cell groups and are connected to a column decoder that controls the voltage of the gate wiring at one end of the memory cell array.

4. The semiconductor memory device as claimed in claim 3, characterized in that, The silicon channel layer of the multilayer stacked MOS transistor is sandwiched between the two gate conductor layers; One of the gate conductor layers is a memory gate, which extends to the edge of the source diffusion layer and the drain diffusion layer through the gate insulating film; The other gate conductor layer is a storage gate, which is shorter than the memory gate and does not extend to the edge of the source diffusion layer and the drain diffusion layer.

5. The semiconductor memory device as claimed in claim 4, characterized in that, Two vertical columnar insulating films, which are not the gate insulating film, are respectively disposed between the storage gate and the source diffusion layer, and between the storage gate and the drain diffusion layer, so that the storage gate is not only separated from the gate insulating film but also contacts the source diffusion layer and the drain diffusion layer.

6. The semiconductor memory device as claimed in claim 5, characterized in that, The columnar insulating film, which is not a gate insulating film, has a length of 10 to 20 nanometers from one end near the storage gate to one end of the silicon channel layer that contacts the source diffusion layer or the drain diffusion layer.

7. The semiconductor memory device as claimed in claim 5, characterized in that, In each MOS transistor layer, multiple memory cells are arranged in a row along a pair of source lines and bit lines; It has a memory cell structure in which two adjacent memory cells share one storage gate and the storage gate is the inverted axis of symmetry; The gate of the memory is configured at both ends of a pair of memory cells, and another pair of memory cells is configured inside it; These adjacent memory gates are sandwiched between vertical columnar insulating films and are insulated from each other.

8. The semiconductor memory device as claimed in claim 5, characterized in that, In each MOS transistor layer, multiple memory cells are arranged in a row along a pair of source lines and bit lines; It has a memory cell structure in which two adjacent memory cells have two different storage gates and the columnar insulating film located between the two storage gates is the axis of inversion symmetry; The gate of the memory is configured at both ends of a pair of memory cells, and another pair of memory cells is configured inside it; These adjacent memory gates are sandwiched between vertical columnar insulating films and are insulated from each other.

9. The semiconductor memory device as claimed in claim 5, characterized in that, The ratio of the width of the silicon channel layer sandwiched between the memory gate and the storage gate, and the width between the columnar insulating film (which is not a gate insulating film) and the memory gate, is 1.8 to 1 to 2.2 to 1. The width of the silicon channel layer between the memory gate and the storage gate is 18–55 nanometers; The width between the columnar insulating film (which is not a gate insulating film) and the gate of the memory is 8–31 nanometers.

10. The semiconductor memory device as claimed in claim 4, characterized in that, When the source diffusion layer and the drain diffusion layer are N-type silicon, when writing "0" data to all memory cells connected to a certain storage gate at the same time, during the operation of writing "0" data, a certain positive voltage is applied to the storage gate connected to the selected memory cell, a certain positive voltage lower than the storage gate is applied to the storage gate, and a voltage lower than the storage gate is applied to the bit line and the source line, thereby removing holes from the silicon channel layer; When the source diffusion layer and the drain diffusion layer are P-type silicon, the voltages opposite in polarity to those in N-type silicon are applied to the bit line, the memory gate, and the storage gate to remove electrons from the silicon channel layer.

11. The semiconductor memory device as claimed in claim 4, characterized in that, When the source diffusion layer and the drain diffusion layer are N-type silicon, when writing "0" data to all memory cells connected to a certain storage gate at the same time, during the operation of writing "0" data, a voltage between 0.5V and 1.5V is applied to the storage gate connected to the selected memory cell, a voltage between 0.2V and 0.8V is applied to the memory gate, and 0V is applied to the bit line and the source line, thereby removing holes from the silicon channel layer; When the source diffusion layer and the drain diffusion layer are P-type silicon, the voltages opposite in polarity to those in N-type silicon are applied to the bit line, the memory gate, and the storage gate to remove electrons from the silicon channel layer.

12. The semiconductor memory device as claimed in claim 4, characterized in that, When the source diffusion layer and the drain diffusion layer are N-type silicon, when writing "1" data to the memory cell connected to a certain memory gate, during the operation of writing "1" data, a positive voltage is applied to the selected memory gate, a negative voltage is applied to the memory gate, a positive voltage is applied to the bit line connected to the memory cell to which "1" data is written, 0V is applied to the bit line connected to the memory cell to which "1" data is not written, and 0V is applied to the source line, so that holes only accumulate in the silicon channel layer of the memory cell to which "1" data is written; When the source diffusion layer and the drain diffusion layer are P-type silicon, the voltages that are opposite in polarity to those in N-type silicon are applied to the bit line, the memory gate, and the storage gate, thereby causing electrons to accumulate in the silicon channel layer.

13. The semiconductor memory device as claimed in claim 4, characterized in that, When the source diffusion layer and the drain diffusion layer are N-type silicon, when writing "1" data to the memory cell connected to a certain memory gate, during the operation of writing "1" data, a voltage between 0.8V and 1.5V is applied to the selected memory gate, a voltage between -0.5V and -1.5V is applied to the memory gate, a voltage between 0.8V and 1.5V is applied to the bit line connected to the memory cell to which "1" data is written, 0V is applied to the bit line connected to the memory cell to which "1" data is not written, and 0V is applied to the source line, so that holes only accumulate in the silicon channel layer of the memory cell to which "1" data is written; When the source diffusion layer and the drain diffusion layer are P-type silicon, the voltages that are opposite in polarity to those in N-type silicon are applied to the bit line, the memory gate, and the storage gate, thereby causing electrons to accumulate in the silicon channel layer.

14. The semiconductor memory device as claimed in claim 4, characterized in that, When the source diffusion layer and the drain diffusion layer are N-type silicon, when reading data from a memory cell connected to a memory gate, a positive voltage is applied to the memory gate, a negative voltage is applied to the storage gate paired with the memory gate, a positive voltage is applied to the bit line connected to the memory cell that is reading data, 0V is applied to the bit line connected to the memory cell that is not reading data, 0V is applied to the source line, and the current flowing from the source line to the bit line of the memory cell that is reading data is detected. The threshold in the "1" state is lower than the threshold in the "0" state, so the current flowing through is greater. Therefore, the difference in current is detected by the sensing amplifier circuit in the line decoder connected to the bit line to determine whether the data is "0" or "1". When the source diffusion layer and the drain diffusion layer are P-type silicon, the voltages opposite to those in the N-type silicon are applied to the bit line, the memory gate, and the storage gate. The current flowing from the source line to the bit line is detected. The threshold in the "1" state is higher than the threshold in the "0" state, so more current flows. Therefore, the difference in current is detected by the sensing amplifier circuit in the line decoder connected to the bit line to determine whether it is "0" or "1" data.

15. The semiconductor memory device as claimed in claim 4, characterized in that, When the source diffusion layer and the drain diffusion layer are N-type silicon, when reading data from a memory cell connected to a memory gate, a voltage between 0.6V and 1.3V is applied to the memory gate, a voltage between -0.5V and -1.5V is applied to the storage gate paired with the memory gate, a voltage between 0.2V and 0.6V is applied to the bit line connected to the memory cell that is reading data, 0V is applied to the bit line connected to the memory cell that is not reading data, 0V is applied to the source line, and the current flowing from the source line to the bit line of the memory cell that is reading data is detected. The threshold in the "1" state is lower than the threshold in the "0" state, so the current flowing through is greater. Therefore, the difference in current is detected by the sensing amplifier circuit in the line decoder connected to the bit line to determine whether the data is "0" or "1". When the source diffusion layer and the drain diffusion layer are P-type silicon, the voltages opposite to those in the N-type silicon are applied to the bit line, the memory gate, and the storage gate. The current flowing from the source line to the bit line is detected. The threshold in the "1" state is higher than the threshold in the "0" state, so more current flows. Therefore, the difference in current is detected by the sensing amplifier circuit in the line decoder connected to the bit line to determine whether it is "0" or "1" data.

16. The semiconductor memory device as claimed in claim 12, characterized in that, When rewriting the data of a memory cell, first rewrite all memory cells connected to the storage gate to which the memory cell is connected to "0", and then selectively write "1" data to the memory cells connected to the memory cell.

17. The semiconductor memory device as claimed in claim 16, characterized in that, When the source diffusion layer and the drain diffusion layer are N-type silicon, when writing or reading "0" or "1" data to a memory cell connected to a certain memory gate, 0V is applied to the memory gate connected to the non-selected memory cell group that has not been written or read, and a certain negative voltage is applied to the memory gate. When the source diffusion layer and the drain diffusion layer are P-type silicon, the voltages applied to the bit line, the memory gate, and the storage gate are opposite in polarity to those applied to N-type silicon.

18. The semiconductor memory device as claimed in claim 16, characterized in that, When the source diffusion layer and the drain diffusion layer are N-type silicon, when writing or reading "0" or "1" data to a memory cell connected to a memory gate, 0V is applied to the memory gate connected to the non-selected memory cell group that has not been written or read, and a voltage between -0.5V and -1.5V is applied to the memory gate. When the source diffusion layer and the drain diffusion layer are P-type silicon, the voltages applied to the bit line, the memory gate, and the storage gate are opposite in polarity to those applied to N-type silicon.

19. The semiconductor memory device as claimed in claim 16, characterized in that, When the source diffusion layer and the drain diffusion layer are N-type silicon, during the standby period when no data is written or read, a negative voltage is applied to the memory gate, and 0V is applied to the memory gate, the bit line and the source line. When the source diffusion layer and the drain diffusion layer are P-type silicon, the voltages applied to the bit line, the memory gate, and the storage gate are opposite in polarity to those applied to N-type silicon.

20. The semiconductor memory device as claimed in claim 16, characterized in that, If data is left unattended for an extended period after being written, the amount of charge accumulated in the silicon channel of the memory cell will change. Therefore, the data in the memory cell should be read and rewritten within a fixed time period.

21. A method for manufacturing a semiconductor memory device, characterized in that, Manufacturing the semiconductor memory device as claimed in claim 1, comprising: On a silicon substrate, a silicon-germanium compound layer is first deposited, followed by an intrinsic silicon semiconductor layer free of N-type and P-type impurities. After repeating this process multiple times, an insulating film is deposited on the stacked film of the silicon-germanium compound layer and the silicon layer. Then, an etch-resistant masking material is deposited on the insulating film, the silicon layer, and the silicon-germanium compound layer; Then, the masking material and the underlying laminated film are patterned to form multiple elongated shapes, and the silicon substrate is exposed where the masking material and the laminated film are etched. Then, after depositing the buffer film, surface grinding is used to expose the surface of the masking material on top of the laminated film, thereby forming a plurality of elongated laminated films and a buffer layer filling the space between the plurality of elongated laminated films. Then, the buffer layer that was buried between each of the long strip-shaped stacked films was removed every other one, and the silicon-germanium compound layer was selectively removed from the space between the long strip-shaped stacked films from which the buffer layer was removed. Then, an insulating film is buried in the space between the elongated stacked films to fill the voids after the silicon-germanium compound layer has been removed. The insulating film deposited outside the voids of the elongated stacked films is then removed by reactive ion etching. Then, the remaining buffer layer is removed, thereby forming a plurality of strip-shaped laminated films of the insulating film and the silicon layer on the silicon substrate; Then, the source diffusion layer, the drain diffusion layer, the gate insulating film, the memory gate, the storage gate, the source line, the bit line, the word line, and the storage gate line are sequentially formed on the stacked film to manufacture a memory cell array.

22. A method for manufacturing a semiconductor memory device, characterized in that, Manufacturing the semiconductor memory device as claimed in claim 1, comprising: On a silicon substrate, a silicon-germanium compound layer is first deposited, followed by an intrinsic silicon semiconductor layer free of N-type and P-type impurities. After repeating this process multiple times, an insulating film is deposited on the stacked film of the silicon-germanium compound layer and the silicon layer. Then, an etch-resistant masking material is deposited on the insulating film, the silicon layer, and the silicon-germanium compound layer; Then, the masking material and the underlying laminated film are patterned to form multiple elongated shapes, and the silicon substrate is exposed where the masking material and the laminated film are etched. Then, after depositing the buffer film, surface grinding is used to expose the surface of the masking material on top of the laminated film, thereby forming a plurality of elongated laminated films and a buffer layer filling the space between the plurality of elongated laminated films. Then, for each strip-shaped laminated film sandwiched between the buffer layers on both sides, the masking material and the laminated film below it are patterned in the central part of the strip-shaped laminated film so that the silicon substrate is exposed where the masking material and the laminated film are etched, and the silicon-germanium compound layer is selectively removed from the etched area. Then, an insulating film is buried in the space between the elongated stacked films to fill the voids after the silicon-germanium compound layer has been removed. The insulating film deposited outside the voids of the elongated stacked films is then removed by reactive ion etching. Then, the remaining buffer layer is removed, thereby forming a plurality of strip-shaped laminated films of the insulating film and the silicon layer on the silicon substrate; Then, the source diffusion layer, the drain diffusion layer, the gate insulating film, the memory gate, the storage gate, the source line, the bit line, the word line, and the storage gate line are sequentially formed on the stacked film to manufacture a memory cell array.

23. The method of manufacturing a semiconductor memory device as claimed in claim 21 or 22, characterized in that, The laminated film, which consists of multiple layers of insulating film and silicon layer sequentially stacked on a substrate and an insulating film deposited on the top layer of the laminate of insulating film and silicon layer, is patterned to form multiple strip-shaped laminated films arranged laterally. From the space along the short side of the adjacent elongated stacked film, a source diffusion layer and a drain diffusion layer containing acceptor or donor impurities are formed at the ends of each silicon layer. Then, in order to form the gate insulating film and the gate conductor layer in the stacked film with vertical columns, the top surface of the stacked film is patterned, and the etched portion of the stacked film is removed at least down to the bottom silicon layer. Then, the gate insulating film is first deposited on the sides and bottom of the etched portion of the laminated film, and then the gate conductor layer is deposited. Then, the gate conductor layer and the gate insulating film are sequentially planar ground to expose the surface of the insulating film at the top of the laminated film; Then, the gate conductor layer is patterned from the top surface to form the memory gate and the storage gate; Then, an insulating film is buried in the etched portion of the gate conductor layer to insulate each memory gate and each storage gate from each other.

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