Semiconductor device and method of manufacturing semiconductor device

Abstract

A semiconductor device includes a semiconductor substrate, a semiconductor layer located on the semiconductor substrate in a thickness direction of the semiconductor substrate and provided with a first device region, a surface oxide film provided to a part of a surface of the semiconductor layer, and a silicon nitride film located on the surface oxide film in the thickness direction, a PNP transistor having a p-type emitter, a p-type collector surrounding the emitter when viewed in the thickness direction, and an n-type base surrounding the collector when viewed in the thickness direction is arranged in the first device region, and a spacer is located between the emitter and the collector when viewed in the thickness direction and between the surface oxide film and the silicon nitride film in the thickness direction.

Description

Technical Field

[0001] This invention relates to semiconductor devices and methods for manufacturing semiconductor devices. Background Technology

[0002] Patent document 1 discloses a lateral bipolar transistor, which is composed of a collector region and an emitter region arranged side by side on the upper part of the base region. The collector region and emitter region are formed by diffusing P-type or N-type impurities contained in the silicon-germanium layer in the base region.

[0003] Existing technical documents

[0004] Patent documents

[0005] Patent document 1: Japanese Patent Application Publication No. 2004-111575. Summary of the Invention

[0006] One aspect of the present invention is to provide a semiconductor device and a method for manufacturing the semiconductor device that can achieve miniaturization and suppress leakage current between the emitter and collector.

[0007] A semiconductor device according to one aspect of the present invention includes: a semiconductor substrate; a semiconductor layer disposed on the semiconductor substrate in the thickness direction and having a first device region thereon; a surface oxide film disposed on a portion of the surface of the semiconductor layer; and a silicon nitride film disposed on the surface oxide film in the thickness direction. A PNP transistor is disposed in the first device region. The PNP transistor has a p-type emitter, a p-type collector surrounding the emitter when viewed from the thickness direction, and an n-type base surrounding the collector when viewed from the thickness direction. The semiconductor device further includes a spacer located between the emitter and the collector when viewed from the thickness direction, and between the surface oxide film and the silicon nitride film in the thickness direction.

[0008] Another aspect of the present invention relates to a method for manufacturing a semiconductor device, comprising: a first step of forming a semiconductor layer on a semiconductor substrate; a second step of forming a surface oxide film on the surface of the semiconductor layer; a third step of forming a p-type first well region, a p-type second well region surrounding the first well region when viewed from the thickness direction of the semiconductor substrate, and an n-type third well region surrounding the second well region when viewed from the thickness direction in a first device region of the semiconductor layer, and forming a fourth well region of a first conductivity type and a fifth well region of a second conductivity type in the second device region of the semiconductor layer; a fourth step of forming a gate insulating film in the second device region; a fifth step of forming polysilicon on an insulating portion of the surface oxide film located in the first device region, and simultaneously forming a gate on the gate insulating film; a sixth step of forming a p-type emitter in the first well region, a p-type collector in the second well region, an n-type base in the third well region, a source region in the fourth well region, and a drain region in the fifth well region; and a seventh step of forming a silicon nitride film covering the polysilicon and the gate, wherein in the fifth step, the insulating portion is located between the emitter and the collector when viewed from the thickness direction. Attached Figure Description

[0009] Figure 1 This is a top view of the chip of the semiconductor device used in the embodiment.

[0010] Figure 2 yes Figure 1 An enlarged view of region II shown.

[0011] Figure 3 It is along Figure 2 A schematic cross-sectional view of line III-III shown.

[0012] Figure 4 It is along Figure 1 A schematic cross-sectional view of line IV-IV is shown.

[0013] Figure 5A This is a schematic cross-sectional view illustrating an example of a method for manufacturing a semiconductor device according to an embodiment.

[0014] Figure 5B This is a schematic cross-sectional view illustrating an example of a method for manufacturing a semiconductor device according to an embodiment.

[0015] Figure 5C This is a schematic cross-sectional view illustrating an example of a method for manufacturing a semiconductor device according to an embodiment.

[0016] Figure 5D This is a schematic cross-sectional view illustrating an example of a method for manufacturing a semiconductor device according to an embodiment.

[0017] Figure 5EThis is a schematic cross-sectional view illustrating an example of a method for manufacturing a semiconductor device according to an embodiment.

[0018] Figure 5F This is a schematic cross-sectional view illustrating an example of a method for manufacturing a semiconductor device according to an embodiment.

[0019] Figure 5G This is a schematic cross-sectional view illustrating an example of a method for manufacturing a semiconductor device according to an embodiment.

[0020] Figure 5H This is a schematic cross-sectional view illustrating an example of a method for manufacturing a semiconductor device according to an embodiment.

[0021] Figure 6 This is a graph showing the base voltage-collector current characteristics of the L-PNP transistor in the reference example.

[0022] Figure 7 This is a graph showing the base voltage-base current characteristics of an L-PNP transistor included in a semiconductor device according to an embodiment.

[0023] Figure 8 This is a diagram showing the Erlie voltage of each L-PNP transistor. Detailed Implementation

[0024] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the following description, elements having the same elements or the same functions will be referred to by the same reference numerals, and repeated descriptions will be omitted. The terms "same" and similar terms in this specification are not limited to "completely identical". In addition, the drawings are for conceptual explanation of the embodiments, and therefore there may be cases where the dimensions of the constituent elements shown and their proportions differ from the actual situation.

[0025] Figure 1 This is a top view of the chip of the semiconductor device according to this embodiment. Figure 2 yes Figure 1 An enlarged view of region II shown. Figure 3 It is along Figure 2 A schematic cross-sectional view of line III-III shown. Figure 4 It is along Figure 1 A schematic cross-sectional view of line IV-IV is shown. Figure 1 and Figure 3 in, omit Figure 2 The wiring diagram is shown. For example... Figure 1 As shown, semiconductor device 1A includes a silicon chip 2 (semiconductor chip) having a cuboid shape. Chip 2 is, for example, one of a plurality of devices formed on a silicon wafer with a diameter of 300 mm (approximately 12 inches).

[0026] Chip 2 has a first main surface 3 and a second main surface 4 as a pair of main surfaces, and a first side surface 5A, a second side surface 5B, a third side surface 5C, and a fourth side surface 5D connecting the first main surface 3 and the second main surface 4. Hereinafter, the extending direction of the first side surface 5A and the second side surface 5B when viewed from above is defined as the first direction X, the extending direction of the third side surface 5C and the fourth side surface 5D when viewed from above is defined as the second direction Y, and the normal direction of the first main surface 3 and the second main surface 4 is defined as the third direction Z. The second direction Y is the direction that intersects with the first direction X when viewed from above, and the third direction Z corresponds to the thickness direction of chip 2. Furthermore, "viewed from above" in this specification is equivalent to viewing from the third direction Z.

[0027] Viewed from the third direction Z, the first main surface 3 and the second main surface 4 are formed into quadrilateral shapes, but are not limited thereto. In this embodiment, the first main surface 3 is the top surface and the second main surface 4 is the bottom surface. Therefore, the structure located near the first main surface 3 in the third direction Z corresponds to the structure located on the top surface side (above) of the semiconductor device 1A, and the structure located near the second main surface 4 in the third direction Z corresponds to the structure located on the bottom surface side (below) of the semiconductor device 1A.

[0028] Semiconductor device 1A includes a first semiconductor region 6 located in the upper region within chip 2. The first semiconductor region 6 is a layer-shaped region extending along a first main surface 3. Therefore, the first semiconductor region 6 is sometimes also referred to as a semiconductor layer. The first semiconductor region 6 is at least a portion of an epitaxial semiconductor layer. The first semiconductor region 6 is exposed, for example, from a first side surface 5A, a second side surface 5B, a third side surface 5C, and a fourth side surface 5D. The thickness of the first semiconductor region 6 is, for example, 5 μm or more and 20 μm or less. The first semiconductor region 6 has a first conductivity type. The impurity concentration of the first semiconductor region 6 is, for example, 1.0 × 10⁻⁶. 10 cm -3 Above and 1.0×10 13 cm -3 In this embodiment, the first conductivity type is n-type.

[0029] Semiconductor device 1A includes a second semiconductor region 7 located in the lower region within chip 2. The second semiconductor region 7 is a region having a second conductivity type and fixed at a predetermined potential, and is in the form of a layer extending along a second main surface 4. The second semiconductor region 7 is exposed, for example, from the second main surface 4 and the first to fourth side surfaces 5A to 5D. In this embodiment, the second semiconductor region 7 is fixed at a back gate potential. The back gate potential can be a reference potential that serves as a reference for circuit operation, or it can be a ground potential. In this embodiment, the second conductivity type is p-type.

[0030] The second semiconductor region 7 is connected to the first semiconductor region 6. The thickness of the second semiconductor region 7 can be 50 μm or more and 400 μm or less. The second semiconductor region 7 is at least a portion of the p-type semiconductor substrate. That is, the chip 2 has a first semiconductor region 6 contained in an epitaxial semiconductor layer and a second semiconductor region 7 contained in a semiconductor substrate. In other words, the chip 2 has a stacked structure including a semiconductor substrate and an epitaxial semiconductor layer located on the semiconductor substrate.

[0031] In at least one of the first semiconductor region 6 and the second semiconductor region 7 of the semiconductor device 1A, a plurality of device regions 8 are defined and spaced apart from each other on the first main surface 3. The number and arrangement of the plurality of device regions 8 are appropriately determined in the semiconductor device 1A. Each of the plurality of device regions 8 contains functional devices formed using regions inside and outside the chip 2. The functional devices include, for example, at least one of semiconductor switching devices, semiconductor rectifier devices, and passive devices. The functional devices may include a circuit network combining at least two of the semiconductor switching devices, semiconductor rectifier devices, and passive devices.

[0032] Semiconductor switching devices include, for example, at least one of bipolar transistors, MISFETs (Metal Insulator Semiconductor Field Effect Transistors), BJTs (Bipolar Junction Transistors), IGBTs (Insulated Gate Bipolar Junction Transistors), and JFETs. Semiconductor rectifier devices may include at least one of pn junction diodes, pin junction diodes, Zener diodes, Schottky barrier diodes, and fast recovery diodes. Passive devices may include at least one of resistors, capacitors, inductors, and fuses.

[0033] Multiple device regions 8 include at least one first transistor region 9A (first device region) and at least one second transistor region 9B (second device region). The first transistor region 9A includes a bipolar transistor structure. In this embodiment, the bipolar transistor structure is a so-called lateral PNP bipolar transistor (L-PNP transistor). In other words, an L-PNP transistor is provided in the first transistor region 9A of this embodiment. The aforementioned bipolar transistor structure is, for example, a high-voltage device. The second transistor region 9B includes a FET structure. In this embodiment, the FET structure is a so-called LDMISFET (Lateral Double Diffuse MISFET), a type of field-effect transistor. In other words, an LDMISFET, which functions as a transistor, is provided in the second transistor region 9B of this embodiment. The aforementioned FET structure is, for example, a high-voltage device capable of applying a drain voltage of 800V or more in the off state. The structures of the first transistor region 9A and the second transistor region 9B will be described sequentially below.

[0034] like Figure 3 As shown, the first transistor region 9A is a region defined by the component separation region DR. The component separation region DR is a region located on at least one of a portion of the first semiconductor region 6 and a portion of the second semiconductor region 7, surrounding the first transistor region 9A when viewed from above. Therefore, the component separation region DR is located between the first transistor region 9A and another device region 8, which includes the second transistor region 9B. The component separation region DR, for example, has a first portion 25 located on the second semiconductor region 7 and a second portion 26 located on the first portion 25. In one example, the first portion 25 and the second portion 26 are both p-type. In one example, the impurity concentration of the second portion 26 is 1.0 × 10⁻⁶. 14 cm -3 Above and 1.0×10 18 cm -3 the following.

[0035] like Figure 3 As shown, a base region 11 is provided in the first transistor region 9A, located on both sides of the first semiconductor region 6 and the second semiconductor region 7, as well as an emitter contact 12, a collector contact 13, and a base contact 14 located in the first semiconductor region 6. Furthermore, the first semiconductor region 6 has a first well region 15 located below the emitter contact 12, a second well region 16 located below the collector contact 13, and a third well region 17 located below the base contact 14. Figure 2As shown, in the first transistor region 9A, there is a wiring W1 electrically connected to the emitter contact 12 via contact C1, a wiring W2 electrically connected to the collector contact 13 via contact C2, and a wiring W3 electrically connected to the base contact 14 via contact C3. Wirings W1, W2, and W3 are spaced apart from each other. Therefore, wirings W1, W2, and W3 are electrically insulated from each other.

[0036] The base region 11 includes an n-type buried region 11a located between the first semiconductor region 6 and the second semiconductor region 7, and an n-type region 11b located in the first semiconductor region 6 and covering the n-type buried region 11a. The impurity concentration of the n-type buried region 11a is higher than that of the n-type region 11b, for example, 1.0 × 10⁻⁶. 15 cm -3 Above and 1.0×10 18 cm -3 The impurity concentration in the n-type region 11b is, for example, 1.0 × 10⁻⁶. 10 cm -3 Above and 1.0×10 16 cm -3 The impurity concentration in the n-type region 11b can be the same as the impurity concentration in the first semiconductor region 6.

[0037] The emitter contact 12 is a p-type region that functions as the p-type emitter in a PNP bipolar transistor. Viewed from above, the emitter contact 12 is located closer to the center of the first transistor region 9A than the collector contact 13. For example, the emitter contact 12 is located in the center of the first transistor region 9A. The impurity concentration of the emitter contact 12 is, for example, 1.0 × 10⁻⁶. 18 cm -3 Above and 1.0×10 21 cm -3 the following.

[0038] The collector contact 13 is a p-type region that functions as the p-type collector in a PNP bipolar transistor. Viewed from above, the collector contact 13 is located closer to the center of the first transistor region 9A than the base contact 14. The collector contact 13 has a frame shape that surrounds the emitter contact 12. The impurity concentration of the collector contact 13 is, for example, 1.0 × 10⁻⁶. 18 cm -3 Above and 1.0×10 21 cm -3 the following.

[0039] The base contact 14 is an n-type region that functions as the base of an n-type transistor in a PNP bipolar transistor. Viewed from above, the base contact 14 has a frame shape that surrounds the collector contact 13 and the emitter contact 12. The impurity concentration of the base contact 14 is, for example, 1.0 × 10⁻⁶. 18 cm -3 Above and 1.0×10 21 cm -3 the following.

[0040] The first well region 15 is a p-type region in contact with the emitter contact 12, and is formed, for example, by the diffusion of p-type impurities contained in the emitter contact 12 into the first semiconductor region 6. The impurity concentration of the first well region 15 is, for example, 1.0 × 10⁻⁶. 15 cm -3 And 1.0×10 18 cm -3 the following.

[0041] The second well region 16 is a p-type region in contact with the collector contact 13, formed, for example, by the diffusion of p-type impurities contained in the collector contact 13 into the first semiconductor region 6. The impurity concentration of the second well region 16 is, for example, 1.0 × 10⁻⁶. 15 cm -3 And 1.0×10 18 cm -3 the following.

[0042] The third well region 17 is an n-type region that contacts the base contact 14, and is formed, for example, by the diffusion of n-type impurities contained in the base contact 14 into the first semiconductor region 6. In this embodiment, the third well region 17 reaches the n-type buried region 11a, but is not limited thereto. The impurity concentration of the third well region 17 is, for example, 1.0 × 10⁻⁶. 15 cm -3 And 1.0×10 18 cm -3 the following.

[0043] like Figure 3 As shown, the first transistor region 9A includes a first insulating film 21 disposed on a portion of the surface 6a of the first semiconductor region 6 and a second insulating film 22 located on the first insulating film 21 in the third direction Z.

[0044] The first insulating film 21, for example, comprises silicon oxide. In this embodiment, the first insulating film 21 is a surface oxide film, i.e., a LOCOS film (Local Oxidation of Silicon Film), formed by selective oxidation of the surface 6a of the first semiconductor region 6, but is not limited thereto. The first insulating film 21 may also be a surface oxide film, i.e., an STI (Shallow Trench Isolation), formed on the surface 6a of the first semiconductor region 6. An STI may also be formed beneath the LOCOS film. The STI, for example, comprises an insulator (silicon oxide) embedded in a trench formed by deeply excavating the semiconductor layer. The first insulating film 21 may have a single-layer structure or a multilayer structure. The thickness of the first insulating film 21 is, for example, 100 nm or more and 1000 nm or less. The first insulating film 21 has a first insulating portion 21a located between the emitter contact 12 and the collector contact 13 when viewed from above, a second insulating portion 21b located between the collector contact 13 and the base contact 14 when viewed from above, and a third insulating portion 21c located outside the base contact 14 when viewed from above. The first insulating portion 21a and the second insulating portion 21b are respectively frame-shaped when viewed from above. The first insulating portion 21a may overlap with the first well region 15 in the third direction Z, or it may overlap with the second well region 16 in the third direction Z. The second insulating portion 21b may overlap with the second well region 16 in the third direction Z, or it may overlap with the third well region 17 in the third direction Z. The third insulating portion 21c may also overlap with the element separation region DR in the third direction Z.

[0045] The second insulating film 22 is a silicon nitride film that at least covers the first insulating film 21. Therefore, the etching rate of the second insulating film 22 is different from that of the silicon oxide film. Thus, for example, when a silicon oxide film is formed on the second insulating film 22, the second insulating film 22 can function as an etch stop layer in the etching of the silicon oxide film. The second insulating film 22 is formed, for example, by CVD (Chemical Vapor Deposition). The thickness of the second insulating film 22 is, for example, 10 nm or more and 100 nm or less. The second insulating film 22 has a first opening 22a on the emitter contact 12, a second opening 22b on the collector contact 13, and a third opening 22c on the base contact 14. The first opening 22a is the area where the contact C1 is located, the second opening 22b is the area where the contact C2 is located, and the third opening 22c is the area where the contact C3 is located. The first opening 22a, the second opening 22b, and the third opening 22c are formed, for example, by etching.

[0046] likeFigure 3 As shown, a spacer S is provided in the first transistor region 9A, located between the emitter contact 12 and the collector contact 13 when viewed from above, and located between the first insulating portion 21a of the first insulating film 21 and the second insulating film 22 in the third direction Z. The spacer S is a component that widens the physical distance between the first semiconductor region 6 (particularly the portion of surface 6a located between the emitter contact 12 and the collector contact 13) and the second insulating film 22, and has a frame shape that surrounds the emitter contact 12 when viewed from above. Therefore, when viewed from above, the emitter contact 12 is surrounded by the spacer S. In this embodiment, the spacer S is conductive and electrically connected to the wiring W3 via the contact C4. Therefore, in this embodiment, the spacer S is electrically connected to the base contact 14 via the wiring W3. The spacer S can be formed of metals such as aluminum, nickel, copper, or known alloys, or it can be formed of polysilicon. In this embodiment, the spacer S comprises polysilicon. In this case, the polysilicon can have a first conductivity type or a second conductivity type. The thickness of the spacer S is greater than 0.1 nm and less than 500 nm.

[0047] A first potential region 111, a second potential region 112, and a drift region 113 are provided within the first semiconductor region 6 in the second transistor region 9B. The first potential region 111 is the region to which a first potential is applied and is located in the center of the second transistor region 9B. The second potential region 112 is the region to which a second potential, different from the first potential, is applied and is separated from the first potential region 111 when viewed in cross-section. The second potential region 112 surrounds the first potential region 111 when viewed from above. For example, the first potential region 111 is a high-potential region to which a high potential (first potential) is applied, and the second potential region 112 is a low-potential region to which a low potential (second potential) is applied. The drift region 113 is located between the first potential region 111 and the second potential region 112.

[0048] The first potential region 111 includes a well region 114 and a drain region 115. The well region 114 and drain region 115 are respectively disposed above the first semiconductor region 6. The well region 114 surrounds and contacts the drain region 115 when viewed from above. Therefore, the potentials of the well region 114 and the drain region 115 are fixed to be equal (drain potential). When viewed from above, the drain region 115 is separated from the peripheral edge of the well region 114. In other words, when viewed from above, the drain region 115 is located further inward than the peripheral edge of the well region 114. The n-type impurity concentration of the well region 114 is higher than that of the first semiconductor region 6. Furthermore, the n-type impurity concentration of the drain region 115 is higher than that of the well region 114. The n-type impurity concentration of the well region 114 is, for example, 1.0 × 10⁻⁶. 15 cm -3 Above and 1.0×1018 cm -3 The n-type impurity concentration in the drain region 115 is, for example, 1.0 × 10⁻⁶. 18 cm -3 Above and 1.0×10 21 cm -3 The n-type impurity concentration in the drain region 115 can also be the same as the impurity concentration in the base contact 14 in the first transistor region 9A.

[0049] In this embodiment, the well region 114 is oblong in shape when viewed from above, but is not limited to this. The well region 114 may also be circular, elliptical, or polygonal (e.g., quadrilateral) when viewed from above. In this embodiment, the drain region 115 is oblong in shape like the well region 114 when viewed from above, but is not limited to this. The drain region 115 may also be circular, elliptical, or polygonal (e.g., quadrilateral) when viewed from above.

[0050] The second potential region 112 includes a p-type body region 116. The body region 116, for example, is an elongated ring shape surrounding the drain region 115 when viewed from above. The body region 116 extends in the third direction Z from the surface 6a of the first semiconductor region 6 to the boundary between the first semiconductor region 6 and the second semiconductor region 7. Therefore, the body region 116 is electrically connected to the second semiconductor region 7 and is fixed at the potential of the second semiconductor region 7 (e.g., the back gate potential). The body region 116 can also be disposed on both the first semiconductor region 6 and the second semiconductor region 7. The p-type impurity concentration of the body region 116 is, for example, 1.0 × 10⁻⁶. 15 cm -3 Above and 1.0×10 18 cm -3 the following.

[0051] Semiconductor device 1A includes a source region 117 disposed in body region 116. In this embodiment, semiconductor device 1A includes a plurality of source regions 117, but is not limited thereto. The plurality of source regions 117 are n-type regions and are fixed at a source potential. Specifically, the plurality of source regions 117 are each given a source potential from outside the chip 2. Between the source regions 117 and the drift region 113 in the first direction X, a p-type channel region 118 in the above-described FET structure is formed in the first semiconductor region 6. Therefore, between the source regions 117 and the drift region 113 in the first direction X, a current path extending in the first direction X is formed in the drift region 113. The source potential is equivalent to the second potential described above. The n-type impurity concentration of the source region 117 is higher than that of the well region 114. The n-type impurity concentration of the source region 117 can be the same as that of the drain region 115. The n-type impurity concentration of the source region 117 is, for example, 1.0 × 10⁻⁶. 18 cm -3Above and 1.0×10 21 cm -3 Furthermore, in the channel region 118, the conduction and non-conduction of the current path between the drain region 115 and the source region 117 are controlled.

[0052] The second potential region 112 includes a contact region 119 disposed in the body region 116. In this embodiment, the semiconductor device 1A includes a plurality of contact regions 119, but is not limited thereto. The plurality of contact regions 119 are all p-type regions. The p-type impurity concentration of each contact region 119 may also be higher than the p-type impurity concentration of the body region 116. For example, the p-type impurity concentration of the contact region 119 may be, for example, 1.0 × 10⁻⁶. 18 cm -3 Above and 1.0×10 21 cm -3 The contact regions 119, when viewed from above, are strip-shaped and located within the body region 116, further inward than the outer peripheral edge of the body region 116. Furthermore, each contact region 119 is located closer to the outer peripheral edge of the body region 116 than the source region 117. Each contact region 119 is in contact with the outer peripheral edge of the body region 116, but is not limited thereto. Each of the multiple contact regions 119 is adjacent to its corresponding source region 117 when viewed from above. Therefore, on the surface portion of the body region 116, there coexisting source regions 117 fixed at a source potential and contact regions 119 fixed at a potential different from that source potential.

[0053] Semiconductor device 1A includes an n-type drift region 113 located between a drain region 115 and a source region 117, and situated on the surface portion of a first semiconductor region 6. The drift region 113, for example, is an elongated annular shape surrounding the drain region 115 when viewed from above. The width of the drift region 113 is, for example, 50 μm or more and 200 μm or less. The width of the drift region 113 corresponds to the distance between a first potential region 111 and a second potential region 112, and is, for example, approximately constant along the elongated annular shape.

[0054] An insulating film 122 is disposed in the second transistor region 9B, which is a portion of the surface 6a of the first semiconductor region 6. The insulating film 122 may contain, for example, silicon oxide. In this embodiment, the insulating film 122 and the first insulating film 21 of the first transistor region 9A (see reference 1) are... Figure 3 Simultaneously formed. The insulating film 122 is located on the first semiconductor region 6, covering the region between the drain region 115 and the source region 117 in the first semiconductor region 6.

[0055] Semiconductor device 1A includes a field electrode 125 (field plate) located on an insulating film 122. The field electrode 125 has functions such as suppressing electric field disturbances in the first semiconductor region 6, suppressing local electric field concentration, and monitoring the high-voltage drain-gate voltage Vdg. It is a high-resistivity film connected to the first potential region 111 and the second potential region 112. The field electrode 125 partially overlaps with the drift region 113 in the third direction Z. In this embodiment, the field electrode 125 does not overlap with the channel region 118 in the third direction Z. The field electrode 125 may, for example, contain polysilicon. In this case, the polysilicon contained in the field electrode 125 may also have the same or substantially the same crystallinity as the polysilicon contained in the spacer S in the first transistor region 9A. The field electrode 125 is electrically connected to at least the drain region 115. In this embodiment, the field electrode 125 forms a potential gradient that gradually changes from the first potential region 111 to the second potential region 112. By providing such a field electrode 125, deviations in the electric field distribution within the drift region 113 are suppressed. The thickness of the field electrode 125 is, for example, 50 nm or more and 500 nm or less.

[0056] The field electrode 125, for example, concentrically surrounds the first potential region 111, including the drain region 115, multiple times when viewed from above. In this embodiment, the field electrode 125 has a spiral shape surrounding the first potential region 111 when viewed from above. The field electrode 125 may also have a linewidth of 0.5 μm or more and 5 μm or less. The linewidth is defined by the width of the direction orthogonal to the extension direction (i.e., the spiral direction) of the field electrode 125. The field electrode 125 may also have a resistance value of 10 MΩ or more and 100 MΩ or less. The spacing of the field electrodes 125 may be 1 μm or more and 10 μm or less. The spacing of the field electrodes 125 is defined by the distance between adjacent line portions. The number of turns of the field electrode 125 is, for example, 5 or more and 100 or less. This number of turns may be 75 or less or 50 or less.

[0057] Semiconductor device 1A includes an inner field electrode 129 located on an insulating film 122 and connected to a field electrode 125. The inner field electrode 129, when viewed from above, is located closer to the drain region 115 than the field electrode 125. For example, the inner field electrode 129 is located in the region surrounded by the field electrode 125 when viewed from above. The potential of the inner field electrode 129 is fixed at a first potential. The inner field electrode 129 may also be part of the field electrode 125. In this case, the inner field electrode 129 functions as the innermost periphery of the field electrode 125. The inner field electrode 129 may, for example, contain the same material as the field electrode 125. The width of the inner field electrode 129 is, for example, more than 1 μm and less than 15 μm. The inner field electrode 129 may also be formed to be wider than the field electrode 125. In this case, the width of the inner field electrode 129 is, for example, more than 1.5 times and less than 5 times the width of the field electrode 125. Furthermore, the width of the inner field electrode 129 may also be less than or equal to the linewidth of the field electrode 125.

[0058] Semiconductor device 1A includes a gate insulating film 131 disposed on a channel region 118 and adjacent to a first semiconductor region 6. A portion of the gate insulating film 131 may also overlap with an insulating film 122. The thickness of the gate insulating film 131 is less than the thickness of the insulating film 122, for example, 10 nm or more and 200 nm or less. That is, the thickness of the gate insulating film 131 is different from the thickness of the first insulating film 21, which is a surface oxide film, and the thickness of the insulating film 122. The gate insulating film 131 has a single-layer structure or a multilayer structure, for example, comprising a silicon oxide film. In this embodiment, the gate insulating film 131 is in the shape of an elongated ring surrounding the insulating film 122 when viewed from above. The gate insulating film 131 covers a portion of the drift region 113 and a portion of the body region 116.

[0059] Semiconductor device 1A includes a gate electrode 132 (gate) located on a gate insulating film 131. The gate electrode 132 may comprise, for example, a metal film, an alloy film, or polysilicon. When the gate electrode 132 comprises polysilicon, the polysilicon may have the same or substantially the same crystallinity as the polysilicon contained in the spacer S in the first transistor region 9A. The gate electrode 132 overlaps not only with the channel region 118 but also with the drift region 113 in the third direction Z. The gate electrode 132, when viewed from above, has an elongated ring shape extending along the channel region 118, but is not limited thereto. The gate electrode 132 has a lead-out portion 133 extending from the gate insulating film 131 to the insulating film 122. The lead-out portion 133, when viewed from above, has an elongated ring shape surrounding the field electrode 125 (described later) and is located on the drift region 113. Furthermore, the gate electrode 132 as a whole is located outside the field electrode 125 when viewed from above.

[0060] Semiconductor device 1A includes an insulating layer 140 for protecting components, wiring, etc. The insulating layer 140 has a laminated structure comprising multiple interlayer insulating films 141 stacked on top of each other. The number of stacked interlayer insulating films 141 is arbitrary and not limited to a specific value. The insulating layer 140 may also contain three or more interlayer insulating films 141. Figure 4 The diagram shows a first interlayer insulating film 141A, a second interlayer insulating film 141B, and a third interlayer insulating film 141C among multiple interlayer insulating films 141. Furthermore, although not shown, multiple interlayer insulating films may also be provided in the first transistor region 9A.

[0061] The first interlayer insulating film 141A, the second interlayer insulating film 141B, and the third interlayer insulating film 141C are sequentially stacked in the third direction Z. In the second transistor region 9B, the first interlayer insulating film 141A at least covers the insulating film 122, the gate insulating film 131, and the gate electrode 132. That is, the gate electrode 132 is located below the first interlayer insulating film 141A. In this embodiment, the first interlayer insulating film 141A is a silicon nitride film formed simultaneously with the second insulating film 22 in the first transistor region 9A. Therefore, the gate electrode 132 in the second transistor region 9B is located below the first interlayer insulating film 141A, which is a silicon nitride film. The second interlayer insulating film 141B is an insulating film that covers the first interlayer insulating film 141A. The third interlayer insulating film 141C is an insulating film that covers the second interlayer insulating film 141B. The thicknesses of the first interlayer insulating film 141A, the second interlayer insulating film 141B, and the third interlayer insulating film 141C are determined, for example, according to the required function of the field electrode 125 and the thickness of the insulating film 122. The second interlayer insulating film 141B and the third interlayer insulating film 141C each comprise at least one of a silicon oxide film and a silicon nitride film. The second interlayer insulating film 141B and the third interlayer insulating film 141C can each have a single-layer structure or a multilayer structure.

[0062] A plurality of wiring films 142 are disposed within the insulating layer 140. In this embodiment, the plurality of interlayer insulating films 141 and the plurality of wiring films 142 are alternately stacked, thus a multilayer wiring structure is provided in the second transistor region 9B. The number of stacked wiring films 142 is arbitrary and not limited to a specific value. Figure 4The diagram shows a first wiring film 142A located on a second interlayer insulating film 141B and a second wiring film 142B located on a third interlayer insulating film 141C, among a plurality of wiring films 142. Each wiring film 142 includes, for example, at least one of an Al film, a Cu film, an AlSiCu alloy film, an AlSi alloy film, and an AlCu alloy film. Therefore, the first wiring film 142A and the second wiring film 142B can each have a single-layer structure or a multilayer structure. Furthermore, although not shown, a multilayer wiring structure can also be provided in the first transistor region 9A.

[0063] A plurality of first through holes 143 and a plurality of second through holes 149 are provided within the insulating layer 140. The plurality of first through holes 143 are conductive portions that electrically connect conductive portions of a first potential region 111, a second potential region 112, and a field electrode 125 located below at least one of the first interlayer insulating film 141A and the second interlayer insulating film 141B to the first wiring film 142A. The plurality of first through holes 143 penetrate at least one of the first interlayer insulating film 141A and the second interlayer insulating film 141B. The plurality of second through holes 149 are, for example, conductive portions of the first wiring film 142A located below the third interlayer insulating film 141C that electrically connect to the second wiring film 142B, and penetrate the third interlayer insulating film 141C. The plurality of first through holes 143 and the plurality of second through holes 149 are, for example, tungsten plugs.

[0064] The first wiring film 142A includes, for example, a first drain wiring 144, a first source wiring 145, a first gate wiring 146, a field wiring 147, and a field wiring 148. The first drain wiring 144 is electrically connected to the drain region 115 via one or more first vias 143. The first source wiring 145 is electrically connected to the source region 117 via one or more first vias 143. The first gate wiring 146 is electrically connected to the gate electrode 132 via one or more first vias 143. The field wiring 147 is electrically connected to one end of the field electrode 125 via one or more first vias 143. The field wiring 147 is, for example, electrically connected to the inner field electrode 129 via one or more first vias 143. The field wiring 147 may also be part of the first drain wiring 144. The field wiring 148 is electrically connected to the other end of the field electrode 125 via one or more first vias 143. The field wiring 148 may also be part of the first source wiring 145.

[0065] Multiple second wiring films 142B include, for example, a second drain wiring 150, a second source wiring 151, and a second gate wiring (not shown). The second drain wiring 150 is electrically connected to the first drain wiring 144 and the field wiring 147 via multiple second vias 149. The second drain wiring 150 overlaps with the drain region 115 and the field wiring 147. The second drain wiring 150 may also overlap with the entire region of the drain region 115 and the entire region of the field wiring 147. The second drain wiring 150 may also overlap with the inner field electrode 129. The second source wiring 151 is electrically connected to the first source wiring 145 and the field wiring 148 via multiple second vias 149. The second source wiring 151, when viewed from above, has a ring shape extending along the body region 116. The second source wiring 151 may also overlap with the gate electrode 132 and the field wiring 148. The second source wiring 151 may also overlap with the entire area of ​​the body region 116, the entire area of ​​the gate electrode 132, and the entire area of ​​the field wiring 148.

[0066] Next, refer to Figures 5A-5H An example of a method for manufacturing a semiconductor device according to this embodiment will be described. Figures 5A-5H These are schematic cross-sectional views illustrating an example of a method for manufacturing a semiconductor device according to this embodiment. Figures 5A-5H The manufacturing methods for device regions different from the first transistor region 9A and the second transistor region 9B are shown respectively. The L-PNP transistor disposed in the first transistor region 9A and the LDMISFET disposed in the second transistor region 9B can be simultaneously formed by the manufacturing methods described below.

[0067] First, as a preparatory step, such as Figure 5A As shown, a portion of the second semiconductor region 7, which serves as a semiconductor substrate, is doped with p-type impurities. This forms a p-type impurity region 31 defining the first device region R1, a p-type impurity region 32 defining the second device region R2, and a p-type impurity region 33 defining the third device region R3. Next, another portion of the second semiconductor region 7 is doped with n-type impurities. This forms n-type impurity regions 34-36 in the first device region R1, the second device region R2, and the third device region R3, respectively. The p-type impurity regions 31-33 subsequently function as part of a device separation region. The n-type impurity regions 34-36 subsequently function, for example, as part of an n-type buried region. Alternatively, the p-type impurity regions 31-33 may be formed after the n-type impurity regions 34-36.

[0068] In this embodiment, an L-PNP transistor is formed after the first device region R1, a DMOS (Double-diffused MOS) transistor is formed after the second device region R2, and a CMOS transistor is formed after the third device region R3. Furthermore, the shape of the L-PNP transistor formed after the first device region R1 is similar to... Figure 3 The L-PNP transistors shown have slightly different shapes, but these L-PNP transistors can be formed simultaneously. Therefore, the description of the manufacturing method of the L-PNP transistor formed subsequently in the first device region R1 can be used as a description of the manufacturing method of the L-PNP transistor disposed in the first transistor region 9A.

[0069] Next, as Figure 5B As shown, a first semiconductor region 6, serving as a semiconductor layer, is formed on the second semiconductor region 7 (first process). In the first process, for example, the first semiconductor region 6 is epitaxially grown on the second semiconductor region 7. In the first process, a portion of the p-type impurities contained in the p-type impurity regions 31-33 diffuses into the first semiconductor region 6. Similarly, a portion of the n-type impurities contained in the n-type impurity regions 34-36 diffuses into the first semiconductor region 6. Thus, a portion of each of the p-type impurity regions 31-33 expands into the first semiconductor region 6, and a portion of each of the n-type impurity regions 34-36 expands into the first semiconductor region 6.

[0070] Next, as Figure 5C As shown, a portion of the surface 6a of the first semiconductor region 6 is oxidized using a known method to form surface oxide films 41-43 (second step). In the second step, surface oxide film 41 is formed in the first device region R1, surface oxide film 42 is formed in the second device region R2, and surface oxide film 43 is formed in the third device region R3. Surface oxide film 41 and... Figure 2 The first insulating film 21 shown is formed simultaneously.

[0071] Next, as Figure 5DAs shown, by performing various doping on the first semiconductor region 6, at least one of a p-type impurity region and an n-type impurity region is formed in the first device region R1 to the third device region R3 respectively (third step). In the third step, a p-type first well region 51, a p-type second well region 52 surrounding the first well region 51 when viewed from a third party to Z, and an n-type third well region 53 surrounding the second well region 52 when viewed from a third party to Z are formed in the first device region R1 of the first semiconductor region 6. A portion of the first well region 51 becomes a portion of the first well region 15 corresponding to the first transistor region 9A. In addition, a portion of the second well region 52 becomes a portion of the second well region 16 corresponding to the first transistor region 9A, and a portion of the third well region 53 becomes a portion of the third well region 17 corresponding to the first transistor region 9A.

[0072] In the third process, an n-type fourth well region 55 and a p-type fifth well region 56 are formed in the second device region R2 of the first semiconductor region 6, and an n-type impurity region 57 is formed in the third device region R3 of the first semiconductor region 6. In the third process, the first well region 51, the second well region 52, and the fifth well region 56 are formed simultaneously. Similarly, the third well region 53 and the fourth well region 55 are formed simultaneously. The n-type impurity region 57 can be formed simultaneously with the third well region 53, or it can be formed in a different timing sequence. The first well region 51, etc., can be formed before or after the formation of the second well region 52, etc.

[0073] In the third process, the component separation region DR1 located between the first device region R1 and the second device region R2, and the component separation region DR2 located between the first device region R1 and the third device region R3 are formed in the first semiconductor region 6.

[0074] Next, as Figure 5E As shown, gate insulating films 61 and 62 are formed in the second device region R2 and the third device region R3, respectively (fourth step). In the fourth step, the gate insulating film 61 is formed in the second device region R2 and the gate insulating film 62 is formed in the third device region R3 by known methods such as thermal oxidation.

[0075] Next, as Figure 5F As shown, polysilicon 71 is formed on a portion of the surface oxide film 41, while gate electrodes 72 and 73 are formed on gate insulating films 61 and 62, respectively (fifth process). In the fifth process, polysilicon 71, which functions as a spacer, is formed on the insulating portion 41a of the surface oxide film 41. The insulating portion 41a is the portion of the surface oxide film 41 that surrounds the first well region 51 and is surrounded by the second well region 52 when viewed from a third direction (Z). Therefore, the insulating portion 41a is located at the emitter contact 81 and collector contact 82 (described later) when viewed from above.Figure 5G Between ), gate 72 is polysilicon formed on gate insulating film 61, functioning as the gate of the subsequently formed DMOS. A portion of gate 72 may be formed on surface oxide film 42 instead of on gate insulating film 61. Gate 73 is polysilicon formed on gate insulating film 62, functioning as the gate of the subsequently formed CMOS. Therefore, gates 72 and 73 comprise polysilicon having the same or substantially the same crystallinity as polysilicon 71.

[0076] Next, as Figure 5G As shown, various doping processes (sixth step) are performed on the first semiconductor region 6. In the sixth step, in the first device region R1, a p-type emitter contact 81 is formed in the first well region 51, a p-type collector contact 82 is formed in the second well region 52, and an n-type base contact 83 is formed in the third well region 53. Furthermore, in the second device region R2, an n-type drain region 84 is formed in the fourth well region 55, and a p-type source region 85 is formed in the fifth well region 56. Additionally, a p-type drain region 86 and a p-type source region 87 are formed in the third device region R3. In the sixth step, the emitter contact 81, collector contact 82, source region 85, drain region 86, and source region 87 are formed simultaneously. Similarly, the base contact 83 and drain region 84 are formed simultaneously. The emitter contact 81, etc., can be formed before or after the formation of the base contact 83, etc.

[0077] Next, as Figure 5H As shown, a silicon nitride film 91 covering polysilicon 71 and gate 72 is formed (seventh step). In the seventh step, the silicon nitride film 91 is formed by a known method such as CVD. The silicon nitride film 91 is formed simultaneously with the second insulating film 22 in the first transistor region 9A and the first interlayer insulating film 141A in the second transistor region 9B. Through the above steps, an L-PNP transistor is formed in the first device region R1, a DMOS (Double-diffused MOS) transistor is formed in the second device region R2, and a CMOS transistor is formed in the third device region R3.

[0078] Subsequently, it is formed and patterned as follows Figure 4 The interlayer insulating film, wiring film, and through-holes are shown. Thus, for example, the polysilicon 71 is electrically connected to the base contact 83. Through the above processes, semiconductor device 1A is manufactured.

[0079] Next, refer to the following examples and instructions. Figures 6-8The effects of the semiconductor device 1A manufactured using the manufacturing method of this embodiment will be explained. The semiconductor device of the reference example described below has the same structure as the semiconductor device 1A of this embodiment, except that the L-PNP transistor does not have a spacer.

[0080] Figure 6 This is a graph showing the base voltage-collector current characteristics of the L-PNP transistor in the reference example. Figure 6 In the diagram, the horizontal axis represents the base voltage, and the vertical axis represents the collector current. Figure 6 In the diagram, line graph 201 shows the base voltage-collector voltage waveform of an L-PNP transistor (hereinafter referred to as the "initial L-PNP transistor") of a reference example that has not undergone a high-temperature voltage stress test (hereinafter also simply referred to as voltage stress test or voltage stress) as described below. This waveform is obtained by changing the base voltage from 0V to -1.2V under the conditions of device temperature: 25°C, collector voltage: -3V, and emitter voltage: ground potential. Line graph 202 shows the base voltage-collector voltage waveform of an L-PNP transistor of a reference example that has undergone a voltage stress test as described below for 250 hours or less (hereinafter referred to as the "L-PNP transistor after short-time stress test"). Curve 203 shows the base voltage-collector voltage waveform of an L-PNP transistor of a reference example that has undergone a voltage stress test as described below for 750 hours or less (hereinafter referred to as the "L-PNP transistor after long-time stress test"). In the aforementioned voltage stress test, the collector potential of the L-PNP transistor was set to ground in an oven at 150°C, while the emitter and base potentials were set to 7V. After the voltage stress test, the L-PNP transistor was removed from the oven and left to stand without any stress. Then, after the temperature of the L-PNP transistor dropped to 25°C, the waveform of the base voltage versus collector voltage of the L-PNP transistor was measured.

[0081] like Figure 6As shown in graphs 201 and 202, the base-collector voltage characteristics of the L-PNP transistor after a short-term stress test are almost unchanged from those of the initial L-PNP transistor. On the other hand, as shown in graphs 201 and 203, the base-collector voltage characteristics of the L-PNP transistor after a long-term stress test are significantly different from those of the initial L-PNP transistor. In particular, as shown in graph 203, the leakage current between the collector and emitter increases significantly in the L-PNP transistor after a long-term stress test when the base voltage is approximately 0V to -0.5V. Therefore, it can be seen that in the L-PNP transistor of the reference example, there is a tendency for the leakage current between the collector and emitter to increase with the duration of voltage stress application.

[0082] Figure 7 This is a graph showing the base voltage-base current characteristics of the L-PNP transistor included in the semiconductor device 1A of this embodiment. Figure 7 In the diagram, the horizontal axis represents the base voltage, and the vertical axis represents the base current. Figure 7 In the diagram, line graph 301 shows the initial base voltage-base current waveform of the L-PNP transistor, line graph 302 shows the base voltage-base current waveform of the L-PNP transistor after a short-term stress test, and line graph 303 shows the base voltage-collector current waveform of the L-PNP transistor after a long-term stress test. These waveforms were obtained by varying the base voltage from 0V to -1.2V under the conditions of device temperature: 25℃, collector voltage: -3V, and emitter voltage: ground potential. Figure 7 As shown, the leakage current of the base current does not change with the application time of the voltage stress.

[0083] The current amplification of a bipolar transistor is expressed as IC (collector current) / IB (base current). Figure 6 , 7 As shown, in the L-PNP transistor of the reference example, the current amplification rate may vary even at low collector currents depending on the duration of voltage stress application. Therefore, in the reference example, it can be said that the current amplification rate of the bipolar transistor is unstable.

[0084] Figure 8 This is a graph showing the Earliest voltages of each L-PNP transistor. Figure 8 In the figures, Figure 401 shows the Earliest voltage of the L-PNP transistor of the embodiment, and Figure 402 shows the Earliest voltage of the L-PNP transistor of the reference example. Figure 8As shown, the Earl voltage of the L-PNP transistor of the semiconductor device 1A in this embodiment is about 25% higher than the Earl voltage of the L-PNP transistor of the semiconductor device in the reference example.

[0085] As described above, the semiconductor device 1A of this embodiment differs from the semiconductor device of the reference example in that it has a spacer S. Therefore, by having a spacer S in the L-PNP transistor, the leakage current between the emitter and collector can be reduced, and the Erlie voltage can be improved. It is presumed that these phenomena are caused by the position of the silicon nitride film, i.e., the second insulating film 22, located on the first insulating film 21. In the reference example, the second insulating film, which is a silicon nitride film, is located directly above the first insulating film. Here, a large number of dangling bonds (unbonded bonds) are contained in the silicon nitride film. The inherent charge of these dangling bonds tends to shift due to the use of semiconductor devices at high temperatures, etc. Due to such changes in the charge state of the second insulating film, there is a tendency for negative charges to be biased towards the interface between the first insulating film and the second insulating film. Thus, for example, if a voltage is applied to the L-PNP transistor of the reference example for a long time at high temperature, holes accumulate at the interface between the first semiconductor region and the first insulating film. Therefore, in the case of applying a voltage to the L-PNP transistor of the reference example for a long time at high temperature, it is presumed that a leakage current is generated between the emitter and collector through the aforementioned accumulated holes.

[0086] In contrast, in the L-PNP transistor of the semiconductor device 1A manufactured by the above-described manufacturing method, viewed from a third-party direction Z, the spacer S is located between the emitter contact 12 and the collector contact 13, and between the first insulating film 21 and the second insulating film 22. As a result, the physical distance between the first semiconductor region 6 and the second insulating film 22 is increased between the emitter contact 12 and the collector contact 13. Therefore, even if a change in the charge state of the second insulating film 22 occurs as described above, holes are unlikely to concentrate at the interface between the first semiconductor region 6 and the first insulating film 21. Therefore, even if, for example, a voltage is applied to the L-PNP transistor of the semiconductor device 1A for a long time at high temperature, leakage current between the emitter contact 12 and the collector contact 13 is unlikely to occur. Therefore, according to this embodiment, even if the first transistor region 9A is miniaturized and a voltage is applied to the semiconductor device 1A for a long time at high temperature, leakage current between the emitter contact 12 and the collector contact 13 can be suppressed. Therefore, in this embodiment, it is presumed that even after the above-mentioned voltage stress test of 2000 hours, the characteristics of the base voltage-collector voltage are almost unchanged from those before the voltage stress test.

[0087] In one example, the spacer S is conductive and electrically connected to the base contact 14. In this case, even when the spacer S is conductive, the charge state of the spacer S is not easily affected by the second insulating film 22. Therefore, even when a voltage is applied to the semiconductor device 1A for a long time at high temperature, leakage current between the emitter contact 12 and the collector contact 13 can be well suppressed.

[0088] In one example, the spacer S comprises polysilicon. Furthermore, a second transistor region 9B, spaced apart from the first transistor region 9A, is provided in the first semiconductor region 6. In the second transistor region 9B, a transistor (LDMISFET) is present, having a source region 117, a drain region 115, and a gate electrode 132 located below a first interlayer insulating film 141A, which is a silicon nitride film. The gate electrode 132 comprises polysilicon with the same or substantially the same crystallinity as the polysilicon contained in the spacer S. Thus, leakage current between the emitter contact 12 and the collector contact 13 in the L-PNP transistor can be effectively suppressed without increasing the manufacturing process of the semiconductor device 1A.

[0089] In one example, the transistor described above has a gate insulating film 131 located below the gate electrode 132, and the thickness of the gate insulating film 131 is different from the thickness of the insulating film 122, which is a surface oxide film. For example, by making the thickness of the gate insulating film 131 smaller than the thickness of the insulating film 122, the switching characteristics of the transistor can be improved.

[0090] In one example, a component separation region DR1 is provided in the first semiconductor region 6, located between the first device region R1 and the second device region R2. This prevents short circuits between the first device region R1 and the second device region R2.

[0091] In one example, the spacer S, viewed from a third-party perspective (Z), has a frame shape surrounding the emitter contact 12. In this case, leakage current between the emitter contact 12 and the collector contact 13 in the L-PNP transistor can be well suppressed.

[0092] The embodiments of the present invention have been described above, but the present invention can also be implemented in other ways.

[0093] In the above embodiments, a structure that reverses the conductivity type of various semiconductor regions can also be used. That is, a p-type region can be configured as an n-type region, and an n-type region can be configured as a p-type region.

[0094] In the above embodiments, a MISFET is formed in the second transistor region, but it is not limited to this. For example, a JFET with a field plate and trench, as shown in the above embodiments, can also be formed in the transistor region. Even in this case, the same effect as in the above embodiments can be achieved.

[0095] In the above embodiments, the component separation region has a first portion and a second portion, but is not limited thereto. For example, in addition to the first and second portions, the component separation region may also have a third portion located on the second portion. In this case, the impurity concentration of the second portion is, for example, 1.0 × 10⁻⁶. 14 cm -3 Above and 1.0×10 18 cm -3 The impurity concentration in Part III is, for example, 1.0 × 10⁻⁶. 15 cm -3 Above and 1.0×10 18 cm -3 the following.

[0096] In the above embodiment, the first semiconductor region may further have a fourth well region surrounding the first well region. The fourth well region is an n-type region in contact with the first well region, located between the collector contact and the emitter contact when viewed from above. The fourth well region is provided, for example, in a manner that does not overlap with the emitter contact and the collector contact in the third direction Z. On the other hand, a spacer overlaps with a portion of the fourth well region through the first insulating film. The impurity concentration of the fourth well region is, for example, 1.0 × 10⁻⁶. 15 cm -3 And 1.0×10 18 cm -3 The following applies. When the first semiconductor region also has a fourth well region, it is possible to suppress malfunctions of L-PNP transistors caused by parasitic capacitance.

[0097] In the above embodiments, the spacer is electrically connected to the base contact, but is not limited thereto. The spacer may also be conductive and grounded. Alternatively, the spacer may also be insulating. In this case, from the viewpoint of eliminating the influence of the aforementioned dangling bonds, the spacer is not formed of silicon nitride, but of, for example, silicon oxide. When the spacer contains silicon oxide, the thickness of the spacer is, for example, 50 nm or more and 500 nm or less.

[0098] In the above embodiments, polysilicon and the gate are formed after the gate insulating film is formed, but this is not a limitation. In other words, in the above embodiments, the fourth and fifth steps are performed sequentially, but this is not a limitation. The fourth and fifth steps can be performed simultaneously. For example, firstly, after forming an insulating film on the first semiconductor region and the surface oxide film, a polysilicon layer is formed on the insulating film. Then, the gate insulating films 61 and 62, the polysilicon 71, and the gates 72 and 73 can be formed by patterning the insulating film and the polysilicon layer. In this case, a portion of the residual insulating film is provided between the polysilicon 71 and the surface oxide film 41. When the fourth and fifth steps are performed simultaneously, the manufacturing method of the semiconductor device can be simplified.

[0099] In the above embodiments, semiconductor devices can be applied, for example, to power modules used in inverter circuits that drive electric motors, which serve as power sources for automobiles (including electric vehicles), trams, industrial robots, air conditioning units, air compressors, electric fans, vacuum cleaners, dryers, refrigerators, etc. Additionally, semiconductor devices can also be applied to power modules used in inverter circuits for solar cells, wind turbines, and other power generation devices. Alternatively, semiconductor devices can also be applied to circuit modules that constitute analog control power supplies, digital control power supplies, etc.

[0100] The above provides a detailed description of one aspect of the present invention. However, these are merely specific examples used to clarify the technical content of the present invention. The present invention should not be limited to these specific examples, and the scope of the present invention is defined only by the scope of the appended claims.

[0101] The following are examples of features extracted from the description and drawings.

[0102] [A1]

[0103] A semiconductor device comprising:

[0104] Semiconductor substrate;

[0105] A semiconductor layer is located on the semiconductor substrate in the thickness direction and has a first device region thereon.

[0106] A surface oxide film, which is disposed on a portion of the surface of the semiconductor layer; and

[0107] A silicon nitride film, which is located on the surface oxide film in the thickness direction.

[0108] A PNP transistor is disposed in the first device region. The PNP transistor has a p-type emitter, a p-type collector surrounding the emitter when viewed from the thickness direction, and an n-type base surrounding the collector when viewed from the thickness direction.

[0109] The semiconductor device further includes a spacer located between the emitter and the collector when viewed from the thickness direction, and between the surface oxide film and the silicon nitride film in the thickness direction.

[0110] [A2]

[0111] According to the semiconductor device described in [A1], the spacer is conductive and electrically connected to the base.

[0112] [A3]

[0113] According to the semiconductor device described in [A1], the spacer is conductive and grounded.

[0114] The semiconductor device according to claim 1.

[0115] [A4]

[0116] The semiconductor device according to [A2] or [A3], wherein the spacer comprises polycrystalline silicon.

[0117] [A5]

[0118] According to the semiconductor device described in [A4], wherein,

[0119] The semiconductor layer also includes a second device region spaced apart from the first device region.

[0120] A transistor is disposed in the second device region, the transistor having a source region, a drain region, and a gate located below the silicon nitride film.

[0121] The gate comprises polysilicon having the same or substantially the same crystallinity as the polysilicon contained in the spacer.

[0122] [A6]

[0123] According to the semiconductor device described in [A5], wherein,

[0124] The transistor also has a gate insulating film located below the gate.

[0125] The thickness of the gate insulating film is different from the thickness of the surface oxide film.

[0126] [A7]

[0127] According to the semiconductor device described in [A5] or [A6], wherein,

[0128] A component separation region is provided in the semiconductor layer between the first device region and the second device region.

[0129] [A8]

[0130] The semiconductor device according to any one of [A2] to [A7], wherein,

[0131] The PNP transistor also has a p-type well region located below the emitter and an n-type well region surrounding the p-type well region when viewed from the thickness direction.

[0132] The spacer overlaps with a portion of the n-type well region across the surface oxide film.

[0133] [A9]

[0134] According to the semiconductor device described in [A1], wherein,

[0135] The spacer comprises silicon oxide.

[0136] The thickness of the spacer is greater than 50 nm and less than 500 nm.

[0137] [A10]

[0138] The semiconductor device according to any one of [A1] to [A9], wherein,

[0139] The spacer has a frame shape that surrounds the emitter when viewed from the thickness direction.

[0140] [A11]

[0141] A method for manufacturing a semiconductor device, comprising:

[0142] The first step is to form a semiconductor layer on a semiconductor substrate;

[0143] The second step involves forming a surface oxide film on the surface of the semiconductor layer.

[0144] In the third step, a p-type first well region, a p-type second well region surrounding the first well region when viewed from the thickness direction of the semiconductor substrate, and an n-type third well region surrounding the second well region when viewed from the thickness direction are formed in the first device region of the semiconductor layer; and a fourth well region of the first conductivity type and a fifth well region of the second conductivity type are formed in the second device region of the semiconductor layer.

[0145] The fourth step involves forming a gate insulating film in the region of the second device.

[0146] In the fifth step, while forming polysilicon on the insulating portion of the surface oxide film located in the first device region, a gate is formed on the gate insulating film.

[0147] The sixth step involves forming a p-type emitter in the first well region, a p-type collector in the second well region, an n-type base in the third well region, a source region in the fourth well region, and a drain region in the fifth well region; and

[0148] The seventh step involves forming a silicon nitride film covering the polysilicon and the gate.

[0149] In the fifth step, the insulating portion is located between the emitter and the collector when viewed from the thickness direction.

[0150] [A12]

[0151] According to the semiconductor device manufacturing method described in [A11], wherein,

[0152] The polycrystalline silicon is electrically connected to the base electrode.

[0153] [A13]

[0154] According to the semiconductor device manufacturing method described in [A11], wherein,

[0155] The polysilicon is grounded.

[0156] [A14]

[0157] The method for manufacturing a semiconductor device according to any one of [A11] to [A13], wherein,

[0158] The gate comprises polycrystalline silicon having the same or substantially the same crystallinity as the polycrystalline silicon.

[0159] [A15]

[0160] The method for manufacturing a semiconductor device according to any one of [A11] to [A14], wherein,

[0161] In the third step, a component separation region is formed in the semiconductor layer between the first device region and the second device region.

[0162] [A16]

[0163] The method for manufacturing a semiconductor device according to any one of [A11] to [A15], wherein,

[0164] The polycrystalline silicon has a frame shape surrounding the emitter when viewed from the thickness direction.

[0165] Explanation of reference numerals in the attached figures

[0166] 1A… Semiconductor Devices

[0167] 2…chip

[0168] 6…First semiconductor region (semiconductor layer)

[0169] 6a… surface

[0170] 7…Second semiconductor region (semiconductor substrate)

[0171] 9A…First transistor region

[0172] 9B…Second transistor region

[0173] 11…base region

[0174] 11a…n type buried area

[0175] 11b…n type region

[0176] 12…Emitter Contact

[0177] 13… Collector Contact

[0178] 14…Base contact portion

[0179] 15, 51…First Tunnel Region

[0180] 16, 52…Second Trap Zone

[0181] 17, 53… Third Trap Zone

[0182] 21…First insulating film (surface oxide film)

[0183] 21a…First Insulation Part (Insulation Section)

[0184] 21b…Second Insulation Part

[0185] 21c…Third Insulation Part

[0186] 22…Second insulating film (surface oxide film)

[0187] 22a…First opening

[0188] 22b…Second opening

[0189] 22c…Third opening

[0190] 31~33…p-type impurity region

[0191] 34~36…n-type impurity region

[0192] 41~43… Surface oxide film

[0193] 41a…Insulation part

[0194] 55…Fourth Trap Zone

[0195] 61, 62, 131… Gate insulating film

[0196] 71…Polycrystalline silicon

[0197] 72, 73… gate

[0198] 81…Emitter Contact

[0199] 82… Collector Contact

[0200] 83…base contact portion

[0201] 84, 86, 115… Drain region

[0202] 85, 87, 117… source regions

[0203] 91…Silicon nitride film

[0204] 111…First Potential Region

[0205] 112…Second Potential Region

[0206] 113… Drift Area

[0207] 122…Insulating film

[0208] 125… Field Electrode

[0209] 129…Inner Field Electrode

[0210] 132…Gate electrode

[0211] 140… Insulation layer

[0212] 141… Interlayer insulating film

[0213] 141A…First interlayer insulating film

[0214] 141B…Second interlayer insulating film

[0215] 141C…Third interlayer insulating film

[0216] DR, DR1, DR2... Component separation areas

[0217] R1…First Device Region

[0218] R2…Second device region

[0219] R3…Third Device Region

[0220] S…spacer.

Claims

1. A semiconductor device, characterized in that, include: Semiconductor substrate; A semiconductor layer is located on the semiconductor substrate in the thickness direction and has a first device region thereon. A surface oxide film, which is disposed on a portion of the surface of the semiconductor layer; and A silicon nitride film, which is located on the surface oxide film in the thickness direction. A PNP transistor is disposed in the first device region. The PNP transistor has a p-type emitter, a p-type collector surrounding the emitter when viewed from the thickness direction, and an n-type base surrounding the collector when viewed from the thickness direction. The semiconductor device further includes a spacer located between the emitter and the collector when viewed from the thickness direction, and between the surface oxide film and the silicon nitride film in the thickness direction.

2. The semiconductor device according to claim 1, characterized in that: The spacer is conductive and electrically connected to the base.

3. The semiconductor device according to claim 1, characterized in that: The spacer is conductive and grounded.

4. The semiconductor device according to claim 2 or 3, characterized in that: The spacer comprises polycrystalline silicon.

5. The semiconductor device according to claim 4, characterized in that: The semiconductor layer also includes a second device region spaced apart from the first device region. A transistor is disposed in the second device region, the transistor having a source region, a drain region, and a gate located below the silicon nitride film. The gate comprises polysilicon having the same or substantially the same crystallinity as the polysilicon contained in the spacer.

6. The semiconductor device according to claim 5, characterized in that: The transistor also has a gate insulating film located below the gate. The thickness of the gate insulating film is different from the thickness of the surface oxide film.

7. The semiconductor device according to claim 5 or 6, characterized in that: A component separation region is provided in the semiconductor layer between the first device region and the second device region.

8. The semiconductor device according to any one of claims 2 to 7, characterized in that: The PNP transistor also has a p-type well region located below the emitter and an n-type well region surrounding the p-type well region when viewed from the thickness direction. The spacer overlaps with a portion of the n-type well region across the surface oxide film.

9. The semiconductor device according to claim 1, characterized in that: The spacer comprises silicon oxide. The thickness of the spacer is greater than 50 nm and less than 500 nm.

10. The semiconductor device according to any one of claims 1 to 9, characterized in that: The spacer has a frame shape that surrounds the emitter when viewed from the thickness direction.

11. A method for manufacturing a semiconductor device, characterized in that, include: The first step is to form a semiconductor layer on a semiconductor substrate; The second step involves forming a surface oxide film on the surface of the semiconductor layer. In the third step, a p-type first well region, a p-type second well region surrounding the first well region when viewed from the thickness direction of the semiconductor substrate, and an n-type third well region surrounding the second well region when viewed from the thickness direction are formed in the first device region of the semiconductor layer; and a fourth well region of the first conductivity type and a fifth well region of the second conductivity type are formed in the second device region of the semiconductor layer. The fourth step involves forming a gate insulating film in the region of the second device. In the fifth step, while forming polysilicon on the insulating portion of the surface oxide film located in the first device region, a gate is formed on the gate insulating film. The sixth step involves forming a p-type emitter in the first well region, a p-type collector in the second well region, an n-type base in the third well region, a source region in the fourth well region, and a drain region in the fifth well region. and The seventh step involves forming a silicon nitride film covering the polysilicon and the gate. In the fifth step, the insulating portion is located between the emitter and the collector when viewed from the thickness direction.

12. The method for manufacturing a semiconductor device according to claim 11, characterized in that: The polycrystalline silicon is electrically connected to the base electrode.

13. The method for manufacturing a semiconductor device according to claim 11, characterized in that: The polysilicon is grounded.

14. The method for manufacturing a semiconductor device according to any one of claims 11 to 13, characterized in that: The gate comprises polycrystalline silicon having the same or substantially the same crystallinity as the polycrystalline silicon.

15. The method for manufacturing a semiconductor device according to any one of claims 11 to 14, characterized in that: In the third step, a component separation region is formed in the semiconductor layer between the first device region and the second device region.

16. The method for manufacturing a semiconductor device according to any one of claims 11 to 15, characterized in that: The polycrystalline silicon has a frame shape surrounding the emitter when viewed from the thickness direction.

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