Selective silicon nitride treatment for backside power supply networks

Abstract

Methods of fabricating logic or memory devices are provided. The methods include selectively depositing a silicon-containing dielectric layer in a source / drain recess on a substrate and through an opening in an oxide liner within the source / drain recess. The silicon-containing dielectric layer is then densified.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of semiconductor devices and semiconductor device manufacturing. More specifically, embodiments of the present invention relate to a method for reducing over-etching of the back-side contacts of both NMOS and PMOS contacts. Background Technology

[0002] Integrated circuits have evolved into complex devices that can include millions of transistors, capacitors, and resistors on a single chip. In the course of integrated circuit development, functional density (i.e., the number of interconnects per chip area) has gradually increased, while geometric dimensions (i.e., the smallest components (or lines) that can be created using manufacturing processes) have decreased.

[0003] Transistors are critical components in most integrated circuits. Since the drive current and therefore speed of a transistor are proportional to its gate width, faster transistors typically require larger gate widths. Therefore, there is a trade-off between transistor size and speed, and the "Fin Field-Effect Transistor" (FinFET) has been developed to resolve this conflict between maximizing drive current and minimizing transistor size. FinFETs are characterized by fin-shaped channel regions, which significantly increase transistor size without substantially increasing its footprint, and are now used in many integrated circuits. However, FinFETs have their own drawbacks.

[0004] As transistor device feature sizes continue to shrink to achieve greater circuit density and higher performance, there is a need to improve transistor device structures and reduce contact resistance. Examples of transistor device structures include planar structures, FinFET structures, and gate-all-around (GAA) structures. Logic gate performance is related to the properties of the materials used and the thickness and area of ​​the structural layers. However, as certain gate features are tailored to accommodate device scaling, challenges arise.

[0005] As the semiconductor manufacturing industry moves into advanced modes below the 2nm node, there is a desire to improve device speed and drive current by reducing contact resistance. Therefore, there is a need for methods to reduce contact resistance.

[0006] Connecting semiconductors to power rails is typically done at the front end of the cell (e.g., semiconductor substrate), which requires a significant cell area. To enable continued area scaling in next-generation logic nodes, back-side power rail formation (referred to as BPR Gen-II) has been explored for the back side of the connection source epitaxial layer for logic transistors (e.g., FinFETs or GAAs).

[0007] Current known methods for back-side source epitaxial contacts result in excessive etching and damage to the device. Therefore, new manufacturing methods are needed. Summary of the Invention

[0008] One or more embodiments of the present invention relate to a method for forming a logic or memory device. In one or more embodiments, the method for forming a logic or memory device includes: selectively depositing a silicon-containing dielectric layer in source / drain recesses on a substrate and through openings in oxide pads within the source / drain recesses; and densifying the silicon-containing dielectric layer.

[0009] Additional embodiments of the invention relate to a processing tool. In one or more embodiments, the processing tool includes: a central transport station including a robot configured to move a wafer; a plurality of processing stations, each connected to the central transport station and providing a processing area separate from the processing of adjacent processing stations, the plurality of processing stations including one or more of a pre-cleaning chamber, an inhibitor soaking chamber, a selective deposition chamber, and a densification chamber; and a controller connected to the central transport station and the plurality of processing stations, the controller being configured to activate the robot to move the wafer between the processing stations, and to cause the processing tool to perform the following operations: selectively depositing a silicon-containing dielectric layer in source / drain recesses on a substrate and through openings in oxide pads within the source / drain recesses; and densifying the silicon-containing dielectric layer.

[0010] A further embodiment of the present invention relates to a method for forming a gate-all-around device. In one or more embodiments, the method for forming a gate-all-around device includes: forming an oxide pad on the sidewall surface of a superlattice structure and on the bottom surface of a source / drain recess of a superlattice structure on an adjacent substrate, the superlattice structure including a plurality of first layers and corresponding plurality of second layers arranged alternately in a plurality of stacked pairs extending between the source / drain recesses; removing a portion of the oxide pad from the bottom surface of the source / drain recess; selectively depositing a silicon-containing dielectric layer in the source / drain recess and through openings in the oxide pad within the source / drain recess; and densifying the silicon-containing dielectric layer. Attached Figure Description

[0011] A more detailed description of the invention, briefly summarized above, can be obtained by referring to some of the embodiments illustrated in the accompanying drawings, so that the above-described technical features of the invention can be understood in detail. However, it will be noted that the drawings illustrate only typical embodiments of the invention and are therefore not intended to limit its scope, as other equivalent embodiments are permissible.

[0012] Figure 1A It is a process flowchart of a method according to one or more implementation methods;

[0013] Figure 1BIt is a process flowchart of a method according to one or more implementation methods;

[0014] Figure 1C It is a process flowchart of a method according to one or more implementation methods;

[0015] Figure 1D It is a process flowchart of a method according to one or more implementation methods;

[0016] Figure 2 A cross-sectional view of a semiconductor device according to one or more embodiments is shown;

[0017] Figure 3 A cross-sectional view of a semiconductor device according to one or more embodiments is shown;

[0018] Figure 4 A cross-sectional view of a semiconductor device according to one or more embodiments is shown;

[0019] Figure 5 A cross-sectional view of a semiconductor device according to one or more embodiments is shown;

[0020] Figure 6 A cross-sectional view of a semiconductor device according to one or more embodiments is shown;

[0021] Figure 7 A cross-sectional view of a semiconductor device according to one or more embodiments is shown;

[0022] Figure 8 A cross-sectional view of a semiconductor device according to one or more embodiments is shown;

[0023] Figure 9 A cross-sectional view of a semiconductor device according to one or more embodiments is shown;

[0024] Figure 10 A cross-sectional view of a semiconductor device according to one or more embodiments is shown;

[0025] Figure 11 A cross-sectional view of a semiconductor device according to one or more embodiments is shown;

[0026] Figure 12 A cross-sectional view of a semiconductor device according to one or more embodiments is shown; and

[0027] Figure 13 Illustrations of clustering tools according to one or more implementations.

[0028] For ease of understanding, the same reference numerals have been used as much as possible to refer to common elements in the figures. The figures are not drawn to scale and have been simplified for clarity. Elements and features of one embodiment may be advantageously incorporated into other embodiments without further explanation. Detailed Implementation

[0029] Before describing several exemplary embodiments of the present invention, it will be understood that the invention is not limited to the details of the architecture or processing steps described in the following description. The invention can be implemented or performed in various ways and in other ways.

[0030] As used in this specification and the appended claims, the term "substrate" refers to a surface or portion thereof on which processing is performed. Unless the context clearly indicates otherwise, those skilled in the art will understand that "substrate" may refer only to a portion of the substrate. Furthermore, "deposition on a substrate" may mean both a bare substrate and a substrate having one or more films or features deposited or formed thereon.

[0031] As used herein, “substrate” refers to any substrate on which a film treatment is performed during manufacturing processes, or a material surface formed on a substrate. For example, substrate surfaces on which treatments can be performed include materials such as silicon, silicon oxide, strained silicon, silicon-on-insulator (SOI), carbon-doped silicon oxide, silicon nitride, doped silicon, germanium, gallium arsenide, glass, sapphire, and any other materials such as metals, metal nitrides, metal alloys, and other conductive materials, depending on the application. Substrates include, but are not limited to, semiconductor wafers. Substrates may be exposed to pretreatment processes for polishing, etching, reduction, oxidation, hydroxylation (or generating or grafting target chemical moieties to impart chemical functionality), annealing, and / or baking of the substrate surface. In addition to film treatments performed directly on the surface of the substrate itself, any film treatment steps disclosed in this invention may also be performed over an underlying layer formed on the substrate, as will be described in more detail later, and the term “substrate surface” is intended to include this underlying layer as indicated by the context. Thus, for example, where a film / layer or portion of a film / layer has been deposited onto the substrate surface, the exposed surface of the newly deposited film / layer becomes the substrate surface. The content of a given substrate surface will depend on the film to be deposited and the specific chemicals used.

[0032] When used in this specification and the appended claims, the terms “precursor,” “reactant,” “reactive gas,” and the like are used interchangeably to refer to any gaseous species that can react with the substrate surface.

[0033] Epitaxy is a process in which the deposited film is forced to be highly crystallized and aligned with the substrate. Epitaxial growth is more broadly defined as the condensation of a gaseous precursor to form a film on a substrate. Liquid precursors can also be used. Gas-phase precursors can be obtained through chemical vapor deposition (CVD) and laser ablation. Several feasible epitaxial techniques are currently available, such as molecular beam epitaxy (MBE), epitaxial CVD, or atomic layer epitaxy (ALE).

[0034] A transistor is a circuit component or element typically formed on a semiconductor device. Depending on the circuit design, transistors are formed on a semiconductor device in addition to capacitors, inductors, resistors, diodes, wires, or other components. Generally, a transistor includes a gate formed between a source region and a drain region. In one or more embodiments, the source and drain regions include doped regions of the substrate and exhibit a doping profile suitable for a particular application. The gate is positioned over a channel region and includes a gate dielectric interposed between the gate electrode and the channel region in the substrate.

[0035] In this context, the term "field-effect transistor" or "FET" refers to a transistor that uses an electric field to control the electrical behavior of a device. Enhancement-mode field-effect transistors typically exhibit very high input impedance at low temperatures. The conductivity between the drain and source terminals is controlled by an electric field in the device, generated by the voltage difference between the body and the gate. The three terminals of an FET are the source (S), through which the carrier enters the channel; the drain (D), through which the carrier leaves the channel; and the gate (G), which terminates the channel conductivity. Conventionally, the current entering the channel at the source (S) is denoted as I. S The current entering the channel at the drain (D) is denoted as I. D The drain-to-source voltage is indicated by V. DS By applying a voltage to the gate (G), the current entering the channel at the drain (i.e., Id) can be controlled. D ).

[0036] A MOSFET (Metal-O-Semiconductor Field-Effect Transistor) is a type of field-effect transistor (FET). It features an insulated gate, the voltage of which determines the device's conductivity. The ability to change conductivity by the amount of applied voltage is used to amplify or switch electronic signals. A MOSFET is based on the modulation of charge concentration through a metal-oxide-semiconductor (MOS) capacitor between the host electrode and the gate electrode, which is located above the host and insulated from all other device regions by a gate dielectric layer. Compared to a MOS capacitor, a MOSFET includes two additional terminals (source and drain), each connected to a separate, highly doped region separated by the host region. These regions can be p-type or n-type, but they are of the same type and opposite in type to the host region. The source and drain (different from the host) are highly doped and indicated by a "+" sign after the doping type.

[0037] If the MOSFET is an n-channel or nMOS FET, the source and drain are in the n+ region, while the bulk is in the p region. If the MOSFET is a p-channel or pMOS FET, the source and drain are in the p+ region, while the bulk is in the n region. The source is so named because it is the origin of the charge carriers flowing through the channel (electrons for n-channels and holes for p-channels); similarly, the drain is where the charge carriers leave the channel.

[0038] In this context, the term "FinFET" refers to a MOSFET transistor built on a substrate, where the gate is placed on two or three sides of the channel, forming a dual-gate or tri-gate structure. FinFET devices have been given the common name FinFET because the channel region forms "fins" on the substrate. FinFET devices feature fast switching times and high current densities.

[0039] When used herein, the term "gate all-around (GAA)" is used to refer to an electronic device, such as a transistor, in which the gate material surrounds a channel region on all sides. The channel region of a GAA transistor may include nanowires or nano-slabs or nanosheets, strip channels, or other suitable channel configurations known to those skilled in the art to which this invention pertains. In one or more embodiments, the channel region of a GAA device has a plurality of vertically spaced horizontal nanowires or horizontal strips, such that the GAA transistor is a stacked horizontal gate all-around (hGAA) transistor.

[0040] An example of gate-all-around (GAA) technology is the complementary field-effect transistor (CFET). When used here, the term "complementary field-effect transistor (CFET)" refers to a transistor comprising NMOS FET devices and PMOS FET devices stacked on top of each other. Each of the NMOS FET devices and PMOS FET devices forming a CFET is a GAA transistor or an hGAA transistor. CFET transistors offer increased on-chip device density and reduced area consumption compared to GAA transistors.

[0041] When used here, the term "nanowire" refers to a nanostructure with a diameter of one nanometer (10⁻⁶). −9Nanowires can be defined as structures with a length-to-width ratio greater than 1000. Alternatively, nanowires can be defined as structures with a thickness or diameter limited to tens of nanometers or less and an unlimited length. Nanowires are used in transistors and some laser applications, and in one or more embodiments, nanowires are made of semiconductor materials, metallic materials, insulating materials, superconducting materials, or molecular materials. In one or more embodiments, nanowires are used in transistors for logic CPUs, GPUs, MPUs, and volatile (e.g., DRAM) and non-volatile (e.g., NAND) devices. As used herein, the term "nanosheet" refers to a two-dimensional nanostructure having a thickness ranging from about 0.1 nm to about 1000 nm.

[0042] Generally, front-end process (FEOL) refers to the first part of integrated circuit manufacturing, including transistor fabrication; mid-end process (MOL) uses a series of contact structures to connect transistors to interconnect components on the chip; and back-end process (BEOL) refers to a series of process steps after the transistor fabrication on the wafer is completed. One or more embodiments of the present invention relate to a method for forming a gate-all-around (GAA) transistor, which can be used in FEOL and / or BEOL processes.

[0043] Embodiments of the present invention are illustrated by way of figures, which depict apparatus (e.g., transistors) and processes for forming transistors according to one or more embodiments of the present invention. The processes shown are merely illustrative possible uses of the disclosed processes, and those skilled in the art will recognize that the disclosed processes are not limited to the illustrated applications.

[0044] One or more embodiments of the present invention are illustrated with reference to the figures. In one or more embodiments, a transistor, such as a gate-all-around transistor, FinFET, CFETS, NMOS, PMOS, and the like, is manufactured. In one or more embodiments, a standard process flow is used to manufacture the transistor, such as a GAA device. One or more of the figures illustrate a portion or step of a multi-step manufacturing process for a semiconductor device, particularly during back-side power supply (BPD).

[0045] Connecting semiconductors to power rails is typically done at the front end of the cell, which requires significant cell area. To enable continued area scaling in next-generation logic nodes, back-side power rail formation (known as BPR Gen-II) on the back side of the connection source epitaxial layer for logic transistors (e.g., FinFETs or GAAs) has been explored.

[0046] Embodiments of the present invention advantageously provide novel integration schemes that reduce over-etching of back-side contacts. Some embodiments relate to a processing and integration scheme that advantageously uses inhibitor processing on the sidewall pads and selective deposition of a silicon-containing layer (e.g., silicon nitride) as an etch stop layer to prevent over-etching. The silicon-containing layer is deposited from bottom to top on the front side of the contact trench from the front side of the wafer. In one or more embodiments, the silicon-containing layer is used as an etch stop layer when the wafer is flipped and subsequent back-side contact trench etching is performed from the back side of the wafer.

[0047] Figures 1A to 1D The diagram illustrates a process flow diagram of methods 10, 30, 50, and 70 for forming a semiconductor device 100 according to one or more embodiments of the present invention. Figures 1A to 1D The method will be referred to later. Figures 2 to 11 To explain, Figures 2 to 11 The text describes the stages of fabrication of a semiconductor structure (specifically, a gate-all-around (GAA) device) according to some embodiments of the present invention. Methods 10, 30, 50, and 70 of one or more embodiments may be part of a multi-step fabrication process for a semiconductor device. Therefore, methods 10, 30, 50, and 70 may be performed in any suitable processing chamber coupled to a clustering tool. The clustering tool may include processing chambers for fabricating semiconductor devices, such as chambers configured for etching, deposition, atomic layer deposition (ALD), physical vapor deposition (PVD), chemical vapor deposition (CVD), oxidation, or any other suitable chamber for fabricating semiconductor devices.

[0048] Figure 1A A process flow diagram illustrating an exemplary method 10 for forming a semiconductor device (e.g., a memory device or a logic device) is provided. Those skilled in the art will recognize that method 10 may include any or all of the processes illustrated. Furthermore, the order of individual processes may be varied for certain portions. Method 10 may begin with any of the listed processes without departing from the invention. (Refer to...) Figure 1A In operation 12, a substrate is provided. In this context, "provided" means that the substrate is made available for processing (e.g., positioned in a processing chamber). In operation 14, the surface of the substrate is cleaned to remove any impurities, such as native oxides. In operation 16, the substrate is exposed to growth inhibitors. In operation 18, a silicon-containing dielectric layer is selectively deposited in the regions of the film stack. In operation 20, the silicon-containing dielectric layer is densified.

[0049] Method 10 in one or more embodiments is an integrated method. In one or more embodiments, method 10 can be performed in one or more processing chambers without disrupting the vacuum between any of operations 12, 14, 16, 18, and 20.

[0050] Figure 1B A process flow diagram illustrating an exemplary method 30 for forming a semiconductor device (e.g., a memory device or a logic device) is provided. Those skilled in the art will recognize that method 30 may include any or all of the illustrated processes. Furthermore, the order of individual processes may be varied for certain portions. Method 30 may begin with any of the listed processes without departing from the invention. (Refer to...) Figure 1B In operation 32, a substrate is provided. In operation 34, the surface of the substrate is cleaned to remove any impurities, such as native oxides. In operation 36, the substrate is exposed to growth inhibitors. In operation 38, a silicon-containing dielectric layer is selectively deposited in the region of the device. Method 30 may then be performed via path A, wherein the silicon-containing dielectric layer is densified in operation 40. Alternatively, after operation 38, method 30 may then be performed via path B, wherein the silicon-containing dielectric layer is densified in operation 44.

[0051] Method 30 in one or more embodiments is an integrated method. In one or more embodiments, method 30 can be performed in one or more processing chambers without disrupting the vacuum between any of operations 32, 34, 36, 38, and 40, or the vacuum between any of 32, 34, 36, 38, and 44.

[0052] Figure 1C A process flow diagram illustrating an exemplary method 50 for forming a semiconductor device (e.g., a memory device or a logic device) is provided. Those skilled in the art will recognize that method 50 may include any or all of the illustrated processes. Furthermore, the order of individual processes may be varied for certain portions. Method 50 may begin with any of the listed processes without departing from the invention. (Refer to...) Figure 1C In operation 52, a substrate is provided. In operation 54, the surface of the substrate is cleaned to remove any impurities, such as native oxides. In operation 56, the substrate is optionally exposed to growth inhibitors. In operation 58, a silicon-containing dielectric layer is selectively deposited in the regions of the film stack. In operation 60, the silicon-containing dielectric layer is densified.

[0053] Method 50 in one or more embodiments is an integrated method. In one or more embodiments, method 50 can be performed in one or more processing chambers without disrupting the vacuum between any of operations 52, 54, 56, 58, and 60.

[0054] Figure 1D A process flow diagram illustrating an exemplary method 70 for forming a semiconductor device (e.g., a memory device or a logic device) is provided. Those skilled in the art will recognize that method 70 may include any or all of the processes illustrated. Furthermore, the order of individual processes may be varied for certain portions. Method 70 may begin with any of the listed processes without departing from the invention. (Refer to...) Figure 1DIn operation 72, a substrate is provided. In operation 74, the surface of the substrate is cleaned to remove any impurities, such as native oxides. In operation 76, the substrate is optionally exposed to growth inhibitors. In operation 78, a silicon-containing dielectric layer is selectively deposited in the region of the device. Method 70 may then be performed via path A, wherein, in operation 80, the silicon-containing dielectric layer is densified. Alternatively, after operation 78, method 70 may then be performed via path B, wherein, in operation 84, the silicon-containing dielectric layer is densified.

[0055] Method 70 in one or more embodiments is an integrated method. In one or more embodiments, method 70 can be performed in one or more processing chambers without disrupting the vacuum between any of operations 72, 74, 76, 78, and 80, or the vacuum between any of 72, 74, 76, 78, and 84.

[0056] Reference Figures 1A to 1D and Figures 2 to 13 Methods 10, 30, 50, and 70 commence operations 12, 32, 52, and 72 by providing substrate 102. In one or more embodiments, a superlattice structure 103 is formed on the top surface 101 of the semiconductor substrate 102.

[0057] In some embodiments, substrate 102 may be a bulk semiconductor substrate. The term bulk semiconductor substrate refers to a substrate in which the entire substrate is composed of semiconductor material. A bulk semiconductor substrate may contain any suitable semiconductor material and / or combination of semiconductor materials for forming a semiconductor structure. For example, the semiconductor layer may contain one or more materials, such as crystalline silicon (e.g., Si). <100> or Si <111> The semiconductor material may be silicon oxide, strained silicon, silicon-germanium, doped or undoped polycrystalline silicon, doped or undoped silicon wafers, patterned or unpatterned wafers, doped silicon, germanium, or other suitable semiconductor materials. In some embodiments, the semiconductor material is silicon (Si). In some embodiments, the semiconductor material may be a doped material, such as n-doped silicon (n-Si) or p-doped silicon (p-Si). In some embodiments, any suitable treatment may be used to dope the substrate, such as ion implantation. In some embodiments, the substrate may be doped to provide a high dose of dopant at a first location on the surface of the substrate 102 to prevent parasitic bottom device activation. A superlattice structure is formed on top of the first location. For example, in some embodiments, the surface of the substrate may have a dopant density of about 10⁻⁶. 18 atoms / cm 3 To about 10 19 atoms / cm 3 .

[0058] Reference Figure 2In some embodiments, source / drain recesses 112 are formed within the semiconductor substrate 102. The source / drain recesses 112 can be formed of any suitable semiconductor material, such as, but not limited to, silicon (Si), germanium (Ge), silicon-germanium (SiGe), or the like. In some embodiments, the source / drain recesses 112 can be formed using any suitable deposition process, such as epitaxial deposition. In some embodiments, the source / drain recesses 112 have a depth ranging from 30 nm to 60 nm.

[0059] At least one superlattice structure 103 is formed on top of the top surface 102a of the semiconductor substrate 102. The superlattice structure 103 is formed adjacent to the source / drain recesses 112 formed in the semiconductor substrate 102. The superlattice structure 103 includes a plurality of first layers 104 and corresponding plurality of second layers 106 arranged alternately in a plurality of stacked pairs. In some embodiments, the plurality of stacked layer groups include silicon (Si) and silicon germanium (SiGe) groups.

[0060] In one or more embodiments, a plurality of first layers 104 comprise a first material and a plurality of corresponding second layers 106 comprise a second material. In one or more embodiments, the first material comprises silicon-germanium (SiGe) and the second material comprises silicon (Si). In other embodiments, the first material comprises silicon (Si) and the second material comprises silicon-germanium (SiGe). In one or more embodiments, the plurality of first layers 104 and the corresponding plurality of second layers 106 may comprise any number of lattice-matching material pairs suitable for forming a superlattice structure. In one or more embodiments, the plurality of first layers 104 and the corresponding plurality of second layers 106 comprise 2 to 50 pairs, or 2 to 20 pairs of lattice-matching materials.

[0061] Typically, parasitic devices are present at the bottom of the superlattice structure 103. In one or more embodiments, as discussed above, the implantation of dopants in the substrate is used to suppress the activation of parasitic devices. In one or more embodiments, the substrate 102 is etched such that the bottom portion of the superlattice structure 103 includes a substrate portion that is not removed, allowing the substrate portion to serve as a bottom release layer of the superlattice structure.

[0062] In one or more embodiments, the thickness of the first layer 104 and the thickness of the second layer 106 are in the range of about 2 nm to about 50 nm, or in the range of about 3 nm to about 20 nm. In one or more embodiments, the average thickness of the first layer 104 is 0.5 to 2 times the average thickness of the second layer 106.

[0063] In one or more embodiments, a dummy gate structure 108 is formed over the superlattice structure 103. The dummy gate structure 108 defines a channel region of the transistor device. The dummy gate structure 108 can be formed using any suitable conventional deposition and patterning process known in the art.

[0064] In one or more embodiments, sidewall spacers 110 are formed along the outer sidewalls of the dummy gate structure 108. The sidewall spacers 110 in one or more embodiments comprise suitable insulating materials known in the art, such as silicon nitride (SiN), silicon oxide (SiOx), silicon oxynitride (SiON), silicon carbide (SiC), or the like. In some embodiments, the sidewall spacers 110 are formed using any suitable conventional deposition and patterning processes known in the art, such as atomic layer deposition, plasma-enhanced atomic layer deposition, plasma-enhanced chemical vapor deposition, or low-pressure chemical vapor deposition.

[0065] Reference Figure 3 In one or more embodiments, oxide pad 114 is deposited in the source / drain recess 112, along the sidewall 105 of the superlattice structure 103, on the top surface 109 of the dummy gate structure 108 and the sidewall spacer 110, and on the bottom surface 107 of the source / drain recess 112. The oxide pad 114 may comprise any suitable material known to those skilled in the art. In one or more embodiments, the oxide pad 112 may comprise materials selected from silicon oxide (SiO2). x Materials containing silicon oxide (SiOC), silicon carbonyl (SiCOH), and the like. When used herein, terms such as “silicon oxide” refer to materials containing both silicon and oxygen. “Silicon oxide” should not be construed as implying any stoichiometric ratio. In other words, dielectric materials containing silicon oxide can be stoichiometric or non-stoichiometric, silicon-rich or silicon-poor.

[0066] Reference Figure 4 In one or more embodiments, the oxide pad 114 is opened to expose the top surface 109 of the dummy gate structure 108 and the sidewall spacer 110, and to expose the bottom surface 107 of the source / drain recess 112. The oxide pad 114 can be removed by any suitable process known to those skilled in the art, including but not limited to reactive ion etching and planarization.

[0067] Reference Figure 5 and Figures 1A to 1DIn operations 14, 34, 54, and 74, for example, the exposed surfaces of the bottom surface 107, top surface 109, and sidewall surfaces 115 of the oxide pad 114 may be cleaned / pre-cleaned. In some embodiments, the cleaning / pre-cleaning process includes sublimation etching for the removal of native oxides. The etching process may be plasma-based or thermal-based. The plasma process may be any suitable plasma (e.g., conductively coupled plasma, inductively coupled plasma, microwave plasma). In one or more embodiments, the cleaning process may include conventional plasma etching or remote plasma-assisted dry etching. In one or more embodiments of remote plasma-assisted dry etching, device 100 is exposed to H2, NF3, and / or NH3 plasma species, such as plasma-excited hydrogen and fluorine species. For example, in some embodiments, device 100 may undergo simultaneous exposure to H2, NF3, and NH3 plasmas. Remote plasma-assisted dry etching can be performed in any suitable pre-cleaning chamber, which may be integrated into one of a variety of multiprocessing platforms. One or more embodiments of the wet etching process may include a hydrofluoric (HF) acid last treatment, i.e., a so-called "HF last" treatment, in which HF etching of the surface is performed to leave hydrogen-sealed ends on the surface. Alternatively, any other liquid system pre-cleaning treatment may be used.

[0068] Reference Figure 5 and Figures 1A to 1D In one or more embodiments, during operations 16, 36, 56, and 76, the semiconductor device 100 is exposed to growth inhibitors to prevent deposition. Growth inhibitors may be added to the sidewall surface 115 of the oxide pad 114 to prevent deposition on the oxide pad 114. In some embodiments, such as Figure 1C As illustrated in method 50, exposing the semiconductor device 100 to a growth inhibitor is optional.

[0069] In one or more embodiments, for example, surface treatment exposed to growth inhibitors is used to ensure that different end-capping groups exist on the sidewall surface 115 of the oxide liner 114 and the bottom surface 107 of the source / drain recess 112, so that the ALD of the subsequent CVD film growth is distinguished based on surface differences. For example, to prepare a bare Si surface end-capped with Si-H groups, diluted HF wet cleaning, dry cleaning, or plasma-based dry cleaning can be used to remove native oxides on the Si surface and form Si-H bonds. To prepare a passivated surface that can block ALD film growth, a hydrophobic surface monolayer can be formed on the silicon oxide surface. For example, alkylamine silanes can be adsorbed onto the silicon oxide surface to form alkylsilane groups on the SiO surface. The ALD film growth chemistry of some embodiments is based on the reaction of silicon halide with ammonia, which can selectively grow on bare Si surfaces but not on passivated SiO surfaces. The maximum thickness achievable by some embodiments is about 100 Å of growth on bare Si, with virtually no film growth on the passivated SiO surface. Periodic SiO and / or SiOC surface regeneration and passivation can be used to enable thicker growth compared to SiO on bare Si.

[0070] Reference Figure 5 According to one or more embodiments of the present invention, exposure to the growth inhibitor may include the formation of a barrier layer 116 having a hydroxyl-terminated surface on the sidewall surface 115 of the oxide liner 114, while the bottom surface 107 of the source / drain recess 112 may have a hydrogen-terminated surface. In some embodiments not shown, the sidewall surface 115 of the oxide liner 114 and the bottom surface 107 of the source / drain recess 112 may also have some native oxide formed thereon. Those skilled in the art will understand that surface atomic bonding is not always simple. For example, the oxide surface may be a bridging oxygen atom bonded to more than one silicon atom, and the stoichiometry of the surface and bulk composition is not necessarily one-to-one.

[0071] The sidewall surface 115 of the oxide pad 114 and the bottom surface 107 of the source / drain recess 112 can be any suitable surface for selective deposition. In some embodiments, the sidewall surface 115 of the oxide pad 114 is a dielectric surface with –OH-terminated groups, while the bottom surface 107 of the source / drain recess 112 comprises a silicon surface with Si-H groups, with or without native oxide. In some embodiments, the bottom surface 107 of the source / drain recess 112 comprises a dielectric surface with –OH-terminated groups, while the sidewall surface 115 of the oxide pad 114 comprises a silicon surface with Si-H groups, with or without native oxide.

[0072] If native oxide is present on the sidewall surface 115 of oxide pad 114 and the bottom surface 107 of source / drain recess 112, removal of the native oxide allows for more efficient selective deposition processing. Exposing device 100 to an etching process removes the native oxide from the sidewall surface 115 of oxide pad 114 and the bottom surface 107 of source / drain recess 112. The etching process can be a wet etching process (e.g., exposure to diluted HF (1%)) or a dry etching process (e.g., exposure to plasma). In some embodiments, the etching process is a plasma-based process. In some embodiments, a plasma-based etching process includes exposing the substrate to plasma containing ammonia and hydrofluoric acid.

[0073] In some embodiments, removing the native oxide from the sidewall surface 115 of the oxide liner 114 and the bottom surface 107 of the source / drain recess 112 provides a surface with substantially hydrogen-only end-capping. When used in this manner, the term "substantially hydrogen-only end-capping" means that the surface end-capping has more than or equal to about 98% of its surface area occupied by hydrogen. In some embodiments, removing the native oxide from the sidewall surface 115 of the oxide liner 114 and the bottom surface 107 of the source / drain recess 112 provides a surface that is substantially oxygen-free end-capping. When used in this manner, the term "substantially oxygen-free end-capping" means that the surface end-capping contains less than about 2% of its surface area occupied by oxygen atoms.

[0074] In one or more embodiments, the process for removing native oxide from the sidewall surface 115 of the oxide liner 114 also removes native oxide from the bottom surface 107 of the source / drain recess 112 to provide a surface that is substantially free of hydrogen end-capping. When used in this manner, the term "substantially free of hydrogen end-capping" means that the surface end-capping of the surface has less than or equal to about 2% of the surface area of ​​hydrogen. In some embodiments, the sidewall surface 115 of the oxide liner 114 contains substantially only hydroxyl end-capping. When used in this manner, the term "substantially only hydroxyl end-capping" means that the surface end-capping of the body surface has hydroxyl groups greater than or equal to about 98% of the surface area of ​​hydroxyl groups.

[0075] The device, including the sidewall surface 115 of the oxide liner 114 and the bottom surface 107 of the source / drain recess 112, is exposed to a growth inhibitor to react with the hydroxyl-terminated surface to form a barrier layer 116. Some embodiments of the growth inhibitor comprise alkylsilanes. In some embodiments, it has the general formula SiR4, wherein each R is independently a C1-C6 alkyl, a substituted or unsubstituted amine, or a substituted or unsubstituted cyclic amine.

[0076] In some embodiments, the alkylsilane comprises substantially no Si-H bonds. When used in this manner, the term "substantially no Si-H bonds" means that the growth inhibitor comprises less than about 1% Si-H bonds based on silicon bonds. In some embodiments, the growth inhibitor forms a surface-capped OSiR on the sidewall surface 115 of the oxide pad 114 and the bottom surface 107 of the source / drain recess 112. x The –OH terminator is replaced. In some embodiments, the growth inhibitor comprises one or more of 1-(trimethylsilyl)pyrrolidine or bis(dimethylamine)dimethylsilane.

[0077] In one or more embodiments, the alkylsilane comprises at least one substituted or unsubstituted cyclic amine having a ring having a number ranging from 4 to 10 atoms. In some embodiments, the alkylsilane comprises a cyclic amine having one nitrogen atom. In some embodiments, the cyclic amine has no more than one nitrogen atom and at least one nitrogen atom. In one or more embodiments, the cyclic amine comprises pyrrolidine, wherein the nitrogen atom of the pyrrolidine is bonded to a silicon atom of the alkylsilane. In some embodiments, the alkylsilane comprises 1-(trimethylsilyl)pyrrolidine. In one or more embodiments, the alkylsilane is substantially composed of 1-(trimethylsilyl)pyrrolidine. When used in this manner, the term "substantially composed of" means that the alkylsilane is greater than or equal to about 98% 1-(trimethylsilyl)pyrrolidine on a molecular basis.

[0078] Device 100 may be exposed to growth inhibitors at any suitable temperature and pressure. In one or more embodiments, device 100 is exposed to growth inhibitors at temperatures ranging from about 50 ºC to about 500 ºC, or from about 100 ºC to about 400 ºC. In some embodiments, device 100 is exposed to growth inhibitors at pressures ranging from about 30 Torr to about 120 Torr, or from about 40 Torr to about 100 Torr, or from about 50 Torr to about 90 Torr. In one or more embodiments, device 100 is exposed to growth inhibitors during a heat treatment without plasma.

[0079] Reference Figure 6 and Figures 1A to 1D In one or more embodiments, during operations 18, 38, 58, and 78, the silicon-containing dielectric layer 118 may be selectively deposited on the bottom surface 107 of the source / drain recess 112, without (or substantially without) deposited on the oxide layer 114. The silicon-containing dielectric layer 118 may be deposited by any suitable method known to those skilled in the art. In one or more embodiments, the silicon-containing dielectric layer 118 is deposited, for example, by atomic layer deposition (ALD) or chemical vapor deposition (CVD), at a temperature less than 500 °C.

[0080] The silicon-containing dielectric layer 118 may comprise any suitable dielectric material known to those skilled in the art. As used herein, the term "dielectric material" refers to a layer of material of an electrical insulator that can be polarized in an electric field. In one or more embodiments, the silicon-containing dielectric layer 118 comprises one or more of silicon nitride (SiN), silicon carbonitride (SiCN), silicon oxynitride (SiON), silicon oxycarbonitride (SiOCN), silicon boride (SiB), and silicon boron nitride (SiBN). In a particular embodiment, the silicon-containing dielectric layer 118 comprises silicon nitride (SiN).

[0081] In one or more embodiments, the deposition of the silicon-containing dielectric layer 118 is selective relative to the sidewall surface 115 of the oxide layer 114 with respect to the bottom surface 107 of the source / drain recess 112, such that the silicon-containing dielectric layer 118 is deposited on the bottom surface 107 of the source / drain recess 112 and not (or substantially not) deposited on the oxide pad 114. When used in this manner, the term "selectively relative to" means that the film is formed on the bottom surface 107 of the source / drain recess 112 to a greater extent than the film that can be formed on the oxide layer 114. For example, the silicon-containing dielectric layer 118 may be formed on the bottom surface 107 of the source / drain recess 112 to be 20, 30, 40, or 50 times thicker than the film formed on the oxide pad 114. In one or more embodiments, the selectivity is greater than 2:1, greater than 5:1, greater than 10:1, or greater than 100:1.

[0082] In one or more embodiments, the silicon-containing dielectric layer 118 has a thickness ranging from greater than 0 Å to 200 Å.

[0083] Unintentionally limited by theory, it was anticipated that the relatively low deposition temperature (i.e., less than 500 °C) would result in a poor-quality silicon-containing dielectric layer 118. Consequently, the poor-quality silicon-containing dielectric layer 118 exhibits a poor wet etch rate (WER) greater than 300 Å.

[0084] The formation of the silicon-containing dielectric layer 118 can occur using any suitable technique, including but not limited to atomic layer deposition. In one or more embodiments, the silicon-containing dielectric layer 118 is formed in a single processing chamber. In other embodiments, the silicon-containing dielectric layer 118 is formed in a batch processing chamber, as shown in FIG. 14. For example, the silicon-containing dielectric layer 118 is formed by sequentially exposing a silicon precursor and a reactant. In some embodiments, the silicon-containing dielectric layer 118 comprises one or more of SiN, SiO, SiON, SiC, SiCO, SiCN, or SiCON. In some embodiments, the silicon-containing dielectric layer 118 comprises silicon and one or more of oxygen, carbon, or nitrogen atoms. In some embodiments, the silicon-containing dielectric layer 118 is doped with one or more of boron (B), arsenic (As), or phosphorus (P) in an atomically significant amount up to about two percent.

[0085] In some embodiments, the silicon precursor comprises a silicon halide, and the reactant comprises ammonia. In some embodiments, the silicon precursor comprises an organosilicon compound with or without halogen atoms. In some embodiments, the reactant includes a nitrogen-contributing species, an oxygen-contributing species, and / or a carbon-contributing species. In some embodiments, the silicon precursor contributes one or more of nitrogen, oxygen, or carbon to the silicon-containing dielectric layer 118.

[0086] In one or more embodiments, the silicon-containing dielectric layer 118 is deposited using ALD or CVD, wherein the bottom surface 107 of the source / drain recess 112 is exposed to a silicon precursor and ammonia to form the silicon-containing dielectric layer 118 on the bottom surface 107 of the source / drain recess 112. The silicon precursor may include any suitable silicon precursor known to those skilled in the art. In one or more embodiments, the silicon precursor comprises silane (SiH4) or polysilane (Si... x H y In some embodiments, the polysilane is selected from disilane (Si2H6), trisilane (Si3H8), and tetrasilane (Si4H6). 10 ), isotetrasilane, neopentasilane (Si5H) 12 ), cyclopentasilane (Si5H) 10 ), hexasilane (C6H) 14 ), and cyclohexane (Si6H) 12 ).

[0087] In a single processing chamber, the substrate can be exposed to silicon precursors and reactants in the same processing area of ​​the chamber. In a batch processing chamber, the substrate can be exposed to silicon precursors and reactants in alternating processing areas of the chamber.

[0088] The silicon-containing dielectric layer 118 can be deposited to a predetermined thickness. After a certain period of time, even in the presence of the barrier layer 116 (from the growth inhibitor), the silicon-containing dielectric layer 118 may begin to deposit on the sidewall surface 115 of the oxide pad 114. Without being limited to any particular theory of operation, it is believed that the barrier layer 116 can be removed by repeated exposure to the deposition reactants. To increase the thickness of the silicon-containing dielectric layer 118 and maintain selectivity, the barrier layer 116 may be replenished periodically. In some embodiments, the device 100 is exposed to the growth inhibitor to deposit the silicon-containing dielectric layer 118 after no more than 20, 30, 40, 50, 60, 70, 80, 90, or 100 atomic layer deposition cycles. In some embodiments, the device 100 is exposed to growth inhibitors after the silicon-containing dielectric layer 118 has been formed to a thickness of about 30 Å to about 100 Å, or after the silicon-containing dielectric layer 118 has been formed to a thickness of up to about 20 Å, 30 Å, 40 Å, 50 Å, 60 Å or 70 Å.

[0089] Regeneration of the barrier layer 116 can be accomplished by any suitable treatment. For example, the surface of the device can be purged with an inert gas (e.g., N2 or He) for a time ranging from about 10 minutes to about 60 minutes at a pressure ranging from about 1 Torr to about 30 Torr. After surface purge, the device can be re-exposed to a growth inhibitor to regenerate the barrier layer 116. In some embodiments, the surface is purged for a time ranging from about 15 minutes to about 50 minutes, or for a time ranging from about 20 minutes to about 40 minutes. In some embodiments, the surface is purged at a pressure ranging from about 10 Torr to about 25 Torr, or for a pressure ranging from about 15 Torr to about 20 Torr.

[0090] In some implementations, the barrier layer 116 is regenerated by first etching the entire surface and then exposing it to the growth inhibitor. The etching process may be the same as that used for pre-cleaning the surface or may be a different etching process.

[0091] The silicon-containing dielectric layer 118 can be formed at any suitable temperature. In some embodiments, the silicon-containing dielectric layer 118 is formed at temperatures ranging from about 200 ºC to about 700 ºC, or from about 300 ºC to about 500 ºC, or from about 350 ºC to about 450 ºC. In some embodiments, the silicon-containing dielectric layer 118 is formed by a heat treatment without plasma exposure. In one or more embodiments, a thermal method is used for the selective deposition of the silicon-containing dielectric layer 118. In a particular embodiment, the heat treatment is performed without plasma and without the formation of a seed layer. In other words, the silicon-containing dielectric layer 118 is selectively deposited directly onto the bottom surface 107 of the source / drain recess 112 without the deposition of an intermediate material layer. As used herein, "seed layer" refers to a layer deposited directly onto the bottom surface 107 of the source / drain recess 112 to promote the subsequent formation / growth of a bulk layer thereon. In some cases, the bulk layer cannot be deposited directly on the bottom surface 107 of the source / drain recess 112 without the deposition of an intermediate material layer; in such cases, a seed layer is required to enable bulk deposition. Advantageously, in one or more embodiments, the silicon-containing dielectric layer 118 is deposited directly on the bottom surface 107 of the source / drain recess 112 as a bulk layer without the deposition of an intermediate material layer. In other embodiments, the silicon-containing dielectric layer 118 is formed by plasma-enhanced processing.

[0092] The deposited silicon-containing dielectric layer 118 may have film properties that can be optimized or improved through post-deposition processing. For example, the deposited silicon nitride film may have a high wet etch rate. Exposing the film to post-deposition processing can be used to improve the wet etch rate of the deposited silicon-containing dielectric layer 118. In some embodiments, post-deposition processing improves the quality of the film. In some embodiments, the improved film quality includes one or more of the following: wet etch rate, refractive index, density, or hydrogen concentration.

[0093] Some embodiments of the post-deposition processing involve exposing the substrate surface to a decoupling plasma. One or more embodiments of the decoupling plasma contain helium. In some embodiments, the decoupling plasma is substantially composed of helium. When used in this manner, the term "substantially composed of helium" means that the plasma contains helium at a percentage of greater than or equal to about 95 atomic percent. The processing pressure in some embodiments ranges from about 1 mTorr to about 1 Torr. Lower pressures can be used for isotropic processing of high aspect ratio structures. The wafer temperature during processing can range from about room temperature to about 500 ºC.

[0094] In some embodiments, the processing platform has an environment in which the substrate surface is not easily oxidized after cleaning. When used in this manner, the term "environment" refers to the surrounding conditions, at least within the central transfer station. In some embodiments, the environment of the processing platform also includes any processing chambers used in the deposition process. For example, if two processing chambers are used in the process, "environment" may include both processing chambers and the central transfer station. In some embodiments, the environment of the processing platform contains water vapor. The water vapor may or may not be mixed with an inert gas. In some embodiments, the water vapor is present in the inert gas in an amount ranging from about 0.1% to about 90% by weight. In some embodiments, the water vapor is present in an amount ranging from about 1% to about 80% by weight, or from about 2% to about 70%, or from about 3% to about 60%, or from about 4% to about 50%, or from about 5% to about 40%, or from about 10% to about 20%. In some implementations, the environment comprises one or more of nitrogen, hydrogen, helium, argon, krypton, neon, or xenon, and contains water vapor in amounts greater than or equal to about 0.1%, 0.5%, 1%, 2%, 3%, 4%, 5%, 6%, 7%, 8%, 9%, 10%, 12%, 14%, 16%, 18%, or 20%.

[0095] According to one or more embodiments, the substrate undergoes processing before and / or after the formation of this layer. This processing can be performed in the same chamber or in one or more separate processing chambers. In some embodiments, the substrate is moved from a first chamber to a separate second chamber for further processing. The substrate can be moved directly from the first chamber to the separate processing chamber, or it can be moved from the first chamber to one or more transfer chambers and then to the separate processing chambers. Thus, the processing apparatus may include multiple chambers connected to the transfer chambers. Such an apparatus may be referred to as a "clustering tool" or a "clustering system" and the like.

[0096] Figure 7 show Figure 1A Operation 20 Figure 1B Operation 40 Figure 1C Operation 60, and Figure 1D Operation 80 or operation 86, wherein the silicon-containing dielectric layer 116 is densified to form a high-quality densified silicon-containing dielectric layer 120.

[0097] The silicon-containing dielectric layer 118 may be densified by any suitable means known to those skilled in the art. In one or more embodiments, the silicon-containing dielectric layer 118 is densified by one or more heat treatments or other processes without adding oxygen into the silicon-containing dielectric layer 120. In one or more embodiments, the silicon-containing dielectric layer 118 is exposed to rapid thermal processing (RTP) to provide a high-quality densified silicon-containing dielectric layer 120. In other embodiments, densifying the silicon-containing dielectric layer 118 comprises exposing the silicon-containing dielectric layer 118 to a high-density plasma at a temperature less than or equal to 500 °C and a pressure less than 1 Torr. The high-density plasma may be selected from one or more of helium (He), hydrogen (H2), nitrogen (N), neon (Ne), argon (Ar), krypton (Kr), and xenon (Xe).

[0098] In one or more embodiments, during operation 20, the selectively deposited silicon-containing dielectric layer 118 is densified at a temperature greater than 800 °C to provide a densified silicon-containing dielectric layer 120. In some embodiments, the silicon-containing dielectric layer 118 is processed at a temperature greater than 1000 °C to provide a densified silicon-containing dielectric layer 120. In one or more embodiments, after processing, the silicon-containing dielectric layer 120 is a high-quality film with a wet etch rate of less than 4 Å / min, including wet etch rates of less than 3 Å / min, less than 2 Å / min, and less than 1 Å / min.

[0099] In one or more embodiments, the densified silicon-containing dielectric layer 120 has a density gradient in the range of 2.2 g / cm³. 3 Up to 3.2 g / cm 3 When used here, the term "gradient" refers to the variation in density throughout the thickness of the material. In other words, the densified silicon-containing dielectric layer 120 has a density gradient, wherein the density of the densified silicon-containing dielectric layer 120 gradually changes from the least dense portion of the film adjacent to the surface deposited thereon (i.e., the bottom surface 107 of the source / drain recess 112).

[0100] In one or more embodiments, the densified silicon-containing dielectric layer 120 has a thickness ranging from greater than 20 Å to less than 100 Å at the region of minimum density closest to the bottom surface 107 of the source / drain recess 112. In one or more embodiments, the densified silicon-containing dielectric layer 120 has a thickness ranging from 5 Å to 25 Å at the region of maximum density furthest from the bottom surface 107 of the source / drain recess 112.

[0101] One or more embodiments of the method are integrated methods. In one or more embodiments, the method can be performed in one or more processing chambers without disrupting the vacuum.

[0102] Reference Figures 8 to 12For example, the formation of a gate-all-around (GAA) device can then be performed using conventional methods. (See reference...) Figure 8 The oxide pad 114 is removed from the device 100, exposing the sidewall surface 105 of the superlattice structure 103. The oxide pad 114 can be removed by any suitable method known to those skilled in the art. In one or more embodiments, the oxide pad 114 is removed by one or more of etching or planarization.

[0103] Reference Figure 9 The method includes laterally etching each of a plurality of first layers 104 to form a plurality of recessed first layers 104' having recessed regions 122 adjacent to the recessed first layers 104' and adjacent to the source / drain recesses 112.

[0104] For example, where the superlattice structure 103 comprises a plurality of second layers 106 containing silicon (Si) and a plurality of first layers 104 containing silicon germanium (SiGe), the plurality of first layers 104 are laterally etched to form a plurality of recessed first layers 104'. The plurality of first layers 104 can be laterally etched using any known etchant selective for the plurality of first layers 104, wherein the etchant etches the plurality of first layers 104 at a significantly higher rate than the plurality of second layers 106. In some embodiments, selective dry etching or wet etching processes can be used. In one or more embodiments, a dry etching process includes exposing the plurality of first layers 104 to commonly used etching silicon gases, reactive ion etching (RIE) from a remote plasma source, ammonia (NH3), nitrogen trifluoride (NF3), and hydrogen (H2). In some embodiments, the plurality of first layers 104 can be etched using wet etchants, such as, but not limited to, aqueous solutions of carboxylic acid / nitric acid / HF and aqueous solutions of citric acid / nitric acid / HF.

[0105] In one or more embodiments, each of the plurality of recessed first layers 104' has a recessed region 122 with a number of recesses relative to the plurality of first layers 104 prior to etching. In other words, the number of recesses refers to the amount of first material removed from the plurality of first layers 104 to form the plurality of recessed first layers 104'. In some embodiments, each of the plurality of recessed first layers 104' has a number of recesses ranging from 1 nm to 4 nm. In some embodiments, the number of recesses is 3 nm.

[0106] Reference Figure 10 The method includes epitaxially growing a source / drain layer 124 on a densified and / or oxidized silicon-containing dielectric layer 120. The epitaxial growth process may include any suitable deposition process, such as those described herein.

[0107] In some embodiments, the source / drain layer 124 has any suitable thickness. In some embodiments, the source / drain layer 124 fills part of the top portion of the source / drain recess 112. In some embodiments, the source / drain layer 124 fills the entire top portion of the source / drain recess 112. In other words, in some embodiments, the depth to which the source / drain layer 124 fills the top portion of the source / drain recess 112 can be defined by the height of the superlattice structure 103 (the total thickness of 2 to 50 pairs of lattice-matching materials, or the total thickness of 2 to 10 pairs).

[0108] The front-side processing is performed according to standard procedures known to those skilled in the art. The device then undergoes wafer 126 bonding and flipping for back-side power processing. In one or more embodiments, the device undergoes polishing and thinning according to standard procedures known to those skilled in the art.

[0109] Reference Figure 11 The opening 128 above the source / drain layer 124 is etched. The opening 128 can be formed by any suitable means known to those skilled in the art. In one or more embodiments, the silicon-containing dielectric layer 120 advantageously serves as an etch stop for forming the opening 128, reducing over-etching of the back-side contact.

[0110] Reference Figure 12 The silicon dielectric layer 120 and the remaining oxide pad 114 are then removed and back-side processed using standard procedures.

[0111] Additional embodiments of the present invention relate to a processing tool 900 for forming a logic or memory device and the method described herein, such as... Figure 13 As shown.

[0112] In one or more embodiments, the processing tool 900 is a cluster tool including at least one central transfer station, such as a first transfer chamber 921 and a second transfer chamber 931, with multiple sides. At least one robot 925, 935 is positioned within at least one central transfer station, such as the first transfer chamber 921 and the second transfer chamber 931, and is configured to move robot blades and wafers to each of the multiple sides.

[0113] In one or more embodiments, the processing tool 900 is a cluster tool comprising multiple processing chambers 902, 904, 906, 908, 910, 912, 914, 916, and 918, also referred to as processing stations, connected to a central transfer station. The various processing chambers provide separate processing areas isolated from adjacent processing stations. The processing chambers can be any suitable chamber, including but not limited to pre-cleaning chambers, inhibitor soaking chambers, selective deposition (ALD) chambers, and densification chambers (RTP). The specific arrangement of the processing chambers and components may vary depending on the cluster tool and should not be construed as limiting the scope of the invention.

[0114] exist Figure 13 In the illustrated embodiment, the plant interface 950 is connected to the front of the processing tool 900. The plant interface 950 includes a loading chamber 954 and a unloading chamber 956 at the front of the plant interface 950. Although the loading chamber 954 is shown on the left and the unloading chamber 956 is shown on the right, those skilled in the art will understand that this is merely a representative of one possible configuration.

[0115] The size and shape of the loading chamber 954 and the unloading chamber 956 can vary depending on the substrate being processed, for example, in a processing tool 900 (e.g., a clustering tool). In the illustrated embodiment, the loading chamber 954 and the unloading chamber 956 are sized to hold a wafer cassette with multiple wafers positioned within it.

[0116] Robot 952 is located within factory interface 950 and can move between loading chamber 954 and unloading chamber 956. Robot 952 is capable of transferring wafers from a cassette in loading chamber 954 through factory interface 950 to a load-locking chamber 960. Robot 952 is also capable of transferring wafers from load-locking chamber 960 through factory interface 950 to a cassette in unloading chamber 956. Those skilled in the art will understand that factory interface 950 may have more than one robot 952. For example, factory interface 950 may have a first robot and a second robot, the first robot transferring wafers between loading chamber 954 and load-locking chamber 960, and the second robot transferring wafers between load-locking chamber 960 and unloading chamber 956.

[0117] In one or more embodiments, the processing tool 900 is a cluster tool having a first segment 920 and a second segment 930. The first segment 920 is connected to the factory interface 950 via load-locking chambers 960, 962. The first segment 920 includes a first transfer chamber 921 having at least one robot 925 positioned therein. The at least one robot 925 is also referred to as a robotic wafer transfer mechanism. The first transfer chamber 921 is centrally positioned with respect to load-locking chambers 960, 962, processing chambers 902, 904, 916, 918, and buffer chambers 922, 924. In some embodiments, the at least one robot 925 is a multi-armed robot capable of independently moving more than one wafer at a time. In some embodiments, the first transfer chamber 921 includes more than one robotic wafer transfer mechanism. The at least one robot 925 in the first transfer chamber 921 is configured to move wafers between chambers surrounding the first transfer chamber 921. Individual wafers are carried on wafer transport blades located at the far end of the first robotic mechanism.

[0118] After the wafer is processed in the first section 920, it can be transferred to the second section 930 via a through-cavity. For example, cavities 922 and 924 can be unidirectional or bidirectional through-cavities. Through-cavities 922 and 924 can be used, for example, to cryogenically cool the wafer before processing in the second section 930 or to allow for wafer cooling or post-processing before moving back to the first section 920.

[0119] The system controller 990 communicates with the first robot 925, the second robot 935, the first plurality of processing chambers 902, 904, 916, 918, and the second plurality of processing chambers 906, 908, 910, 912, 914. The system controller 990 can be any suitable component capable of controlling the processing chambers and robots. For example, the system controller 990 can be a computer, including a central processing unit, memory, suitable circuitry, and storage.

[0120] The processing can typically be stored as a software routine in the memory of the system controller 990. When the software routine is executed by the processor, it causes the processing chamber to perform the processing of the present invention. The software routine can also be stored and / or executed by a second processor (not shown), which is remote from the hardware controlled by the processor. Some or all of the methods of the present invention can also be executed in hardware. Thus, the processing can be implemented in software and in hardware using a computer system, such as, for example, an application-specific integrated circuit or other type of hardware implementation, or as a combination of software and hardware. When executed by the processor, the software routine transforms a general-purpose computer into a dedicated computer (controller) that controls the operation of the chamber, causing the processing to be executed.

[0121] In some embodiments, the system controller 990 is configured to control a selective deposition chamber to selectively deposit a silicon-containing dielectric layer in the source / drain regions at temperatures less than 500 °C. In some embodiments, the system controller 990 is configured to activate a plasma processing chamber to expose the silicon-containing dielectric layer for heat treatment at temperatures greater than 800 °C to provide a densified silicon-containing dielectric layer, having a wet etch rate of less than 4 Å / min.

[0122] In one or more embodiments, the processing tool includes: a central transport station containing a robot configured to move a wafer; a plurality of processing stations, each connected to the central transport station and providing a processing area separate from the processing of adjacent processing stations, the plurality of processing stations including one or more of a pre-cleaning chamber, an inhibitor immersion chamber, a selective deposition chamber, a densification chamber, and an oxide chamber; and a controller connected to the central transport station and the plurality of processing stations, the controller being configured to activate the robot to move the wafer between the processing stations and to control the processing occurring in each processing station. In one or more embodiments, the controller causes the processing tool to perform the following operations: pre-cleaning the surface of an oxide pad on a substrate having source / drain regions; exposing the oxide pad to growth inhibitors; selectively depositing a silicon-containing dielectric layer in the source / drain regions of the substrate; and densifying the silicon-containing dielectric layer. The processing tool is maintained under vacuum.

[0123] Spatial relative terms such as “below,” “under,” “lower,” “above,” “above,” and similar expressions are used herein to simplify descriptions of the relationship between one element and another, as illustrated in the figures. It will be understood that spatial relative terms are intended to cover different orientations of a device (such as a semiconductor device) in use or operation, other than those depicted in the figures. For example, if the device in the figures is inverted, an element described as “below” or “under” other elements or features will be oriented “above” those elements or features. Thus, the exemplary term “below” can encompass both above and below orientations. Devices may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial relative descriptors used herein will be interpreted accordingly.

[0124] The use of the terms “a” and “an” and “the” and similar indicative terms in the context of describing the materials and methods discussed herein (particularly in the context of the following claims) is intended to constructively cover both the singular and plural, unless otherwise specified herein or clearly contradicted by the context. Numerical ranges mentioned herein are intended only as shorthand for each separate numerical value falling within these ranges individually, and each separate numerical value is incorporated into this specification as if individually mentioned herein, unless otherwise specified herein. All methods described herein may be performed in any suitable order, unless otherwise specified herein or clearly contradicted by the context. The use of any and all example or exemplary language (e.g., “such as”) provided herein is intended only to better illustrate the materials and methods and does not impose any limitation on the scope, unless otherwise stated. No language in this specification should be construed as indicating that any non-declared element is necessary for the implementation of the disclosed materials and methods.

[0125] Throughout this specification, the references to "one embodiment," "some embodiments," "one or more embodiments," "some embodiments," or "an embodiment" indicate that a particular element, structure, material, or characteristic described with respect to that embodiment is included in at least one embodiment of the invention. Therefore, examples of phrases such as "in one or more embodiments," "in some embodiments," "in one embodiment," "in some embodiments," or "in an embodiment" appearing in various places throughout this specification do not necessarily refer to the same embodiment of the invention. In one or more embodiments, the particular elements, structures, materials, or characteristics may be combined in any suitable manner.

Claims

1. A method for forming a logic or memory device, the method comprising: Selectively deposit a silicon-containing dielectric layer in the source / drain recesses on the substrate and through openings in the oxide pads within the source / drain recesses; and The silicon-containing dielectric layer is densified.

2. The processing method of claim 1, further comprising: exposing the oxide pad to a growth inhibitor before selectively depositing the silicon-containing dielectric layer.

3. The processing method of claim 1, wherein the processing method is performed in a processing tool without breaking the vacuum, and wherein the processing tool is selected from the group consisting of a single processing chamber and a batch processing chamber.

4. The processing method of claim 1, wherein densifying the silicon-containing dielectric layer forms a densified silicon-containing dielectric layer having a density gradient.

5. The processing method of claim 1, wherein the silicon-containing dielectric layer comprises one or more of silicon nitride (SiN), silicon carbonitride (SiCN), silicon oxynitride, silicon oxycarbonitride (SiOCN), silicon boride (SiB), and silicon boronitride (SiBN).

6. The processing method of claim 1, wherein the superlattice structure is adjacent to the source / drain recess on the substrate, the superlattice structure having a plurality of first layers and corresponding plurality of second layers arranged alternately in a plurality of stacked pairs, the plurality of stacked pairs extending between the source / drain recesses on the substrate.

7. The processing method of claim 1, wherein the selective deposition of the silicon-containing dielectric layer comprises deposition at a temperature of less than 500 °C.

8. The processing method of claim 1, wherein the silicon-containing dielectric layer has a wet etching rate of less than 1 Å / min.

9. The processing method of claim 1, wherein densifying the silicon-containing dielectric layer comprises: exposing the silicon-containing dielectric layer to a rapid thermal processing (RTP) process.

10. The processing method of claim 1, wherein densifying the silicon-containing dielectric layer comprises: exposing the silicon-containing dielectric layer to a high-density plasma at a temperature less than or equal to 500 °C and a pressure less than 1 Torr, said high-density plasma being selected from one or more of nitrogen (N), helium (He), hydrogen (H2), neon (Ne), argon (Ar), krypton (Kr), and xenon (Xe).

11. The processing method of claim 1, wherein the silicon-containing dielectric layer has a thickness ranging from greater than 0 Å to 200 Å.

12. The processing method of claim 1, further comprising: pre-cleaning the surface of the oxide pad within the source / drain recess on the substrate before selectively depositing the silicon-containing dielectric layer.

13. A processing tool, the processing tool comprising: A central transfer station, comprising robots configured to move the chip; Multiple processing stations, each connected to the central transfer station and providing a processing area separate from adjacent processing stations, the multiple processing stations comprising one or more of a pre-cleaning chamber, an inhibitor soaking chamber, a selective deposition chamber, and a densification chamber; and A controller, connected to the central transfer station and the plurality of processing stations, is configured to activate the robot to move the wafer between the processing stations and to cause the processing tool to perform the following operations: Selectively deposit a silicon-containing dielectric layer in the source / drain recesses on the substrate and through openings in the oxide pads within the source / drain recesses; and The silicon-containing dielectric layer is densified.

14. The processing tool of claim 13, wherein the controller is configured to cause the processing tool to perform one or more of the following further operations: Before selectively depositing the silicon-containing dielectric layer: Pre-clean the surface of the oxide pads within the source / drain recesses on the substrate; and The oxide liner was exposed to growth inhibitors.

15. A method of forming a gate-all-around device, the method comprising: An oxide pad is formed on the sidewall surface of the superlattice structure and on the bottom surface of the source / drain recess of the superlattice structure on an adjacent substrate. The superlattice structure includes a plurality of first layers and a corresponding plurality of second layers arranged alternately in a plurality of stacked pairs, the plurality of stacked pairs extending between the source / drain recesses. Remove a portion of the oxide pad from the bottom surface of the source / drain recess; A silicon-containing dielectric layer is selectively deposited in the source / drain recess and in the openings of the oxide pads passing through the source / drain recess; and The silicon-containing dielectric layer is densified.

16. The method of claim 15, further comprising: pre-cleaning the sidewall surface of the oxide pad and exposing the oxide pad to one or more growth inhibitors prior to selectively depositing the silicon-containing dielectric layer.

17. The method of claim 15, wherein densifying the silicon-containing dielectric layer forms a densified silicon-containing dielectric layer having a density gradient.

18. The method of claim 15, wherein the selective deposition of the silicon-containing dielectric layer comprises deposition at a temperature of less than 500 °C.

19. The method of claim 15, wherein densifying the silicon-containing dielectric layer comprises exposing the silicon-containing dielectric layer to a rapid thermal processing (RTP) process.

20. The method of claim 15, wherein densifying the silicon-containing dielectric layer comprises: exposing the silicon-containing dielectric layer to a high-density plasma at a temperature less than or equal to 500 °C and a pressure less than 1 Torr, said high-density plasma being selected from one or more of nitrogen (N), helium (He), hydrogen (H2), neon (Ne), argon (Ar), krypton (Kr), and xenon (Xe).

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