Semiconductor device comprising a compound semiconductor material having superlattice layers

Abstract

A semiconductor device can include a semiconductor substrate and a superlattice layer on the semiconductor substrate. The superlattice layer can include a plurality of stacked groups of layers, where each group of layers includes a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of the adjacent base semiconductor portions. The semiconductor device can also include a III-N semiconductor stack including a plurality of III-N semiconductor layers over the superlattice layer.

Description

Technical Field

[0001] This disclosure generally relates to semiconductor devices, and more specifically, to semiconductor devices having enhanced semiconductor materials and associated methods. Background Technology

[0002] Structures and techniques have been proposed to enhance the performance of semiconductor devices, such as by improving charge carrier mobility. For example, U.S. Patent Application No. 2003 / 0057416 by Currie et al. discloses a strained material layer of silicon, silicon-germanium, and relaxable silicon, including impurity-free zones (which would otherwise cause performance degradation). The biaxial strain generated in the upper silicon layer alters the carrier mobility, thereby enabling devices with higher speeds and / or lower power. Published U.S. Patent Application No. 2003 / 0034529 by Fitzgerald et al. discloses a CMOS inverter also based on a similar strained silicon technique.

[0003] Takagi's U.S. Patent No. 6,472,685 B2 discloses a semiconductor device comprising a silicon-carbon layer sandwiched between silicon layers, such that the conduction band and valence band of the second silicon layer are subjected to tensile strain. Electrons with smaller effective mass and already confined within the second silicon layer by the electric field applied to the gate electrode are thus asserted to have higher mobility for the n-channel MOSFET.

[0004] U.S. Patent No. 4,937,204 to Ishibashi et al. discloses a superlattice in which fewer than eight monolayers are epitaxially grown alternately and comprising multiple layers including fractional, binary, or binary compound semiconductor layers. The direction of the main current flow is perpendicular to the layers of the superlattice.

[0005] U.S. Patent No. 5,357,119 to Wang et al. discloses a Si-Ge short-period superlattice with higher mobility achieved by reducing alloy scattering in the superlattice. Following these ideas, U.S. Patent No. 5,683,934 to Candelaria discloses a mobility-enhanced MOSFET comprising a channel layer comprising silicon and an alloy of a second material present in the silicon lattice in a percentage that places the channel layer under tensile stress.

[0006] Tsu's U.S. Patent No. 5,216,262 discloses a quantum well structure comprising two barrier regions and a thin epitaxially grown semiconductor layer sandwiched between the barriers. Each barrier region comprises alternating SiO2 / Si layers, typically ranging in thickness from two to six monolayers. A much thicker silicon portion is sandwiched between the barrier layers.

[0007] A paper titled "Phenomena in silicon nanostructure devices," published online on September 6, 2000, in Applied Physics and Materials Science & Processing (pp. 391-402) by Tsu, discloses a silicon / oxygen semiconductor atomic superlattice (SAS). The Si / O superlattice is disclosed as useful in silicon quantum and light-emitting devices. Specifically, a green electroluminescent diode structure was constructed and tested. Current flow in the diode structure is vertical, i.e., perpendicular to the layers of the SAS. The disclosed SAS can comprise semiconductor layers separated by adsorbed materials such as oxygen atoms and CO molecules. The growth of silicon beyond the adsorbed monolayer of oxygen is described as epitaxy with a considerably low defect density. One SAS structure includes a 1.1 nm thick silicon portion, approximately eight atomic layers of silicon, while another structure has a silicon thickness twice that of the 1.1 nm thick silicon portion. The article titled “Chemical Design of Direct-Gap Light-Emitting Silicon” by Luo et al., published in Physical Review Letters, Volume 89, Issue 7 (August 12, 2002), further discusses Tsu’s luminescent SAS structure.

[0008] U.S. Patent No. 7,105,895 to Wang et al. discloses a thin silicon barrier building block with oxygen, carbon, nitrogen, phosphorus, antimony, arsenic, or hydrogen, thereby reducing the current flowing vertically through the lattice by more than four orders of magnitude. The insulating / barrier layer allows for the deposition of low-defect epitaxial silicon adjacent to the insulating layer.

[0009] UK patent application 2,347,520 published by Mears et al. discloses that the principles of aperiodic photonic bandgap (APBG) structures can be applied to electronic bandgap engineering. Specifically, the application discloses that material parameters (e.g., the location of band minimums, effective mass, etc.) can be adjusted to produce novel aperiodic materials with desired bandgap structure properties. Other parameters (such as electrical conductivity, thermal conductivity, and dielectric constant or magnetic permeability) are disclosed as also being designed into the material.

[0010] Furthermore, U.S. Patent No. 6,376,337 to Wang et al. discloses a method for producing an insulating or barrier layer for semiconductor devices, which includes depositing a silicon layer and at least one additional element on a silicon substrate, thereby creating a substantially defect-free deposited layer that allows for the deposition of substantially defect-free epitaxial silicon on the deposited layer. Alternatively, a monolayer of one or more elements (preferably containing oxygen) is adsorbed onto the silicon substrate. Multiple insulating layers sandwiched between the epitaxial silicon layers form a barrier composite.

[0011] Despite the existence of such solutions, further enhancements may be expected in terms of using advanced semiconductor materials and processing technologies to improve the performance of semiconductor devices. Summary of the Invention

[0012] A semiconductor device may include a semiconductor substrate and a superlattice layer on the semiconductor substrate. The superlattice layer may include multiple stacked layers, each layer comprising multiple stacked base semiconductor monolayers defining base semiconductor portions, and at least one non-semiconductor monolayer constrained within a crystal lattice of an adjacent base semiconductor portion. The semiconductor device may also include a III-N semiconductor stack comprising multiple III-N semiconductor layers located above the superlattice layer.

[0013] In an example implementation, the III-N semiconductor stack may include a III-N semiconductor nucleation layer adjacent to the superlattice layer, a III-N semiconductor transition layer adjacent to the III-N semiconductor nucleation layer, at least one III-N semiconductor buffer layer adjacent to the III-N semiconductor transition layer, a III-N semiconductor spacer layer adjacent to the at least one III-N semiconductor buffer layer, and a III-N semiconductor barrier layer adjacent to the III-N semiconductor spacer layer. For example, the III-N semiconductor nucleation layer may include AlN, the III-N semiconductor transition layer may include at least one of AlN, GaN, or AlGaN, the at least one III-N semiconductor buffer layer may include GaN, the III-N semiconductor spacer layer may include AlN, and the III-N semiconductor barrier layer may include AlGaN.

[0014] In some embodiments, the semiconductor substrate may include a monocrystalline silicon substrate having a (111) orientation and an offset angle of 0.5° or less. Similarly, for example, the base semiconductor monolayer may include silicon, and at least one non-semiconductor monolayer may include oxygen and / or carbon.

[0015] The method is for manufacturing semiconductor devices, and the method may include forming a superlattice layer comprising multiple stacked layers on a semiconductor substrate. Each layer group may include multiple stacked basic semiconductor monolayers defining basic semiconductor portions, and at least one non-semiconductor monolayer constrained within a crystal lattice of an adjacent basic semiconductor portion. The method may also include forming a III-N semiconductor stack above the superlattice layer, the III-N semiconductor stack comprising multiple III-N semiconductor layers.

[0016] In an example implementation, forming a III-N semiconductor stack may include forming a III-N semiconductor nucleation layer adjacent to a superlattice layer, forming a III-N semiconductor transition layer adjacent to the III-N semiconductor nucleation layer, forming at least one III-N semiconductor buffer layer adjacent to the III-N semiconductor transition layer, forming a III-N semiconductor spacer layer adjacent to the at least one III-N semiconductor buffer layer, and forming a III-N semiconductor barrier layer adjacent to the III-N semiconductor spacer layer.

[0017] For example, the III-N semiconductor nucleation layer may include AlN, the III-N semiconductor transition layer may include at least one of AlN, GaN and AlGaN, the at least one III-N semiconductor buffer layer may include GaN, the III-N semiconductor spacer layer may include AlN, and the III-N semiconductor barrier layer may include AlGaN.

[0018] In an example embodiment, the semiconductor substrate may include a monocrystalline silicon substrate having a (111) orientation and an offset angle of 0.5° or less. For example, the base semiconductor monolayer may include silicon, and at least one non-semiconductor monolayer may include oxygen and / or carbon. Attached Figure Description

[0019] Figure 1 This is a greatly enlarged schematic cross-sectional view of a superlattice used in a semiconductor device according to an example embodiment.

[0020] Figure 2 yes Figure 1 A perspective schematic atomic diagram of a portion of the superlattice shown.

[0021] Figure 3 This is a greatly enlarged schematic cross-sectional view of another embodiment of the superlattice according to the example embodiment.

[0022] Figure 4 This is a schematic cross-sectional view of a semiconductor device comprising a III-N group semiconductor stack and a superlattice layer, which provides advantages in an example embodiment.

[0023] Figure 5 This is a schematic cross-sectional view of another semiconductor device comprising a III-N group semiconductor stack and a superlattice layer, providing enhanced stress / strain control in an example embodiment.

[0024] Figure 6 According to the example embodiment Figure 4 A schematic cross-sectional view of III-N group semiconductors stacked at a superlattice layer separated from the Si (111) substrate to couple to a second substrate.

[0025] Figure 7 It is a diagram manufacturing process. Figure 4-6 A flowchart of an embodiment of the method.

[0026] Figure 8 and Figure 9 This is a schematic cross-sectional view of an example piezoelectric device, which includes a III-N group piezoelectric layer located on a superlattice layer.

[0027] Figure 10 The illustration is for manufacturing. Figure 8 and Figure 9 A flowchart of an example method for piezoelectric devices.

[0028] Figure 11 This is a schematic cross-sectional view of a semiconductor device according to an example embodiment, including III-N group and Si circuit regions located above a superlattice.

[0029] Figure 12 The illustration shows a manufacturing process in an example embodiment. Figure 11 The flowchart of the method for developing semiconductor devices. Detailed Implementation

[0030] Example embodiments will now be described more fully below with reference to the accompanying drawings, in which example embodiments are illustrated. However, embodiments may be implemented in many different forms and should not be construed as limited to the specific examples set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete. The same reference numerals denote the same elements throughout, and apostrophes are used in different embodiments to denote similar elements.

[0031] Generally, this disclosure relates to semiconductor devices having an enhanced semiconductor superlattice therein to provide performance-enhancing characteristics. In this disclosure, the enhanced semiconductor superlattice may also be referred to as an "MST" layer or "MST technology".

[0032] More specifically, MST technology involves advanced semiconductor materials, such as superlattices 25 described further below. In previous work, the applicant theoretically argued that certain superlattices, as described herein, reduce the effective mass of charge carriers, and thus lead to higher charge carrier mobility. See, for example, U.S. Patent No. 6,897,472, which is hereby incorporated herein by reference in its entirety.

[0033] Further development by the applicant has determined that the presence of an MST layer can advantageously improve the mobility of free carriers in semiconductor materials, such as at the interface between silicon and an insulator (e.g., SiO2 or HfO2). The applicant theoretically believes (but does not wish to be limited to) that this is likely due to various mechanisms. One mechanism is by reducing the concentration of charged impurities near the interface, by reducing the diffusion of these impurities, and / or by trapping impurities so that they do not reach the vicinity of the interface. Charged impurities cause Coulomb scattering, which reduces mobility. Another mechanism is by improving the quality of the interface. For example, oxygen emitted from the MST film can provide oxygen to the Si-SiO2 interface, thereby reducing substoichiometric SiO2. x The presence of interstitials. Alternatively, the trapping of interstitials by the MST layer can reduce the concentration of interstitial silicon near the Si-SiO2 interface, thereby reducing the formation of substoichiometric SiO2. x The trend. The substoichiometric SiO₂ at the Si-SiO₂ interface is known. x Compared to stoichiometry, SiO2 exhibits poor insulating properties. Reducing the substoichiometric SiO2 at the interface... x The amount of [material] more effectively confines free carriers (electrons or holes) within silicon, thereby improving the mobility of these carriers by means of an electric field applied parallel to the interface, as is standard practice in field-effect transistor (“FET”) structures. Scattering caused by the direct influence of the interface is called “surface roughness scattering,” which can be advantageously reduced by proximity to the MST layer and subsequent annealing or during thermal oxidation.

[0034] In addition to the enhanced mobility properties of the MST structures, they can also be formed or used in a manner that provides piezoelectric, pyroelectric, and / or ferroelectric properties that are advantageous for use in a wide variety of device types, as further discussed in U.S. Patent No. 7,517,702, which is hereby incorporated herein by reference in its entirety.

[0035] Now for reference Figure 1 and Figure 2 The material or structure is in the form of a superlattice 25, the structure of which is controlled at the atomic or molecular level and can be formed using known techniques of atomic or molecular layer deposition. The superlattice 25 comprises multiple layers 45a-45n arranged in a stacked relationship, as detailed in the specific reference. Figure 1 A schematic cross-sectional view is best used to understand this.

[0036] Each layer group 45a-45n of the superlattice 25 illustratively includes a plurality of stacked base semiconductor monolayers 46 defining corresponding base semiconductor portions 46a-46n and one or more non-semiconductor monolayers 50 thereon. For clarity, the non-semiconductor monolayers 50 are... Figure 1 Dots are used to indicate the direction.

[0037] The non-semiconductor monolayer 50 illustratively includes a non-semiconductor monolayer confined within the crystal lattice of an adjacent base semiconductor portion. "Confined within the crystal lattice of an adjacent base semiconductor portion" means that at least some semiconductor atoms from the opposing base semiconductor portions 46a-46n are chemically bonded together through the non-semiconductor monolayer 50 therebetween. Figure 2 As seen in [the diagram]. Generally, this configuration is made possible by controlling the amount of non-semiconductor material deposited on the semiconductor portions 46a-46n using atomic layer deposition techniques, such that not all (i.e., less than all or 100% coverage) of the available semiconductor bonding sites are occupied by bonds with non-semiconductor atoms, as will be discussed further below. Therefore, when another monolayer 46 of semiconductor material is deposited on or above the non-semiconductor monolayer 50, the newly deposited semiconductor atoms will occupy the remaining empty bonding sites of the semiconductor atoms below the non-semiconductor monolayer.

[0038] In other embodiments, more than one such non-semiconductor monolayer may be possible. It should be noted that references herein to non-semiconductor or semiconductor monolayers refer to the material used for the monolayer being either non-semiconductor or semiconductor if formed in bulk. That is, as those skilled in the art will recognize, a single monolayer of a material (such as silicon) does not necessarily exhibit the same properties as when formed in bulk or as a relatively thick layer.

[0039] Furthermore, this superlattice structure can advantageously act as a barrier to dopant and / or material diffusion between layers vertically above and below the superlattice 25. These properties can therefore advantageously allow the superlattice 25 to provide an interface for a high-k dielectric in one example embodiment, which not only reduces the diffusion of high-k material into the channel region but also advantageously reduces unwanted scattering effects and improves device mobility, as those skilled in the art will recognize.

[0040] The superlattice 25 also illustratively includes a capping layer 52 on the upper group 45n. The capping layer 52 may include a plurality of base semiconductor monolayers 46. The capping layer 52 may have between 2 and 100 monolayers of base semiconductors, and more preferably between 10 and 50 monolayers.

[0041] Each base semiconductor portion 46a-46n may include a base semiconductor selected from the group consisting of group IV semiconductors, group III-V semiconductors, and group II-VI semiconductors. Of course, as those skilled in the art will recognize, the term "group IV semiconductor" also includes group IV-IV semiconductors. More specifically, for example, the base semiconductor may include at least one of silicon and germanium.

[0042] Each non-semiconductor monolayer 50 may comprise, for example, a non-semiconductor selected from the group consisting of oxygen, nitrogen, fluorine, carbon, and carbon-oxygen. It is also desirable for the non-semiconductor to remain thermally stable during the deposition of the next layer, thereby facilitating fabrication. In other embodiments, the non-semiconductor may be another inorganic or organic element or compound compatible with a given semiconductor process, as will be recognized by those skilled in the art.

[0043] It should be noted that the term "monolayer" means including both a single atomic layer and a single molecular layer. It should also be noted that a non-semiconductor monolayer 50 provided by a single monolayer also means including monolayers in which not all possible sites are occupied (i.e., less than full or 100% coverage). For example, see special reference. Figure 2 The atomic diagram illustrates a 4 / 1 repeating structure with silicon as the base semiconductor material and oxygen as the band modifier. In the example shown, only half of the possible sites for oxygen are occupied.

[0044] In other embodiments and / or with different materials, as those skilled in the art will recognize, this half-occupancy will not necessarily be the case. Indeed, even in this schematic diagram, it can be seen that the individual oxygen atoms in a given monolayer are not precisely aligned along a flat plane, as those skilled in the art of atomic deposition will recognize. For example, the preferred occupied range is approximately one-eighth to one-half of all possible oxygen sites, but other amounts may be used in some embodiments.

[0045] Silicon and oxygen are currently widely used in conventional semiconductor processing; therefore, manufacturers will be able to readily use these materials described herein. Atomic deposition or monolayer deposition is also now widely used. Consequently, as those skilled in the art will recognize, semiconductor devices incorporating the superlattice 25 according to the invention can be readily adopted and implemented.

[0046] Now, additional references Figure 3Now, another embodiment of the superlattice 25' according to the invention, which has different properties, is described. In this embodiment, a repeating pattern of 3 / 1 / 5 / 1 is illustrated. More specifically, the lowest basic semiconductor portion 46a' has three monolayers, and the second lowest basic semiconductor portion 46b' has five monolayers. This pattern is repeated throughout the superlattice 25'. The non-semiconductor monolayers 50' may each comprise a single monolayer. For this superlattice 25' comprising Si / O, the enhancement of charge carrier mobility is independent of the orientation of the layers in the plane. Figure 3 Other components not specifically mentioned above are related to the above references. Figure 1 The components discussed are similar and need not be discussed further here.

[0047] In some device embodiments, all the base semiconductor portions of the superlattice can be the same number of monolayers thick. In other embodiments, at least some of the base semiconductor portions can be of different numbers of monolayers thick.

[0048] Turn now Figures 4 to 6 Example embodiments are provided in which one or more of the aforementioned MST films are integrated into III-N semiconductor (e.g., GaN and AlN) devices to provide fabrication and / or performance benefits superior to conventional III-N semiconductor devices. As background, various approaches are used to fabricate III-N structures on silicon substrates, such as for high-power, high-frequency, and high-temperature applications. For example, these structures can be used in RF transistors, power transistors, piezoelectric sensors, and optoelectronic devices (e.g., LEDs, micro-LEDs, lasers, optical detectors, etc.), as will be discussed further below. However, due to material variations, such approaches may be subject to excessive stress and / or bending.

[0049] Figure 4 The semiconductor device 100 shown illustratively includes an MST film 125 on a substrate 101 to provide mechanical compliance for stress management. More specifically, in the illustrated example, the MST film 125 is utilized more to provide a mechanical interface between the Si(111) substrate and the overlying III-N layer stack 102, rather than the enhanced electrical behavior of the MST film described above. More specifically, the applicant theoretically believes (but does not wish to be limited thereto) that the MST film 125 interface will advantageously provide less stress in the overlying nitride film, resulting in less wafer curvature (warpage / bending), which in turn advantageously allows for the growth of a thicker GaN layer.

[0050] Above the AlN nucleation layer 103 is a transition layer 104. Most typically, such a transition layer is a gradient AlGaN layer as shown, or a superlattice of alternating semiconductor materials may also be used. Above the transition layer 104 is a first GaN buffer layer 105, which is typically doped with, for example, C or Fe to improve breakdown.

[0051] The nucleation layer 103, transition layer 104, and first GaN buffer layer 105 are important for stress management. In the case of electronic devices such as transistors, the thickness of the transition layer 104 and the first GaN buffer layer 105 is typically voltage-dependent (higher voltage = thicker epitaxy = more difficult). For example, for RF and microwave applications (e.g., at operating voltages < 200 V and operating frequencies > 100 MHz), their combined thickness can be on the order of approximately ~1.5 micrometers (µm), and for power electronics applications (e.g., at operating frequencies < 10 MHz), they can be on the order of approximately ~4-6 µm.

[0052] The second GaN buffer layer 106 is located above the first GaN buffer layer 105, and it is typically undoped to promote the desired two-dimensional electron gas (2DEG) transport properties. Above the second GaN buffer layer 106 is a barrier layer 107 (here, AlGaN), which is the primary driver of on-state characteristics (drain current, pinch-off voltage, etc.). In the illustrated configuration, an AlN spacer layer 108, a GaN capping layer 109, and a SiNx capping layer are also provided, but these layers are optional. The AlN spacer layer 108 may be included to help enhance transport properties. The GaN capping layer 109 can help reduce leakage current and / or customize surface properties, and the SiNx capping layer 110 can help passivate the surface.

[0053] The example also shows a 2DEG layer 112, which is an electronic sheet located below the interface between the AlN spacer layer 108 or the AlGaN barrier 107 and the second GaN buffer layer 106. It should be noted that the 2DEG layer 112 is not grown like the other layers in the stack 102, but rather is a result of the layer design. The 2DEG layer 112 carries current during device operation.

[0054] In the illustrated embodiment, an MST layer 125 is grown on a Si (111) substrate 101, followed by the growth of a capping layer 152. Generally, the capping layer 152 will be relatively small, allowing the MST film 125 to be close to the overlying layer (here, the AlN nucleation layer 103) to provide maximum stress relief. For example, the capping layer 152 may have a thickness in the range of 3-5 nm, but other thicknesses may be used in different embodiments. In addition to the lattice mismatch between Si (111) and AlN, there is also a lattice mismatch between AlN and GaN, where AlN has a slightly smaller lattice. The MST film 125 can advantageously mitigate the stress caused by both of these mismatches.

[0055] Different variations of the MST film 125 can also be used, such as having oxygen (MST-O) or carbon (MST-C) as a non-semiconductor material (or a combination of both in some instances). Other variations may include the number of layers / thickness, layer configuration (e.g., 3 / 1 / 5 / 1, 4 / 1, etc.), and the depth of the MST layer 125 in the substrate, which is determined by the thickness of the capping layer 152.

[0056] In this regard, Figure 5 Another example semiconductor device 100' is provided, in which an MST-C layer 125' is positioned directly adjacent to an AlN nucleation layer 103' on top of a substrate 101'. That is, this configuration integrates an MST-C film 125' (e.g., an MST film comprising a silicon monolayer 46 and a carbon non-semiconductor monolayer 50) designed to place a large amount of C within the Si substrate 101', and more specifically, very close to the surface (and possibly without a capping layer). The applicant theoretically believes (but does not wish to be limited thereto) that this could advantageously transform the surface of substrate 101' into a "SiC-like" substrate, meaning it provides the benefits of SiC (a wide-bandgap semiconductor material that offers better lattice matching than Si with GaN) without the high costs associated with fabricating a complete SiC substrate. Since the MST-C film 125' exhibits properties similar to SiC, it can also enhance thermal conductivity, as those skilled in the art will recognize, in addition to providing improved lattice matching.

[0057] For this application, a layering scheme similar to those discussed above can be used to grow the MST-C film 125', and different annealing temperatures can be used to provide different SiC "signatures". That is, the MST-C film 125' is not bulk SiC, but the applicant theoretically believes that it will exhibit bulk SiC characteristics sufficient to achieve the aforementioned benefits of improved lattice matching and thermal conductivity relative to silicon substrates.

[0058] This approach may be particularly advantageous because it overcomes the difficulties of previous attempts to grow epitaxial SiC on silicon, such as nucleation and registration. Although the mismatch in the evolution of the growth / defect structure is reduced when GaN is grown over the MST-C film 125', the AlN nucleation layer 103' can still be used (although it may be omitted in some configurations). Further details regarding the integration of a carbon monolayer within the MST film are set forth in U.S. Patent No. 11,837,634 to Weeks et al., which is assigned to the applicant and is hereby incorporated herein by reference in its entirety.

[0059] In some embodiments, device 100 (or 100') can be used in RF applications, where an MST film 100 is used to reduce parasitic channel effects. As background, during GaN nucleation growth on a silicon substrate, diffusion of group III materials into the substrate occurs. This forms a P-type region in substrate 101, which results in parasitic channels. Since the MST film 125 affects the dopant diffusion distribution and helps terminate diffusion tails into Si, positioning the MST film 125 relatively close to the surface of substrate 101 can similarly suppress dopant diffusion into the substrate beneath the MST film. In the case of RF devices, this can advantageously provide improved power and efficiency and reduce microwave losses, for example.

[0060] Previous approaches to suppressing this diffusion involved lowering the processing temperature. However, this can lead to other problems, particularly in stress management. However, the present approach, with the integrated MST film 125 as shown, allows for the reduction of parasitic channels while also allowing fabrication at higher desired temperatures for enhanced stress management. Furthermore, in some embodiments, the MST film 125 can also allow for the localization of reverse charges (dopants) to counteract any potential dopants that might otherwise propagate down from above, as those skilled in the art will recognize.

[0061] In some embodiments, an integrated nitrogen-containing MST film 125 may be used to provide beneficial effects with respect to the AlN nucleation layer 103. More specifically, the applicant theoretically believes (but does not wish to be limited thereto) that the nitrogen-containing MST film 125 can reduce the level of complexity by using the same material (N) as in the top (AlN) nucleation layer 103. Moreover, in some configurations, the SiN barrier between the substrate and the nucleation layer 103 can also help reduce Al migration.

[0062] Turn now Figure 6In some embodiments, the MST film 125 can be used as a self-separating layer to advantageously enable the peeling off of the III-N epitaxial stack 102. More specifically, if the MST film 125 is close to the surface of the Si substrate 101, then the MST film can be used as a separation layer (by definition, a layer with reduced mechanical strength) to cleave or remove the layer above the MST film from the underlying substrate 101. This can be done mechanically, as those skilled in the art will recognize. This approach offers technical advantages because if the capping layer 152 is used little or no, then all the material above the MST separation layer 125 is III-N and can be relatively easily bonded to the second substrate 113, such as a heat sink (e.g., for power devices), a sapphire substrate (e.g., for optical devices), or in some cases, can be used with both ends exposed (e.g., for front and back transfers).

[0063] For use as a separation layer, in some embodiments, the MST film 125 may have a higher concentration of non-semiconductor atoms than, for example, those used in other ways for applications to enhance conductivity. In other words, in the case of the MST-O layer 125 (Si / O), the MST layer can more closely approximate an oxide layer and exhibit fewer bulk silicon characteristics, as those skilled in the art will recognize. Oxygen-based MST films allow H to segregate near oxygen, which can help weaken bonds and reduce strength. Therefore, in some embodiments, H can be introduced into the stack to reduce the strength of the MST layer 125, thereby making it a separation layer.

[0064] For applications such as micro-LEDs, the "stripped" III-N stack can be bonded to a pre-patterned, finished CMOS digital wafer and interconnected through III-materials to produce LED displays, as those skilled in the art will recognize. Examples of nitrides that can be used above the separation layer for various applications include AlN, GaN, InN, ScN, and alloys thereof.

[0065] It should be noted that the MST layer 125 can be used with a variety of different (111) wafer configurations, including both axial and off-axis wafers. For many applications, silicon (111) wafers have an off-axis angle of about 4°, while typical GaN device implementations utilize axial (no off-axis, 0°) silicon (111) wafers. The applicant theoretically believes (but does not wish to be limited thereto) that the MST film can advantageously provide stress relief on a relatively wide range of wafers, including axial (111) wafers and 4° off-axis (111) wafers. In some embodiments, to minimize the lattice mismatch between Si (111) and AlN, for example, it may be desirable to use axial (111) wafers, or off-axis wafers with an off-axis angle of about 0.5° or less. Again, by way of example, the thickness of the MST film 125 can be up to about 100 nm, and more specifically in the range of about 20 nm to 100 nm.

[0066] The illustrated structure 100 is for use in electronic devices; however, those skilled in the art will recognize that many other embodiments are possible and included within the scope of this disclosure, including different configurations of the top IIIA / B group material for fabricating different types of circuits. Utilizing these various device configurations, the integration of the MST film 125 interface can advantageously provide less final wafer warpage compared to conventional devices without this interface. In addition to producing a mechanically compliant layer that improves stress / strain control in GaN epitaxy, the MST layer 125 can also provide other technical advantages, including: the ability to use a SEMI standard substrate instead of thicker silicon; the ability to grow thinner epitaxial stacks (improved reactor throughput); and improved III-N crystal quality.

[0067] Additional reference Figure 7 Flowchart 170 shows that the method for manufacturing the above-described structure begins at block 171. At block 172, a superlattice 125 is formed on substrate 101 (or 125' in the case of device 100'). At block 173, a III-N group stack 102 can then be formed on the superlattice 125 / capping layer 152. As described above, in some embodiments, at block 174, the GaN stack 102 may optionally be separated from substrate 101 and bonded to a second substrate 113 (block 175), or used with both ends exposed. Figure 7 The method is explained illustratively at box 176.

[0068] Turn now Figures 8 to 9Example embodiments are provided in which MST films 225, 225' are advantageously integrated into piezoelectric devices or filters 200, 200'. The illustrated devices integrate MST films 225, 225' into a relatively shallow depth in substrates 201, 201' (e.g., Si(111) substrates) to provide stress management as described above. Again, the depth of capping layers 252, 252' can be varied as needed and may be omitted in some cases. In the same manner as described above, MST films 225, 225' advantageously enable the growth of high-quality (i.e., fewer defects) piezoelectric layers 214, 214' on substrates 201, 201'. In the illustrated example, piezoelectric layers 214, 214' are crystalline AlN filter materials, but various piezoelectric materials (including AlN, ScN, or alloys thereof) may be used in different embodiments.

[0069] Furthermore, the piezoelectric filters 200, 200' also include electrodes 215, 215' on the piezoelectric layers 214, 214', the electrodes being configured to induce acoustic waves along the surface of the piezoelectric layers to define a surface acoustic wave (SAW) filter. Figure 8 The piezoelectric layer is configured to induce acoustic waves within the piezoelectric layer to define a bulk acoustic wave (BAW) filter. Figure 9 Furthermore, the MST layers 225, 225' can also provide a reduction in wafer curvature (warpage and / or bending) after growth, as discussed further above.

[0070] Additional reference Figure 10 Flowchart 270, beginning at block 271, illustratively describes a method for manufacturing piezoelectric devices 200, 200', including: at block 272, forming superlattice layers 225, 225' (and optional capping layers 252, 252') on substrates 201, 201', followed by forming piezoelectric layers 214, 214' on / above the superlattice (block 273). For example, crystalline AlN or other suitable piezoelectric materials can be used. Furthermore, at block 274, electrodes 215, 215' (e.g., SAW or BAW) appropriately configured for the specific device are formed. Figure 10 The method is illustrated and ends at box 275.

[0071] Turn now Figure 11An example embodiment is provided in which an MST film is advantageously integrated into a CMOS / III-N hybrid device 300. As background, attempts have been made to implement GaN devices directly next to Si logic devices. However, such approaches typically cannot provide large-scale integration on a wafer. Part of the difficulty lies in the fact that CMOS device fabrication requires Si with a (100) orientation. However, as discussed above, this is undesirable for forming III-N materials. Instead, a first MST layer 325a (and optionally a capping layer 352a) is formed on a Si (111) handle wafer 301. A Si (100) active device layer 311 and a buried oxide (BOX) layer 303 are positioned over the MST film 325a and capping layer 352a above the handle wafer 301 for forming a SiCMOS circuit device 313. However, between the CMOS device regions, the Si (100) can be etched down into the Si (111) handle wafer 301. Within this window (trench), a III-N device layer 312 can be epitaxially grown, on which a second type of circuit device 314 can be formed to provide a hybrid circuit configuration. As further discussed above, the III-N device layer 312 can correspondingly have reduced stress.

[0072] In the illustrated example, a second MST layer 325b (and optional capping layer 352b) is provided beneath one or more of the CMOS circuit devices 313 to provide mobility enhancement and / or dopant distribution control features, as discussed further above. In some embodiments, the first MST layer 325a on the Si (111) carrier wafer 301 may comprise carbon (MST-C), also as discussed above. Generally, the carrier wafer 301 may experience relatively high temperature fluctuations, for which the MST-C film 325a may be particularly beneficial, as those skilled in the art will recognize.

[0073] In one example implementation, an example CMOS / III-group integration can be used in microprocessor circuit systems that typically require buck conversion to achieve a suitable low operating voltage. The example embodiment can advantageously allow this buck conversion to be performed locally where needed, which the applicant theoretically believes (but does not wish to be limited to) can provide significant energy savings in microprocessor applications. This approach can also be applied to other types of electronics (e.g., RF transistors, power transistors, etc.), piezoelectric sensors, and optoelectronic devices (e.g., LEDs, micro-LEDs, lasers, optical detectors, etc.).

[0074] The example configuration advantageously allows monolithic integration of Si CMOS devices 313 and III-N group (e.g., GaN) devices 314 on bonded SOI wafers with different Si crystal orientations. Other approaches may utilize cavity SOIs, etc., as those skilled in the art will recognize. Moreover, this approach combines the benefits of MST films for independent III-N epitaxial structures with the ability to leverage these benefits to improve heterogeneous integration (i.e., reduced stress and / or the ability to grow thinner films).

[0075] Turn now Figure 12 In flowchart 370, the method of fabricating a hybrid semiconductor device 300 begins at block 371, wherein an MST layer 325a (and optionally a capping layer 352a) is formed on a carrier wafer 301 (block 372). The method further illustratively includes: at block 373, forming a first Si device layer 311 (e.g., a Si (100) layer) on a superlattice 352a; and at block 374, forming a second device layer 312 on a superlattice laterally adjacent to the first device layer. The second device layer 312 comprises a III-N semiconductor (e.g., GaN, AlN, or a stack of III-N material layers as described above). The method also illustratively includes at blocks 375 and 376, forming a first device 313 (e.g., CMOS) on the first device layer 311; and forming a second device 314 on the second device layer 312. Figure 12 The method is explained illustratively at box 377.

[0076] In variations of the above embodiments, the MST film can be used to deliver non-semiconductor atoms (e.g., O, C, N) to the Si / AlN interface. More specifically, the MST film can be annealed at a relatively high temperature to reposition atoms from one or more non-semiconductor monolayers from their original positions within the MST film in the Si substrate to the Si / AlN interface region. For example, annealing or heating can be performed before, during, or after the AlN formation step to cause non-semiconductor atoms from the MST layer to accumulate at the Si / AlN interface.

[0077] As further discussed in U.S. Patent No. 10,109,479, which is also assigned to the assignee and is hereby incorporated herein by reference in its entirety, the buried insulating layer can be formed by depositing an MST layer and subsequently annealing the structure. Annealing can be performed in an inert atmosphere (e.g., N2, Ar, He, etc.) at a temperature of about 750°C or higher, and more preferably in the range of about 800°C to 1000°C. In some embodiments, a non-inert atmosphere (e.g., H2) can also be used, for example, depending on the temperature range used. For example, in the case of oxygen, annealing causes the inserted non-semiconductor monolayer swirl to decompose.

[0078] The applicant theoretically believes (but does not wish to be limited thereto) that oxygen atoms in the oxygen-MST layer (MST-O) will diffuse, and some of them will relocate to the Si / AlN interface. Depending on the embodiment, the original MST film structure may no longer be present after annealing and / or further processing. It will be appreciated that exemplary annealing times, temperatures, and environments, as well as dosages and monolayer spacings, can vary depending on the specific application and the materials used. Generally, for example, the amount of non-semiconductor atoms at the Si / AlN interface can be in the range of 40-60% of the non-semiconductor atoms present in the initially formed MST film.

[0079] The applicant theoretically argues that non-semiconductor atoms repositioned to the Si / AlN interface provide similar stress-relieving benefits as MST films directly adjacent to the interface, as discussed above. That is, both approaches can be used to position non-semiconductor atoms either directly adjacent to or at the interface region, but in slightly different ways.

[0080] Other approaches to achieving this result may also be potentially used in different embodiments, such as depositing a single non-semiconductor monolayer on top of the Si substrate prior to forming the AlN layer. In this regard, the amount of deposited non-semiconductor atoms may still be relatively low, allowing semiconductor bonds to propagate across the non-semiconductor atoms to sustain crystal growth, as discussed above with reference to MST film formation. In yet another example, non-semiconductor atoms could be implanted at the Si / AlN interface to achieve stress-reducing properties.

[0081] Benefiting from the teachings presented in the foregoing description and associated drawings, those skilled in the art will conceive of many modifications and other embodiments of the invention. Therefore, it should be understood that the invention is not limited to the specific embodiments disclosed, and other modifications and embodiments are intended to be included within the scope of the appended claims.

Claims

1. A semiconductor device, comprising: Semiconductor substrate; A superlattice layer located on the semiconductor substrate, the superlattice layer comprising a plurality of stacked layer groups, each layer group comprising a plurality of stacked basic semiconductor monolayers defining a basic semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of an adjacent basic silicon portion. as well as A III-N semiconductor stack, comprising multiple III-N semiconductor layers located above the superlattice layer.

2. The semiconductor device of claim 1, wherein the III-N semiconductor stack comprises: III-N group semiconductor nucleation layer adjacent to the superlattice layer; III-N semiconductor transition layer adjacent to the III-N semiconductor nucleation layer; as well as At least one III-N semiconductor buffer layer adjacent to the III-N semiconductor transition layer.

3. The semiconductor device of claim 2, wherein the III-N group semiconductor nucleation layer comprises AlN.

4. The semiconductor device of claim 2, wherein the III-N group semiconductor transition layer comprises at least one of AlN, GaN, and AlGaN.

5. The semiconductor device of claim 2, wherein the at least one III-N group semiconductor buffer layer comprises GaN.

6. The semiconductor device of claim 2, wherein the III-N semiconductor stack further comprises: III-N semiconductor spacer layer adjacent to the at least one III-N semiconductor buffer layer; as well as The III-N group semiconductor barrier layer adjacent to the III-N group semiconductor spacer layer.

7. The semiconductor device of claim 6, wherein the III-N group semiconductor spacer layer comprises AlN.

8. The semiconductor device of claim 6, wherein the III-N group semiconductor barrier layer comprises AlGaN.

9. The semiconductor device of claim 1, wherein the semiconductor substrate comprises a single-crystal silicon substrate having a (111) orientation and an offset angle of 0.5° or less.

10. The semiconductor device of claim 1, wherein the basic semiconductor monolayer comprises silicon.

11. The semiconductor device of claim 1, wherein the at least one non-semiconductor monolayer comprises oxygen.

12. The semiconductor device of claim 1, wherein the at least one non-semiconductor monolayer comprises carbon.

13. A semiconductor device, comprising: A monocrystalline silicon substrate having a (111) orientation and an off-center angle of 0.5° or less; A superlattice layer located on the single-crystal silicon substrate, the superlattice layer comprising a plurality of stacked layer groups, each layer group comprising a plurality of stacked basic semiconductor monolayers defining a basic semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of an adjacent basic semiconductor portion. as well as A III-N semiconductor stack located above the superlattice layer, the III-N semiconductor stack comprising The III-N group semiconductor nucleation layer adjacent to the superlattice layer, The III-N semiconductor transition layer adjacent to the III-N semiconductor nucleation layer, At least one III-N semiconductor buffer layer adjacent to the III-N semiconductor transition layer.

14. The semiconductor device of claim 13, wherein the III-N group semiconductor nucleation layer comprises AlN.

15. The semiconductor device of claim 13, wherein the III-N group semiconductor transition layer comprises at least one of AlN, GaN, and AlGaN.

16. The semiconductor device of claim 13, wherein the at least one III-N group semiconductor buffer layer comprises GaN.

17. The semiconductor device of claim 13, wherein the III-N semiconductor stack further comprises: III-N semiconductor spacer layer adjacent to the at least one III-N semiconductor buffer layer; as well as The III-N group semiconductor barrier layer adjacent to the III-N group semiconductor spacer layer.

18. The semiconductor device of claim 17, wherein the III-N group semiconductor spacer layer comprises AlN.

19. The semiconductor device of claim 17, wherein the III-N group semiconductor barrier layer comprises AlGaN.

20. A method for manufacturing a semiconductor device, comprising: A superlattice layer is formed on a semiconductor substrate. The superlattice layer includes multiple stacked layers, each layer including multiple stacked basic semiconductor monolayers defining a basic semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of an adjacent basic semiconductor portion. as well as A III-N semiconductor stack is formed above the superlattice layer, the III-N semiconductor stack comprising multiple III-N semiconductor layers.

21. The method of claim 20, wherein forming the III-N semiconductor stack comprises: Forming a III-N group semiconductor nucleation layer adjacent to the superlattice layer; Forming a III-N group semiconductor transition layer adjacent to the III-N group semiconductor nucleation layer; as well as At least one III-N semiconductor buffer layer is formed adjacent to the III-N semiconductor transition layer.

22. The method of claim 21, wherein the III-N semiconductor nucleation layer comprises AlN.

23. The method of claim 21, wherein the III-N semiconductor transition layer comprises at least one of AlN, GaN, and AlGaN.

24. The method of claim 21, wherein the at least one III-N semiconductor buffer layer comprises GaN.

25. The method of claim 21, wherein forming the III-N semiconductor stack further comprises: Form a III-N semiconductor spacer layer adjacent to the at least one III-N semiconductor buffer layer; as well as A III-N group semiconductor barrier layer is formed adjacent to the III-N group semiconductor spacer layer.

26. The method of claim 25, wherein the III-N semiconductor spacer layer comprises AlN.

27. The method of claim 25, wherein the III-N semiconductor barrier layer comprises AlGaN.

28. The method of claim 20, wherein the semiconductor substrate comprises a single-crystal silicon substrate having a (111) orientation and an offset angle of 0.5° or less.

29. The method of claim 20, wherein the basic semiconductor monolayer comprises silicon.

30. The method of claim 20, wherein the at least one non-semiconductor monolayer comprises oxygen.

31. The method of claim 20, wherein the at least one non-semiconductor monolayer comprises carbon.

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