Semiconductor device and power conversion device

Abstract

A semiconductor device (200) includes: a first package (1) having a control IC chip (22) for controlling a MOSFET (3) for power conversion and a single capacitor (21) for supplying power to the control IC chip (22); a MOSFET (3) located outside the first package (1) and turned on and off by receiving a control signal from the control IC chip (22); and a second package (2) having wiring (lead frame (4), wiring (5), source electrode wiring (6), and gate electrode wiring (7)) for electrically connecting the control IC chip (22) and the electrodes of the MOSFET (3) in the first package (1), and the first package (1), the MOSFET (3) and the wiring are sealed with molding resin (33).

Description

Technical Field

[0001] This invention relates to a semiconductor device and a power conversion device. Background Technology

[0002] In power control and motor control of industrial equipment, electric railway vehicles, automobiles, and home appliances, a semiconductor device is used that integrates multiple switching elements such as power MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors) and IGBTs (Insulated Gate Bipolar Transistors), as well as freewheeling diodes, into a single module.

[0003] To drive MOSFETs used for power conversion, circuitry and power supplies are needed to control their on / off states. To handle large conversion capacities, MOSFET chips have become larger, requiring large capacitors that are difficult to integrate into ICs for power supply. However, in existing pin configurations, it's difficult to mount capacitors in a single package for miniaturization and performance improvement because the positive terminal of the capacitor's lead frame is exposed outside the package. To avoid this, a package that further covers the entire circuitry from the outside is needed.

[0004] Examples of this include the technologies in Patent Document 1 and Patent Document 2.

[0005] In Patent Document 1, a single capacitor, MOSFET, and IC are integrated into a single package, which is then mounted onto an external package. In other words, the entire circuit is temporarily mounted within the package, which is then further double-packaged.

[0006] In Patent Document 2, a single capacitor, MOSFET and IC are integrated into a single package.

[0007] Existing technical documents

[0008] Patent documents

[0009] Patent Document 1: Japanese Patent Application Publication No. 2017-98276

[0010] Patent Document 2: Japanese Patent Application Publication No. 2015-116053 Summary of the Invention

[0011] The problem that the invention aims to solve

[0012] The devices described in Patent Documents 1 and 2 temporarily mount the entire circuit, consisting of a single capacitor, a MOSFET, and an IC, within a package. The device described in Patent Document 1 further double-packages this circuit. Therefore, the following problems arise: it necessitates a larger package size, making it difficult to miniaturize and reduce the thickness of the device, and reducing heat dissipation makes it difficult to increase power conversion capacity.

[0013] The present invention was made in view of the following circumstances, and its object is to provide a semiconductor device and a power conversion device that can achieve thinning and miniaturization of the package, and reduce the thermal resistance of the semiconductor device and increase its size and capacity.

[0014] Methods for solving problems

[0015] To address the aforementioned issues, the semiconductor device of the present invention is a power conversion semiconductor device, characterized by comprising: a first package having a control IC chip for controlling a MOSFET element for power conversion, and a single capacitor for supplying power to the control IC chip; the MOSFET element being located outside the first package and being switched on and off by receiving a control signal from the control IC chip; and a second package having wiring electrically connecting the electrodes of the control IC chip and the MOSFET element within the first package, wherein the control IC chip, the MOSFET element, and the wiring are sealed by a molding component.

[0016] Invention Effects

[0017] According to the present invention, a semiconductor device and a power conversion device can be provided, which can achieve thinning and miniaturization of the outer packaging, and reduce the thermal resistance of the semiconductor device and increase its size and capacity. Attached Figure Description

[0018] Figure 1 This is a top view of a semiconductor device according to the first embodiment of the present invention.

[0019] Figure 2 This is a side view of a semiconductor device according to the first embodiment of the present invention.

[0020] Figure 3 This is a top view showing the structure of the first package of the semiconductor device according to the first embodiment of the present invention.

[0021] Figure 4 yes Figure 3 Side view.

[0022] Figure 5 This is a circuit diagram of the control IC chip of the semiconductor device according to the first embodiment of the present invention.

[0023] Figure 6 This is a side view showing the structure of the first package of the semiconductor device according to the second embodiment of the present invention.

[0024] Figure 7 Is using Figure 6 The first package is an example of a power conversion device that constitutes an autonomous synchronous rectifier half-bridge.

[0025] Figure 8 yes Figure 7 Circuit diagram of the power conversion device of the autonomous synchronous rectifier half-bridge.

[0026] Figure 9 This is a side view showing the structure of the first package of the semiconductor device according to the third embodiment of the present invention.

[0027] Figure 10 This is a side view showing the structure of the first package of the semiconductor device according to the fourth embodiment of the present invention.

[0028] Figure 11 This is a side view showing the structure of a semiconductor device having the first package of the fifth embodiment of the present invention.

[0029] Figure 12 This is a side view showing the structure of the first package of the semiconductor device according to the sixth embodiment of the present invention.

[0030] Figure 13 This is a graph showing the relationship between the gate voltage, normalized to the threshold voltage of the MOSFET, and the resistance (au) of the MOSFET when it is turned on.

[0031] Figure 14 This is an example of a power conversion device that is a self-synchronous rectified full-bridge power converter, which is constructed from the first package of the semiconductor device according to the seventh embodiment of the present invention.

[0032] Figure 15 yes Figure 14 Circuit diagram of the power conversion device of the autonomous synchronous rectification full bridge.

[0033] Figure 16 This is an example of a power conversion device that is configured as an autonomous synchronous rectification full-bridge by the first package of the semiconductor device according to the eighth embodiment of the present invention.

[0034] Figure 17 It means Figure 16 A side view of the structure of the first package 1 of the semiconductor device.

[0035] Figure 18 This is a block diagram illustrating the circuit structure of the power conversion device according to the third embodiment of the present invention. Detailed Implementation

[0036] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0037] (First Implementation)

[0038] The semiconductor device according to the first embodiment of the present invention will be described. In this embodiment, a vertical Nch MOSFET is used as an example of a power conversion element, but other MOS gate drive transistors such as IGBTs or other power transistors may also be used.

[0039] Figure 1 This is a diagram showing the structure of the semiconductor device 200 according to the first embodiment, and is a top view (top perspective view) of the semiconductor device 200 viewed from above. Figure 2 yes Figure 1 Side view (lateral perspective view). In each figure, structures with the same structure or similar function are labeled with the same reference numerals, and detailed descriptions of repeated parts are omitted.

[0040] In addition, Figure 1 In the top view, for convenience, the arrangement of lower-level components that are not visible due to the presence of upper-level components is described in advance, while making the arrangement of the upper-level components visible.

[0041] like Figure 1 As shown, the semiconductor device 200 is a power conversion semiconductor device, comprising a package 1 (hereinafter referred to as the first package 1) housing a control IC chip and a single capacitor, an outer package 2 (hereinafter referred to as the second package 2), a MOSFET 3 (a MOSFET element for power conversion), a lead frame 4, wiring 5, source electrode wiring 6 (wiring connecting the first package 1 and the MOSFET 3), gate electrode wiring 7 (wiring connecting the first package 1 and the MOSFET 2), and molding resin 8 (molding component). Figure 2 ), and solders 9, 10, 11, 12, and 13 ( Figure 2 ).

[0042] The first package 1 has a control IC chip 22 for controlling the MOSFET 3 for rectification and a single capacitor 21 for supplying power to the control IC chip 22 and the MOSFET 3.

[0043] MOSFET3 is located outside the first package 1 and is turned on and off by receiving control signals from the control IC chip 22 inside the first package 1.

[0044] The second package 2 has a control IC chip 22 (described later) inside the first package 1. Figure 3 and Figure 4The wiring (lead frame 4, wiring 5, source electrode wiring 6, gate electrode wiring 7) that is electrically connected to the electrodes of MOSFET3 is sealed with molding resin 8 to control IC chip 22, MOSFET3 and wiring 4~7.

[0045] The drain electrodes on the back of the first package 1 of the semiconductor device 200 and the MOSFET 3 are connected to the lead frame 4 via solders 9 and 13. Furthermore, in the semiconductor device 200, the source electrode and gate electrode of the MOSFET 3 are connected to the source electrode wiring 6 and the gate electrode wiring 7 via bonding materials such as solder. The source electrode wiring 6 and the gate electrode wiring 7 are then connected to the control IC chip 22 (control circuit IC) (described later) housed inside the first package 1 via bonding materials such as solder. Figure 3 and Figure 4 )connect.

[0046] In the semiconductor device 200, the drain electrode of the MOSFET 3 is output to the outside from the outer package 2 via the lead frame 4, and the source electrode of the MOSFET 3 is output to the outside from the second package 2 via a clamp and a lead frame 5 connected thereto. The drain and source electrodes of the MOSFET 3 correspond to the control of the power supply of the semiconductor device 200.

[0047] The control IC chip 22 is connected to the source electrode (terminal), gate electrode (terminal), and drain electrode (terminal) of the MOSFET 3, and can connect the individual capacitors 21 (described later) in the same package according to the state of the MOSFET 3. Figure 3 as well as Figure 4 It serves as a power source to control the on / off state of MOSFET3.

[0048] Thus, the semiconductor device 200 includes: a first package 1, which includes a control IC chip 22 constituting a circuit for driving the MOSFET 3, and a single capacitor 21 (described later) for supplying power to the control IC chip 22. Figure 3 as well as Figure 4 ); MOSFET3, which is located outside the first package 1, receives control signals from the control IC chip 22 to turn on and off; and the second package 2, which has source electrode wiring 6 and gate electrode wiring 7 (wiring connecting the first package 1 and MOSFET2) connecting the first package 1 and MOSFET2, and is formed by sealing the control IC chip 22, MOSFET3 and wiring 6, 7, etc. with molding resin 8.

[0049] The semiconductor device 200 houses the control IC chip 22 (described later) within the first package 1. Figure 3 and Figure 4 ) and single-cell capacitor 21 (described later) Figure 3 and Figure 4The control IC chip 22 inside the first package 1 receives power from the individual capacitor 21 and autonomously controls the power of the MOSFET 3 located outside the first package 1. Thus, the semiconductor device 200 can autonomously control the power of the MOSFET 3 without providing control signals or external power terminals for the MOSFET 3.

[0050] Additionally, in the semiconductor device 200, wiring 5 (which becomes the main wiring of the source electrode) Figure 1 The MOSFET 200 is directly connected to MOSFET 3, thus enabling a reduction in wiring height and a thinner second package 2 as the outer packaging. This allows for a reduction in thermal resistance, miniaturization, and increased capacity of the semiconductor device 200, and further enables the development of power conversion devices using it. Figure 18 Miniaturization, large capacity, and high efficiency of ( ).

[0051] <First Package 1>

[0052] Figure 3 This is a plan view (top perspective view) showing the structure of the first package 1 of the semiconductor device 200 according to the first embodiment. Figure 4 yes Figure 3 Side view (side perspective perspective).

[0053] like Figure 3 as well as Figure 4 As shown, semiconductor device 200 ( Figure 1 The first package 1 includes a single capacitor 21, a control IC chip 22, lead frames 23, 24, 25, 26, capacitor terminals (positive voltage side) 27, capacitor terminals (negative voltage side) 28, wiring 29, 30, 31, 32 (wiring electrically connecting the control IC chip 22 to the electrodes of the MOSFET 3), molding resin 33, and bonding materials 34, 35, 36. The first package 1 is a cuboid shape formed by molding resin 33, having a surface (top surface) 1a, a back surface 1b, and a side surface 1c. Figure 4 ).

[0054] The wiring 29, 30, 31, and 32 mentioned above can also be conductors or strips.

[0055] Additionally, the lead frame is sometimes appropriately referred to as a terminal. Both terminals and lead frames are parts that connect to external wiring, so they are not distinguished and are referred to as lead frames. On the other hand, terminals (parts of the component) that extend from the component, such as capacitor terminals 27 or 28, are called "terminals".

[0056] The capacitor terminals 27 on the positive voltage side and 28 on the negative voltage side of the individual capacitor 21 within the first package 1 are connected to lead frames 23 and 24 respectively via bonding materials. The control IC chip 22 is connected to the lead frame 24 via bonding materials and to lead frames 23, 24, 25, and 26 via wirings 29, 30, 31, and 32 respectively. They are sealed with molding resin 33.

[0057] The ends of lead frames 23, 24, 25, and 26 protrude from the side (side 1c) of the molding resin 33, the back (back 1b) of the first package 1, or the surface (surface 1a) of the first package 1, enabling connection to an external circuit. Additionally, in Figure 3 and Figure 4 In this configuration, capacitor terminals 27 and 28 protrude from the surface of the molding resin 33 (surface 1a of the first package 1). Therefore, the control IC chip 22 within the first package 1 can interact with... Figure 1 The MOSFET3 and the external circuit for electrical characteristic testing (illustration omitted) are connected.

[0058] Additionally, in the following description, the drain electrode, source electrode, and gate electrode of a MOSFET are sometimes simply referred to as drain, source, and gate, respectively.

[0059] exist Figure 3 as well as Figure 4 In this process, the capacitor terminal 28 (the terminal connected to the drain, source, and gate electrodes of the MOSFET element) of the single capacitor 21 of the first package 1 is connected to the source of the MOSFET 3, and the lead frame 25 (the terminal connected to the drain, source, and gate electrodes of the MOSFET element) is connected to the gate of the MOSFET 3 via a clamp. Additionally, the back surface 26b of the lead frame 26 (the terminal connected to the drain, source, and gate electrodes of the MOSFET element) is soldered to the lead frame 4 (where the MOSFET 3 is mounted) Figure 1 , Figure 2 The gate, source, and drain of MOSFET3 are connected to the control IC chip 22, enabling control of MOSFET3.

[0060] By providing terminals exposed on the surface 1a or back 1b of the first package 1 and connecting each terminal to the electrode of the MOSFET, the wiring between the MOSFET 3 can be simplified and miniaturized.

[0061] Alternatively, the terminals exposed from the side 1c of the first package 1 can also be used for wiring.

[0062] <Control IC Chip 22>

[0063] Figure 5 This diagram illustrates an example of a circuit that autonomously synchronously rectifies and drives a MOSFET, serving as a control IC chip 22.

[0064] The control IC chip 22 includes a voltage conversion circuit 41, a diode 42, a control determination circuit 43, and a drive circuit 44 connected to the drain of the MOSFET 3. The control IC chip 22 and the single capacitor 21 are housed together in the first package 1. In addition, the output of the voltage conversion circuit 41 of the control IC chip 22 is connected to the drain of the MOSFET 3, the output of the drive circuit 44 is connected to the gate of the MOSFET 3, and the capacitor terminal (negative voltage side) of the single capacitor 21 is connected to the source of the MOSFET 3 as the low-potential power supply of the control IC chip 22.

[0065] When a positive voltage is applied to the drain of MOSFET3, control IC chip 22 charges the individual capacitor 21. Control IC chip 22 uses a self-powered power supply based on the voltage of charging individual capacitor 21, determines the direction of current in MOSFET3 through control determination circuit 43, and applies voltage between the gate and source of MOSFET3 through drive circuit 44 to control the MOSFET3 to turn on and off.

[0066] When a voltage is applied to MOSFET3, the single capacitor 21 charges itself from the drain voltage of MOSFET3. When MOSFET3 is turned off, the charged charge is used as a power source to supply power to the load side (control IC chip 22 and MOSFET3). Figure 5 (Reverse current in the path of diode 42). That is, the self-power of the single capacitor 21 is based on applying a positive voltage to the drain of MOSFET3. Therefore, the terminal of the single capacitor 21 is connected to the drain of MOSFET3 via the source of MOSFET3 and the circuit of the control IC.

[0067] The control IC chip 22 does not require external control signals or power supply for the MOSFET 3, which is the object of control. When the current flowing through the MOSFET 3 changes from the source to the drain direction, the MOSFET 3 can be turned on without external commands. That is, the control IC chip 22 can be used as a control IC for autonomous synchronous rectification to reduce the conduction losses of the MOSFET's built-in diode.

[0068] <Effects of the First Implementation Method>

[0069] Semiconductor device 200 according to the first embodiment of the present invention Figure 1 , Figure 2The device comprises: a first package 1 having a control IC chip 22 for controlling a MOSFET 3 for rectification, and a single capacitor 21 for supplying power to the control IC chip 22; a MOSFET 3 located outside the first package 1, which receives a control signal from the control IC chip 22 and is turned on and off; and a second package 2 having wiring (lead frame 4, wiring 5, source electrode wiring 6, and gate electrode wiring 7) that electrically connects the control IC chip 22 and the electrodes of the MOSFET 3 within the first package 1, and is formed by sealing the control IC chip 22, the MOSFET 3 and these wirings with molding resin 33.

[0070] With this structure, even when a large-capacity individual capacitor 21, which is difficult to integrate, is incorporated into a miniaturized first package 1 excluding the MOSFET 3. Furthermore, the control IC chip 22 and the individual capacitor 21 in the first package 1 are connected to the MOSFET 3 outside the first package 1 via wiring (lead frame 4, wiring 5, source electrode wiring 6, gate electrode wiring 7), and they are sealed with molding resin 33 to form a second package 2. Thus, the positive terminal of the lead frame carrying the individual capacitor 21 is not exposed from the mounting package (second package 2), allowing for mounting with existing pin configurations. Furthermore, it eliminates the need for the large, difficult-to-miniaturize package structure with low flexibility, which requires externally covering the entire circuit consisting of the MOSFET 3, control IC chip 22, and individual capacitor 21, as described in Patent Documents 1 and 2.

[0071] Therefore, in this embodiment, even when equipped with a large-capacity single capacitor 21 and a large-scale MOSFET 3, it is possible to achieve a thinner and smaller second package 2 as the outer packaging, thereby reducing the thermal resistance of the semiconductor device and achieving miniaturization and increased capacity. Furthermore, it is possible to achieve miniaturization, increased capacity, and higher efficiency in the power conversion device using it.

[0072] In particular, according to this embodiment, the control IC chip 22 for driving the MOSFET3 and the single-cell capacitor 21 for self-powered operation are housed in the first package 1. The first package 1 and the MOSFET3 disposed outside it are connected by wiring and sealed by molding resin 33 to form the second package 2. Therefore, in addition to the reduction of thermal resistance, miniaturization, and increased capacitance of the semiconductor device, the freedom of arrangement and shape of the wiring such as the first package 1, MOSFET3, and lead frame in the second package 2 is greatly improved. This increased freedom of arrangement and shape has the effect of expanding ease of implementation and versatility when mounting the semiconductor device. In addition, through the design of the arrangement and shape, it is also expected that the thickness of the outer package (second package 2) can be further reduced.

[0073] Furthermore, in the semiconductor device 200, the control IC chip 22 within the first package 1 receives power from the individual capacitor 21 and autonomously controls the power of the MOSFET 3 located outside the first package 1. Thus, the semiconductor device 200 can autonomously control the power of the MOSFET 3 without providing control signals or external power terminals for the MOSFET 3.

[0074] In addition, in this embodiment, the first package 1 ( Figure 3 , Figure 4 In the MOSFET 3, the capacitor terminal 27 (one terminal) on the positive voltage side of the single capacitor 21 is connected to the source electrode of the MOSFET 3, and the capacitor terminal 28 (the other terminal) on the negative voltage side of the single capacitor 21 is connected to the drain electrode of the MOSFET 3 via the circuit of the control IC chip 22.

[0075] With this structure, the gate, source, and drain of MOSFET3 are connected to the control IC chip 22, which enables the control of MOSFET3.

[0076] In addition, in this embodiment, the first package 1 ( Figure 3 , Figure 4 It has terminals that connect to the drain electrode, source electrode and gate electrode of MOSFET3, and the terminals are formed on the surface (first main surface) side or the back (second main surface) side of the control IC chip 22 within the first package 1.

[0077] exist Figure 3 and Figure 4 In this process, the capacitor terminal 28 of the single capacitor 21 of the first package 1 is connected to the source of the MOSFET 3, and the lead frame 25 and the gate of the MOSFET 3 are connected by clamps. These terminals are formed on the surface (first main surface) side of the control IC chip 22 within the first package 1. Additionally, solder is used to connect the back surface 26b of the lead frame 26 to the lead frame 4 (where the MOSFET 3 is mounted)... Figure 1 , Figure 2 The terminals connected to the back surface 26b of the lead frame 26 are formed on the back surface (second main surface) of the control IC chip 22 within the first package 1.

[0078] With this structure, the source and gate of MOSFET3 are connected on the surface (first main surface) side of the control IC chip 22, and the drain of MOSFET3 is connected on the back side (second main surface) side via the back side 26b of the lead frame 26, thus enabling control of MOSFET3.

[0079] (Second Implementation)

[0080] Figure 6This is a side view (side perspective view) showing the structure of the first package 1 of the semiconductor device according to the second embodiment. Regarding... Figure 4 The same components are marked with the same symbol. Figure 6 The first package 1 shown can replace Figure 1 The semiconductor device 200 shown is used in the first package 1.

[0081] In the second embodiment, the terminals 24, 25, and 26 of the first package 1 (refer to [reference needed] regarding terminals 24 and 26) Figure 6 Regarding terminal 25, refer to... Figure 7 The circuit extends outward from side 1c and connects with the driven MIOSFETs 51 and 52 (see reference). Figure 7 )connect.

[0082] Because terminals 24, 25, and 26 protrude from side 1c, the first package 1 and its terminals 24, 25, and 26 can be manufactured flat. Since bending of terminals 24, 25, and 26 or the lead frame connected to them is not required, the manufacturing process is simplified. However, in a structure where any one of terminals 24, 25, and 26 protrudes from side 1c, there are installation constraints when configuring the first package 1.

[0083] Figure 7 Is using Figure 6 The first package 1 is an example of a power conversion device (semiconductor device) that constitutes an autonomous synchronous rectifier half-bridge.

[0084] like Figure 7 As shown, the semiconductor device 200A is a power conversion device with an autonomous synchronous rectification half-bridge, comprising: two first packages 1; a second package 2; MOSFETs 51 and 52 (MOSFET elements for rectification); lead frames 55, 56, and 57 (first lead frames that mount MOSFET elements and first packages); wiring 58, 59, 60, and 61; and source electrode wiring 6 (wiring connecting the first packages and MOSFET elements).

[0085] Figure 8 yes Figure 7 Circuit diagram of the autonomous synchronous rectifier half-bridge power conversion device (semiconductor device 200A).

[0086] exist Figure 8 In the circuit structure of the semiconductor device 200A shown, the control IC chip of the first package 1 (illustration omitted, see reference) Figure 5 Voltage conversion circuit (illustration omitted, refer to...) Figure 5The input of the drive circuit 44 is connected to the drain of MOSFETs 51 and 52, and the output of the drive circuit 44 is connected to the gate of MOSFETs 51 and 52. A single capacitor (illustrated but not shown, see reference) Figure 5 The capacitor terminal (negative voltage side) of the MOSFET is connected to the source of MOSFETs 51 and 52 as the low-potential power supply for the control IC chip. Through the control IC chip, the individual capacitors are charged when a positive voltage is applied to the drain of MOSFETs 51 and 52. The control IC chip applies a voltage between the gate and source of MOSFETs 51 and 52 to control their on / off states.

[0087] <Effects of the Second Implementation>

[0088] In this embodiment, the second package 2 ( Figure 7 It has first lead frames 55, 56, and 57 that house MOSFETs 51 and 52 and a first package 1. The terminals of the first package 1 are connected to the drain or source electrodes of MOSFETs 51 and 52 through the first lead frames 55, 56, and 57.

[0089] By adopting this mounting structure, the number of wiring components connecting the first package 1 to the MOSFETs 51 and 52 can be reduced. In addition, by easily filling the lower part of the first package 1 with molding resin, the mounting process can be simplified, and a smaller and more assemblable semiconductor device 200A can be provided.

[0090] (Third Implementation)

[0091] Figure 9 This is a side view (side perspective view) showing the structure of the first package 1 of the semiconductor device according to the third embodiment. Regarding... Figure 6 Identical structural parts are labeled with the same symbols. Figure 9 The first package 1 shown can be used for Figure 1 as well as Figure 2 The semiconductor device 200 shown Figure 7 The semiconductor device 200A shown is shown.

[0092] like Figure 9As shown, a single-cell capacitor 21 is mounted outside the first package 1 (on the upper surface in this case). The first package 1 has exposed terminals 23 and 24 (terminals connecting the drain, source, and gate electrodes of the MOSFET element) formed by lead frames on its upper surface (surface 1a). These terminals 23 and 24 are connected to the positive voltage side capacitor terminal 27 and the negative voltage side capacitor terminal 28 of the single-cell capacitor 21 via bonding materials 36 and 35. Furthermore, although not shown, the terminal 24 is exposed at multiple locations on the surface, allowing for connection to wiring. One location is connected to the negative voltage side capacitor terminal 28 of the single-cell capacitor 21, while other locations are connected to the source electrode of the MOSFET (not shown). The placement of the MOSFET by the first package 1 is described later, for example. Figure 11 As shown.

[0093] [Effects of the Third Implementation]

[0094] The semiconductor device in this embodiment ( Figure 9 In the first package 1, a MOSFET 3 is provided with a power supply. Figure 1 , Figure 2 The lead frames 23, 24, and 25 (in the drain, source, and gate electrodes) connect the drain, source, and gate electrodes. Figure 9 In the middle, terminal 25 is not shown), at least one of the terminals (in Figure 9 In the middle, terminals 23 and 24 are formed on the side of the first package 1.

[0095] This structure reduces the amount of wiring material required to connect the first package 1 to the MOSFET 3. Furthermore, the ease of filling the lower part of the first package 1 with molding resin simplifies the assembly process, resulting in a smaller and more easily assemblable semiconductor device.

[0096] Furthermore, the semiconductor device in this embodiment ( Figure 9 In the first package 1, terminals 23 and 24 (fourth lead frame) are provided to connect the control IC chip 22 and the individual capacitor 21. A portion of the terminals 23 and 24 are exposed from the surface 1a or the back surface 1b (surface 1a in this embodiment) of the first package 1 as bonding materials 36 and 35. The capacitor terminal 27 on the positive voltage side and the capacitor terminal 28 on the negative voltage side of the individual capacitor 21 are connected to the bonding materials 36 and 35.

[0097] According to this structure, by mounting the individual capacitor 21 on the outside of the first package 1, miniaturization and simplification of the assembly process can be achieved by thinning the first package 1.

[0098] (Fourth Implementation)

[0099] Figure 10This is a side view (side perspective view) showing the structure of the first package 1 of the semiconductor device according to the fourth embodiment. Regarding... Figure 9 Identical structural parts are labeled with the same symbols. Figure 10 The first package 1 shown can be used for Figure 1 as well as Figure 2 The semiconductor device 200 shown Figure 7 The semiconductor device 200A shown is shown.

[0100] like Figure 10 As shown, the first package 1 and Figure 9 Similarly, a single-unit capacitor 21 is mounted on the surface 1a of the first package 1.

[0101] Figure 10 The first package 1 shown contains a control IC 22 connected to a single capacitor 21 and a MOSFET 3. Figure 1 , Figure 2 The lead frames 23, 24, and 25 of the gate drive wiring 31 are exposed as terminals on the surface 1a side of the first package 1. The first package 1 is a structure in which the lead frames 24 and 25 are respectively connected to the source and gate of the driven MOSFET. The lead frame 26 is exposed as an exposed portion 26b on the back side 1b of the first package 1, and the exposed portion 26b is connected to the drain of the driven MOSFET 3.

[0102] [Effects of the Fourth Implementation]

[0103] The semiconductor device in this embodiment ( Figure 10 In the first package 1, a MOSFET 3 is provided with a power supply. Figure 1 , Figure 2 The terminals connecting the drain electrode, source electrode, and gate electrode (in) Figure 10 (referred to as lead frames) 23, 4, 25, at least one of lead frames 23, 24, 25 (in Figure 10 The lead frames 23 and 24 are formed on the surface 1a side of the first package 1.

[0104] Based on this structure, and Figure 9 Similarly, in the case of the first package 1, by mounting the individual capacitor 21 on the outside of the first package 1, miniaturization and simplification of the assembly process can be achieved by thinning the first package 1.

[0105] (Fifth Implementation)

[0106] Figure 11 This is a side view (side perspective view) showing the structure of the semiconductor device 200B having the first package 1 of the fifth embodiment. Figure 11This is an example of a structure in which the first package 1 is disposed on the MOSFET. Regarding... Figure 6 Identical structural parts are labeled with the same symbols.

[0107] Figure 11 The semiconductor device 200B shown has a first package 1 mounted on a MOSFET 3.

[0108] In particular, when the MOSFET3 is large in size, the first package 1 can be mounted on the MOSFET3.

[0109] In semiconductor device 200B, lead frame 25 (a second lead frame connected to the source electrode and gate electrode of the MOSFET element) connected to the source of MOSFET 3 and lead frame 24 (a second lead frame connected to the source electrode and gate electrode of the MOSFET element) connected to the gate of MOSFET 3 are exposed from the back side 1b of the first package 1. The exposed lead frames 25 and 24 are connected to the source and gate of MOSFET 3 by solder 61. In addition, lead frame 26 (a third lead frame connected to the drain electrode of MOSFET element) connected to the drain of MOSFET 3 is exposed from the side side 1c of the first package 1 and connected to the drain of MOSFET 3 via lead frame 4.

[0110] [Effects of the Fifth Implementation]

[0111] The semiconductor device in this embodiment ( Figure 11 In the first package 1, lead frames 24 and 25 are connected to the source and gate electrodes of the MOSFET 3, and lead frame 26 is connected to the drain electrode of the MOSFET 3. A portion of the second lead frame is exposed as an exposed portion from the back side 1b of the first package 1, and this exposed portion is electrically connected to the source and gate electrodes of the MOSFET 3. Lead frame 26 is exposed from the side of the first package 1, and is connected to the first lead frames 55, 56, and 57. Figure 7 ) connected via the first lead frame 55, 56, 57 ( Figure 7 It is connected to the drain electrode of MOSFET3.

[0112] With this structure, the semiconductor device 200B can reduce the area required for mounting the first package 1, enabling miniaturization of the package of the semiconductor device 200B, mounting of larger MOSFETs, and increasing the capacity of the semiconductor device.

[0113] (Sixth Implementation Method)

[0114] Figure 12 This is a side view (side perspective view) showing the structure of the first package 1 of the semiconductor device according to the sixth embodiment. Regarding... Figure 6Identical structural parts are labeled with the same symbols. Figure 12 The first package 1 shown can be used for Figure 1 as well as Figure 2 The semiconductor device 200 shown Figure 7 The semiconductor device 200A shown Figure 11 The semiconductor device 200B shown is shown.

[0115] like Figure 12 As shown, the first package 1 is longitudinally arranged on the lead frame 24 with the capacitor terminal 27 on the positive voltage side and the capacitor terminal 28 on the negative voltage side of the single capacitor 21 facing the surface 1a and the back side 1b of the first package 1, respectively.

[0116] exist Figure 12 In the first package 1 shown, the capacitor terminal 27 on the positive voltage side and the capacitor terminal 28 on the negative voltage side of the single capacitor 21 are longitudinally arranged on the lead frame 24, so that the single capacitor 21 is arranged parallel to the control IC chip 220.

[0117] [Effects of the Sixth Implementation Method]

[0118] The single-unit capacitor 21 is a thin-walled single-unit capacitor (planar and thin capacitor) such as a chip capacitor on which capacitance is formed on Si. By using the thin-walled single-unit capacitor 21, the first package 1 can be made thinner. Therefore, the thickness of the package of the semiconductor device using the first package 1 can be reduced. As a result, miniaturization of the semiconductor device and large capacitance due to reduced thermal resistance can be achieved. Furthermore, when using a thin capacitor, attention should be paid to the voltage applied to the single-unit capacitor (described later). Figure 13 ).

[0119] <Applying voltage to a single capacitor>

[0120] The applied voltage to the single-cell capacitor 21 will be described.

[0121] The first package 1 of the semiconductor device in the first to sixth embodiments carries an IC and a single-cell capacitor 21. Therefore, the insight into the overvoltage of the single-cell capacitor 21 is reflected in all the semiconductor devices of the first to sixth embodiments. The single-cell capacitor 21 of the first package 1 of the semiconductor device 200 of the first embodiment (… Figure 12 For example, ( ).

[0122] In the semiconductor devices 200, 200A, and 200B of the first to sixth embodiments, Figure 5The voltage conversion circuit 41 of the control IC chip 22 shown generates an applied voltage to the individual capacitor 21. In this case, the voltage conversion circuit 41 sets the applied voltage to the individual capacitor 21 to be less than four times the threshold voltage of the MOSFET to be controlled.

[0123] Figure 13 This is a graph showing the relationship between the gate voltage, normalized to the threshold voltage of the MOSFET, and the resistance (au) of the MOSFET when it is turned on.

[0124] The resistance of a MOSFET when it is turned on (on-resistance) is the resistance between the drain and source when the MOSFET is turned on. The smaller the value, the less power loss (power loss) during operation.

[0125] like Figure 13 As shown, the resistance of the MOSFET decreases as the gate voltage increases from the MOSFET's turn-on threshold voltage, but saturates at about three times the threshold voltage, and can be sufficiently reduced. Therefore, by setting the applied voltage to the individual capacitor 21 to less than four times the threshold voltage of the MOSFET to be controlled, even taking into account the decrease in capacitor voltage caused by current consumption during circuit operation, the voltage of the individual capacitor 21 is applied as the MOSFET's gate voltage during turn-on via the control IC.

[0126] As a result, the MOSFET can achieve sufficiently low on-time resistance, the semiconductor device can achieve low loss, and the miniaturization of the insulating film of the individual capacitor 21 can be achieved through thin-film technology, as well as the miniaturization and large capacitance of the semiconductor devices 200, 200A, and 200B using the individual capacitor 21.

[0127] The voltage applied to the aforementioned single capacitor 21 varies depending on the MOSFET being applied, but as an example, an applied voltage of 16V or less is considered.

[0128] Furthermore, the voltage applied to the individual capacitor 21 is set to be less than four times the threshold voltage of the MOSFET to be controlled, and this is also the case for the semiconductor devices 200C and 200D of the seventh and eighth embodiments described later. In addition, it is not limited to the first package 1 in the semiconductor devices of each embodiment, but can also be applied in a package that integrates the MOSFET, the control IC chip and the individual capacitor (for example, the device of Patent Document 2).

[0129] In the semiconductor devices of various embodiments, by setting the applied voltage to the individual capacitor 21 to less than four times the threshold voltage of the MOSFET to be controlled, the individual capacitor 21 can be miniaturized. As a result, the first package 1, which carries the individual capacitor 21, can be miniaturized and thinned, and the semiconductor device using the first package 1 can be miniaturized and have a large capacitance.

[0130] (Seventh Implementation)

[0131] Figure 14 This is an example of a power conversion device (semiconductor device) consisting of a single-phase, self-synchronous rectifier full-bridge power converter constructed from the first package 1 of the semiconductor device according to the seventh embodiment. Regarding... Figure 7 Identical structural parts are labeled with the same symbols.

[0132] like Figure 14 As shown, the semiconductor device 200C is a power conversion device with autonomous synchronous rectification full bridge, comprising: four first packages 1; a diode bridge 81 (second package); MOSFETs 86, 87, 88, and 89 (MOSFET elements for rectification); lead frames 91, 92, 93, and 94; gate electrode wirings 95, 96, 97, and 98; source electrode wirings 99, 100, 101, and 102 (wirings connecting the first packages 1 to MOSFETs 86, 87, 88, and 89); wirings 103, 104, 105, and 106; molding resin 107; and an opening 108.

[0133] Figure 14 The semiconductor device 200C shown uses a combination of four first packages 1 and MOSFETs to form a diode bridge circuit. Furthermore, as described above, the first package 1 houses a control IC chip 22 with autonomous synchronous rectification control function (e.g., Figure 3 ) and single-unit capacitor 21 (e.g. Figure 3 The encapsulation of ).

[0134] Four first packages 1 are connected to lead frames 91, 92, 93, and 94, which are connected to the drains of MOSFETs 86, 87, 88, and 89, respectively, via their respective drain terminals on the back side. Furthermore, the four first packages 1 are connected to MOSFETs 86, 87, 88, and 89 via their respective gate electrode wirings 95, 96, 97, 98, and source electrode wirings 99, 100, 101, and 102.

[0135] Semiconductor device 200C is entirely sealed with molding resin 107, forming a diode bridge 81 with self-synchronizing rectification function. In this case, the first package 1 is suitable for… Figure 3 and Figure 4 The first encapsulation of the structure shown.

[0136] Figure 15 yes Figure 14 Circuit diagram of the autonomous synchronous rectifier full-bridge power conversion device (semiconductor device 200C).

[0137] exist Figure 15 In the circuit structure of the semiconductor device 200C shown, the control IC chip of the first package 1 (not shown, see reference) Figure 5 Voltage conversion circuit (illustration omitted, refer to...) Figure 5 The output of the drive circuit 44 is connected to the drain of MOSFET 3, and the output of the drive circuit 44 is connected to the gates of MOSFETs 86, 87, 88, and 89. (Single capacitor omitted, see reference...) Figure 5 The capacitor terminal (negative voltage side) of the MOSFET is connected to the source of MOSFETs 86, 87, 88, and 89 as the low-potential power supply for the control IC chip. The control IC chip charges the individual capacitors when a positive voltage is applied to the drain of MOSFETs 86, 87, 88, and 89. The control IC chip applies a voltage between the gate and source of MOSFETs 86, 87, 88, and 89 to control their on / off states.

[0138] [Effects of the seventh implementation method]

[0139] According to the semiconductor device 200C of this embodiment, the diode bridge 81 with autonomous synchronous rectification can be made thinner, and the thermal resistance of the semiconductor device can be reduced, miniaturized, and its capacity increased. If the diode bridge 81 with such effects is applied, for example, as a power conversion device used as a rectifier diode for converting AC to DC power from commercial AC power (…),… Figure 18 This enables the miniaturization, large capacity, and high efficiency of the power conversion device.

[0140] Furthermore, the configuration of the circuitry driving MOSFETs 86, 87, 88, and 89 within the outer package (second package; diode bridge 81) can be changed to match the shape of the wiring and the orientation of the components. This also increases the freedom of setting the mounting holes for the heat sink fins, enabling the provision of a higher output and a smaller semiconductor device.

[0141] (Eighth Implementation)

[0142] Figure 16 This is an example of a power conversion device (semiconductor device) that is configured with an autonomous synchronous rectification full-bridge by the first package 1 of the semiconductor device according to the eighth embodiment. Regarding... Figure 14 Identical structural parts are labeled with the same symbols.

[0143] like Figure 16As shown, the semiconductor device 200D is a power conversion device with an autonomous synchronous rectification full-bridge, comprising: four first packages 1 (described later). Figure 17 ); diode bridge 81 (second package); MOSFETs 86, 87, 88, 89 (MOSFET elements for rectification); lead frames 91, 92, 93, 94; gate electrode wirings 95, 96, 97, 98; source electrode wirings 99, 100, 101, 102 (wirings connecting the first package 1 to MOSFETs 86, 87, 88, 89); drain electrode wirings 112, 113, 114, 115; wirings 103, 104, 105, 106; molding resin 107; and opening 108.

[0144] Figure 16 The semiconductor device 200D shown uses a combination of four first packages 1 and MOSFETs to form a diode bridge circuit.

[0145] Four first packages 1 are connected to lead frames 91, 92, 93, and 94, which are connected to the drains of MOSFETs 86, 87, 88, and 89, respectively, via their respective drain terminals on the back side. Furthermore, the four first packages 1 are connected to MOSFETs 86, 87, 88, and 89 via their respective gate electrode wirings 95, 96, 97, 98, and source electrode wirings 99, 100, 101, and 102.

[0146] Four first packages 1 are connected to lead frames 91, 92, 93, and 94, which are connected to the sources of MOSFETs 86, 87, 88, and 89, respectively, via their respective source terminals on the back side. Furthermore, the four first packages 1 are connected to MOSFETs 86, 87, 88, and 89T via their respective gate electrode wirings 95, 96, 97, and 98. Additionally, lead frames 91, 92, 93, and 94, which are connected to the drains of MOSFETs 86, 87, 88, and 89, and each first package 1 are connected to MOSFETs 86, 87, 88, and 89 via drain electrode wirings 112, 113, 114, and 115.

[0147] The semiconductor device 200D is entirely sealed with molding resin 107, forming a diode bridge 81 with autonomous synchronous rectification function. In this case, the first package 1 is suitable for… Figure 17 The encapsulation of the structure shown.

[0148] Figure 17 It means Figure 16 A side view (side perspective view) of the structure of the first package 1 of the semiconductor device 200D. (For comparison with...) Figure 12 Identical structural parts are labeled with the same symbols.

[0149] exist Figure 17In the first package 1 shown, MOSFE86, 87, 88, 89 ( Figure 16 Terminals 26 and 25, which are connected to the drain and gate of MOSFE86, 87, 88, and 89, are exposed from the surface 1a of the first package 1, and terminal 24, which is connected to the source of MOSFE86, 87, 88, and 89, is exposed from the back side 1b of the first package 1.

[0150] [Effects of the Eighth Implementation]

[0151] The semiconductor device 200D according to this embodiment, similar to the semiconductor device 200C of the seventh embodiment, can achieve a thinner diode bridge 81 for autonomous synchronous rectification, and can achieve a reduction in thermal resistance, miniaturization, and increased capacity of the semiconductor device. If the diode bridge 81 with such effects is applied to a power conversion device (… Figure 18 This enables the miniaturization, large capacity, and high efficiency of the power conversion device.

[0152] (Ninth Implementation)

[0153] The power conversion device according to the ninth embodiment of the present invention will be described.

[0154] Figure 18 This is a block diagram showing the circuit structure of the power conversion device according to the ninth embodiment of the present invention.

[0155] Figure 18 This illustrates, for example, a power conversion device 300 that converts power from an input AC power source 301 to a DC output 302 from a commercial power source.

[0156] The power conversion device 300 includes semiconductor devices 200, 200A to 200D, a power factor correction (PFC) circuit 310 that suppresses high-order harmonic components to a low level and makes the power factor close to 1, a smoothing capacitor 320, and a DC / DC conversion circuit 330.

[0157] Semiconductor devices 200, 200A to 200D are, for example, diode bridges.

[0158] [Effects of the Ninth Implementation Method]

[0159] According to the power conversion device 300 of this embodiment, by applying the semiconductor devices 200, 200A, 200B, 200C, and 200D of the first to eighth embodiments to the power conversion device 300, the power conversion device 300 can be miniaturized, have a large capacity, and be highly efficient.

[0160] This invention is not limited to the embodiments described above. Other modifications and applications are included as long as they do not depart from the spirit of the invention as set forth in the claims. For example, the embodiments described above are given in detail to aid in understanding the invention and are not necessarily limited to all the described structures. Furthermore, a portion of the structure of one embodiment can be replaced with the structure of another embodiment, and the structure of another embodiment can be added to the structure of one embodiment. Additionally, regarding a portion of the structure of each embodiment, other structures can be added, deleted, or replaced.

[0161] For example, the chip configuration and wiring of the semiconductor elements constituting semiconductor devices 200, 200A, 200B, 200C, and 200D are not limited to the manner shown in the figure.

[0162] As a semiconductor device, besides MOSFETs, it can also be any of the following: unipolar devices such as JFETs (Junction Field Effect Transistors) and bipolar devices such as IGBTs. Furthermore, depending on the device, the main terminal and sensing terminal are referred to as "collector" and "emitter" instead of the aforementioned "drain" and "source".

[0163] Symbol Explanation

[0164] 1: First package (package housing the control IC chip and individual capacitors), 1a: Surface of the first package, 1b: Back side of the first package, 1c: Side of the first package, 2: Second package (outer package), 3, 51, 52, 87 to 89: MOSFET (MOSFET element for power conversion), 4: Lead frame (wiring connecting the control IC chip to the electrodes of the MOSFET element and external electrical connections), 5: Wiring (wiring connecting the electrodes of the MOSFET element to external electrical connections), 6: Source electrode connection 7: Gate electrode wiring (wiring that electrically connects the control IC chip to the electrodes of the MOSFET element), 8, 33, 107: Molding resin (molded parts), 9, 10, 11, 12, 13, 34, 35, 36: Bonding materials (solder, conductive paste, etc.), 21: Single capacitor, 22: Control IC chip, 23: Terminal (lead frame) (the terminal to which the drain, source, and gate electrodes of the MOSFET element are connected) (terminal 23 in...) Figure 9 as well as Figure 10 The fourth lead frame is in the middle, 24 and 25: terminals (lead frames) (terminals connected to the drain, source, and gate electrodes of the MOSFET element) (the second lead frame connected to the source and gate electrodes of the MOSFET element) (terminal 24 is in Figure 9and Figure 10 26: Wireframe (third lead frame connected to the drain electrode of the MOSFET element), 27: Capacitor terminal on the positive voltage side of the single capacitor (one terminal of the single capacitor), 28: Capacitor terminal on the negative voltage side of the single capacitor (terminal connected to the other terminal of the single capacitor, the drain electrode, source electrode and gate electrode of the MOSFET element), 55, 56, 57: Wireframe (first lead frame housing the MOSFET element and the first package), 81: Diode bridge (second package), 91, 92, 93, 94: Wireframe, 95, 96, 97, 98: Gate electrode wiring, 99, 100, 101, 102: Source electrode wiring (wiring connecting the first package and the MOSFET element), 103, 104, 105, 106: Wiring, 108: Through hole, 200, 200A, 200B, 200C, 200D: Semiconductor device, 300: Power conversion device.

Claims

1. A semiconductor device for power conversion, characterized in that, have: The first package includes a control IC chip for controlling MOSFET elements for power conversion and a single capacitor for supplying power to the control IC chip. The MOSFET element, located outside the first package, is turned on and off by receiving control signals from the control IC chip. as well as The second package has wiring that electrically connects the control IC chip and the electrodes of the MOSFET element within the first package, and is formed by sealing the control IC chip, the MOSFET element, and the wiring through a molding component.

2. The semiconductor device according to claim 1, characterized in that, One terminal of the single capacitor in the first package is connected to the source electrode of the MOSFET element, and the other terminal of the single capacitor is connected to the drain electrode of the MOSFET element via the circuit of the control IC chip.

3. The semiconductor device according to claim 1, characterized in that, The first package has terminals that are connected to the drain electrode, source electrode, and gate electrode of the MOSFET element. The terminal is formed on the first main surface side or the second main surface side of the back of the control IC chip within the first package.

4. The semiconductor device according to claim 3, characterized in that, The second package includes a first lead frame housing the MOSFET element and the first package, wherein the terminals of the first package are connected to the drain electrode or source electrode of the MOSFET element through the first lead frame.

5. The semiconductor device according to claim 1, characterized in that, The first package has terminals for connecting the drain electrode, source electrode, and gate electrode of the MOSFET element. At least one of the terminals is formed in the side direction of the first package.

6. The semiconductor device according to claim 4, characterized in that, The first package includes a second lead frame connected to the source electrode and the gate electrode of the MOSFET element, and a third lead frame connected to the drain electrode of the MOSFET element. A portion of the second lead frame is exposed as a recess from the back of the first package, and this recess is electrically connected to the source and gate electrodes of the MOSFET element. The third lead frame is exposed from the side of the first package, connected to the first lead frame, and connected to the drain electrode of the MOSFET element via the first lead frame.

7. The semiconductor device according to claim 1, characterized in that, The first package includes a fourth lead frame for connecting the control IC chip and the individual capacitor. A portion of the fourth lead frame is exposed as a terminal from the surface or back of the first package, and the terminal of the individual capacitor is connected to this terminal.

8. The semiconductor device according to claim 1, characterized in that, The applied voltage of the individual capacitor is less than four times the threshold voltage of the MOSFET element.

9. The semiconductor device according to any one of claims 1 to 8, characterized in that, The first package and the MOSFET element constitute a rectifier bridge circuit with the function of synchronous rectification.

10. A power conversion device, characterized in that, A semiconductor device having any one of claims 1 to 9.

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