Integrated circuit die stack with double-sided bridge die

Abstract

Disclosed herein is a dual-sided bridge die, an integrated circuit die package assembly having a dual-sided bridge die, and a method for manufacturing an integrated circuit die package assembly. A dual-sided bridge die includes a substrate; a first redistribution layer constructed on a top surface of the substrate and configured to couple with a bottom surface of a first integrated circuit die; and a second redistribution layer constructed on a bottom surface of the substrate and configured to couple with a top surface of a second integrated circuit die. The top surface and the bottom surface of the substrate are disposed on opposite sides of the substrate, respectively.

Description

Technical Field

[0001] Embodiments of the present invention generally relate to integrated circuit die stacks with double-sided bridging dies, and more specifically, to integrated circuit die stacks with double-sided bridging dies that enable lateral communication between integrated circuit dies at both lower and higher levels. Background Technology

[0002] Electronic devices such as tablets, computers, copiers, digital cameras, smartphones, control systems, and ATMs typically utilize chip-packaged assemblies to enhance functionality. To improve processing power, chip packaging solutions often involve vertically mounting multiple integrated circuit dies onto a packaging substrate to form a die stack. This integrated circuit die stack can include dies used for memory, logic, communication, power management, or other functions.

[0003] In integrated circuit die stacking, dies at the same or different levels typically need to communicate with each other at high speed and with high integrity. Current die stacking designs do not yet provide an effective solution for such high-speed and high-integrity lateral communication.

[0004] Therefore, an improved integrated circuit die stacking method is needed. Summary of the Invention

[0005] This document discloses a double-sided bridging die, an integrated circuit die package assembly having the double-sided bridging die, and a method for manufacturing the integrated circuit die package assembly. A double-sided bridging die includes a substrate; a first redistribution layer formed on a top surface of the substrate and configured to be coupled to a bottom surface of a first integrated circuit die; and a second redistribution layer formed on the bottom surface of the substrate and configured to be coupled to a top surface of a second integrated circuit die. The top surface and the bottom surface of the substrate are respectively disposed on opposite sides of the substrate.

[0006] According to one embodiment, the integrated circuit die packaging assembly includes a packaging substrate and an integrated circuit die stack. The integrated circuit die stack includes a plurality of integrated circuit dies disposed at a first level of the stack; a plurality of integrated circuit dies disposed at a second level vertically stacked above the first level; and a plurality of integrated circuit dies disposed at a third level vertically stacked above the second level. The plurality of integrated circuit dies at the second level include double-sided bridging dies configured to provide lateral communication for at least two dies at the first level and for at least two dies at the third level.

[0007] According to another embodiment, an integrated circuit die packaging assembly includes a packaging substrate and an integrated circuit die stack disposed above the packaging substrate. The integrated circuit die stack includes: a plurality of first-level integrated circuit dies and second-level integrated circuit dies, the first-level and second-level integrated circuit dies being disposed at a first level of the integrated circuit die stack. The integrated circuit die includes: a double-sided bridging die disposed at a second level, the second level being vertically stacked above and partially overlapping the first-level and second-level integrated circuit dies. The integrated circuit die includes: a first third-level integrated circuit die disposed at a third level, the third level being vertically stacked above and partially overlapping the double-sided bridging die disposed at the second level. The double-sided bridging die is configured to provide lateral communication between at least the first-level integrated circuit die and the first third-level integrated circuit die.

[0008] According to one embodiment, a method of manufacturing an integrated circuit die package assembly includes mounting a plurality of integrated circuit dies of a first level on a first level; disposing a plurality of integrated circuit dies of a second level on top of the integrated circuit dies of the first level, the plurality of integrated circuit dies of the second level including double-sided bridging terminals; disposing a plurality of integrated circuit dies of a third level on top of the integrated circuit dies of the second level; forming an integrated circuit die stack by connecting the integrated circuit dies of the first level, the second level, and the third level; and mounting the integrated circuit die stack on a package substrate. The connection includes connecting the double-sided bridging terminal to at least two integrated circuit dies of the first level and at least two integrated circuit dies of the third level. According to one embodiment, a method of manufacturing an integrated circuit die package assembly includes: mounting a double-sided bridging die to a first-level integrated circuit die and a second-level integrated circuit die, the first-level integrated circuit die and the second-level integrated circuit die defining a first level, and the double-sided bridging die defining a second level; mounting a first-level third-level integrated circuit die of a third level on the double-sided bridging die to form an integrated circuit die stack; and mounting the integrated circuit die stack on a package substrate. Attached Figure Description

[0009] To gain a more detailed understanding of the above-described features of the invention, a more specific description of the invention, which has been briefly summarized above, can be obtained by referring to embodiments, some of which are illustrated in the accompanying drawings. However, it should be noted that the drawings illustrate only typical embodiments of the invention and should therefore not be considered as limiting the scope of the invention, as other equivalent embodiments are permissible.

[0010] Figure 1a illustrates a schematic cross-sectional view of an electronic device having an integrated circuit die stack according to one embodiment of the present application, the integrated circuit die stack having a double-sided bridging die.

[0011] Figure 1b illustrates a schematic top view of an IC die stack according to one embodiment of this application.

[0012] Figure 2a illustrates a schematic close-up view of a three-level IC die stack having double-sided bridge die at each level according to one embodiment of the present application.

[0013] Figure 2b illustrates a schematic close-up view of a three-level IC die stack having double-sided bridge die at both the first and third levels according to one embodiment of the present application.

[0014] Figure 2c illustrates a schematic configuration of an IC die stack including a double-sided bridge die connected to other die stacks according to one embodiment of this application.

[0015] Figure 3a is a schematic cross-sectional view of a double-sided bridge pipe core with passive devices according to one embodiment of the present application.

[0016] Figure 3b illustrates a schematic cross-sectional view of another double-sided bridge core with passive devices according to one embodiment of this application.

[0017] Figure 3c illustrates a schematic cross-sectional view of another double-sided bridge core with active devices according to one embodiment of this application.

[0018] Figure 4 An illustrative manufacturing process for manufacturing a double-sided bridge pipe core according to one embodiment of this application is shown.

[0019] Figure 5 An illustrative manufacturing process for manufacturing a bridge tube core with two redistribution layers is shown according to one embodiment of this application.

[0020] Figure 6 An illustrative manufacturing process for manufacturing an IC die stack with double-sided bridge dies is illustrated according to one embodiment of this application.

[0021] Figure 7 An example of a method for manufacturing an integrated circuit die package assembly having a double-sided bridge die is illustrated according to one embodiment of the present application.

[0022] For ease of understanding, the same reference numerals are used where possible to denote common elements in the figures. It is conceivable that elements of one embodiment can be advantageously incorporated into other embodiments. Detailed Implementation

[0023] A double-sided bridging die with two redistribution layers is disclosed. The double-sided bridging die enables lateral communication between integrated circuit dies at both lower and higher levels. The double-sided bridging die is configured to include passive devices, such as capacitors, adjacent to the input and / or output wiring of the double-sided bridging die. The double-sided bridging die may also include active devices, such as active circuitry. A chip package using the double-sided bridging die includes redistribution layers constructed on the top and bottom surfaces of a substrate, such as silicon, glass, or any other suitable substrate. The redistribution layer at the top surface is connected to other integrated circuit dies disposed in higher levels via high-density interconnects, such as thermo-pressed joints, hybrid joints, microbumps, or any other suitable interconnects. The redistribution layer at the bottom surface is also connected to other integrated circuit dies disposed in lower levels via high-density interconnects, such as thermo-pressed joints, hybrid joints, microbumps, or any other suitable interconnects. The spacing of the hybrid joints is denser than connections made via wire bonding or solder balls, thus enabling high-density, high-speed data transmission. Integrated passive and / or components (such as capacitors and active circuitry) can be included in the redistribution layer or substrate. Having connectors on both sides of the double-sided bridging die also reduces warpage by increasing the mechanical stiffness of the chip package architecture, making the chip package more robust and reliable. Furthermore, the double-sided bridging die shortens the wiring distance between IC dies within the chip package, thereby increasing processing speed while advantageously improving signal integrity.

[0024] Turning now to Figure 1a, an exemplary integrated circuit (IC) die package assembly 110 is disposed on a printed circuit board (PCB) 136 and connected to the PCB 136 via a plurality of electrical connections 138 (such as solder balls or other suitable connectors). The IC die package assembly 110 and the PCB 136 together form at least a portion of an electronic device 100. The electronic device 100 may be a tablet device, computer, copier, digital camera, smartphone, control system, ATM, server, or other solid-state memory and / or logic device.

[0025] IC die package assembly 110 includes an IC die stack 104 mounted to an optional interposer 112. According to one embodiment, the IC die stack 104 can be directly mounted to a package substrate 122. IC die package assembly 110 also includes an optional reinforcement 140 coupled to the package substrate 122 and configured to enhance the anti-warping properties of the package substrate 122 against out-of-plane deformation. IC die package assembly 110 also includes a cover 128 configured to cover the IC die stack 104 and dissipate heat generated by the IC die package assembly 110.

[0026] IC die stack 104 includes multiple levels of IC dies stacked vertically to each other. For example, four levels of IC dies are shown in Figure 1a: first level 130, second level 132, third level 134, and fourth level 144. IC dies in the same level are configured to be substantially coplanar with each other. According to one embodiment, IC die stack 104 is not limited to only four levels of IC dies, and may include five (5) or even more IC die levels. The IC dies disposed at the first level 132 include two IC dies 114. The dies 114 at the first level 130 may be directly connected to the interposer 112 or the package substrate 122. Connectors between the multiple levels of IC dies may include solder balls, microbumps, thermo-pressed joints, hybrid joints, through-silicon vias, or other suitable connectors.

[0027] As shown in Figure 1a, two IC dies 124 and a double-sided bridging die 106 are disposed in the second layer and vertically stacked above IC die 114. According to one embodiment, the two IC dies 114 in the lower layer are configured to communicate with each other via the double-sided bridging die 106 disposed in the second layer 132. The two IC dies 114 can also communicate with each other via an interposer layer 112. According to one embodiment, the double-sided bridging die 106 includes multiple integrated passive and / or active devices, such as capacitors, inductors, and active circuitry.

[0028] The number of dies in each level is not limited to two (2) or three (3) dies as shown in Figure 1a. Each level may include more dies, such as four (4), six (6), ten or even more dies. IC dies in the same level may include a single IC die, a stack of IC dies or a combination thereof.

[0029] Figure 1a also illustrates the relative dimensions of IC dies in different layers according to one embodiment. The length of each die is shown in the horizontal direction, while the height of each die is shown in the vertical direction. In one example, a double-sided bridging die 106 disposed at the second layer 132 is connected to an IC die 114 of the first layer 130. As a result, the length of the double-sided bridging die 106 is greater than the length of the gap 115 formed between the IC dies 114. Each IC die 114 may overlap with both the double-sided bridging die 106 and the IC die 124. In one example, the length of the top surface of the IC die 114 is configured to be greater than the length of the bottom surface of the IC die 124, such that the bottom surface of the IC die 124 is completely mounted on the top surface of the IC die 114. Therefore, each IC die in the IC die 114 may have a larger dimension than the IC die 124. For example, the IC die 114 has a top surface area (length × width) greater than the bottom surface area of ​​the IC die 124.

[0030] In one embodiment, the double-sided bridging connector 106 and the IC die 124 are connected to the IC die 114 via a plurality of hybrid connectors. The double-sided bridging connector 106 is configured to provide high-speed and high-integrity data transmission between the dies 114 located at the first level 130.

[0031] In the example depicted in Figure 1a, two IC dies 146 are disposed at a third level 134 and are vertically stacked above IC die 124 and double-sided bridging die 106. According to one embodiment, the two IC dies 146 at the third level 134 are configured to communicate with each other via the double-sided bridging die 106 disposed at a second level 132. In one embodiment, the double-sided bridging die 106 includes wiring connectors and hybrid bonding elements on both the top and bottom surfaces for connection to IC dies 114 and 146. The use of hybrid bonding elements reduces the contact pitch, and the bonding elements on both the top and bottom surfaces advantageously improve the rigidity of the chip package, which improves the reliability of solder and other chip-to-chip connections. The double-sided bridging die 106 allows lateral communication between multiple IC dies at the same level, which is above or below the double-sided bridging die 106, whereas in a conventional package these communications would require vertical routing down to the substrate and then back up to the die. Therefore, the double-sided bridging connector 106 shortens the wiring distance between dies at different levels, thereby improving signal integrity and processing performance. The double-sided bridging connector 106 can also be configured to provide communication between IC dies at different levels, such as between IC die 146 at the third level and IC die 114 at the first level.

[0032] In the example depicted in Figure 1a, the fourth layer 144 includes a fill die 126 configured to fill the space between the third layer 134 and the cap 128. The fill die 126 is configured to raise the height of the IC die stack 104 to the same height as the reinforcement 140. The fill die 126 may include a semiconductor substrate, such as a silicon substrate. In one example, the fill die 126 forms a non-conductive contact with and is not electrically connected to the die 124. Similarly, the IC die stack 104 is not limited to only four layers. The IC die stack 104 may include more or fewer IC die layers. Additionally, each layer may include more or fewer IC dies. In another example, the fourth layer 144 may include multiple IC dies, which may include double-sided bridging dies.

[0033] IC dies 114, 124, and 146 can be programmable logic devices, such as field-programmable gate arrays (FPGAs), memory devices, optical devices, processors, or other IC logic structures. Interconnects between different levels of IC dies can include hybrid bonding pads or micro-solder balls. IC die stack 104 is mounted to the top surface of interposer 112 via die connectors 118. Die connectors 118 can be in the form of multiple solder points, also known as "microbumps".

[0034] Interposer 112 includes circuitry for electrically connecting IC die stack 104 to circuitry on package substrate 122. Solder connectors 120 (also referred to as “package bumps” or “C4 bumps”) provide electrical connections between the circuitry of interposer 112 and the circuitry of package substrate 122. Package substrate 122 may be mounted and connected to PCB 136 using solder balls 138, sockets, wire bonding, or other suitable techniques.

[0035] The lower mold 142 can be used to fill the space not occupied by the solder connector 120 between the PCB 136 and the interposer 112 or the package substrate 122. The gap filler material 116 can be used to fill the gaps within the IC die stack 104.

[0036] Figure 1b illustrates a schematic top view of an IC die stack 104 according to one embodiment. Multiple IC dies are mounted on an interposer layer 112. The multiple IC dies include: IC dies 114a, 114b, 114c, and 114d at a first level; IC dies 124a, 124b, 124c, 124d and a double-sided bridging die 106 at a second level; and IC dies 146a, 146b, 146c, and 146d at a third level. Figure 2 also includes an illustration showing the IC dies or the fill pattern of each level. Fill die 126 is not shown in Figure 1b. The double-sided bridging die 106 is disposed between IC dies 146 and IC dies 114 and is configured to provide data communication between IC dies 146 and between IC dies 114. The IC dies may be separated by gaps 115. IC dies can communicate with each other via an interposer 112 and / or a double-sided bridge dies 106. IC dies 114a, 114b, 114c, and 114d are connected to multiple IC dies in the second level. For example, two IC dies 124a and 124c are mounted on the top surfaces of IC dies 114a and 114c, respectively. In one embodiment, the IC die can be connected to the interposer 112 and not directly connected to any other IC die.

[0037] In one embodiment, IC dies 114a to 114d are coupled to double-sided bridging die 106 for high-speed and high-integrity communication. As shown in FIG1b, a portion of each of the IC dies 114a to 114d is disposed below and overlaps a portion (such as a corner) of the double-sided bridging die 106. Hybrid bonding member 202 electrically and mechanically connects the overlapping portions of the IC dies 114a to 114d and the double-sided bridging die 106 to enable communication between them while also increasing the warp resistance of the chip package. For example, IC die 114a at the first level can communicate with any of the IC dies 114b, 114c, and 114d via the double-sided bridging die 106. IC dies 146a and 146b at the third level are also coupled to the double-sided bridging die 106 for high-speed and high-integrity communication. As shown in Figure 1b, a portion of each of the IC dies 146a and 146b is disposed above and overlaps a portion (such as a corner) of the double-sided bridging die 106. The hybrid connector 202 electrically and mechanically connects the overlapping portions of the IC dies 146a and 146b and the double-sided bridging die 106 to enable communication between them, while also increasing the warp resistance of the chip package. Therefore, because the wiring distance between the dies is shortened via the double-sided bridging die 106, it can provide faster and more robust data communication than the interposer 112.

[0038] As discussed above, the double-sided bridging die 106 is connected to a plurality of IC dies 114a to 114d and 146a to 146b via hybrid bonding members 202. The hybrid bonding members 202 are disposed on both the top and bottom surfaces of the double-sided bridging die 106. The hybrid bonding members include metal-to-metal bonding members formed by a hybrid bonding process. For example, pressure and heat can be used to form metal-to-metal bonding members to form eutectic metal bonding members. The hybrid bonding members can be formed by bonding dielectric material around bonding pads to first secure the IC die, and then fusing the metal materials of the bonding pads together to create electrical interconnects. The dielectric material around the bonding pads is selected from materials suitable for hybrid bonding to another dielectric material. Materials suitable for hybrid bonding include polybenzoxazole (PBO), polyimide (PI), benzocyclobutene (BCB), combinations thereof, etc. According to one embodiment, the spacing between the hybrid bonding members 202 is less than 10 μm, 5 μm, or 1 μm. The hybrid bonding of the double-sided bridging die 106 provides a significantly denser connection spacing than wire bonding or micro-solder balls. Therefore, the communication bandwidth between hybrid-bonded IC dies is significantly greater than that of conventional devices. Other connectors, such as thermo-pressed joints and micro-bumps, can also be used to connect the double-sided bridging die to other IC dies.

[0039] In one embodiment, the hybrid joints 202 of the double-sided bridging connector core 106 are interconnected via a plurality of wiring connectors 204 (shown in FIG. 2). The plurality of wiring connectors 204 may include metal traces formed in a stacked layer. The wiring connectors 204 terminate at hybrid bonding pads configured to form one side of the hybrid joint 202.

[0040] As shown in Figure 1b, the IC die may include multiple through-silicon vias (TSVs) 206, such as 206a and 206b. TSV 206a connects the bridging die 106 to IC dies at the first and third levels. TSV 206b connects IC dies 124a, 124b, 124c, and 124d at the second level to IC dies 114a, 114b, 114c, and 114d at the first level. TSV 206 provides vertical connections between IC dies at different levels. TSV 206 can transmit several types of signals, including power, ground connections, data signals, test signals, control signals, timing signals, encryption signals, or any other signals transmitted from one die to another. The double-sided bridging die 106 may also include multiple TSVs 210 connected to adjacent levels of other IC dies. The inclusion of TSV 206a in the double-sided bridging die 106 increases design flexibility by not limiting the TSV to certain areas of the IC die in the layer adjacent to the adjacent double-sided bridging die 106. In other words, the ability to use TSV 206a in addition to TSV 206b allows for greater flexibility in power, grounding, and signal routing, ultimately improving signal integrity and device performance.

[0041] Figure 2a illustrates a schematic configuration of the first, second, and third layers of an IC die stack 104 according to one embodiment. As described above, a double-sided bridging die 106 is disposed at the second layer 132. The bottom side of the double-sided bridging die 106 is connected to two dies 114a and 114b disposed at the first layer 130. The top surface of the double-sided bridging die 106 is connected to two dies 146a and 146b disposed at the third layer 134. Compared to a single-sided bridging die with connectors only at one of the bottom or top surfaces, the double-sided bridging die 106 has better warpage resistance due to the mechanical connections at both the bottom and top surfaces. The double-sided bridging die 106 also provides more connectors and higher speeds than a single-sided bridging die.

[0042] In one example, the bottom surface of the double-sided bridging connector 106 directly covers and connects to the lower-level dies, while the top surface of the double-sided bridging connector 106 lies directly beneath and connects to the higher-level dies. IC dies 114a and 114b can have larger dimensions than IC dies 124a and 124b. IC dies 146 and 146b can also have larger dimensions than IC dies 124a and 124b. Therefore, IC die 124a is entirely disposed on the top surface of IC die 114a or the bottom surface of IC die 146a. Because IC dies 114a and 146a are larger than IC die 124a, IC dies 114 and 146 have sufficient space for the wiring required to establish high-density interconnects. According to one embodiment, the double-sided bridging connector 106, as well as dies 114 and 146, are connected via multiple hybrid connectors 202a and 202b.

[0043] The gap 212 between dies 114a and 114b is filled with a gap filler material 116, such as a dielectric material. The gap filler material 116 also fills other gaps formed between dies located at the second and third layers. Die 114a at the first layer is not limited to being connected to only two dies at the second layer. Die 114a can be connected to three, four, or five IC dies at the second layer. According to one embodiment, at least one die at the second layer connected to die 114 is configured as a double-sided bridging die, which provides lateral data communication between die 114 at the first layer and die 146 at a higher layer.

[0044] According to one embodiment, the double-sided bridging die 106 is coupled to IC dies 114 and 146 via any suitable connector, such as a hybrid connector, BEOL, thermoforming connector, or micro-solder ball. IC dies 114, 124, and 146 may also include multiple TSVs 206. The double-sided bridging die 106 may also include TSVs 210a and 210b coupled to TSVs 206. For example, the TSV 206 of IC die 146a may be coupled to the TSV 210a of the double-sided bridging die 106, which in turn is coupled to the TSV 206 of IC die 114a.

[0045] Figure 2b illustrates a schematic configuration of an IC die stack 150 according to one embodiment. The IC die stack 150 includes three (3) levels 130, 132, and 134 of IC dies, respectively. One or more additional levels of IC dies may be provided on the first and / or second levels. Double-sided bridging dies may be provided in two or more IC dies and are configured to provide interconnects between IC dies at lower and / or higher levels, and / or to provide interconnects to substrate 122 or interposer 112. By having double-sided bridging dies in multiple levels, wiring between interconnect dies in different levels can be shortened to improve performance and increase signal integrity. For example, a double-sided bridging die 166 is disposed at the third layer 134 together with IC dies 146a to 146c; another double-sided bridging die 164 is disposed at the second layer 132 together with IC dies 124a to 124b; and another double-sided bridging die 162 is disposed at the first layer together with IC dies 114a to 114c. The bottom surface of the double-sided bridging die 166 is coupled to IC dies 124a and 124b. The top surface of the double-sided bridging die 166 may be coupled to an IC die, interposer, or substrate (not shown) of another layer. The double-sided bridging die 164 at the second layer 132 may be configured similarly to the bridging die 106 shown in FIG. 2a. The bottom surface of the double-sided bridging die 164 is coupled to IC dies 114a and 114b. The top surface of the double-sided bridging die 164 is coupled to IC dies 146a and 146b. When the double-sided bridging die 162 is disposed in the first layer, the double-sided bridging die 162 is connected to IC dies 124b and 124b and the interposer 112 or package substrate 122. The double-sided bridging die 166 can be connected to the double-sided bridging die 162 via TSVs 206 and 210 for direct connection to other layers (not shown) without utilizing space within the die of other layers.

[0046] Figure 2c illustrates a schematic configuration of an IC die stack 160 according to one embodiment. The IC die stack 160 may have more levels of IC dies, but Figure 2c shows only two levels. Compared to dies 114a and 114b in Figure 2a, the first level 130 of the IC die stack 160 may include other die stacks, such as IC die stacks 152a and 152b, each serving as an electronic device. For example, IC die stack 152a includes four (4) IC dies 1521a, 1522a, 1523a, and 1524a stacked on top of each other, wherein die 1521a is connected to a double-sided bridge die 106. IC die stack 152b includes two (2) dies 1521b and 1522b stacked on top of each other, which are then mounted on the top surface of die 114b. Molding compound 182a can be used to fill the space defined between IC dies 1522a and 114a within stack 152a. Molding compound 182a can also be used to fill the space defined between IC dies 1524a and 114a, and the space defined between IC dies 1522a and 1523a within stack 152a. IC die stack 152b similarly has molding compound 182b filling the gap spaces within IC die stack 152b. As shown in FIG. 2c, IC die 1522b is connected to IC die 1521a via the bottom surface of double-sided bridging die 106. The top surface of double-sided bridging die 106 can be used to connect to a die of another layer or substrate or interposer (not shown). In another example, one of the IC die stacks 152a and 152b may be formed from a single die, while the other IC die stacks may be formed from multiple layers of IC dies. In one embodiment, the top surfaces of IC dies 1521a and 1522b are substantially coplanar, such that they are connected to the double-sided bridging die 106. When the IC die stacks 152a and 152b may not have similar heights, gap filler material 116 or IC dies may be used to increase the height of the device.

[0047] Figure 3a illustrates a schematic cross-sectional view of a double-sided bridging core 106 according to one embodiment. The double-sided bridging core 106 includes a substrate 302, a bottom stacked layer 304, and a top stacked layer 306. The double-sided bridging core 106 also includes a plurality of TSVs 308. The substrate 302 may be a silicon substrate, a glass substrate, a silicon carbide substrate, a germanium substrate, or other suitable substrate. Stacked layers 304 and 306 may also be referred to as redistribution layers (RDLs). The bottom stacked layer 304 includes wiring connectors 312 connected to hybrid bonding pads 310 disposed on the bottom surface 316 of the double-sided bridging core 106. The top stacked layer 306 includes wiring connectors 322 connected to hybrid bonding pads 320 disposed on the top surface 326 of the double-sided bridging core 106. Passive and / or active devices 314, 324 may be further integrated into the bottom stacked layer 304 and the top stacked layer 306, respectively. Some examples of passive devices 314 include capacitors, inductors, resistors, sensors, transducers, circuit protection devices, piezoelectric devices, resonators, switches, etc. Some examples of active devices 324 include diodes, rectifiers, varactor diodes, transistors, thyristors, etc.

[0048] Each of stacked layers 304 and 306 includes two or more metal layers patterned to form metal wiring defining wiring connectors 312 and 322. Dielectric layers are disposed between the metal layers to prevent short circuits between the wiring connectors. The wiring connectors terminate at hybrid bonding pads used to form one side of hybrid bonding pads 202a and 202b that electrically and mechanically connect the wiring connectors of the double-sided bridging core 106 to the other cores.

[0049] According to one embodiment, devices 314 and 324 may include passive devices, such as capacitors, resistors, inductors, etc., integrated in the stacked layer to improve power or signal integrity. The passive devices are connected to other IC dies connected to the double-sided bridge die 106 via wiring connectors. The passive devices can improve the signal quality transmitted by the wiring connectors. In one embodiment, the passive devices may be disposed in the stacked layer and adjacent to signal wiring connectors 312 and 322. In another embodiment, the passive devices may also be disposed in the substrate.

[0050] Figure 3b illustrates a schematic cross-sectional view of a double-sided bridging core 300 according to one embodiment. The double-sided bridging core 300 includes a bottom stack layer 304 and a top stack layer 306. In one embodiment, the bottom stack layer 304 and the top stack layer 306 may have the same arrangement of wiring connectors and hybrid connectors. In another embodiment, the two stack layers have different arrangements of wiring connectors and hybrid connectors. For simplicity, Figure 3b only annotates the components of the bottom stack layer 304. The stack layer 304 includes a plurality of integrated passive devices 340 disposed adjacent to wiring connectors 342. A first connector 344 connects the wiring connectors 342 to the integrated passive devices 340. The wiring connectors 342 may also be connected at a position adjacent to the integrated passive devices 340 via a second connector 346. In this way, one integrated passive device 340 may be shared by multiple wiring connectors 342.

[0051] Figure 3c illustrates a schematic cross-sectional view of a double-sided bridge housing 350 having one or more integrated active devices according to one embodiment. The double-sided bridge housing 350 includes one or more active devices 352 and 354. The active devices 352 and 354 may be disposed in a substrate 302 or in a stacked layer 304 or 306. The active devices may serve as memory controller circuitry, including an on-package memory controller 352 and an off-package memory controller 354. The on-package memory controller circuitry 352 is configured to control memory disposed within package 110. The off-package memory controller circuitry 354 is typically configured to control communication with memory not within chip package 110 (e.g., remote from the chip package). In one example, the off-package memory controller circuitry 354 is configured to communicate via a package substrate with one or more memory devices mounted to a PCB; in other words, memory devices located within electronics 100 but not within chip package 110. In addition to the active devices 352 and 354, the double-sided bridge core 350 may also include one or more passive devices 314 and 324.

[0052] In one example, memory controller circuits 352 and 354 include one or more active circuits such as interconnect circuits, last-level cache (HALL) circuitry for high-bandwidth memory attachments, tag circuitry, memory circuitry, memory controller circuitry, memory devices, and direct memory access (DMA) circuitry. Silicon bridge 330 may include consensus station circuitry comprising N consensus station circuits. The HALL circuitry comprises N HALL circuits, the tag circuitry comprises N tag circuits, and the memory controller circuitry comprises N memory controller circuits. N is greater than 1. In one example, N is 2, 4, or 8 or a larger number.

[0053] Figure 4This is an illustrative manufacturing process 400 for manufacturing a double-sided bridging tube dies 106 according to one embodiment of this application. At operation 402, two single-sided bridging tube dies 430 are formed in a substrate 420, such as a silicon wafer. Each single-sided bridging tube die 430 has a TSV 434, passive / active devices 432, and a stacked layer 304. The stacked layer 304 is formed and exposed only on one side of the single-sided bridging tube die 430.

[0054] At operation 404, substrate 420 and single-sided bridging core 430 are attached together to carrier 1. Stacked layer 304 is in contact with carrier 1.

[0055] At operation 406, substrate 420 on the side opposite to stacked layer 304 is removed using any suitable method (such as grinding, milling, or any other suitable method). TSV is exposed. At operation 406, another substrate 438 with two single-sided bridging tube cores 436 is similarly formed and attached to carrier 2. Substrate 438 and single-sided bridging tube cores 436 are configured in a similar manner to substrate 420 and single-sided bridging tube cores 430. Stacked layer 307 of single-sided bridging tube cores 436 is in contact with carrier 2.

[0056] At operation 408, carrier 2 is flipped together with substrate 438. Then, the exposed sides of single-sided bridging cores 430 and 436 are attached to each other. The TSVs of single-sided bridging cores 430 and 436 are bonded to each other. The TSVs are connected. Operation 408 forms two double-sided bridging cores 106 between the two carriers, each double-sided bridging core having a bottom stacked layer 304 and a top stacked layer 306.

[0057] At operation 410, carrier 1 is removed, thereby exposing the stacked layer 304. A gap 440 is also formed to separate the two double-sided bridge pipe cores 106 from each other.

[0058] At operation 412, carrier 2 is partially removed, with a predetermined amount of spare material 422 remaining on the double-sided bridging connector die. The spare material 422, which serves as a height buffer, will be removed later when the double-sided bridging connector die 106 is mounted in the IC die stack. After operation 412, individual double-sided bridging connector dies 106 are formed, with the spare material 422 attached to the top surface of each double-sided bridging connector die.

[0059] Figure 5This is an illustrative manufacturing process 500 for manufacturing a bridging core 520 having two stacked layers, according to one embodiment of this application. Compared to a double-sided bridging core 106 with two stacked layers on opposite sides, the bridging core 520 has two stacked layers 514 and 516 disposed adjacent to each other. In one embodiment, the stacked layers 514 and 516 are disposed at the middle portion of the bridging core 520. Operation 502 is similar to operation 402, wherein two single-sided bridging cores 510 are formed in a substrate. Operation 502 forms two substrates, each substrate having two single-sided bridging cores. In the single-sided bridging core 510, the stacked layer 514 is exposed. In the single-sided bridging core 512, the stacked layer 516 is also exposed.

[0060] At operation 504, two substrates are attached to each other via exposed stacked layers 514 and 516. Operation 504 forms a bridging core 520 having two stacked layers 514 and 516. The two stacked layers 514 and 516 are adjacent to each other and disposed in the middle portion of the bridging core 520.

[0061] At operation 506, one substrate is removed, thereby exposing the TSV. At operation 506, the other substrate is partially removed, leaving spare material 522 attached to one side of the bridge die 520. A gap is also formed between the two silicon bridges 520 to separate them.

[0062] Figure 6 This is an illustrative manufacturing process 600 for manufacturing an IC die stack according to one embodiment of this application. Prior to operation 602, dies 114, 124, 146 and double-sided bridging die 106 have been manufactured. Dies 114, 124, 146 and double-sided bridging die 106 may have different heights. According to one embodiment, die 124 and double-sided bridging die 106 are disposed at the same level and each includes spare material 418 and 422 of a certain depth. Spare materials 418 and 422 have no electrical traces or devices and are designed to be removed by appropriate methods such as grinding, milling or other processes. Spare materials 418 and 422 are disposed on the passive side of die 124 and double-sided bridging die 106.

[0063] At operation 602, die 114 is mounted to carrier 1 to form the first layer of the IC die. Carrier 1 can be made of any material that can support the die during chip manufacturing, such as a silicon substrate or any other suitable substrate. Gap filler material 116 is deposited in the gaps between dies 114.

[0064] At operation 604, the mandrel 124 and the double-sided bridging mandrel 106 are mounted on top of the mandrel 114. A connection is formed between the double-sided bridging mandrel 106 and the mandrel 114. More gap filler material 116 is deposited to secure the mandrel 124 and the double-sided bridging mandrel 106.

[0065] At operation 606, spare materials 418, 422 and gap filler material 116 are removed by appropriate methods (such as grinding, milling, or any other suitable technique). As a result, die 124 and double-sided bridge die 106 have similar heights and the TSV is exposed. Operation 606 forms the second level of the IC die.

[0066] At operation 608, IC die 146 is positioned at the third layer. A connection is formed between double-sided bridging connector die 106 and die 146. Operations 602 to 608 can be repeated to add more layers and double-sided bridging connectors to the IC die stack.

[0067] At operation 610, carrier 2 is mounted on top of IC die 146. Carrier 2 holds the IC die stack together before the IC die stack is mounted on the interposer or package substrate.

[0068] At operation 612, remove carrier 1. Expose the bottom surface of the first layer. Now, the IC die stack can be mounted on the package substrate, interposer, or another substrate.

[0069] Figure 7 A method for manufacturing an integrated circuit die stack according to one embodiment of this application is illustrated. Multiple IC dies are manufactured prior to operation 702. Also according to... Figure 4 or Figure 5 The process shown manufactures a double-sided silicon bridge. At operation 702, a double-sided bridge die is mounted to a first-level integrated circuit die and a second-level die. The first-level die and the second-level die define a first level, and the double-sided bridge die defines a second level. At operation 704, a first-level integrated circuit die of the third level is mounted on the double-sided bridge die to form an integrated circuit die stack. At operation 706, the integrated circuit die stack is mounted on a packaging substrate. The dies of each level can be disposed together using a common carrier or arranged individually.

[0070] In addition to the examples described above, the disclosed techniques may also be expressed in the following non-limiting embodiments.

[0071] Example 1. A double-sided bridging die, the double-sided bridging die comprising: a substrate; a first redistribution layer formed on a top surface of the substrate and configured to be coupled to a bottom surface of a first integrated circuit die; and a second redistribution layer formed on a bottom surface of the substrate and configured to be coupled to a top surface of a second integrated circuit die, wherein the top surface and the bottom surface of the substrate are respectively disposed on opposite sides of the substrate.

[0072] Example 2. The double-sided bridging tube core according to Example 1, wherein the first redistribution layer and the second redistribution layer include a plurality of hybrid joints and wiring connectors.

[0073] Example 3. The double-sided bridge pipe core according to Example 2, wherein the spacing of the hybrid joint is less than 10 μm.

[0074] Example 4. The double-sided bridge pipe core according to Example 1, the double-sided bridge pipe core further includes passive devices and / or active devices.

[0075] Example 5. The double-sided bridge tube die according to Example 1, the double-sided bridge tube die further includes a plurality of through silicon vias.

[0076] Example 6. The double-sided bridge tube core according to Example 1, the double-sided bridge tube core further includes an active circuit disposed in the substrate.

[0077] Example 7. The double-sided bridging tube core according to Example 1, wherein the first redistribution layer and the second redistribution layer include the same arrangement of hybrid joints and wiring connectors.

[0078] Example 8. An integrated circuit die packaging assembly, the integrated circuit die packaging assembly comprising: a packaging substrate; and an integrated circuit die stack disposed above the packaging substrate, the integrated circuit die stack comprising: a first-level integrated circuit die and a second-level integrated circuit die, the first-level integrated circuit die and the second-level integrated circuit die being disposed at a first level of the integrated circuit die stack; a double-sided bridging die, the double-sided bridging die being disposed at a second level, the second level being vertically stacked above the first-level integrated circuit die and the second-level integrated circuit die and partially overlapping with the first-level integrated circuit die and the second-level integrated circuit die; and a first third-level integrated circuit die, the first third-level integrated circuit die being disposed at a third level, the third level being vertically stacked above the double-sided bridging die disposed at the second level and partially overlapping with the double-sided bridging die, wherein the double-sided bridging die is configured to provide at least lateral communication between the first-level integrated circuit die and the second-level integrated circuit die.

[0079] Example 9. An integrated circuit die packaging assembly according to Example 8, wherein the double-sided bridge die includes: a substrate; a first redistribution layer formed on the top surface of the substrate and configured to be coupled to the bottom surface of the first integrated circuit die; and a second redistribution layer formed on the bottom surface of the substrate and configured to be coupled to the top surface of the second integrated circuit die, wherein the top surface and the bottom surface of the substrate are respectively disposed on opposite sides of the substrate.

[0080] Example 10. An integrated circuit die packaging assembly according to Example 9, wherein the first redistribution layer and the second redistribution layer include a plurality of hybrid bonding members and wiring connectors.

[0081] Example 11. An integrated circuit die packaging assembly according to Example 10, wherein the spacing between the plurality of hybrid bonding members is less than 10 μm.

[0082] Example 12. An integrated circuit die packaging assembly according to Example 9, wherein the double-sided bridge die includes passive devices and / or active devices.

[0083] Example 13. An integrated circuit die packaging assembly according to Example 9, wherein the double-sided bridge die includes a plurality of through-silicon vias.

[0084] Example 14. An integrated circuit die packaging assembly according to Example 9, wherein the double-sided bridge die includes active circuitry disposed in the substrate.

[0085] Example 15. An integrated circuit die packaging assembly according to Example 9, wherein the first redistribution layer and the second redistribution layer include the same arrangement of hybrid bonding members and wiring connectors.

[0086] Example 16. The integrated circuit die packaging assembly according to Example 8, the integrated circuit die packaging assembly further includes an intermediary layer connected to the packaging substrate and the integrated circuit die stack.

[0087] Example 17. According to the integrated circuit die packaging assembly of Example 8, the integrated circuit die packaging assembly further includes: a first second-level integrated circuit die, the first second-level integrated circuit die being disposed in the second level, the second level being mounted on the top surface of the first level and connected to the bottom surface of the first third-level integrated circuit die.

[0088] Example 18. The integrated circuit die packaging assembly according to Example 8 further includes a fill die disposed in a fourth layer of the integrated circuit die stack, the fill die being not electrically connected to the plurality of integrated circuit dies at the third layer.

[0089] Example 19. A method for manufacturing an integrated circuit die package assembly comprising multiple layers of integrated circuit dies, the method comprising: mounting a double-sided bridging die to a first-layer integrated circuit die and a second-layer integrated circuit die, the first-layer integrated circuit die and the second-layer integrated circuit die defining a first layer and the double-sided bridging die defining a second layer; mounting a first-layer integrated circuit die of a third layer on the double-sided bridging die to form an integrated circuit die stack; and mounting the integrated circuit die stack on a package substrate.

[0090] Example 20. According to the method of Example 19, the method further includes: mounting the second-third-level integrated circuit die of the third level on the double-sided bridge die; and mounting a filler die on the third level, wherein the filler die is not electrically connected to the first-third-level integrated circuit die and the second-third-level integrated circuit die of the third level.

[0091] While the foregoing describes embodiments of the present invention, other and further embodiments of the present invention may be designed without departing from the basic scope of the present invention, and the scope of the present invention is defined by the appended claims.

Claims

1. A double-sided bridge connector core, the double-sided bridge connector core comprising: Substrate; A first redistribution layer is constructed on the top surface of the substrate and configured to be coupled to the bottom surface of the first integrated circuit die. as well as A second redistribution layer is formed on the bottom surface of the substrate and configured to be coupled to the top surface of the second integrated circuit die. The top surface and the bottom surface of the substrate are respectively disposed on opposite sides of the substrate.

2. The double-sided bridging core according to claim 1, wherein the first redistribution layer and the second redistribution layer comprise the same arrangement of hybrid joints and wiring connectors.

3. An integrated circuit die packaging assembly, the integrated circuit die packaging assembly comprising: Packaging substrate; as well as An integrated circuit die stack, wherein the integrated circuit die stack is disposed above the packaging substrate, the integrated circuit die stack comprising: A first-level integrated circuit die and a second-level integrated circuit die are disposed at the first level of the integrated circuit die stack. A double-sided bridging connector die, wherein the double-sided bridging connector die is disposed at a second level, the second level being vertically stacked above the first-level integrated circuit die and the second-level integrated circuit die and partially overlapping with the first-level integrated circuit die and the second-level integrated circuit die; and The first three-level integrated circuit die is disposed at the third level. The third level is vertically stacked above the double-sided bridging die disposed at the second level and partially overlaps with the double-sided bridging die. The double-sided bridge die is configured to provide lateral communication between at least a first-level integrated circuit die and a second-level integrated circuit die.

4. The integrated circuit die packaging assembly according to claim 3 or the double-sided bridging die according to claim 1, wherein the double-sided bridging die comprises: Substrate; A first redistribution layer is constructed on the top surface of the substrate and configured to be coupled to the bottom surface of the first integrated circuit die. as well as A second redistribution layer is formed on the bottom surface of the substrate and configured to be coupled to the top surface of the second integrated circuit die. The top surface and the bottom surface of the substrate are respectively disposed on opposite sides of the substrate.

5. The integrated circuit die packaging assembly of claim 4 or the double-sided bridge die of claim 1, wherein the first redistribution layer and the second redistribution layer comprise a plurality of hybrid bonding members and wiring connectors.

6. The integrated circuit die packaging assembly of claim 4 or the double-sided bridge die of claim 1, wherein the first redistribution layer and the second redistribution layer comprise a plurality of hybrid bonding members and wiring connectors; and wherein the spacing between the plurality of hybrid bonding members is less than 10 μm.

7. The integrated circuit die packaging assembly according to claim 4 or the double-sided bridge die according to claim 1, wherein the double-sided bridge die comprises passive devices and / or active devices.

8. The integrated circuit die packaging assembly according to claim 4 or the double-sided bridging die according to claim 1, wherein the double-sided bridging die includes a plurality of through-silicon vias.

9. The integrated circuit die packaging assembly according to claim 4 or the double-sided bridge die according to claim 1, wherein the double-sided bridge die includes active circuitry disposed in the substrate.

10. The integrated circuit die package assembly of claim 4 or the double-sided bridge die of claim 1, wherein the first redistribution layer and the second redistribution layer comprise the same arrangement of hybrid bonding members and wiring connectors.

11. The integrated circuit die packaging assembly according to claim 3 or the double-sided bridge die according to claim 1, wherein the integrated circuit die packaging assembly or the double-sided bridge die further comprises an interposer layer that is stacked and connected to the packaging substrate and the integrated circuit die.

12. The integrated circuit die packaging assembly according to claim 3 or the double-sided bridging die according to claim 1, wherein the integrated circuit die packaging assembly or the double-sided bridging die further comprises: The first two-level integrated circuit die is disposed in the second level, and the second level is mounted on the top surface of the first level and connected to the bottom surface of the first three-level integrated circuit die.

13. The integrated circuit die packaging assembly of claim 3 or the double-sided bridging die of claim 1, wherein the integrated circuit die packaging assembly or the double-sided bridging die further comprises a filler die disposed in a fourth layer of the integrated circuit die stack, the filler die being not electrically connected to the plurality of integrated circuit dies at the third layer.

14. A method for manufacturing a multi-layered integrated circuit die package assembly comprising an integrated circuit die, the method comprising: A double-sided bridging connector die is installed on a first-level integrated circuit die and a second-level die, the first-level die and the second-level die defining a first level, and the double-sided bridging connector die defining a second level; The first three-level integrated circuit die of the third level is mounted on the double-sided bridge die to form an integrated circuit die stack; as well as The integrated circuit dies are stacked and mounted on the packaging substrate.

15. The method of claim 14, further comprising: The third-level second and third-level integrated circuit die is mounted on the double-sided bridge die; as well as A filler die is mounted on the third layer, and the filler die is not electrically connected to the first and second third-layer integrated circuit dies of the third layer.

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