Interposer substrate with integrated stepped die cavity and related integrated circuit (IC) package and method of manufacture

Abstract

Interposer substrates with integrated stepped die cavities and related integrated circuit (IC) packages and related methods of manufacture. Die cavities integrated in an outer layer of an interposer substrate provide space for a die to extend into the interposer substrate (e.g., to facilitate increased die height). Forming the die cavities in the outer layer facilitates positioning of metal interconnects in an outer metallization layer of the interposer substrate adjacent to the die cavities, and can also enhance heat dissipation for a die extending into the die cavities. Forming the die cavities in the outer layer of the interposer substrate also facilitates reducing a distance between the interposer substrate and a package substrate to facilitate coupling of the interposer substrate to the package substrate with vertically interconnects of reduced height. This facilitates vertically interconnects of reduced aspect ratio and reduced pitch, enabling support of dies with higher input / output (I / O) connection densities.

Description

[0001] Priority application

[0002] This application claims priority to U.S. Provisional Patent Application Serial No. 63 / 622,604, filed January 19, 2024, entitled “Interposer Substrate with Integrated Step Die Cavity, and Related Integrated CIRCUIT (IC) Packages and Fabrication Methods,” the entire contents of which are incorporated herein by reference.

[0003] This application also claims priority to U.S. Patent Application Serial No. 18 / 605,021, filed March 14, 2024, entitled “Interposer Substrate with Integrated Step Die Cavity, and Related Integrated CIRCUIT (IC) Packages and Fabrication Methods,” the entire contents of which are incorporated herein by reference. background

[0004] I. Technical Field

[0005] The field of this disclosure relates to interposer substrates that provide support and electrical interfaces between multiple electronic devices (such as semiconductor dies) in an integrated circuit (IC) package.

[0006] II. Background Technology

[0007] Integrated circuits (ICs) are the cornerstone of electronic devices. ICs are packaged in IC packages, also known as “semiconductor packages” or “chip packages.” An IC package includes one or more semiconductor dies (“dies” or “dice”) that serve as the IC, mounted on and electrically coupled to a substrate that serves as a wiring substrate (e.g., a package substrate) to provide physical support and electrical interfaces to the dies. The dies are electrically connected to metal interconnects (e.g., metal traces) exposed in an upper layer of the substrate as part of a signal wiring path. The substrate also includes one or more metallization layers comprising metal interconnects (e.g., metal traces, metal lines), wherein vertical interconnect vias (vias) couple these metal interconnects together between adjacent metallization layers to provide electrical interfaces between the dies. In the case where the substrate is a package substrate, the substrate also includes a lower outer metallization layer comprising metal interconnects coupled to external metal interconnects (e.g., ball grid array (BGA) interconnects) to provide external interfaces between the dies within the IC package. External metal interconnects can also be coupled (e.g., soldered) to traces in a printed circuit board (PCB) to attach the package to the PCB and electrically interconnect its die with the circuitry of the PCB.

[0008] Some IC packages are referred to as multi-die (multi-die) IC packages, which include multiple dies contained within the IC package for different purposes or applications. For example, a multi-die IC package may include a first application die (e.g., a processor or system-on-a-chip (SoC)) and a separate second die providing support circuitry for the application die. Splitting the main application / function into a separate die is an alternative to putting all such application / function circuitry into a single die. Manufacturing costs and complexity increase disproportionately with die size. For example, the second die may include a die with power management circuitry for a modem, processor, or memory (as an example). These multi-die IC packages can be provided in the form of three-dimensional (3D) IC (3DIC) packages. A 3DIC package may include a die package comprising a first die coupled to a first bottom package substrate and encapsulated in a molding layer. The 3DIC may then include a second die coupled to the first die via an interposer substrate that is part of the second die package. An interposer substrate is coupled to a die package and a molding layer of the die package. A vertical interconnect disposed in the molding layer of the die package and adjacent to the first die in the lateral / horizontal direction connects the metal interconnects in the interposer substrate to the metal interconnects in the package substrate, thereby providing a signal wiring path between the second die and the first die through the corresponding interposer substrate and package substrate of the second die and the first die.

[0009] As the number of input / output (I / O) pins to be housed in a 3DIC package increases, the pitch of the vertical interconnects within the 3DIC package may need to be reduced to support such a higher number of I / O connections. Otherwise, the area of ​​the 3DIC package may have to be increased, which may be undesirable. However, given the aspect ratio of the vertical interconnects, reducing the pitch of the vertical interconnects using known or available manufacturing methods may not be possible. Summary of the Invention

[0010] The aspects disclosed herein include an interposer substrate having an integrated stepped die cavity. Related integrated circuit (IC) packages including such interposer substrates and related manufacturing methods are also disclosed. The interposer substrate has one or more metallization layers to facilitate interconnection of multiple electronic devices, such as semiconductor dies (“dies”). Each metallization layer in the interposer substrate has metal interconnects (e.g., metal lines, metal traces) insulated by an insulating layer, wherein the metal interconnects provide signal routing paths in a first horizontal direction within the interposer substrate. Vias are formed in the insulating layer to interconnect the metal interconnects between vertically adjacent metallization layers to provide signal routing paths in a second vertical direction. For example, the interposer substrate may be disposed in a three-dimensional (3D) IC (3DIC) package to facilitate signal routing from a second upper die coupled to the interposer substrate to a lower package substrate in the die package, thereby providing electrical coupling between the second die and a first die coupled to the package substrate. In this 3DIC package, a first lower die and a vertical interconnect can be disposed in the molding layer of the die package and the vertical interconnect is adjacent to the first die to provide a signal wiring path between the interposer substrate and the package substrate of the die package and the first die.

[0011] In an exemplary aspect, the die cavity is integrated in at least a portion of the outer layer of an interpolator substrate configured as part of an IC package to be coupled to the die package. The die cavity provides space for a portion of a first die in the coupled die package, as part of the IC package, to extend partially into the die cavity in a second vertical direction without necessarily increasing the height of the molding layer of the die package. For example, the height and area of ​​the first die may have been increased to reduce hot spots at extreme temperatures. Furthermore, by providing the die cavity in the outer layer of the interpolator substrate to receive a portion of the die, the remaining portion of the outer layer of the interpolator substrate, which defines the die cavity in a first horizontal direction and remains outside the die cavity, can extend further into the molding layer of the die package in the second vertical direction without interfering with the die. This reduces the vertical distance between the interpolator substrate and the package substrate in the second vertical direction in which vertical connections are formed, facilitating the creation of vertical interconnects with reduced aspect ratios and reduced pitch, thereby enabling the support of dies with higher density input / output (I / O) connections. Therefore, when the interposer substrate is included in a 3DIC package, vertical interconnects with reduced height and aspect ratio can be provided by a combination of: a first vertical interconnect with reduced height in the outer layer coupled to a second vertical interconnect with reduced height in the molding layer of the die package. This allows the vertical interconnects located between the interposer substrate and the package substrate to be provided with reduced pitch, thereby enabling higher I / O density dies.

[0012] In other exemplary aspects, the die cavity is formed by a removed portion of the outer layer of the interposer substrate, which will be adjacent to the die package when the interposer substrate is incorporated into the IC package. Removing a portion of the outer layer of the interposer substrate forms a stepped die cavity. For example, one of the outer layers of the interposer substrate to which a portion has been removed to form the die cavity may be a solder mask. Another outer layer of the interposer substrate to which a portion has been removed to also form a portion of the die cavity may be an outer metallization layer of the interposer substrate in which a solder mask is formed. In either case, the metallization layout of the outer metallization layer of the interposer substrate may be designed and the outer metallization layer may be manufactured such that after a portion of the outer layer of the interposer substrate is removed to form the die cavity, the metal interconnects in the outer metallization layer are retained adjacent to the die cavity as residuals. Thus, when the die cavity is formed in the outer layer of the interposer substrate, these residual metal interconnects remain adjacent to the die extending into the die cavity and still exist in the outer metallization layer of the interposer substrate when the interposer substrate is incorporated into the IC package. The metal interconnects adjacent to the die cavity and thermally coupled to the die extending into the die cavity provide heat dissipation from the die through the metal interconnects and the interposer substrate. The metal interconnects in the outer metallization layer of the interposer substrate that are retained as residues adjacent to the die cavity can also be coupled to other metal interconnects in other metallization layers of the interposer substrate to provide additional efficient heat dissipation paths through the interposer substrate. Furthermore, in other exemplary aspects, a portion of the outer layer of the interposer substrate may be removed to form the die cavity, such that the residual metal interconnects in the outer metallization layer of the interposer substrate are also exposed in the die cavity. This enhances the thermal coupling between the metal interconnects in the interposer substrate and the die extending into the die cavity for improved heat dissipation because there is no insulating material between the metal interconnects and the die cavity in the interposer substrate.

[0013] In another example, a die cavity is formed by removing a portion of the outer layer of the interposer substrate, including a portion of the solder mask layer of the interposer substrate and a portion of the outer metallization layer of the interposer substrate adjacent to the solder mask layer. If a portion of the outer metallization layer of the interposer substrate is also removed to form part of the die cavity, a stepped structure may also exist in the outer metallization layer adjacent to the die cavity. This is a result of removing a portion of the outer metallization layer of the interposer substrate to a given depth in a second vertical direction, resulting in a thinner portion remaining adjacent to the thicker portion of the outer metallization layer. This stepped structure may be prone to fracture due to the reduced strength and stiffness of the thinner portion of the outer metallization layer. However, the outer metallization layer in the interposer substrate is manufactured like or similarly to other metallization layers in the interposer substrate. Therefore, the coefficient of thermal expansion (CTE) of the outer metallization layer and other metallization layers in the interposer substrate may have a small difference. Therefore, even with a stepped structure resulting from the formation of a thinner portion of the outer metallization layer to form part of the die cavity, the outer metallization layer may be less prone to fracture and less susceptible to delamination. For example, the outer metallization layer and other metallization layers in the interposer substrate can be formed using the same manufacturing process and include a stronger, more rigid insulating layer material, such as prepreg glass (PPG). This contrasts with forming the die cavity, for example, in a separate coating (e.g., a resin-coated copper (RCC) layer) comprising a coating material (e.g., resin) applied to metal pillars plated onto the outer metallization layer of the interposer substrate. The separate coating may have a larger CTE and / or a greater CTE difference compared to the metallization layer of the interposer substrate, due to the larger CTE of the coating compared to the material of the insulating layer used to form the metallization layer of the interposer (including the outer metallization layer with an integrated die cavity).

[0014] In one example, the outer metallization layer may be processed during die cavity formation such that the metal interconnects in the outer metallization layer adjacent to the die cavity are also directly exposed to the die cavity. This eliminates the need for insulating material between the outer surface of the metal interconnects in the interposer substrate and the die cavity, improving thermal coupling between the die cavity and the metal interconnects in the outer metallization layer of the interposer substrate. Since etching or otherwise removing a portion of the metal interconnects that will form the die cavity and is adjacent to it exposes the outer surface of the metal interconnects to the die cavity, the metal interconnects in the outer metallization layer can be exposed to the die cavity. Alternatively, when forming the die cavity, etching or otherwise removing a portion of the metal interconnects may also be performed as part of a single removal process (e.g., surface grinding) by removing a portion of the insulating layer of the outer metallization layer in place of or along with a portion of the metal interconnects.

[0015] In other examples, the outer metallization layer of the interposer substrate may be designed adjacent to the die cavity, including metal interconnects in the form of two-dimensional (2D) metal plates for enhanced thermal coupling with the die extending into the die cavity, thereby facilitating heat dissipation. The metal plates may be present in the outer metallization layer without being altered to form part of the die cavity, or may be residual metal plates resulting from etching into the metal plates formed in the outer metallization layer of the interposer substrate. In another example, when the die cavity is formed in the outer layer of the interposer substrate, multiple metal interconnects not part of a single metal plate may be retained as residues adjacent to the die cavity in the outer metallization layer of the interposer substrate. In yet another example, when the die cavity is formed in the outer layer of the interposer substrate, multiple metal interconnects not part of a single metal plate may be retained as residues adjacent to the die cavity in the outer metallization layer of the interposer substrate, wherein such residual metal interconnects are recessed from the bottom surface of the outer metallization layer. The morphology of the residual metal interconnects and / or metal plates in the outer layer that are exposed to the die cavity due to the formation of the die cavity is based on the layout of the metal interconnects in the outer layer in the area where the die cavity will be formed and the manufacturing method for forming the die cavity in the outer layer.

[0016] In this regard, in one exemplary aspect, an interposer substrate is provided. The interposer substrate includes a first metallization layer extending in a first direction. The first metallization layer includes a plurality of first metal interconnects; and one or more second metal interconnects, each including a first surface. The interposer substrate also includes an outer layer adjacent to the first metallization layer in a second direction orthogonal to the first direction. The outer layer includes an outer insulating layer including a plurality of outer metal interconnects, each of the plurality of outer metal interconnects being coupled to a first metal interconnect among the plurality of first metal interconnects. The interposer substrate also includes a die cavity adjacent in at least a portion of the outer insulating layer to a first surface of each of the one or more second metal interconnects in the second direction.

[0017] In another exemplary aspect, a method of manufacturing an interposer substrate for an IC package is provided. The method includes forming a first metallization layer extending in a first direction, the forming including: forming a plurality of first metal interconnects; and forming one or more second metal interconnects, each including a first surface. The method further includes forming an outer layer adjacent to the first metallization layer in a second direction orthogonal to the first direction, the forming including: forming an outer insulating layer including a plurality of outer metal interconnects each coupled to a first metal interconnect among the plurality of first metal interconnects. The method further includes forming a die cavity adjacent in at least a portion of the outer insulating layer to a first surface of each of the one or more second metal interconnects in the second direction.

[0018] In another exemplary aspect, an IC package is provided. The IC package includes a die package comprising: a package substrate including a plurality of fourth metal interconnects; a first die coupled to the package substrate; and a plurality of vertical interconnects, each of the plurality of vertical interconnects coupled to a fourth metal interconnect among the plurality of fourth metal interconnects. The IC package further includes an interposer substrate coupled to the die package in a second direction orthogonal to a first direction. The interposer substrate includes a first metallization layer extending in the first direction, the first metallization layer including: a plurality of first metal interconnects; and one or more second metal interconnects, each of the one or more second metal interconnects including a first surface. The interposer substrate further includes an outer layer coupled to the die package and located between the die package and the first metallization layer in the second direction. The outer layer includes an outer insulating layer comprising a plurality of outer metal interconnects, each of which is coupled to a first metal interconnect among the plurality of first metal interconnects and a vertical interconnect among the plurality of vertical interconnects. The interposer substrate also includes a die cavity adjacent, in at least a portion of the outer insulating layer, to a first surface of each of the one or more second metal interconnects in a second direction. The first die is at least partially disposed within the die cavity in the second direction. Attached Figure Description

[0019] Figure 1A and Figure 1B This is a side view of an exemplary integrated circuit (IC) package, which includes an interposer substrate coupled to a die package, the die package including a first lower die coupled to the package substrate, wherein an outer layer of the interposer substrate adjacent to the first die includes an integrated die cavity.

[0020] Figure 2A-1 and Figure 2A-2 These are corresponding side views and close-up partial side views of an exemplary interpolator substrate, which is in the form of an embedded trace substrate (ETS) interpolator substrate having an integrated die cavity and being configured as... Figure 1A and Figure 1B The interposer substrate in the IC package, wherein the outer ETS metallization layer has a metal plate exposed to the die cavity to facilitate enhanced thermal coupling with the die extending into the die cavity;

[0021] Figure 2B This is a side view of another exemplary interposer substrate, which is in the form of an ETS interposer substrate, has an integrated die cavity, and can be configured as... Figure 1A and Figure 1B The interposer substrate in the IC package, wherein the outer ETS metallization layer has metal interconnects exposed to the die cavity to facilitate enhanced thermal coupling with the die extending into the die cavity;

[0022] Figure 2C Yes, this is a side view of another exemplary interposer substrate, which is in the form of an ETS interposer substrate, has an integrated die cavity, and can be configured as... Figure 1A and Figure 1B The interposer substrate in the IC package, wherein the outer ETS metallization layer has recessed metal interconnects exposed to the die cavity to facilitate enhanced thermal coupling with the die extending into the die cavity;

[0023] Figure 3A and Figure 3B This is a side view of another exemplary IC package, which includes an interpolator substrate in the form of a coreless modified semi-additive process (mSAP) interpolator substrate coupled to a die package, the die package including a first lower die coupled to the package substrate, wherein the outer layer of the coreless mSAP interpolator substrate adjacent to the first die includes an integrated die cavity.

[0024] Figure 4A This is a side view of another exemplary interposer substrate, which is in the form of a coreless mSAP interposer substrate, having an integrated die cavity and being configured as... Figure 3A and Figure 3B The interposer substrate in the IC package, wherein the outer mSAP metallization layer has a metal plate exposed to the die cavity to facilitate enhanced thermal coupling with the die extending into the die cavity;

[0025] Figure 4B This is a side view of another exemplary interposer substrate, which is in the form of a coreless mSAP interposer substrate, having an integrated die cavity and being configured as... Figure 3A and Figure 3B The interposer substrate in the IC package, wherein the outer mSAP metallization layer has metal interconnects exposed to the die cavity to facilitate enhanced thermal coupling with the die extending into the die cavity;

[0026] Figure 4C This is a side view of another exemplary interposer substrate, which is in the form of a coreless mSAP interposer substrate, having an integrated die cavity and being configured as... Figure 3A and Figure 3B The interposer substrate in the IC package, wherein the outer mSAP metallization layer has recessed metal interconnects exposed to the die cavity to facilitate enhanced thermal coupling with the die extending into the die cavity;

[0027] Figure 5A and Figure 5B This is a side view of another exemplary IC package, which includes an interpolator substrate in the form of a die-embedded mSAP interpolator substrate coupled to a die package. The die package includes a first lower die coupled to the package substrate, wherein an outer layer of the die-embedded mSAP interpolator substrate adjacent to the first die includes an integrated die cavity.

[0028] Figure 6A This is a side view of another exemplary interposer substrate, which is in the form of a cored mSAP interposer substrate, having an integrated die cavity and being configured as... Figure 5A and Figure 5B The interposer substrate in the IC package, wherein the outer mSAP metallization layer has a metal plate exposed to the die cavity to facilitate enhanced thermal coupling with the die extending into the die cavity;

[0029] Figure 6B This is a side view of another exemplary interposer substrate, which is in the form of a cored mSAP interposer substrate, having an integrated die cavity and being configured as... Figure 5A and Figure 5B The interposer substrate in the IC package, wherein the outer mSAP metallization layer has metal interconnects exposed to the die cavity to facilitate enhanced thermal coupling with the die extending into the die cavity;

[0030] Figure 6C This is a side view of another exemplary interposer substrate, which is in the form of a cored mSAP interposer substrate, having an integrated die cavity and being configured as... Figure 5A and Figure 5B The interposer substrate in the IC package, wherein the outer mSAP metallization layer has recessed metal interconnects exposed to the die cavity to facilitate enhanced thermal coupling with the die extending into the die cavity;

[0031] Figure 7 This is a flowchart illustrating an exemplary process for manufacturing an interposer substrate that can be coupled to a die package, wherein the outer layer of the interposer substrate includes an integrated die cavity, the interposer substrate including but not limited to Figures 1A to 6C Interpolator substrate in the middle;

[0032] Figures 8A to 8D This is an example of manufacturing. Figures 1A to 2C A flowchart illustrating an exemplary manufacturing process of the interpolator substrate;

[0033] Figures 9A to 9I-3 It is based on Figures 8A to 8DAn exemplary manufacturing process in which an interpolator substrate is manufactured, and an exemplary manufacturing stage during the manufacturing process;

[0034] Figure 10A and Figure 10B This is a flowchart illustrating an exemplary process for manufacturing an IC package including an interposer substrate, wherein the outer layer of the interposer substrate includes an integrated die cavity, and the interposer substrate includes, but is not limited to, [other types of interposers]. Figures 1A to 6C The interpolator substrate in the IC package, and including but not limited to the interpolator substrate. Figures 1A to 6C and Figure 9I-3 Interpolator substrate and Figures 1A to 1B , Figures 3A to 3B and Figures 5A to 5B IC packages in the middle;

[0035] Figures 11A to 11D It is based on Figures 10A to 10B An exemplary manufacturing stage during the manufacturing of an IC package in an exemplary manufacturing process;

[0036] Figure 12 This is a block diagram of an exemplary wireless communication device, which includes one or more IC packages, each including an interposer substrate, wherein the outer layer of the interposer substrate includes an integrated die cavity. The one or more IC packages including the interposer substrate include, but are not limited to, those... Figures 1A to 6C , Figures 9I-1 to 9I-3 and Figure 11D Interpolator substrate and Figures 1A to 1B , Figures 3A to 3B , Figures 5A to 5B and Figure 11D IC packages in the middle, and can be manufactured according to the manufacturing process (including but not limited to) Figure 7 , Figures 8A to 8D and Figures 10A to 10B To manufacture (using the exemplary manufacturing process in the example); and

[0037] Figure 13 This is a block diagram of an exemplary electronic device in the form of a processor-based system. The exemplary electronic device includes one or more IC packages, each including an interposer substrate. The outer layer of the interposer substrate includes an integrated die cavity. The one or more IC packages including the interposer substrate include, but are not limited to, those... Figures 1A to 6C , Figures 9I-1 to 9I-3 and Figure 11D Interpolator substrate and Figures 1A to 1B , Figures 3A to 3B , Figures 5A to 5B and Figure 11D IC packages in the middle, and can be manufactured according to the manufacturing process (including but not limited to) Figure 7 , Figures 8A to 8D and Figures 10A to 10B (Exemplary manufacturing process in the example) to manufacture. Detailed Implementation

[0038] Several exemplary aspects of this disclosure will now be described with reference to the accompanying drawings. The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any aspect described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other aspects.

[0039] The aspects disclosed herein include an interposer substrate having an integrated stepped die cavity. Related integrated circuit (IC) packages including such interposer substrates and related manufacturing methods are also disclosed. The interposer substrate has one or more metallization layers to facilitate interconnection of multiple electronic devices, such as semiconductor dies (“dies”). Each metallization layer in the interposer substrate has metal interconnects (e.g., metal lines, metal traces) insulated by an insulating layer, wherein the metal interconnects provide signal routing paths in a first horizontal direction within the interposer substrate. Vias are formed in the insulating layer to interconnect the metal interconnects between vertically adjacent metallization layers to provide signal routing paths in a second vertical direction. For example, the interposer substrate may be disposed in a three-dimensional (3D) IC (3DIC) package to facilitate signal routing from a second upper die coupled to the interposer substrate to a lower package substrate in the die package, thereby providing electrical coupling between the second die and a first die coupled to the package substrate. In this 3DIC package, a first lower die and a vertical interconnect can be disposed in the molding layer of the die package and the vertical interconnect is adjacent to the first die to provide a signal wiring path between the interposer substrate and the package substrate of the die package and the first die.

[0040] In an exemplary aspect, the die cavity is integrated in at least a portion of the outer layer of an interpolator substrate configured as part of an IC package to be coupled to the die package. The die cavity provides space for a portion of a first die in the coupled die package, as part of the IC package, to extend partially into the die cavity in a second vertical direction without necessarily increasing the height of the molding layer of the die package. For example, the height and area of ​​the first die may have been increased to reduce hot spots at extreme temperatures. Furthermore, by providing the die cavity in the outer layer of the interpolator substrate to receive a portion of the die, the remaining portion of the outer layer of the interpolator substrate, which defines the die cavity in a first horizontal direction and remains outside the die cavity, can extend further into the molding layer of the die package in the second vertical direction without interfering with the die. This reduces the vertical distance between the interpolator substrate and the package substrate in the second vertical direction in which vertical connections are formed, facilitating the creation of vertical interconnects with reduced aspect ratios and reduced pitch, thereby enabling the support of dies with higher density input / output (I / O) connections. Therefore, when the interposer substrate is included in a 3DIC package, vertical interconnects with reduced height and aspect ratio can be provided by a combination of: a first vertical interconnect with reduced height in the outer layer coupled to a second vertical interconnect with reduced height in the molding layer of the die package. This allows the vertical interconnects located between the interposer substrate and the package substrate to be provided with reduced pitch, thereby enabling higher I / O density dies.

[0041] In other exemplary aspects, the die cavity is formed by a removed portion of the outer layer of the interposer substrate, which will be adjacent to the die package when the interposer substrate is incorporated into the IC package. Removing a portion of the outer layer of the interposer substrate forms a stepped die cavity. For example, one of the outer layers of the interposer substrate to which a portion has been removed to form the die cavity may be a solder mask layer. Another outer layer of the interposer substrate to which a portion has been removed to also form a portion of the die cavity may be an outer metallization layer of the interposer substrate in which a solder mask layer is formed. In either case, the metallization layout of the outer metallization layer of the interposer substrate may be designed and the outer metallization layer manufactured such that after a portion of the outer layer of the interposer substrate is removed to form the die cavity, metal interconnects in the outer metallization layer are retained as residues adjacent to the die cavity. Thus, when the die cavity is formed in the outer layer of the interposer substrate, these residual metal interconnects will remain in the outer metallization layer of the interposer substrate, adjacent to the die extending into the die cavity, when the interposer substrate is incorporated into the IC package. Metal interconnects adjacent to the die cavity and thermally coupled to the die extending into the die cavity provide heat dissipation from the die through the metal interconnects and the interposer substrate. Metal interconnects in the outer metallization layer of the interposer substrate that are retained as residues adjacent to the die cavity can also be coupled to other metal interconnects in other metallization layers of the interposer substrate to provide additional efficient heat dissipation paths through the interposer substrate. Furthermore, in other exemplary aspects, a portion of the outer layer of the interposer substrate can be removed to form the die cavity, such that residual metal interconnects in the outer metallization layer of the interposer substrate are also exposed to the die cavity. This enhances the thermal coupling between the metal interconnects in the interposer substrate and the die extending into the die cavity for improved heat dissipation because there is no insulating material between the metal interconnects and the die cavity in the interposer substrate.

[0042] In this respect, Figure 1A and Figure 1B This is a side view of an exemplary integrated circuit (IC) package 100, which includes an interposer substrate 102 coupled to a die package 104. Figure 1AAs shown, the die package 104 includes a first lower die 106 coupled to the package substrate 108. In this example, the package substrate 108 is an embedded trace substrate (ETS) substrate 108, meaning that one or more of the metallization layers 112(1), 112(2) (also referred to as ETS metallization layers 112(1), 112(2)) of this substrate include corresponding metal interconnects 114(1), 114(2) in the form of metal traces 116(1), 116(2) embedded in the corresponding insulating layers 118(1), 118(2). The metallization layers 112(1), 112(2) extend in a first horizontal direction (X-axis direction and Y-axis direction). The metal traces 116(1), 116(2) may be formed to facilitate both horizontal wiring in the first horizontal direction (X-axis direction and / or Y-axis direction) and vertical wiring in the second vertical direction (Z-axis direction). The die package 104 includes a molding layer 117 made of molding material 119 disposed on the package substrate 108 and surrounding and adjacent to the first die 106 to insulate the vertical interconnect 130 (e.g., metal balls such as copper balls or solder balls) and the die interconnect 132 of the first die 106, and to provide stability to the first die 106.

[0043] In this example, such as Figure 1AAs shown, the package substrate 108 of the die package 104 also includes an outer layer 110, which in this example is an outer solder mask layer 120. The outer layer (including the outer layer 110) is a layer forming the outer side of the component device, which in this case is the package substrate 108. The outer solder mask layer 120 is adjacent to the second metallization layer 112(2) in the second vertical direction (Z-axis direction). The outer solder mask layer 120 includes an outer insulating layer 122 having metal interconnects 124 in the form of metal pillars 126 (in the form of metal interconnects (e.g., copper pillars)), which are exposed to allow external metal interconnects 129 (e.g., solder balls) to couple to the metal pillars 126 for external signal routing. The ETS package substrate 108 can be considered as a three (3) layer (3L) substrate having its two (2) metallization layers 112(1), 112(2) and solder mask layer 120. However, this is not limiting, and the package substrate 108 may have fewer or more than three (3) layers (e.g., a two-layer (2L) package substrate or a four-layer (4L) package substrate). In this example, metal pillars 126 are formed on and coupled to vias 128 (2) in the second metallization layer 112 (2), which in turn are coupled to metal traces 116 (2), which are coupled to vias 128 (1) in the first metallization layer 112 (1) and metal traces 116 (1) to provide signal routing in the package substrate 108. In this example, the signal routing is provided from external metal interconnects 129, through the package substrate 108, and to vertical interconnects 130 (e.g., solder balls, ball grid array (BGA) interconnects) coupled to the interposer substrate 102. The die interconnect 132 of the first die 106 is also coupled to the first metallization layer 112 (1) of the package substrate 108 to provide signal wiring to the first die 106, which may be from the external metal interconnect 129 or from the interposer substrate 102 via the vertical interconnect 130.

[0044] For reference Figure 1BThe IC package 100 shown in this example has an interposer substrate 102 that is also an ETS interposer substrate 134. This means that one or more of the metallization layers 136(1), 136(2) (also referred to as ETS metallization layers 136(1), 136(2)) of the interposer substrate include corresponding metal interconnects 138(1), 138(2) in the form of metal traces 140(1), 140(2) embedded in the corresponding insulating layers 142(1), 142(2). It should be noted that the first metallization layer 136(1) is an outer / outer metallization layer relative to the metallization layers 136(1), 136(2) because the first metallization layer 136(1) forms the outer side of the metallization layers 136(1), 136(2). The metallization layers 136(1), 136(2) extend in a first horizontal direction (X-axis direction and Y-axis direction). Metal traces 140(1) and 140(2) can be formed to facilitate both horizontal wiring in a first horizontal direction (X-axis direction and / or Y-axis direction) and vertical wiring in a second vertical direction (Z-axis direction).

[0045] It should be noted that in this example, the insulating layers 142(1), 142(2) of the interposer substrate 102 are made of organic materials (such as organic substrates). Corresponding metal interconnects 138(1), 138(2) are formed therein as embedded metal interconnects 138(1), 138(2) within the corresponding insulating layers 142(1), 142(2). The organic materials can be composed of carbon-based compounds, which can be lightweight and inexpensive. Organic materials are also easier to fabricate and process due to their organic nature, which can help reduce fabrication costs and speed up production time. However, it should be noted that the interposer substrate 102 can also be formed of inorganic materials (such as, for example, silicon). Silicon can provide improved electrical properties for signal transmission and thermal properties for heat dissipation, such as in cases where improved heat dissipation is desired from die 106 through interposer substrate 102 and through the insulating layers 142(1), 142(2) of the interposer substrate and the metal interconnects 138(1), 138(2) of the interposer substrate adjacent to die 106 in the second vertical direction (Z-axis direction). However, silicon can be a more expensive material compared to organic materials. Silicon may also require more complex fabrication processes to form and process the insulating layers of the interposer substrate and the metal interconnects formed therein or on it, which can be more complex and lead to potentially increased manufacturing costs and time.

[0046] It should also be noted that the interposer substrate 102 can also be configured as other types of interposer substrates. As another example, the interposer substrate 102 can also be configured as a modified semi-additive process (mSAP) interposer substrate, meaning that one or more metallization layers of the interposer substrate will include metal interconnects formed adjacent to the respective insulating layers 142(1), 142(2). As another example, the interposer substrate 102 can be configured as a redistribution layer (RDL) substrate, wherein one or more metallization layers of the interposer substrate will be incorporated into an RDL in which metal interconnects can be formed, and laterally extend in a first horizontal direction (X-axis direction and / or Y-axis direction) to redistribute the electrical connection between the interposer substrate 102 and the package substrate 108. Where the respective metal interconnects 114(1) to 114(2), 138(1) to 138(2) of the RDL have different pitches, these RDLs can facilitate the electrical connection of the package substrate 108 to the interposer substrate 102.

[0047] In this example, such as Figure 1B As shown, the interposer substrate 102 also includes an outer layer 144, which in this example is an outer solder mask layer 144. The outer layer (including the outer layer 144) is a layer forming the outer side of the component device, which in this case is the interposer substrate 102. The outer solder mask layer 144 is adjacent to the first metallization layer 136(1) of the interposer substrate 102 in the second vertical direction (Z-axis direction). The fact that the outer solder mask layer 144 is adjacent to the first metallization layer 136(1) means that the solder mask layer 144 is positioned next to or close to the first metallization layer 136(1) in the second vertical direction (Z-axis direction). In this example, the solder mask layer 144 and the first metallization layer 136(1) are directly adjacent to each other (meaning that each one contacts the other). However, an intermediate material or coating may exist, for example, between the solder mask 144 and the first metallization layer 136(1), such that the solder mask 144 and the first metallization layer 136(1) remain adjacent to each other but not directly adjacent (meaning they are not in direct contact). The outer solder mask 144 includes an outer insulating layer 146 having outer metal interconnects 148 in the form of metal pillars 150 (in the form of metal interconnects, e.g., copper pillars or pads) exposed to allow vertical interconnects 130 to couple to the metal pillars 150 for signal wiring between the interposer substrate 102 and the package substrate 108 of the die package 104. It should be noted that, although not shown, a second die and / or other electrical components may be coupled to the interposer substrate 102 for support and for signal wiring through the interposer substrate 102 to the die package 104. In this case, the IC package 100 may be considered a three-dimensional (3D) IC (3DIC) package.

[0048] Continue to refer to Figure 1B In this example, metal pillars 150 are formed on and coupled to metal traces 140(1) in the first metallization layer 136(1), which in turn are coupled to vias 152(1), which are coupled to metal traces 140(2) in the second metallization layer 136(2) and vias 152(2) to provide signal routing in the interposer substrate 102. In this example, the interposer substrate 102 also includes an outer solder mask 154, which includes an insulating layer 156 having metal interconnects 158 in the form of metal pillars exposed to be electrically coupled to another electrical component coupled to the interposer substrate 102 for signal routing. The ETS interposer substrate 134 can be considered as a three (3) layer (3L) substrate having its two (2) metallization layers 136(1), 136(2) and solder mask 154. However, this is not limiting, and the interposer ETS package substrate 134 may have fewer or more than three (3) layers (e.g., two (2L) ETS interposer substrates or four (4L) ETS interposer substrates).

[0049] Continue to refer to Figure 1B As discussed in more detail below, the interposer substrate 102 includes a die cavity 162 integrated within an outer solder mask layer 144 and a portion of a first metallization layer 136(1) of the interposer substrate 102. In this example, the die cavity 162 is formed by creating a missing region in the outer solder mask layer 144 and a portion of the first metallization layer 136(1) adjacent to the outer solder mask layer 144. For example, as discussed in more detail below, the die cavity 162 can be formed in the interposer substrate 102 by removing (e.g., etching) a portion of the insulating layer 146 of the outer solder mask layer 144 and a portion of the insulating layer 142(1) of the first metallization layer 136(1) of the interposer substrate 102. The die cavity 162 allows the upper portion 164 of the first die 106 to extend into a region of the interposer substrate 102 in the second vertical direction (Z-axis direction), where the solder mask 144 and a portion of the first metallization layer 136(1) would normally be present without the die cavity 162. The die cavity 162 provides space for the first die 106 to extend at least partially into the die cavity 162 in the second vertical direction (Z-axis direction) without increasing the height of the molding layer 117 of the die package 104 in the second vertical direction (Z-axis direction). For example, the height of the first die 106 may have been increased to extend internal devices and internal interconnect layers, thereby avoiding or reducing hot spots of extreme temperatures within the first die 106. In this example, by surrounding the first die 106, the molding layer 117 also provides a second die cavity 166 for the first die 106, which opens to the die cavity 162 to provide a die cavity that can support the full height H1 of the first die 106.

[0050] In this example, such as Figure 1B As shown, a die cavity 162 is provided in the outer solder mask layer 144 of the interposer substrate 102, allowing the outer portion 168 of the outer solder mask layer 144 located outside the die cavity 162 in the first horizontal direction (X-axis and Y-axis directions) to further extend in the molding layer 117 of the die package 104 in the second vertical direction (Z-axis direction) without interfering with the first die 106. This reduces the vertical distance D1 between the interposer substrate 102 and the package substrate 108 in the second vertical direction (Z-axis direction) in which the vertical interconnect 130 is arranged to form a vertical connection, to facilitate the production of vertical interconnects 130 with a reduced aspect ratio and a reduced pitch P1, thereby supporting dies with higher density input / output (I / O) connections. Therefore, when the interposer substrate 102 is disposed within the IC package 100, vertical interconnects with reduced height and aspect ratio can be provided by a combination of: a first reduced-height metal pillar 150 and a vertical interconnect 130 in the outer solder mask layer 144 coupled to a second reduced-height vertical interconnect 130 in the molding layer 117 of the die package 104. This allows the vertical interconnects between the interposer substrate 102 and the package substrate 108 to be provided with a reduced pitch, thereby supporting higher I / O density dies.

[0051] Figure 2A-1 and Figure 2A-2 These are corresponding side views and close-up partial side views of the interpolator substrate 102A, which is in the form of ETS interpolator substrate 134A and can be configured as... Figure 1A and Figure 1B The interpolator substrate 102 and ETS interpolator substrate 134 are in the IC package 100. It should be noted that the interpolator substrate 102A can be an organic interpolator substrate or an inorganic interpolator substrate, and may include one or more RDLs as discussed above with respect to the interpolator substrate 102. Figure 2A-1 and Figure 2A-2 Intercalator substrates 102A and 134A in Figure 1A and Figure 1B The common elements between the interpolator substrates 102 and 134 are shown by common element marking.

[0052] like Figure 2A-1 and Figure 2A-2 As shown, a first stepped structure 200 is formed, wherein a portion of the solder resist layer 144 is removed to form a sidewall 202, thereby forming a stepped die cavity 162 integrated within the solder resist layer 144. In this example, the die cavity 162 is also formed by the absence or removal of material from the outer solder resist layer 144 and a portion of the first metallization layer 136(1). Figure 2A-2As shown, the removal or absence of material in the first metallization layer 136(1) creates a recessed layer portion 204 of the first metallization layer 136(1) with a height H2 that intersects the die cavity 162 in the first horizontal direction (X-axis direction and / or Y-axis direction), and a non-recessed layer portion 206 of the first metallization layer 136(1) located outside the die cavity 162 and not intersecting the die cavity 162 in the first horizontal direction (X-axis direction and / or Y-axis direction) with a height H3. The recessed layer portion 204 forms a recessed region 205 in the first metallization layer 136(1), wherein the recessed region 205 forms a part of the die cavity 162. Furthermore, as Figure 2A-2 As shown, in this example, because the sidewall 208 of the first metallization layer 136(1) formed by the portion of the first metallization layer 136(1) removed to form the die cavity 162 is not coplanar with the sidewall 202 of the solder resist layer 144 in the second vertical direction (Z-axis direction), the second stepped structure 210 is formed by the portion of the first metallization layer 136(1) adjacent to the removed portion of the die cavity 162. The second stepped structure 210 is formed at the interface between the non-recessed portion 206 and the recessed portion 204 of the first metallization layer 136(1). However, since the second stepped structure 210 is formed by removing a portion of the first metallization layer 136(1), which can be a more rigid material (such as prepreg glass (PPG) material), the presence of the recessed portion 204 of the first metallization layer 136(1) will still be rigid enough to prevent the interposer substrate 102A from warping and the first metallization layer 136(1) from being at risk of delamination.

[0053] Continue to refer to Figure 2A-1 and Figure 2A-2Some of the first metal interconnects 138(1)(1) and 138(2)(1) are located outside the die cavity 162 in the first horizontal direction (X-axis direction and / or Y-axis direction), meaning that the first metal interconnects 138(1)(1) and 138(2)(1) do not intersect with the die cavity 162 in the first horizontal direction (X-axis direction and / or Y-axis direction). The metal pillars 150 of the solder mask layer 144 are also located outside the die cavity 162 in the first horizontal direction (X-axis direction and / or Y-axis direction), meaning that the metal pillars 150 do not intersect with the die cavity 162 in the first horizontal direction (X-axis direction and / or Y-axis direction). However, other first metal interconnects 138(1)(2), 138(2)(2) are located within the die cavity 162 in the first horizontal direction (X-axis direction and / or Y-axis direction), meaning that these other first metal interconnects 138(1)(2), 138(2)(2) intersect with and are adjacent to the die cavity 162 in the first horizontal direction (X-axis direction and / or Y-axis direction). It should be noted that the metal interconnects 138(1)(2), 138(2)(2) may be completely or only partially located within the die cavity 162 in the first horizontal direction (X-axis direction and / or Y-axis direction). In this example, since a portion of the first metallization layer 136(1) has been removed to the lower surface 212 of the first metal interconnects 138(1)(2) adjacent to the die cavity 162, such as... Figure 2A-2 As shown, this means that the first metal interconnect 138(1)(2) is positioned closer to the die cavity 162, where the thermal coupling between the first metal interconnect and the die cavity 162 can provide increased thermal coupling and heat dissipation for the die extending into the die cavity 162. Thus, the lower surface 212 of the first metal interconnect 138(1)(2) is directly adjacent to the die cavity 162, meaning that the first metal interconnect 138(1)(2) is directly accessible through the die cavity 162. However, the lower surface 212 of the first metal interconnect 138(1)(2) may also be indirectly adjacent to the die cavity 216, meaning that there may be an intermediate component or material between the lower surface 212 of the first metal interconnect 138(1)(2) and the die cavity 162.

[0054] Furthermore, in this example, such as Figure 2A-2 As shown, the lower surface 212 of the first metal interconnect 138(1)(2) is exposed to the die cavity 162 in this example to enhance thermal coupling, such that the material of the insulating layer 142(1) is not disposed between the lower surface 212 of the first metal interconnect 138(2)(1) and the die cavity 162, but this is not mandatory. In this example, as Figure 2A-1 and Figure 2A-2As shown, the first metal interconnect 138(1)(2) is in the form of a metal plate 214 to provide a larger area of ​​metal material, thereby providing increased thermal coupling with the die cavity 162 for heat dissipation. In this example, the first metallization layer 136(1) also includes its vias 152(1), which are coupled to the metal plate 214 and other metal interconnects 138(2)(2) and the vias 152(2) to provide a thermal conduction path through the interposer substrate 102A for improved heat dissipation.

[0055] Figure 2B This is a side view of another exemplary interposer substrate 102B, which is in the form of an ETS interposer substrate 134B and can be configured as... Figure 1A and Figure 1B The interpolator substrate 102 and ETS interpolator substrate 134 are in the IC package 100. It should be noted that the interpolator substrate 102B can be an organic interpolator substrate or an inorganic interpolator substrate, and may include one or more RDLs as discussed above with respect to the interpolator substrate 102. Figure 2B Intercalator substrates 102B and 134B in Figures 1A to 1B , Figure 2A-1 and Figure 2A-2 Common elements among the interpolator substrates 102, 102A, 134, and 134A are indicated by common element markings.

[0056] refer to Figure 2B Some vias 152(1)(1) and 152(2)(1), which are in the form of metal interconnects, are located outside the die cavity 162 in the first horizontal direction (X-axis direction and / or Y-axis direction), meaning that the vias 152(1)(1) and 152(2)(1) do not intersect the die cavity 162 in the first horizontal direction (X-axis direction and / or Y-axis direction). However, other vias 152(1)(2) and 152(2)(2), which are in the form of metal interconnects, are located inside the die cavity 162 in the first horizontal direction (X-axis direction and / or Y-axis direction), meaning that these other vias 152(1)(2) and 152(2)(2) intersect with and are adjacent to the die cavity 162 in the first horizontal direction (X-axis direction and / or Y-axis direction). In this example, since a portion of the first metallization layer 136(1) has been removed to the bottom surface 216 of the via 152(1)(2) adjacent to the die cavity 162, this means that the via 152(1)(2) is positioned close to the die cavity 162, wherein the thermal coupling of the via with the die cavity 162 can provide increased thermal coupling and heat dissipation for the die extending into the die cavity 162.

[0057] Furthermore, in this example, such as Figure 2BAs shown, the bottom surface 216 of vias 152(1)(2) is exposed to the die cavity 162 in this example to enhance thermal coupling, such that the material of the insulating layer 142(1) is not disposed between the bottom surface 216 of vias 152(1)(2) and the die cavity 162, but this is not mandatory. Thus, the bottom surface 216 of vias 152(1)(2) is directly adjacent to the die cavity 162, meaning that vias 152(1)(2) can be directly accessed through the die cavity 162. However, the bottom surface 216 of vias 152(1)(2) can also be indirectly adjacent to the die cavity 216, meaning that there can be an intermediate component or material between the bottom surface 216 of vias 152(1)(2) and the die cavity 162. In this example, the bottom surface 216 of vias 152(1)(2) is coplanar with the first bottom surface 218 of the recessed layer portion 204 of the first metallization layer 136(1). The first bottom surface 218 is opposite to the second top surface 220 of the first metallization layer 136(1) in the second vertical direction (Z-axis direction). In this example, the first metallization layer 136(1) also includes its vias 152(1)(2), which are coupled to the metal interconnects 138(2)(2) and the vias 152(2)(2) to provide a thermal conduction path through the interposer substrate 102B for improved heat dissipation.

[0058] Figure 2C This is a side view of another exemplary interpolator substrate 102C in the form of an ETS interpolator substrate 134C, which may be configured as... Figure 1A and Figure 1B The interpolator substrate 102 and ETS interpolator substrate 134 are in the IC package 100. It should be noted that the interpolator substrate 102C can be an organic interpolator substrate or an inorganic interpolator substrate, and may include one or more RDLs as discussed above with respect to the interpolator substrate 102. Figure 2C Intercalator substrates 102C and 134C in Figures 1A to 2B Common elements among interpolator substrates 102, 102A, 102B, 134, 134A, and 134B are indicated by common element markings.

[0059] refer to Figure 2C The vias 152(1)(2) and 152(2)(2), which are in the form of metal interconnects, are located within the die cavity 162 in the first horizontal direction (X-axis direction and / or Y-axis direction), like Figure 2BAs in the interposer substrate 102B. However, in this example, the bottom surface 216 of the via 152(2)(1) is recessed from the bottom surface 218 of the recessed layer portion 204 of the first metallization layer 136(1). This may be due to an etching or removal process for removing the metal portion of the via 152(1)(2) in the first metallization layer 136(1). In this example, the bottom surface 216 of the via 152(1)(2) is still exposed to the die cavity 162 for improved thermal coupling. In this example, the bottom surface 216 of the via 152(1)(2) is directly adjacent to the die cavity 162, meaning that the via 152(1)(2) is directly accessible through the die cavity 162. However, the bottom surface 216 of the via 152(1)(2) may also be indirectly adjacent to the die cavity 216, which means that there may be an intermediate component or material between the bottom surface 216 of the via 152(1)(2) and the die cavity 162.

[0060] Figure 3A and Figure 3B This is a side view of another exemplary IC package 300, which also includes a dieless interposer substrate 302 coupled to a die package 304. Figure 3A As shown, the interposer substrate 302 is a coreless interposer substrate 302 because it does not include a core layer provided to enhance the rigidity of the interposer substrate 302. It should be noted that the interposer substrate 302 can be an organic or inorganic interposer substrate and may include one or more RDLs as discussed above with respect to the interposer substrate 102. Figure 3A and Figure 3B IC package 300 and Figure 1A and Figure 1B Common components among the IC packages 100 are shown by common component markings.

[0061] However, in such Figure 3AIn the IC package 300 shown, the package substrate 308 of the die package 304 is a modified semi-additive process (mSAP) package substrate 308, meaning that one or more of the metallization layers 312(1), 312(2) (also referred to as mSAP metallization layers 312(1), 312(2)) of the package substrate include corresponding metal interconnects 314(1), 314(2) formed adjacent to the corresponding insulating layers 318(1), 318(2). The metallization layers 312(1), 312(2) extend in a first horizontal direction (X-axis direction and Y-axis direction). The metal interconnects 314(1), 314(2) can be formed to facilitate both horizontal wiring in the first horizontal direction (X-axis direction and / or Y-axis direction) and vertical wiring in the second vertical direction (Z-axis direction). The die package 304 includes a molding layer 117 made of molding material 119 disposed on the package substrate 308 and surrounding and adjacent to the first die 106 to insulate the vertical interconnect 130 and the die interconnect 132 of the first die 106, and to provide stability to the first die 106.

[0062] In this example, the package substrate 308 of the die package 304 also includes an outer layer 110, which in this example is an outer solder mask 120. The outer solder mask 120 is adjacent to the second metallization layer 312(2) in the second vertical direction (Z-axis direction). The outer solder mask 120 includes an outer insulating layer 122 having metal interconnects 124 in the form of metal pillars 126 exposed to allow external metal interconnects 129 (e.g., solder balls) to couple to the metal pillars 126 for external signal routing. The mSAP package substrate 308 can be considered as a three (3) layer (3L) substrate having its two (2) metallization layers 312(1), 312(2) and solder mask 120. However, this is not limiting, and the mSAP package substrate 308 may have fewer or more than three (3) layers (e.g., a two-layer (2L) package substrate or a four-layer (4L) package substrate). In this example, metal pillars 126 are formed on and coupled to vias 328(2) in the second metallization layer 312(2), which in turn are coupled to metal interconnects 314(2), which are coupled to vias 328(1) in the first metallization layer 312(1) and metal interconnects 314(1) to provide signal routing in the package substrate 308. In this example, the signal routing is provided from external metal interconnects 129, through the package substrate 308, and to vertical interconnects 130 (e.g., solder balls, ball grid array (BGA) interconnects) coupled to the interposer substrate 302. Die interconnects 132 of the first die 106 are also coupled to the first metallization layer 312(1) of the package substrate 308 to provide signal routing to the first die 106, which may originate from external metal interconnects 129 or from the interposer substrate 302 via vertical interconnects 130.

[0063] like Figure 3BAs shown, in this example, the coreless interposer substrate 302 of the IC package 300 is also a coreless mSAP interposer substrate 334, meaning that one or more of the metallization layers 336(1), 336(2) (also referred to as mSAP metallization layers 336(1), 336(2)) of this coreless interposer substrate include corresponding metal interconnects 338(1), 338(2) formed adjacent to the corresponding insulating layers 342(1), 342(2). It should be noted that the first metallization layer 336(1) is the outer layer / outer metallization layer relative to the metallization layers 336(1), 336(2) because the first metallization layer 336(1) forms the outer side of the metallization layers 336(1), 336(2). The metallization layers 336(1), 336(2) extend in the first horizontal direction (X-axis direction and Y-axis direction). Metal interconnects 338(1) and 338(2) can be configured to facilitate both horizontal wiring in a first horizontal direction (X-axis direction and / or Y-axis direction) and vertical wiring in a second vertical direction (Z-axis direction).

[0064] In this example, the interposer substrate 302 also includes an outer layer 344, which in this example is an outer solder mask layer 344. The outer layer (including the outer layer 344) is a layer forming the outer side of the component device, which in this case is the interposer substrate 302. The outer solder mask layer 344 is adjacent to the first metallization layer 336(1) of the interposer substrate 302 in the second vertical direction (Z-axis direction). The fact that the outer solder mask layer 344 is adjacent to the first metallization layer 336(1) means that the solder mask layer 344 is positioned next to or close to the first metallization layer 336(1) in the second vertical direction (Z-axis direction). In this example, the solder mask layer 344 and the first metallization layer 336(1) are directly adjacent to each other (meaning that each is in contact with the other). However, for example, there may be an intermediate material or coating between the solder resist layer 344 and the first metallization layer 336(1) such that the solder resist layer 344 and the first metallization layer 336(1) are still adjacent to each other but not directly adjacent to each other (meaning they are not in direct contact with each other).

[0065] The outer solder mask 344 includes an outer insulating layer 346 having outer metal interconnects 348 in the form of metal pillars 350 (in the form of metal interconnects, e.g., copper pillars). These metal pillars are exposed to allow vertical interconnects 130 to couple to the metal pillars 350 for signal wiring between the interposer substrate 302 and the package substrate 308 of the die package 304. It should be noted that, although not shown, a second die and / or other electrical components may be coupled to the interposer substrate 302 for support and for signal wiring through the interposer substrate 302 to the die package 304. In this case, the IC package 300 can be considered a 3DIC package. In this example, metal pillars 350 are formed on and coupled to metal interconnects 338(1) in the first metallization layer 336(1), which in turn are coupled to vias 352(1), which are coupled to metal interconnects 338(2) in the second metallization layer 336(2). The vias 352(2) provide signal wiring in the interposer substrate 302. In this example, the interposer substrate 302 also includes an outer solder mask layer 354, which includes an insulating layer 356 having openings 358 to expose the second metal interconnects 338(2) in the second metallization layer 336(2). The mSAP interposer substrate 334 can be considered as a three (3) layer (3L) substrate having its two (2) metallization layers 336(1), 336(2) and solder mask layer 354. However, this is not limiting, and the mSAP interpolator substrate 334 may have fewer or more than three (3) layers (e.g., two (2L) interpolator substrates or four (4L) interpolator substrates).

[0066] Continue to refer to Figure 3B The interposer substrate 302 includes a die cavity 362 integrated within an outer solder mask layer 344. In this example, the die cavity 362 is formed by creating a missing region in the outer solder mask layer 344. For example, as discussed in more detail below, in this example, a portion of the insulating layer 346 of the outer solder mask layer 344 is removed (e.g., etched), rather than as... Figure 1A and Figure 1BAs provided in the IC package 100, a die cavity 362 is formed in the interposer substrate 302 by removing a portion of the first metallization layer 336(1). The die cavity 362 allows the upper portion 164 of the first die 106 to extend into a region of the interposer substrate 302 in the second vertical direction (Z-axis direction), where the solder mask layer 344 would normally be present without the die cavity 362. The die cavity 362 provides space for the first die 306 to extend at least partially into the die cavity 362 in the second vertical direction (Z-axis direction) without increasing the height of the molding layer 117 of the die package 304 in the second vertical direction (Z-axis direction). By surrounding the first die 106, the molding layer 117 also provides a second die cavity 166 for the first die 106, which opens into the die cavity 362 to provide a die cavity capable of supporting the full height H1 of the first die 106.

[0067] In this example, providing a die cavity 362 in the outer solder mask layer 344 of the interposer substrate 302 allows the outer portion 368 of the outer solder mask layer 344 located outside the die cavity 362 in the first horizontal direction (X-axis and Y-axis directions) to further extend in the molding layer 117 of the die package 304 in the second vertical direction (Z-axis direction) without interfering with the first die 106. This reduces the vertical distance D2 between the interposer substrate 302 and the package substrate 308 in the second vertical direction (Z-axis direction) in which the vertical interconnect 130 is arranged to form a vertical connection, which is beneficial to producing vertical interconnects 130 with a reduced aspect ratio and a reduced pitch P2, thereby supporting dies with higher density I / O connections. Therefore, when the interposer substrate 302 is disposed within the IC package 300, vertical interconnects with reduced height and aspect ratio can be provided by the following combination: a first reduced-height metal pillar 350 in the outer solder mask layer 344 and a vertical interconnect 130 coupled to a second reduced-height vertical interconnect 130 in the molding layer 117 of the die package 304. This allows the vertical interconnects between the interposer substrate 302 and the package substrate 308 to be provided with a reduced pitch, thereby supporting higher I / O density dies.

[0068] Figure 4A This is a corresponding side view of another interposer substrate 302A, which takes the form of a cored mSAP interposer substrate 334A and can be configured as... Figure 3A and Figure 3B The interpolator substrate 302 in the IC package 300. It should be noted that the interpolator substrate 302A can be an organic interpolator substrate or an inorganic interpolator substrate, and may include one or more RDLs as discussed above with respect to the interpolator substrate 102. Figure 4A Intercalator substrates 302A and 334A in Figure 3A and Figure 3B The common elements between the interpolator substrates 302 and 334 are shown by common element marking.

[0069] like Figure 4A As shown, a first stepped structure 400 is formed, wherein a portion of the solder mask layer 344 is removed to form a sidewall 402, thereby forming a stepped die cavity 362 integrated within the solder mask layer 344. Some first metal interconnects 338(1)(1), 338(2)(1) are located outside the die cavity 362 in the first horizontal direction (X-axis direction and / or Y-axis direction), meaning that the first metal interconnects 338(1)(1), 338(2)(1) do not intersect with the die cavity 362 in the first horizontal direction (X-axis direction and / or Y-axis direction). Some metal pillars 350(1) of the solder mask layer 344 are also located outside the die cavity 362 in the first horizontal direction (X-axis direction and / or Y-axis direction), meaning that the metal pillars 350(1) do not intersect with the die cavity 362 in the first horizontal direction (X-axis direction and / or Y-axis direction). However, another metal pillar 350(2) of the solder mask 344 is located within the die cavity 362 in the first horizontal direction (X-axis and / or Y-axis direction), meaning that the other metal pillar 350(2) intersects with and is adjacent to the die cavity 362 in the first horizontal direction (X-axis and / or Y-axis direction). In this example, since a portion of the solder mask 344 has been removed to the bottom surface 412 of the metal pillar 350(2) adjacent to the die cavity 362, this means that the metal pillar 350(2) is positioned closer to the die cavity 362, where the thermal coupling between the metal pillar and the die cavity 362 can provide increased thermal coupling and heat dissipation for the die extending into the die cavity 362. In this example, the bottom surface 412 of the metal pillar 350(2) is directly adjacent to the die cavity 362, meaning that the bottom surface 412 of the metal pillar 350(2) is directly accessible through the die cavity 362. However, the bottom surface 412 of the metal column 350(2) may also be indirectly adjacent to the core cavity 362, which means that there may be an intermediate component or material between the bottom surface 412 of the metal column 350(2) and the core cavity 362.

[0070] Furthermore, in this example, the bottom surface 412 of the metal pillar 350(2) is exposed to the die cavity 362 to enhance thermal coupling, such that the material of the insulating layer 346 is not disposed between the bottom surface 412 of the metal pillar 350(2) and the die cavity 362, but this is not mandatory. In this example, the metal pillar 350(2) is in the form of a metal plate 414 to provide a larger area of ​​metal material, thereby providing increased thermal coupling with the die cavity 362 for heat dissipation. In this example, the first metallization layer 336(1) also includes its vias 352(1), which are coupled to the metal plate 414 and other metal interconnects 338(1)(1), 338(2)(1) and vias 352(2) to provide a thermal conduction path through the interposer substrate 302A for improved heat dissipation.

[0071] Figure 4B This is a side view of another exemplary interposer substrate 302B, which is in the form of a coreless mSAP interposer substrate 334B and can be configured as... Figure 3A and Figure 3B The interpolator substrate 302 in the IC package 300. It should be noted that the interpolator substrate 302B can be an organic interpolator substrate or an inorganic interpolator substrate, and may include one or more RDLs as discussed above with respect to the interpolator substrate 102. Figure 4B Intercalator substrates 302B and 334B in Figures 3A to 3B and Figure 4A Common elements among the interpolator substrates 302, 302A, 334, and 334A are indicated by common element markings.

[0072] refer to Figure 4B Some vias 352(1)(1) and 352(2)(1) of the first metallization layer 336(1) in the form of metal interconnects are located outside the die cavity 362 in the first horizontal direction (X-axis direction and / or Y-axis direction), meaning that the vias 352(1)(1) and 352(1)(2) do not intersect the die cavity 362 in the first horizontal direction (X-axis direction and / or Y-axis direction). However, other vias 352(1)(2) and 352(2)(2) of the first metallization layer 336(1) in the form of metal interconnects are located inside the die cavity 362 in the first horizontal direction (X-axis direction and / or Y-axis direction), meaning that these other vias 352(1)(2) and 352(2)(2) intersect and are adjacent to the die cavity 362 in the first horizontal direction (X-axis direction and / or Y-axis direction). In this example, the first metallization layer 336(1) is an mSAP metallization layer, which means that the via 352(1)(2) is located close to the die cavity 362, wherein the thermal coupling of the via with the die cavity 362 can provide increased thermal coupling and heat dissipation for the die extending into the die cavity 362.

[0073] Furthermore, in this example, such as Figure 4B As shown, the lower surface 416 of vias 352(1)(2) is exposed to the die cavity 362 in this example to enhance thermal coupling, such that the material of the insulating layer 346 is not disposed between the lower surface 416 of vias 352(1)(2) and the die cavity 362, but this is not mandatory. In this example, the first metal interconnect layer 336(1) also includes its metal interconnects 338(1), which are coupled to the metal interconnects 338(2) and vias 352(2)(2) to provide a thermal conduction path through the interposer substrate 302B for improved heat dissipation. In this example, the lower surface 416 of vias 352(1)(2) is directly adjacent to the die cavity 362, meaning that the lower surface 416 of vias 352(1)(2) is directly accessible through the die cavity 362. However, the lower surface 416 of the via 352(1)(2) may also be indirectly adjacent to the die cavity 362, which means that there may be an intermediate component or material between the lower surface 416 of the via 352(1)(2) and the die cavity 362.

[0074] Figure 4C This is a side view of another exemplary interposer substrate 302C, which is in the form of a coreless mSAP interposer substrate 334C and can be configured as... Figure 3A and Figure 3B The interpolator substrate 302 in the IC package 300. It should be noted that the interpolator substrate 302C can be an organic interpolator substrate or an inorganic interpolator substrate, and may include one or more RDLs as discussed above with respect to the interpolator substrate 102. Figure 4C Intercalator substrates 302C and 334C in Figures 3A to 3B and Figure 4B Common elements among interpolator substrates 302, 302A, 302B, 334, 334A, and 334B are indicated by common element markings.

[0075] refer to Figure 4C The vias 352(1)(2) and 352(2)(2), which are in the form of metal interconnects, are located within the die cavity 362 in the first horizontal direction (X-axis direction and / or Y-axis direction), like Figure 4BAs in the interposer substrate 302B. However, in this example, the lower surface 416 of the vias 352(1)(2) is recessed from the bottom surface 418 of the first metallization layer 336(1). This may be due to an etching or removal process for removing the metal portion of the vias 352(1)(2) in the first metallization layer 336(1). In this example, the lower surface 416 of the vias 352(1)(2) is still exposed to the die cavity 362 for improved thermal coupling. In this example, the lower surface 416 of the vias 352(1)(2) is directly adjacent to the die cavity 362, meaning that the lower surface 416 of the vias 352(1)(2) is directly accessible through the die cavity 362. However, the lower surface 416 of the via 352(1)(2) may also be indirectly adjacent to the die cavity 362, which means that there may be an intermediate component or material between the lower surface 416 of the via 352(1)(2) and the die cavity 362.

[0076] Figure 5A and Figure 5B This is a side view of another exemplary IC package 500, which also includes a die-mounted interposer substrate 502 coupled to the die package 304, like... Figure 3A and Figure 3B Like the IC package 300 in the middle. Figure 5A As shown, the interposer substrate 502 is a cored interposer substrate 502 because it includes a core layer 504 provided to enhance the rigidity of the interposer substrate 502. It should be noted that the interposer substrate 502 can be an organic or inorganic interposer substrate and can include one or more RDLs as discussed above with respect to the interposer substrate 102. Figure 5A and Figure 5B IC package 500 and Figure 3A and Figure 3B Common components among the IC packages 300 are indicated by common component markings.

[0077] like Figure 5A As shown, the IC package 500 includes a cored interpolator substrate 502, which serves as a cored mSAP interpolator substrate 534. As... Figure 5BAs shown, the interposer substrate 502, which is the cored mSAP interposer substrate 534, means that one or more of the metallization layers 336(1), 336(2) (also referred to as mSAP metallization layers 336(1), 336(2)) of the interposer substrate include corresponding metal interconnects 338(1), 338(2) formed adjacent to the corresponding insulating layers 342(1), 342(2). The metallization layers 336(1), 336(2) extend in a first horizontal direction (X-axis direction and Y-axis direction). The metal interconnects 338(1), 338(2) can be formed to facilitate both horizontal wiring in the first horizontal direction (X-axis direction and / or Y-axis direction) and vertical wiring in the second vertical direction (Z-axis direction). The core layer 504 is disposed between the metallization layers 336(1), 336(2) in the second vertical direction (Z-axis direction) and coupled to these metallization layers. In this example, core layer 504 includes vias 552(1) and 552(2) that couple a first metal interconnect 338(1) to a second metal interconnect 338(2) to provide signal routing through core layer 504.

[0078] Continue to refer to Figure 5B The interposer substrate 502 includes a die cavity 362 integrated in the outer solder mask layer 344, like Figure 3A and Figure 3B As in the interpolator substrate 302. The above is about... Figure 3A and Figure 3B The IC package 300 describes the details of the die cavity 362.

[0079] Figure 6A This is a corresponding side view of another exemplary interposer substrate 502A, which takes the form of a cored mSAP interposer substrate 534A and can be configured as... Figure 5A and Figure 5B The interpolator substrate 502 in the IC package 500. Figure 6A Intercalator substrates 502A and 534A in Figure 5A and Figure 5B Common elements between interpolator substrates 502 and 534 are indicated by common element designation. It should be noted that interpolator substrate 502A can be an organic or inorganic interpolator substrate and may include one or more RDLs as discussed above with respect to interpolator substrate 102. In this example, like... Figure 4A Like the interposer substrate 302A in the middle, the metal pillar 350(2) is in the form of a metal plate 414 to provide a larger area of ​​metal material, thereby providing increased thermal coupling with the die cavity 362 for heat dissipation. Figure 6A Intercalator substrates 502A and 534A in Figure 5A and Figure 5BOther details of the common elements between interpolator substrates 502 and 534 are as previously described.

[0080] Figure 6B This is a side view of another exemplary interposer substrate 502B, which is in the form of a cored mSAP interposer substrate 534B and can be configured as... Figure 5A and Figure 5B The interpolator substrate 502 in the IC package 500. Figure 6B Intercalator substrates 502B and 534B in Figures 5A to 5B and Figure 6A Common elements among interpolator substrates 502, 502A, 534, and 534A are indicated by common element designations. It should be noted that interpolator substrate 502B can be an organic or inorganic interpolator substrate and may include one or more RDLs as discussed above with respect to interpolator substrate 102. (Similar to...) Figure 4B As discussed in the example interpolator substrates 302B and 334B, Figure 6B In this example, the lower surface 416 of the via 352(1)(2) in the first metallization layer 336(1) of the interposer substrate 502B is exposed to the die cavity 362 to enhance thermal coupling, such that the material of the insulating layer 346 is not disposed between the lower surface 416 of the via 352(1)(2) and the die cavity 362, but this is not necessary. Figure 6B Intercalator substrates 502B and 534B in Figure 5A and Figure 5B Other details of the common elements between interpolator substrates 502 and 534 are as previously described.

[0081] Figure 6C This is a side view of another exemplary interposer substrate 502C, which takes the form of a cored mSAP interposer substrate 534C and can be configured as... Figure 5A and Figure 5B The interpolator substrate 502 in the IC package 500. Figure 6C Intercalator substrates 502C and 534C in Figures 5A to 6B Common elements among interpolator substrates 502, 502A, 502B, 534, 534A, and 534B are indicated by common element designations. Note that interpolator substrate 502C may be an organic or inorganic interpolator substrate and may include one or more RDLs as discussed above with respect to interpolator substrate 102.

[0082] refer to Figure 6CThe vias 352(1)(2) and 352(2)(2), which are in the form of metal interconnects, are located within the die cavity 362 in the first horizontal direction (X-axis direction and / or Y-axis direction), like Figure 6B As in the interposer substrate 502B. However, in this example, the lower surface 416 of the vias 352(1)(2) is recessed from the bottom surface 418 of the first metallization layer 336(1). This may be due to an etching or removal process for removing the metal portion of the vias 352(1)(2) in the first metallization layer 336(2). In this example, the lower surface 416 of the vias 352(1)(2) is still exposed to the die cavity 362 for improved thermal coupling.

[0083] An interposer substrate that can be coupled to a die package can be manufactured according to a manufacturing process, wherein the outer layer of the interposer substrate includes an integrated die cavity for supporting die extension into the interposer substrate by: exposing metal interconnects in the outer metallization layer of the interposer substrate to the die cavity for enhanced die heat dissipation; and / or reducing the distance between the interposer substrate and the package substrate, thereby supporting vertical interconnects with reduced aspect ratio and reduced pitch to couple the interposer substrate to the package substrate for signal routing, the interposer substrate including but not limited to Figures 1A to 6C The interpolator substrate in the middle. In this respect, Figure 7 This illustrates the manufacture of interpolation substrates (including but not limited to) Figures 1A to 6C A flowchart of an exemplary manufacturing process 700 for interpolator substrates 102, 102A, 102B, 102C, 302, 302A, 302B, 302C, 502, 502A, 502B, 502C) is provided. The interpolator substrate includes an integrated die cavity for supporting die extension into the interpolator substrate by: exposing metal interconnects in the outer metallization layer of the interpolator substrate to the die cavity for enhanced die heat dissipation; and / or reducing the distance between the interpolator substrate and the package substrate, thereby supporting vertical interconnects with reduced aspect ratio and reduced pitch to couple the interpolator substrate to the package substrate for signal routing. Figure 7 The manufacturing process 700 is discussed with reference to the interposer substrates 102, 102A in Figures 1 to 2A, but this manufacturing process is not limiting and can be used to manufacture... Figures 2B to 6C The interpolator substrates in the middle are 102B, 102C, 302, 302A, 302B, 302C, 502, 502A, 502B, and 502C.

[0084] In this respect, such as Figure 7 As shown, the manufacturing process 700 of the interposer substrate 102 may include forming a first metallization layer 136(1) extending in a first direction (X-axis direction and / or Y-axis direction). Figure 7 (in frame 702). Forming the first metallization layer 136(1) includes forming a plurality of first metal interconnects 138(1)(1). Figure 7 (in the frame 704); and forming one or more second metal interconnects 138(1)(2), each including a first (bottom) surface 216. Figure 7 (Box 706 in the middle). Manufacturing process 700 also includes forming an outer layer 144, which is adjacent to the first metallization layer 136(1) in a second direction (Z-axis direction) orthogonal to the first direction (X-axis direction and / or Y-axis direction). Figure 7 (Box 708 in the middle). Forming the outer layer 144 includes forming an outer insulating layer 146, which includes a plurality of outer metal interconnects 148 (1)(1) each coupled to a plurality of first metal interconnects 138(1)(1). Figure 7 (Frame 710 in the middle). Manufacturing process 700 also includes forming a die cavity 162, which is adjacent in a second direction (Z-axis direction) to the first (bottom) surface 216 of each of one or more second metal interconnects 138(1)(2) in at least a portion of the outer insulation layer 146. Figure 7 (Box 712 in the middle).

[0085] An interposer substrate that can be coupled to a die package can be manufactured in other manufacturing processes, wherein the outer layer of the interposer substrate includes an integrated die cavity for supporting die extension to the interposer substrate by: exposing metal interconnects in the outer metallization layer of the interposer substrate to the die cavity for enhanced die heat dissipation; and / or reducing the distance between the interposer substrate and the package substrate to support vertical interconnects with reduced aspect ratio and reduced pitch to couple the interposer substrate to the package substrate for signal routing, the interposer substrate including but not limited to Figures 1A to 6C The interpolator substrates in the middle are 102, 102A, 102B, 102C, 302, 302A, 302B, 302C, 502, 502A, 502B, and 502C.

[0086] For example, Figures 8A to 8D This is a flowchart illustrating a manufacturing process 800 of an interpolator substrate, the interpolator substrate including an integrated die cavity that supports die extension into the interpolator substrate by: exposing metal interconnects in the outer metallization layer of the interpolator substrate to the die cavity for enhanced die heat dissipation; and / or reducing the distance between the interpolator substrate and the package substrate, thereby enabling vertical interconnects with reduced aspect ratio and reduced pitch to couple the interpolator substrate to the package substrate for signal routing, the interpolator substrate including but not limited to... Figures 1A to 6CThe interpolator substrates in the middle are 102, 102A, 102B, 102C, 302, 302A, 302B, 302C, 502, 502A, 502B, and 502C. Figures 9A to 9I-3 It is based on Figures 8A to 8D Exemplary manufacturing stages 900A to 900I-3 during the manufacturing of the interpolator substrate in the exemplary manufacturing process 800 are described below. Figures 1A to 1B and Figure 2A-2 Discussion of exemplary interpolator substrates 102 and 102A Figures 8A to 8D The manufacturing process 800 is mentioned, but this process is not limiting and can be used to manufacture... Figures 2B to 6C The interpolator substrates in the middle are 102B, 102C, 302, 302A, 302B, 302C, 502, 502A, 502B, and 502C.

[0087] In this respect, such as Figure 9A As shown in exemplary manufacturing stage 900A, the first step in the manufacturing process 800 of the interposer substrate 102 may be providing a carrier substrate 902 in which a metallization layer is formed ( Figure 8A (Box 802 in the middle). Then, as... Figure 9B As shown in exemplary manufacturing stage 900B, the next step in manufacturing process 800 is to deposit first metal layers 904, 906 (e.g., copper layers) on each respective side 908, 910, and then pattern metal interconnects 138(1) in the respective first metal layers 904, 906 as part of the preparation of metallization layers. Figure 8A (See box 804 in the image). For example, after first metal layers 904, 906 are disposed as continuous metal layers on both sides 908, 910 of carrier substrate 902, a photoresist layer may be laminated over the first metal layers 904, 906, and then selectively exposed and developed to define the desired pattern of the first metal interconnect 138(1) which will be part of the first metallization layer 136(1). In this example, it should be noted that the process involves forming metallization layers of two (2) interposer substrates 102, which can then be removed from the carrier substrate 902 respectively to provide two (2) separate interposer substrates 102 for inclusion in an IC package. Then, as... Figure 9C As shown in exemplary manufacturing stage 900C, the next step in manufacturing process 800 is to form a first insulating layer 142(1) on the first metal interconnect 138(1) on each side 908, 910 of the carrier substrate 902 as part of the first metallization layer 136(1). Figure 8A (See box 806 in the image). For example, insulating layer 142(1) may be a layer of PPG material.

[0088] Then, as Figure 9DAs shown in exemplary manufacturing stage 900D, the next step in manufacturing process 800 is to form a first via 152 (1) in the first insulating layer 142 (1) to form a first metallization layer 136 (1). Figure 8B (in box 808). Then the second metal layers 912, 914 are disposed on the first metallization layer 136 (1), and are then selectively exposed and developed to define the desired pattern of the second metal interconnect 138 (2) which will be part of the second metallization layer 136 (2). For example, after the second metal layers 912, 914 are disposed on both sides 908, 910 of the first metallization layer 136 (1) as continuous metal layers, a photoresist layer may be laminated on the second metal layers 912, 914, and then selectively exposed and developed to define the desired pattern of the second metal interconnect 138 (2) which will be part of the second metallization layer 136 (2). Then, as Figure 9E As shown in exemplary manufacturing stage 900E, the next step in manufacturing process 800 is to form a second insulating layer 142(2) on the second metal interconnect 138(2) as part of the second metallization layer 136(2). Figure 8B (See box 810 in the image). For example, the second insulating layer 142(2) can be a PPG material layer. Then, as... Figure 9F As shown in the exemplary manufacturing stage 900F, the next step in the manufacturing process 800 is to form a second via 152 (2) in the second insulating layer 142 (2) to form a second metallization layer 136 (2) and to form a metal interconnect 158 ​​for the area that will become a solder resist layer. Figure 8B (Box 812 in the middle).

[0089] Then, as Figure 9G As shown in the exemplary manufacturing stage 900G, the next step in the manufacturing process 800 is to separate the carrier substrate 902 from the metallization layers 136(1), 136(2) constructed on each side 908, 910 to provide separate structures, thereby ultimately providing two (2) separate intercalator substrates 102. Figure 8C (Box 814 in the middle). Then, as... Figure 9H As shown in exemplary manufacturing stage 900H, in preparation for the formation of solder mask layer 144 and die cavity 162, metal pillars 150 (e.g., copper pillars) are formed to contact the first metal interconnect 138 (1) exposed from the first metallization layer 136 (1). Figure 8C (Box 816 in the text). Additionally, as... Figure 9HAs shown in manufacturing stage 900H, a first metal interconnect 138(1)(2) located within the die cavity 162 can be etched in a first horizontal direction (X-axis direction and / or Y-axis direction) to expose the first metal interconnect 138(1)(2) to the die cavity 162 for better thermal conductivity, as previously discussed. Figure 1A and Figure 1B The interpolator substrate 102 discussed in the paper.

[0090] Then, as corresponding Figure 9I-1 , Figure 9I-2 and Figure 9I-3 Exemplary manufacturing stages 900I-1, 900I-2, and 900I-3 (these exemplary manufacturing stages are related to...) Figure 9H As shown in the manufacturing stage 900H (mutually exclusive stage), the final interpolator substrates 102A, 102B, and 102C are formed. Figure 8D (Frames 818-1, 818-2, and 818-3 in the diagram). The final interpolator substrates 102A, 102B, and 102C are respectively located in... Figures 2A-1 to 2A-2 , Figure 2B and Figure 2C The interpolator substrates shown are those previously described. Figures 9I-1 to 9I-3 As shown, a portion of forming the final interposer substrates 102A, 102B, and 102C involves forming insulating layers on the metal interconnects 158 and metal pillars 150 to form corresponding solder resist layers 154 and 144 on the respective second metallization layer 136(2) and first metallization layer 136(1). Figure 9I-1 As shown, the metal interconnects 138(1)(2) are as previously described. Figure 2A-1 and Figure 2A-2 The metal plate 214 described in the interposer substrate 102A. The first insulating layer 142(1) of the first metallization layer 136(1) is also processed, wherein material is removed to extend the die cavity 162 into the first metallization layer 136(1), thereby creating a second stepped structure 210. Figure 9I-2 As shown, the metal interconnects 138(1)(2) are as previously described. Figure 2B Vias 152(1)(2) are described in the interposer substrate 102B. The first insulating layer 142(1) of the first metallization layer 136(1) is also processed, wherein material is removed to extend the die cavity 162 into the first metallization layer 136(1), thereby creating a second stepped structure 210. As... Figure 9I-3 As shown, the metal interconnects 138(1)(2) are as previously described. Figure 2BThe vias 152(1)(2) described in the interposer substrate 102B are recessed into the first insulating layer 142(1). The first insulating layer 142(1) of the first metallization layer 136(1) is also processed in which material is removed to extend the die cavity 162 into the first metallization layer 136(1), thereby creating the second stepped structure 210.

[0091] Figures 10A to 10B This is a flowchart illustrating a manufacturing process 1000 for manufacturing an IC package including an interpolator substrate. The interpolator substrate includes an integrated die cavity that supports die extension into the interpolator substrate by: exposing metal interconnects in the outer metallization layer of the interpolator substrate to the die cavity for enhanced die heat dissipation; and / or reducing the distance between the interpolator substrate and the package substrate, thereby enabling vertical interconnects with reduced aspect ratio and reduced pitch to couple the interpolator substrate to the package substrate for signal routing. The interpolator substrate includes, but is not limited to, […]. Figures 1A to 6C The interpolator substrates in the middle are 102, 102A, 102B, 102C, 302, 302A, 302B, 302C, 502, 502A, 502B, and 502C. Figures 11A to 11D It is based on Figures 10A to 10B The exemplary manufacturing process 1000 in the example describes exemplary manufacturing stages 1100A to 1100D during the manufacturing of an IC package, and the IC package includes, but is not limited to, exemplary manufacturing stages 1100A to 1100D. Figures 1A to 1B , Figures 3A to 3B and Figures 5A to 5B The IC packages in question are 100, 300, and 500.

[0092] In this respect, such as Figure 11A As shown in the exemplary manufacturing stage 1100A, the first step in the manufacturing process 1000 may be providing a packaging substrate 108 prepared for coupling of the first die 106. Figure 10A (Box 1002 in the middle). Then, as... Figure 11B As shown in exemplary manufacturing stage 1100B, the next step in manufacturing process 1000 may be coupling the first die 106 to the packaging substrate 108 to form a die package 104. Figure 10A (Box 1004 in the text). Then, as... Figure 11C As shown in the exemplary manufacturing stage 1100C, the next step in the manufacturing process 1000 is to provide an interposer substrate 102 to be coupled to the die package 104 to form an IC package 1102. Figure 10B (Frame 1006 in the middle). The first die 106 of the die package 104 is aligned with the die cavity 162 in the second vertical direction (Z-axis direction), and the metal post 150 is also aligned with the vertical interconnect 130 of the die package 104 in the second vertical direction (Z-axis direction). Then, as Figure 11D As shown in the exemplary manufacturing stage 1100D, the next step in the manufacturing process 1000 involves coupling the interposer substrates 102, 102B to the die package 104 to form the IC package 1102. Figure 10B (Box 1008 in the image). In this example, the interpolator substrate 102 is... Figure 2B The interpolator substrate 102B is used, but this interpolator substrate is not limiting.

[0093] It should be understood that the terms “first,” “second,” “third,” etc., used herein are relative terms and do not imply limitation or a strict orientation. It should also be understood that the terms “top,” “upper,” “above,” “bottom,” “lower,” and “below” used herein are relative terms and do not imply limitation or a strict orientation. An element referred to as “top,” “upper,” or “above” does not always need to be oriented above an element referred to as “bottom,” “lower,” or “below” relative to the ground, and vice versa. An element referred to as “top,” “upper,” “above,” or “bottom,” “lower,” or “below” may be at the top or bottom only relative to the example and the specific example illustrated. An element referred to as “top,” “upper,” “above,” “bottom,” “lower,” or “below” in another element is not necessarily relative to the ground, and vice versa. An element referred to as “top,” “upper,” or “above” may be above or below such other element only relative to the example and the specific example illustrated.

[0094] Furthermore, as discussed in this paper, "adjacent" objects refer to objects being next to or near another stated object. Adjacent objects may not be directly physically coupled to each other. Objects can be directly adjacent to another object, meaning that such objects are directly next to or near another object, without any other object or layer situated between the directly adjacent objects. Objects can be indirectly or indirectly adjacent to another object, meaning that such objects are not directly next to or near each other, but rather with an intermediate object or layer situated between the indirectly adjacent objects.

[0095] IC packages with interpolation substrates can be disposed in or integrated into any processor-based device. These interpolation substrates include an integrated die cavity that supports die extension into the interpolation substrate in such a way that: metal interconnects in the outer metallization layer of the interpolation substrate are exposed to the die cavity for enhanced die heat dissipation; and / or the distance between the interpolation substrate and the package substrate is reduced, thereby enabling vertical interconnects with reduced aspect ratio and reduced pitch to couple the interpolation substrate to the package substrate for signal routing; one or more IC packages including interpolation substrates include, but are not limited to, those with interpolation substrates. Figures 1A to 6C , Figures 9I-1 to 9I-3 and Figure 11D The interpolator substrates 102, 102A, 102B, 102C, 302, 302A, 302B, 302C, 502, 502A, 502B, 502C and... Figures 1A to 1B , Figures 3A to 3B , Figures 5A to 5B and Figure 11D The IC packages 100, 300, 500, and 1102 are available, and can be customized according to the manufacturing process (including but not limited to...) Figure 7 , Figures 8A to 8D and Figures 10A to 10B The exemplary manufacturing processes 700, 800, 1000, and any aspects disclosed herein are used to manufacture the interposer substrate, wherein the outer layer of the interposer substrate includes an integrated die cavity that can support die extension into the interposer substrate by exposing metal interconnects in the outer metallization layer of the interposer substrate to the die cavity for enhanced die heat dissipation; and / or reducing the distance between the interposer substrate and the package substrate, thereby enabling vertical interconnects with reduced aspect ratio and reduced pitch to couple the interposer substrate to the package substrate for signal wiring. Examples not limited to these include: set-top boxes, entertainment units, navigation devices, communication devices, fixed location data units, mobile location data units, Global Positioning System (GPS) devices, mobile phones, cellular phones, smartphones, Session Initiation Protocol (SIP) phones, tablet devices, tablet phones, servers, computers, portable computers, mobile computing devices, wearable computing devices (e.g., smartwatches, health or fitness trackers, glasses, etc.), desktop computers, personal digital assistants (PDAs), monitors, computer monitors, televisions, tuners, radios, satellite radios, music players, digital music players, portable music players, digital video players, video players, digital video disc (DVD) players, portable digital video players, automobiles, vehicle components, avionics systems, drones, and multi-rotor aircraft.

[0096] In this respect, Figure 12 An exemplary wireless communication device 1200 is illustrated, which includes one or more IC packages 1202, 1202(1), 1202(2) (including but not limited to...) Figures 1A to 1B , Figures 3A to 3B , Figures 5A to 5B and Figure 11D IC packages 100, 300, 500, and 1102, each of which includes interposer substrates 1203, 1203(1), and 1203(2) (including but not limited to) Figures 1A to 6C , Figures 9I-1 to 9I-3 and Figure 11DThe interposer substrates 102, 102A, 102B, 102C, 302, 302A, 302B, 302C, 502, 502A, 502B, 502C), each of the one or more IC packages includes an interposer substrate. The interposer substrate includes an integrated die cavity that supports die extension into the interposer substrate by: exposing metal interconnects in the outer metallization layer of the interposer substrate to the die cavity for enhanced die heat dissipation; and / or reducing the distance between the interposer substrate and the package substrate, thereby enabling support for a reduced aspect ratio. The interposer substrate is coupled to the package substrate for signal routing by vertical interconnects with reduced pitch; one or more IC packages include an interposer substrate, wherein the outer layer of the interposer substrate includes an integrated die cavity that supports die extension into the interposer substrate by exposing metal interconnects in the outer metallization layer of the interposer substrate to the die cavity for enhanced die heat dissipation; and / or reducing the distance between the interposer substrate and the package substrate, thereby enabling vertical interconnects with reduced aspect ratio and reduced pitch to couple the interposer substrate to the package substrate for signal routing. IC packages 1202, 1202(1), 1202(2) and their interposer substrates 1203, 1203(1), 1203(2) may be manufactured according to the manufacturing process (including but not limited to) Figure 7 , Figures 8A to 8D and Figures 10A to 10B The exemplary manufacturing processes 700, 800, 1000 in this document are used to manufacture the product and any of the aspects disclosed herein.

[0097] As an example, the wireless communication device 1200 may include any of the devices mentioned above or may be incorporated into any of the devices mentioned above. Figure 12 As shown, the wireless communication device 1200 includes a transceiver 1204 and a data processor 1206. The data processor 1206 may include memory for storing data and program code. The transceiver 1204 includes a transmitter 1208 and a receiver 1210 supporting bidirectional communication. Generally, the wireless communication device 1200 may include any number of transmitters 1208 and / or receivers 1210 for any number of communication systems and frequency bands. All or part of the transceiver 1204 may be implemented on one or more analog ICs, RF ICs (RFICs), mixed-signal ICs, etc.

[0098] The transmitter 1208 or receiver 1210 can be implemented using either a superheterodyne architecture or a direct conversion architecture. In a superheterodyne architecture, the signal undergoes multi-stage frequency conversion between RF and baseband; for example, for receiver 1210, it is converted from RF to intermediate frequency (IF) in one stage and then from IF to baseband in another stage. In a direct conversion architecture, the signal is converted between RF and baseband in a single stage. Superheterodyne and direct conversion architectures can use different circuit blocks and / or have different requirements. Figure 12 In the wireless communication device 1200, the transmitter 1208 and the receiver 1210 are implemented using a direct frequency conversion architecture.

[0099] In the transmission path, data processor 1206 processes the data to be transmitted and provides I and Q analog output signals to transmitter 1208. In the exemplary wireless communication device 1200, data processor 1206 includes digital-to-analog converters (DACs) 1212(1) and 1212(2) to convert digital signals generated by data processor 1206 into I and Q analog output signals (e.g., I and Q output currents) for further processing.

[0100] Within transmitter 1208, low-pass filters 1214(1) and 1214(2) filter the I and Q analog output signals, respectively, to remove unwanted signals caused by the previous digital-to-analog conversion. Amplifiers (AMPs) 1216(1) and 1216(2) amplify the signals from low-pass filters 1214(1) and 1214(2), respectively, and provide I and Q baseband signals. Upconverter 1218 upconverts the I and Q baseband signals using the I and Q TX LO signals from the transmit (TX) local oscillator (LO) signal generator 1222 via mixers 1220(1) and 1220(2) to provide upconverted signal 1224. Filter 1226 filters the upconverted signal 1224 to remove unwanted signals caused by upconversion and noise in the receive band. Power amplifier (PA) 1228 amplifies the up-converted signal 1224 from filter 1226 to obtain the desired output power level and provide a transmit RF signal. The transmit RF signal is routed through duplexer or switch 1230 and transmitted via antenna 1232.

[0101] In the receiving path, antenna 1232 receives signals transmitted by the base station and provides the received RF signal, which is routed through duplexer or switch 1230 and provided to low-noise amplifier (LNA) 1234. Duplexer or switch 1230 is designed to operate using a specific receive (RX) to TX duplexer frequency separation, such that the RX signal is isolated from the TX signal. The received RF signal is amplified by LNA 1234 and filtered by filter 1236 to obtain the desired RF input signal. Downconversion mixers 1238(1) and 1238(2) mix the output of filter 1236 with the I and Q RX LO signals (i.e., LO_I and LO_Q) from RX LO signal generator 1240 to generate I and Q baseband signals. The I and Q baseband signals are amplified by AMPs 1242(1) and 1242(2) and further filtered by low-pass filters 1244(1) and 1244(2) to obtain I and Q analog input signals, which are provided to data processor 1206. In this example, data processor 1206 includes analog-to-digital converters (ADCs) 1246(1) and 1246(2) to convert the analog input signals into digital signals to be further processed by data processor 1206.

[0102] exist Figure 12 In the wireless communication device 1200, a TX LO signal generator 1222 generates I and Q TXLO signals for up-conversion, while an RX LO signal generator 1240 generates I and Q RX LO signals for down-conversion. Each LO signal is a periodic signal with a specific base frequency. A TX phase-locked loop (PLL) circuit 1248 receives timing information from a data processor 1206 and generates control signals for adjusting the frequency and / or phase of the TX LO signals from the TX LO signal generator 1222. Similarly, an RX PLL circuit 1250 receives timing information from a data processor 1206 and generates control signals for adjusting the frequency and / or phase of the RX LO signals from the RX LO signal generator 1240.

[0103] Figure 13 An example of a processor-based system 1300 is illustrated, which includes one or more IC packages 1302, 1302(1) to 1302(8) (including but not limited to) Figures 1A to 1B , Figures 3A to 3B , Figures 5A to 5B and Figure 11D IC packages 100, 300, 500, 1102, etc., each of the one or more IC packages includes interposer substrates 1304, 1304(1) to 1304(8) (including but not limited to) Figures 1A to 6C , Figures 9I-1 to 9I-3 and Figure 11D The interposer substrates 102, 102A, 102B, 102C, 302, 302A, 302B, 302C, 502, 502A, 502B, and 502C include an integrated die cavity that supports die extension to the interposer substrate by exposing metal interconnects in the outer metallization layer of the interposer substrate to the die cavity for enhanced die heat dissipation; and / or reducing the distance between the interposer substrate and the package substrate, thereby enabling support for vertical interconnects with reduced aspect ratio and reduced pitch. Interpolating an interpolator substrate to a package substrate for signal routing; one or more IC packages including an interpolator substrate, wherein the outer layer of the interpolator substrate includes an integrated die cavity that supports die extension into the interpolator substrate by: exposing metal interconnects in the outer metallization layer of the interpolator substrate to the die cavity for enhanced die heat dissipation; and / or reducing the distance between the interpolator substrate and the package substrate, thereby enabling vertical interconnects with reduced aspect ratio and reduced pitch to couple the interpolator substrate to the package substrate for signal routing. IC packages 1302, 1302(1) to 1302(8) and their interpolator substrates 1304, 1304(1) to 1304(8) may be manufactured according to the manufacturing process (including but not limited to) Figure 7 , Figures 8A to 8D and Figures 10A to 10B The exemplary manufacturing processes 700, 800, 1000 in this document are used to manufacture the product and any of the aspects disclosed herein.

[0104] In this example, the processor-based system 1300 may include an interposer substrate 1304 included in an IC package 1302 (such as a system-on-a-chip (SoC) 1306). The processor-based system 1300 includes a CPU 1308, which includes one or more processors 1310, which may also be referred to as a CPU core or processor core. The CPU 1308 may be disposed in the IC package 1302(1) including the interposer substrate 1304(1). The CPU 1308 may have a cache memory 1312 coupled to the CPU 1308 for fast access to temporarily stored data. The CPU 1308 is coupled to a system bus 1314 and may be coupled to master and slave devices included in the processor-based system 1300. As is well known, the CPU 1308 communicates with these other devices by exchanging address, control, and data information via the system bus 1314. For example, the CPU 1308 may communicate a bus transaction request to a memory controller 1316, which is an example of a slave device. Figure 13 Not illustrated, but multiple system buses 1314 may be provided, each of which constitutes a different architecture.

[0105] Other master and slave devices can be connected to system bus 1314. For example... Figure 13 As illustrated, by way of example, these devices may include a memory system 1320, one or more input devices 1322, one or more output devices 1324, one or more network interface devices 1326, and one or more display controllers 1328, the memory system including a memory controller 1316 and a memory array 1318. The memory system 1320 may be disposed in an IC package 1302(2) including an interpolator substrate 1304(2). The network interface device 1326 may be disposed in an IC package 1302(3) including an interpolator substrate 1304(3). Each of the memory system 1320, one or more input devices 1322, one or more output devices 1324, one or more network interface devices 1326, and one or more display controllers 1328 may be disposed in the same or different circuit packages. Input device 1322 and / or output device 1324 may be disposed in corresponding IC packages 1302(4), 1302(5) including corresponding interpolator substrates 1304(4), 1304(5). Input device 1322 may include any type of input device, including but not limited to input keys, switches, voice processors, etc. Output device 1324 may include any type of output device, including but not limited to audio, video, other visual indicators, etc. Network interface device 1326 may be any device configured to allow the exchange of data to and from network 1330. Network 1330 may be any type of network, including but not limited to wired or wireless networks, private or public networks, local area networks (LANs), wireless local area networks (WLANs), wide area networks (WANs), Bluetooth. ™ Networks and the Internet. The network interface device 1326 can be configured to support any type of communication protocol desired.

[0106] CPU 1308 may also be configured to access display controller 1328 via system bus 1314 to control information transmitted to one or more displays 1332. Display 1332 may be disposed in IC package 1302(6) including interpolator substrate 1304(6). Display controller 1328 transmits information to be displayed to display 1332 via one or more video processors 1334, which process the information to be displayed into a format suitable for display 1332. As an example, display controller 1328 and video processor 1334 may be disposed in corresponding IC packages 1302(7), 1302(8) including interpolator substrates 1304(7), 1304(8), or in the same IC package 1302, or in the same IC package 1302(1) containing CPU 1308. Display 1332 may include any type of display, including but not limited to cathode ray tube (CRT), liquid crystal display (LCD), plasma display, light-emitting diode (LED) display, etc.

[0107] Those skilled in the art will further understand that the various exemplary logic blocks, modules, circuits, and algorithms described in connection with the aspects disclosed herein can be implemented as electronic hardware, stored in memory or another computer-readable medium and executed by a processor or other processing device, or a combination of both. The memory disclosed herein can be of any type and size and can be configured to store any type of information desired. To clearly illustrate this interchangeability, the functionality of the various exemplary components, blocks, modules, circuits, and steps has been generally described above. How such functionality is implemented depends on the specific application, design choices, and / or design constraints imposed on the overall system. Those skilled in the art may implement the described functionality in different ways for each specific application, but such specific implementation decisions should not be construed as departing from the scope of this disclosure.

[0108] The various exemplary logic blocks, modules, and circuits described in conjunction with the aspects disclosed herein may be implemented or executed using a processor, digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic unit, discrete hardware component, or any combination thereof, designed to perform the functions described herein. The processor may be a microprocessor, but in alternative embodiments, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors cooperating with a DSP core, or any other such configuration).

[0109] The aspects disclosed herein may be embodied in hardware and instructions stored in the hardware, and may reside in, for example, random access memory (RAM), flash memory, read-only memory (ROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), registers, hard disks, removable disks, CD-ROMs, or any other form of computer-readable medium known in the art. An exemplary storage medium is coupled to a processor, enabling the processor to read information from and write information to the storage medium. Alternatively, the storage medium may be integral with the processor. The processor and storage medium may reside in an ASIC. The ASIC may reside in a remote station. Alternatively, the processor and storage medium may reside as discrete components in a remote station, base station, or server.

[0110] It should also be noted that the operational steps described in any of the exemplary aspects of this document are described for the purpose of providing examples and discussion. The described operations may be performed in many different orders other than the order illustrated. Furthermore, the operations described in a single operational step may actually be performed in multiple different steps. In addition, one or more operational steps discussed in the exemplary aspects may be combined. It should be understood that, as will be apparent to those skilled in the art, many different modifications may be made to the operational steps illustrated in the flowcharts. Those skilled in the art will also understand that any of a variety of different techniques and arts can be used to represent information and signals. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be mentioned throughout the above description may be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or optical particles, or any combination thereof.

[0111] The prior description of this disclosure is provided to enable any person skilled in the art to make or use this disclosure. Various modifications to this disclosure will be apparent to those skilled in the art, and the general principles defined herein can be applied to other variations. Therefore, this disclosure is not intended to be limited to the examples and designs described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

[0112] Specific implementation examples are described in the following numbered clauses:

[0113] 1. An interpolator substrate, the interpolator substrate comprising:

[0114] A first metallization layer, extending in a first direction, comprising:

[0115] Multiple first metal interconnects; and

[0116] One or more second metal interconnects, each of the one or more second metal interconnects including a first surface;

[0117] An outer layer, which is adjacent to the first metallization layer in a second direction orthogonal to the first direction, includes:

[0118] An outer insulating layer, the outer insulating layer comprising a plurality of outer metal interconnects each coupled to a first metal interconnect in the plurality of first metal interconnects; and

[0119] A die cavity, wherein the die cavity is adjacent in the second direction to a first surface of each of the one or more second metal interconnects in at least a portion of the outer insulation layer.

[0120] 2. The interposer substrate according to Clause 1, wherein at least a portion of the first surface of the one or more second metal interconnects is exposed to the die cavity.

[0121] 3. The interposer substrate according to Clause 1 or 2, wherein the one or more second metal interconnects comprise metal plates.

[0122] 4. The interposer substrate according to clause 1 or 2, wherein:

[0123] The first metallization layer includes a third surface and a fourth surface opposite to the third surface in the second direction.

[0124] The third surface is adjacent to the die cavity and intersects the die cavity in the second direction; and

[0125] The first surface of the one or more second metal interconnects is coplanar with the fourth surface in the first direction.

[0126] 5. The interposer substrate according to clause 1 or 2, wherein:

[0127] The first metallization layer includes a third surface and a fourth surface opposite to the third surface in the second direction.

[0128] The third surface is adjacent to the die cavity and intersects the die cavity in the second direction; and

[0129] The first surface of the one or more second metal interconnects is recessed from the fourth surface into the first metallization layer in the first direction.

[0130] 6. The interposer substrate according to any one of clauses 1 to 5, wherein:

[0131] The outer layer includes a solder resist layer;

[0132] The plurality of external metal interconnects include a plurality of metal pillars; and

[0133] The solder resist layer includes a plurality of first openings, each of which is adjacent to one of the plurality of metal pillars.

[0134] 7. The interposer substrate according to Clause 6, wherein the plurality of metal pillars do not intersect the die cavity in the second direction.

[0135] 8. The interposer substrate according to any one of clauses 1 to 7, wherein the plurality of first metal interconnects do not intersect the die cavity in the second direction.

[0136] 9. An interposer substrate according to any one of clauses 1 to 8, wherein the one or more second metal interconnects intersect the die cavity at least partially in the second direction.

[0137] 10. The interposer substrate according to any one of clauses 1 to 9, further comprising: a second metallization layer, the second metallization layer being adjacent to the first metallization layer in the first direction.

[0138] in:

[0139] The first metallization layer is located between the outer layer and the second metallization layer in the first direction; and

[0140] The second metallization layer includes a plurality of third metal interconnects, each of which is coupled to a first metal interconnect among the plurality of first metal interconnects.

[0141] 11. The interpolator substrate according to any one of claims 1 to 10, wherein the first metallization layer comprises an embedded trace substrate (ETS) metallization layer, the embedded trace substrate (ETS) metallization layer comprising a first insulating layer,

[0142] The plurality of first metal interconnects include a plurality of first metal traces embedded in the first insulating layer.

[0143] 12. The interposer substrate according to Clause 11, wherein the one or more second metal interconnects include a plurality of second vias.

[0144] 13. The interposer substrate according to clause 11 or 12, wherein:

[0145] The first insulating layer further includes:

[0146] The non-recessed layer portion includes the plurality of first metal traces and has a first height in the second direction; and

[0147] The recessed layer portion includes the one or more second metal interconnects and forms a recessed region adjacent to the first surface of the one or more second metal interconnects; the recessed layer portion has a second height in the second direction that is less than the first height; and

[0148] The core cavity also includes the recessed area.

[0149] 14. The interposer substrate according to Clause 13, wherein the first insulating layer includes a stepped structure formed in a first portion of a second portion of the non-recessed layer portion adjacent to the recessed layer portion in the first direction.

[0150] 15. The interposer substrate according to Clause 14, wherein the die cavity is adjacent to the stepped structure.

[0151] 16. The interposer substrate according to any one of clauses 1 to 10, wherein the first metallization layer comprises a modified semi-additive process (mSAP) metallization layer, and the modified semi-additive process (mSAP) metallization layer comprises a first insulating layer.

[0152] The plurality of first metal interconnects are adjacent to the first insulating layer.

[0153] 17. The interposer substrate according to Clause 16, wherein the one or more second metal interconnects include a plurality of second vias.

[0154] 18. The interposer substrate according to clause 16 or 17, wherein:

[0155] The first insulating layer includes:

[0156] A first layer portion, the first layer portion having a first height in the second direction and adjacent to the plurality of first metal interconnects in the second direction; and

[0157] The second layer portion has the first height in the second direction and is adjacent to the one or more second metal interconnects in the second direction.

[0158] 19. The interposer substrate according to any one of Clauses 16 to 18, wherein the interposer substrate does not include a core layer.

[0159] 20. The interposer substrate according to any one of clauses 16 to 18, the interposer substrate further comprising: a core layer adjacent to the first metallization layer;

[0160] The first metallization layer is located between the core layer and the outer layer in the second direction.

[0161] 21. An interposer substrate according to any one of Clauses 1 to 20, said interposer substrate being integrated into a device selected from the group consisting of: set-top boxes; entertainment units; navigation devices; communication devices; fixed location data units; mobile location data units; global positioning system (GPS) devices; mobile phones; cellular phones; smartphones; session initiation protocol (SIP) phones; tablet computers; tablet phones; servers; computers; portable computers; mobile computing devices; wearable computing devices; desktop computers; personal digital assistants (PDAs); computer monitors; televisions; tuners; radios; satellite radios; music players; digital music players; portable music players; digital video players; video players; digital video disc (DVD) players; portable digital video players; automobiles; vehicle components; avionics systems; unmanned aerial vehicles; and multirotor aircraft.

[0162] 22. A method of manufacturing an interposer substrate for an integrated circuit (IC) package, the method comprising:

[0163] Forming a first metallization layer extending in a first direction, the formation comprising:

[0164] Forming multiple first metal interconnects; and

[0165] Form one or more second metal interconnects, each including a first surface;

[0166] Forming an outer layer adjacent to the first metallization layer in a second direction orthogonal to the first direction, the formation comprising:

[0167] An outer insulating layer is formed, the outer insulating layer comprising a plurality of outer metal interconnects each coupled to a first metal interconnect in the plurality of first metal interconnects; and

[0168] A die cavity is formed, wherein the die cavity is adjacent in the second direction to the first surface of each of the one or more second metal interconnects in at least a portion of the outer insulation layer.

[0169] 23. The method according to Clause 22, wherein forming the die cavity further comprises: exposing at least partially the first surface of the one or more second metal interconnects.

[0170] 24. The method according to clause 22 or 23, wherein forming the one or more second metal interconnects comprises: forming a metal plate.

[0171] 25. The method according to clause 22 or 23, wherein forming the one or more second metal interconnects comprises: forming the one or more second metal interconnects coplanar with a third surface of the first metallization layer, the third surface being adjacent to the die cavity and intersecting the die cavity in the second direction.

[0172] 26. The method according to clause 22 or 23, wherein forming the one or more second metal interconnects comprises: forming the one or more second metal interconnects recessed from a third surface of the first metallization layer, the third surface being adjacent to the die cavity and intersecting the die cavity in the second direction.

[0173] 27. The method according to any one of clauses 22 to 26, wherein forming the die cavity further comprises: removing a portion of the outer insulating layer adjacent to the one or more second metal interconnects from the outer layer.

[0174] 28. The method according to Clause 27, wherein forming the die cavity further comprises: removing a portion of the first insulating layer adjacent to the one or more second metal interconnects from the first metallization layer.

[0175] 29. An integrated circuit (IC) package, the integrated circuit (IC) package comprising:

[0176] Die package, the die package comprising:

[0177] A packaging substrate, the packaging substrate including a plurality of fourth metal interconnects;

[0178] A first die, the first die being coupled to the packaging substrate; and

[0179] Multiple vertical interconnects, each of which is coupled to a fourth metal interconnect among the multiple fourth metal interconnects; and

[0180] An interposer substrate, the interposer substrate being coupled to the die package in a second direction orthogonal to the first direction, the interposer substrate comprising:

[0181] A first metallization layer, extending in the first direction, comprising:

[0182] Multiple first metal interconnects; and

[0183] One or more second metal interconnects, each of the one or more second metal interconnects including a first surface;

[0184] An outer layer, coupled to the die package and located in the second direction between the die package and the first metallization layer, the outer layer comprising:

[0185] An outer insulating layer, the outer insulating layer comprising a plurality of outer metal interconnects each coupled to a first metal interconnect in the plurality of first metal interconnects and a vertical interconnect in the plurality of vertical interconnects; and

[0186] A die cavity, wherein the die cavity is adjacent, in at least a portion of the outer insulating layer, to a first surface of each of the one or more second metal interconnects in the second direction;

[0187] The first die is at least partially disposed in the die cavity in the second direction.

[0188] 30. The IC package according to Clause 29, wherein the die package further includes a second surface adjacent to the package substrate and a molding layer of the first die;

[0189] in:

[0190] The interposer substrate is coupled to the molding layer; and

[0191] The plurality of vertical interconnects are disposed in the molding layer.

Claims

1. An interpolator substrate, the interpolator substrate comprising: A first metallization layer, extending in a first direction, comprising: Multiple first metal interconnects; and One or more second metal interconnects, each of the one or more second metal interconnects including a first surface; An outer layer, which is adjacent to the first metallization layer in a second direction orthogonal to the first direction, includes: An outer insulating layer, the outer insulating layer comprising a plurality of outer metal interconnects each coupled to a first metal interconnect in the plurality of first metal interconnects; and A die cavity, wherein the die cavity is adjacent in the second direction to a first surface of each of the one or more second metal interconnects in at least a portion of the outer insulation layer.

2. The interposer substrate of claim 1, wherein at least a portion of the first surface of the one or more second metal interconnects is exposed in the die cavity.

3. The interposer substrate of claim 1, wherein the one or more second metal interconnects comprise a metal plate.

4. The interpolator substrate according to claim 1, wherein: The first metallization layer includes a third surface and a fourth surface opposite to the third surface in the second direction. The third surface is adjacent to the die cavity and intersects the die cavity in the second direction; and The first surface of the one or more second metal interconnects is coplanar with the fourth surface in the first direction.

5. The interpolator substrate according to claim 1, wherein: The first metallization layer includes a third surface and a fourth surface opposite to the third surface in the second direction. The third surface is adjacent to the die cavity and intersects the die cavity in the second direction; and The first surface of the one or more second metal interconnects is recessed from the fourth surface into the first metallization layer in the first direction.

6. The interpolator substrate according to claim 1, wherein: The outer layer includes a solder resist layer; The plurality of external metal interconnects include a plurality of metal pillars; and The solder resist layer includes a plurality of first openings, each of which is adjacent to one of the plurality of metal pillars.

7. The interposer substrate according to claim 6, wherein the plurality of metal pillars do not intersect the die cavity in the second direction.

8. The interposer substrate of claim 1, wherein the plurality of first metal interconnects do not intersect the die cavity in the second direction.

9. The interposer substrate of claim 1, wherein the one or more second metal interconnects at least partially intersect the die cavity in the second direction.

10. The interposer substrate of claim 1, further comprising: A second metallization layer is adjacent to the first metallization layer in the first direction. in: The first metallization layer is located between the outer layer and the second metallization layer in the first direction; and The second metallization layer includes a plurality of third metal interconnects, each of which is coupled to a first metal interconnect among the plurality of first metal interconnects.

11. The interpolator substrate of claim 1, wherein the first metallization layer comprises an embedded trace substrate (ETS) metallization layer, the embedded trace substrate (ETS) metallization layer comprising a first insulating layer, The plurality of first metal interconnects include a plurality of first metal traces embedded in the first insulating layer.

12. The interposer substrate of claim 11, wherein the one or more second metal interconnects include a plurality of second vias.

13. The interpolator substrate according to claim 11, wherein: The first insulating layer further includes: The non-recessed layer portion includes the plurality of first metal traces and has a first height in the second direction; and The recessed layer portion includes the one or more second metal interconnects and forms a recessed region adjacent to the first surface of the one or more second metal interconnects; the recessed layer portion has a second height in the second direction that is less than the first height; and The core cavity also includes the recessed area.

14. The interposer substrate of claim 13, wherein the first insulating layer comprises a stepped structure formed in a first portion of a second portion of the non-recessed layer portion adjacent to the recessed layer portion in the first direction.

15. The interposer substrate of claim 14, wherein the die cavity is adjacent to the stepped structure.

16. The interpolator substrate of claim 1, wherein the first metallization layer comprises a modified semi-additive process (mSAP) metallization layer, and the modified semi-additive process (mSAP) metallization layer comprises a first insulating layer. The plurality of first metal interconnects are adjacent to the first insulating layer.

17. The interposer substrate of claim 16, wherein the one or more second metal interconnects include a plurality of second vias.

18. The interpolator substrate according to claim 16, wherein: The first insulating layer includes: A first layer portion, the first layer portion having a first height in the second direction and adjacent to the plurality of first metal interconnects in the second direction; and The second layer portion has the first height in the second direction and is adjacent to the one or more second metal interconnects in the second direction.

19. The interpolator substrate according to claim 16, wherein the interpolator substrate does not include a core layer.

20. The interposer substrate of claim 16, further comprising: A core layer, the core layer being adjacent to the first metallization layer; The first metallization layer is located between the core layer and the outer layer in the second direction.

21. The interposer substrate of claim 1, wherein the interposer substrate is integrated into a device selected from the group consisting of: set-top boxes; entertainment units; navigation devices; communication devices; fixed location data units; mobile location data units; global positioning system (GPS) devices; mobile phones; cellular phones; smartphones; session initiation protocol (SIP) phones; tablet computers; tablet phones; servers; computers; portable computers; mobile computing devices; wearable computing devices; desktop computers; personal digital assistants (PDAs); computer monitors; televisions; tuners; radios; satellite radios; music players; digital music players; portable music players; digital video players; video players; digital video disc (DVD) players; portable digital video players; automobiles; vehicle components; avionics systems; unmanned aerial vehicles; and multirotor aircraft.

22. A method of manufacturing an interposer substrate for an integrated circuit (IC) package, the method comprising: Forming a first metallization layer extending in a first direction, the formation comprising: Forming multiple first metal interconnects; and Form one or more second metal interconnects, each including a first surface; Forming an outer layer adjacent to the first metallization layer in a second direction orthogonal to the first direction, the formation comprising: An outer insulating layer is formed, the outer insulating layer comprising a plurality of outer metal interconnects each coupled to a first metal interconnect in the plurality of first metal interconnects; and A die cavity is formed, wherein the die cavity is adjacent in the second direction to the first surface of each of the one or more second metal interconnects in at least a portion of the outer insulation layer.

23. The method of claim 22, wherein forming the core cavity further comprises: The first surface of the one or more second metal interconnects is at least partially exposed.

24. The method of claim 22, wherein forming the one or more second metal interconnects comprises: Forming a metal plate.

25. The method of claim 22, wherein forming the one or more second metal interconnects comprises: The one or more second metal interconnects are formed with a third surface coplanar with the third surface of the first metallization layer, the third surface being adjacent to the die cavity and intersecting the die cavity in the second direction.

26. The method of claim 22, wherein forming the one or more second metal interconnects comprises: The one or more second metal interconnects are formed by recessing from a third surface of the first metallization layer, the third surface being adjacent to the die cavity and intersecting the die cavity in the second direction.

27. The method of claim 22, wherein forming the die cavity further comprises: Remove the portion of the outer insulating layer adjacent to the one or more second metal interconnects from the outer layer.

28. The method of claim 27, wherein forming the die cavity further comprises: Remove the portion of the first insulating layer adjacent to the one or more second metal interconnects from the first metallization layer.

29. An integrated circuit (IC) package, the integrated circuit (IC) package comprising: Die package, the die package comprising: A packaging substrate, the packaging substrate including a plurality of fourth metal interconnects; A first die, the first die being coupled to the packaging substrate; and Multiple vertical interconnects, each of which is coupled to a fourth metal interconnect among the multiple fourth metal interconnects; and An interposer substrate, the interposer substrate being coupled to the die package in a second direction orthogonal to the first direction, the interposer substrate comprising: A first metallization layer, extending in the first direction, comprising: Multiple first metal interconnects; and One or more second metal interconnects, each of the one or more second metal interconnects including a first surface; An outer layer, coupled to the die package and located in the second direction between the die package and the first metallization layer, the outer layer comprising: An outer insulating layer, the outer insulating layer comprising a plurality of outer metal interconnects each coupled to a first metal interconnect in the plurality of first metal interconnects and a vertical interconnect in the plurality of vertical interconnects; and A die cavity, wherein the die cavity is adjacent, in at least a portion of the outer insulating layer, to a first surface of each of the one or more second metal interconnects in the second direction; The first die is at least partially disposed in the die cavity in the second direction.

30. The IC package of claim 29, wherein the die package further comprises a second surface adjacent to the package substrate and a molding layer of the first die; in: The interposer substrate is coupled to the molding layer; and The plurality of vertical interconnects are disposed in the molding layer.

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