Multi-channel data synchronous acquisition transmission system and method

Abstract

This invention discloses a multi-channel data synchronous acquisition and transmission system and method, belonging to the field of PET imaging technology. It includes: building a multi-channel integrated architecture using a FESA chip; independently connecting the simulated nuclear signal from the PET detector to the corresponding channel; synchronously acquiring arrival time and pulse amplitude information through amplification and pulse discrimination; and outputting asynchronous digital event data to a PCB board; the PCB board utilizes timing phase-locked loop parameters and a distributed digital phase-locked loop array to achieve cross-channel timing phase-locking and phase deviation calibration, generating a standardized imaging data stream; furthermore, based on pulse amplitude analysis of energy information, and combined with time intervals, using time windows and energy windows to dual-filter matching events; reconstructing PET tomographic images through filtering and backprojection; and evaluating image quality in real time. This invention improves the synchronization accuracy and phase consistency of multi-channel acquisition, optimizes PET imaging quality, and enhances system stability.

Description

Technical Field

[0001] This invention belongs to the field of PET imaging technology, specifically a multi-channel data synchronous acquisition and transmission system and method. Background Technology

[0002] Positron emission tomography (PET) systems rely on multi-channel detectors to acquire gamma photon signals in parallel, placing extremely high demands on time synchronization, phase consistency, and front-end digitization accuracy. Traditional PET acquisition architectures often employ discrete analog circuits and general-purpose ADC modules, which are prone to issues such as clock drift and inconsistent transmission delays between channels, resulting in large timestamp deviations and phase inaccuracies, making it difficult to meet sub-nanosecond synchronization requirements. Existing multi-channel acquisition schemes generally suffer from low integration, insufficient independent channel time measurement and front-end digitization capabilities, and cross-channel timing calibration relies on complex post-processing, leading to low efficiency and poor stability in phase deviation correction. Furthermore, coincidence event screening is susceptible to interference from time and energy information errors, resulting in a high false positive rate and directly reducing imaging contrast and uniformity. In addition, the system lacks a closed-loop image quality control mechanism, parameters cannot be adaptively optimized, and errors tend to accumulate over long-term operation, making it difficult to consistently guarantee high-resolution and high-stability PET imaging results. Therefore, there is an urgent need for a highly integrated, high-precision, and closed-loop calibrable multi-channel synchronous acquisition and transmission technology to address the bottlenecks of insufficient synchronization accuracy, poor phase consistency, and unstable imaging quality in existing technologies, thereby improving the overall performance of PET systems. Summary of the Invention

[0003] To address the shortcomings of existing technologies, this invention proposes a multi-channel data synchronous acquisition and transmission system and method. It utilizes a FESA chip to build an integrated architecture with multiple acquisition channels, independently connecting the simulated nuclear signal from the PET detector to the corresponding channel. After amplification and pulse discrimination, arrival time and pulse amplitude information are synchronously acquired, and asynchronous digital event data is output to the PCB board. The PCB board uses timing phase-locked loop parameters and a distributed digital phase-locked loop array to achieve cross-channel timing phase-locking and phase deviation calibration, generating a standardized imaging data stream. Energy information is then analyzed based on pulse amplitude, and events are selected using both time and energy windows based on time intervals. The PET tomographic image is reconstructed through filtering and backprojection, and image quality is evaluated in real time. This invention improves the synchronization accuracy and phase consistency of multi-channel acquisition, optimizes PET imaging quality, and enhances system stability.

[0004] To achieve the above objectives, the present invention provides the following technical solution:

[0005] Multi-channel data synchronous acquisition and transmission methods include:

[0006] S1: The FESA chip is used to build a multi-acquisition channel integrated acquisition architecture, and all analog nuclear signals output by the PET detector are connected to the FESA chip of the acquisition architecture one by one.

[0007] S2: The FESA chip sequentially amplifies and pulses each analog core signal, synchronously collects the arrival time and pulse amplitude information of each analog core signal, calculates the time interval data between channels through the arrival time information, and completes multi-channel independent time measurement and front-end digital processing by combining preset time measurement parameters, and outputs multi-channel asynchronous digital event data to the PCB board.

[0008] S3: The PCB board retrieves the preset timing phase-locking parameters, performs cross-channel timing phase-locking and phase deviation calibration on the multi-channel asynchronous digital event data, and generates a standardized imaging data stream with unified channel timing.

[0009] S4: Determine the energy information of gamma photon events based on the pulse amplitude information in the standardized imaging data stream, combine it with the inter-channel time interval data to complete the coincidence event screening, and reconstruct the PET tomographic image.

[0010] S5: Real-time detection of PET tomographic images. When the image quality is lower than the preset image quality threshold, the timing measurement parameters of the FESA chip or the timing lock parameters of the PCB board are adjusted through the closed loop of the system control link.

[0011] Specifically, the specific steps of S1 include:

[0012] Based on the total number of gamma photon event output channels of the PET detector, the number of internal acquisition channels of the FESA chip is determined and configured; the input terminal of each internal acquisition channel of the FESA chip is exclusively connected to a corresponding analog nuclear signal output terminal of the PET detector through an impedance-matched differential signal link, so that each analog nuclear signal can be independently accessed by the corresponding internal acquisition channel; the gamma photon event is a data entity of a single effective photon interaction detected by the PET detector, and is the smallest effective data unit.

[0013] Specifically, the FESA chip sequentially amplifies and discriminates each analog core signal, simultaneously acquiring the arrival time and pulse amplitude information of each analog core signal, including:

[0014] Each established internal acquisition channel in the FESA chip is assigned an independent preamplifier unit. Each preamplifier unit receives the analog core signal input from the corresponding internal acquisition channel, performs amplitude normalization amplification processing on the received analog core signal, and outputs an amplified core pulse signal with consistent amplitude.

[0015] The amplitude-consistent amplified nuclear pulse signal output by the preamplifier unit is transmitted in parallel to the dual-path parallel processor of each internal acquisition channel; the dual-path parallel processor includes a first path and a second path.

[0016] The dual-path parallel processor obtains the voltage amplitude of the amplified core pulse signal through the pulse leading edge detection circuit set in the first path, and compares the voltage amplitude with the trigger threshold determined based on the channel background noise. When the voltage amplitude of the amplified core pulse signal exceeds the trigger threshold for the first time, the current time is recorded and a corresponding arrival timestamp is generated. The arrival timestamp is used as the arrival time information of the amplified core pulse signal.

[0017] The dual-path parallel processor, upon arrival at the time of timestamp generation, captures the maximum voltage value of the amplified core pulse signal through the peak sample-and-hold circuit set in the second path, quantizes the captured maximum voltage value to form a corresponding pulse amplitude code, and uses the pulse amplitude code as the pulse amplitude information of the amplified core pulse signal.

[0018] Specifically, the output process of the asynchronous digital event data includes:

[0019] The FESA chip's time measurement core processor acquires the arrival timestamps output by each internal acquisition channel, reads the arrival timestamps of each internal acquisition channel according to a preset polling order, and calculates the difference between the arrival timestamps of the current channel and the previous channel to obtain the time interval data between channels.

[0020] The time measurement core processor calculates time offset compensation values ​​independently for each internal acquisition channel based on the basic time reference provided by the external crystal oscillator, the time interval data between channels, and the preset time measurement parameters.

[0021] The arrival timestamps of each internal acquisition channel are linearly corrected in the time domain using the time offset compensation value to obtain the corrected independent channel time stamps.

[0022] The time measurement core processor encapsulates the corrected independent channel time stamps, pulse amplitude codes, and unique channel identifiers corresponding to each internal acquisition channel into asynchronous digital event data.

[0023] Specifically, the steps of S3 include:

[0024] The multi-channel timing calibration field-programmable gate array on the PCB receives the asynchronous digital event data and reads the pre-stored timing phase-locked loop parameter set from the onboard non-volatile memory; the timing phase-locked loop parameter set contains the initial timing phase offset value corresponding to the unique channel identifier of each internal acquisition channel; the multi-channel timing calibration field-programmable gate array is configured with a distributed digital phase-locked loop array, and each phase-locked loop in the distributed digital phase-locked loop array uniquely corresponds to one internal acquisition channel;

[0025] The multi-channel timing calibration field-programmable gate array determines the reference channel from all internal acquisition channels and uses the corrected independent channel time stamp corresponding to the reference channel as the reference time phase.

[0026] Each phase-locked loop uses the independent channel time stamp after correction of the corresponding internal acquisition channel as the phase to be calibrated, compares it with the reference time phase, and calibrates and corrects its own channel phase in combination with the initial timing phase offset value.

[0027] Once the phase deviations of all internal acquisition channels have been calibrated and corrected, the multi-channel timing calibration field-programmable gate array merges the corrected independent channel timestamps of each internal acquisition channel in chronological order to form a standardized imaging data stream with unified channel timing.

[0028] Specifically, when the distributed digital phase-locked loop array is calibrated and corrected, a master-slave synchronous cascaded structure is adopted, including:

[0029] The distributed digital phase-locked loop array uses the corrected independent channel time stamps of each internal acquisition channel to designate the channel with the smallest corrected independent channel time stamp as the master synchronization channel and the remaining channels as slave synchronization channels.

[0030] The corrected independent channel time stamp corresponding to the main synchronization channel is set as the reference time phase and sent to the digital phase-locked loops corresponding to each of the slave synchronization channels through the synchronization broadcast link.

[0031] Each digital phase-locked loop corresponding to the synchronization channel takes the corrected independent channel time stamp of its own channel as the phase to be calibrated, and inputs the phase to be calibrated as the phase feedback signal to the internal phase detector. The phase detector compares the input phase feedback signal with the received reference time phase in real time to obtain the instantaneous phase error, and then adds the instantaneous phase error to the initial timing phase offset value of the current channel to obtain the pre-corrected phase error signal.

[0032] The pre-corrected phase error signal is input to the loop filter. The loop filter filters and processes the pre-corrected phase error signal, converts it into a frequency control word, and inputs the frequency control word to the internal numerically controlled oscillator. The numerically controlled oscillator adjusts its output phase according to the magnitude and direction of the frequency control word.

[0033] The adjusted output phase of the numerically controlled oscillator is used as the new phase to be calibrated for the current channel, and is sent to the phase detector as a phase feedback signal again until the instantaneous phase error is reduced to zero.

[0034] Specifically, the steps of S4 include:

[0035] A digital signal processing component connected to a multi-channel timing calibration field-programmable gate array parses the pulse amplitude code from the standardized imaging data stream and converts the pulse amplitude code into energy information corresponding to gamma photon events;

[0036] The digital signal processing component extracts corrected independent channel time stamps from the standardized imaging data stream, and filters out matching event pairs based on the corrected independent channel time stamps and energy information;

[0037] The matching event pairs are transmitted to the image reconstruction processor, which processes them using a filtered back projection algorithm to generate PET tomographic images.

[0038] Specifically, the process of filtering matching event pairs based on the corrected independent channel timestamps and energy information employs a dual filtering mechanism of time windows and energy windows, including:

[0039] The digital signal processing component acquires the preset coincidence time window width and coincidence energy window upper and lower limits;

[0040] Extract corrected independent channel time stamps and energy information corresponding to all gamma photon events from the standardized imaging data stream;

[0041] Calculate the absolute value of the time difference between the corrected independent channel time stamps corresponding to any two different gamma photon events;

[0042] When the absolute value of the time difference is less than or equal to the width of the time window, and the energy information corresponding to the two gamma photon events is between the upper and lower limits of the energy window, the two gamma photon events are determined to be a pair of coincident events.

[0043] Specifically, the steps of S5 include:

[0044] Acquire PET tomographic images, calculate the contrast-to-noise ratio and uniformity index of the PET tomographic images, and obtain a real-time comprehensive image quality score;

[0045] The real-time image quality comprehensive score is compared with a preset image quality threshold. When the real-time image quality comprehensive score is lower than the preset image quality threshold, a parameter optimization request is generated. The parameter optimization request carries parameter type identification information and parameter value information.

[0046] The parameter optimization request is transmitted to the configuration register of the FESA chip and the parameter update interface of the PCB board via the system control link; the system control link uses an arbitration method based on message identifiers to transmit the parameter optimization request.

[0047] The configuration register of the FESA chip adjusts the timing measurement parameters according to the parameter optimization request, and the parameter update interface of the PCB board updates the initial timing phase offset value in the timing phase-locked loop parameter set according to the parameter optimization request.

[0048] A multi-channel data synchronous acquisition and transmission system includes:

[0049] The data acquisition module is configured with internal acquisition channels based on the total number of channels of the PET detector. It is exclusively connected to the analog nuclear signal output terminal of the PET detector through an impedance-matched differential signal link to complete the amplification of the analog nuclear signal, pulse discrimination, synchronous acquisition of arrival time information and pulse amplitude information, and output of multiple channels of asynchronous digital event data.

[0050] The timing calibration module is used to retrieve pre-stored timing phase-locking parameters, determine the reference channel, and complete cross-channel timing phase-locking and phase deviation calibration in a master-slave synchronous cascade structure. It merges the phase-calibrated channel time stamps to generate a standardized imaging data stream.

[0051] The image reconstruction module uses a dual filtering mechanism of time window and energy window to complete the screening of matching events, and processes the matching event pairs through a filtering back projection algorithm to generate PET tomographic images.

[0052] The control and detection module is used to detect the image quality of PET tomographic images in real time, calculate the contrast-to-noise ratio and uniformity index to obtain a comprehensive real-time image quality score. When the comprehensive real-time image quality score is lower than the preset image quality threshold, a parameter optimization request is sent to the FESA chip configuration register and PCB board parameter update interface through the system control link to adjust the time measurement parameters and timing phase-locked loop parameters.

[0053] Compared with the prior art, the beneficial effects of the present invention are:

[0054] 1. This invention proposes a multi-channel data synchronous acquisition and transmission method. By constructing an integrated architecture with multiple acquisition channels using a FESA chip, each channel is equipped with an independent preamplifier unit and a dual-path parallel processor. This method can synchronously and accurately acquire the arrival time and pulse amplitude information of the core signal, complete independent time measurement and front-end digital processing of multiple channels, improve the time synchronization accuracy and data acquisition consistency between channels, effectively reduce the deviation caused by clock drift and transmission delay, and solve the problems of insufficient synchronization accuracy and low integration of traditional architectures.

[0055] 2. This invention proposes a multi-channel data synchronous acquisition and transmission method, which adopts cross-channel timing phase-locked loop and phase calibration technology, combined with master-slave synchronous cascaded digital phase-locked loop array to achieve rapid phase deviation correction, and improves the accuracy of coincidence event screening through a dual mechanism of time window and energy window. With the cooperation of real-time image quality detection and parameter closed-loop adjustment, the time measurement parameters and timing phase-locked loop parameters can be dynamically optimized to continuously ensure imaging stability and clarity, and improve the imaging quality, operational reliability and overall performance of the PET system. Attached Figure Description

[0056] Figure 1 This is a schematic diagram of the multi-channel data synchronous acquisition and transmission method of the present invention;

[0057] Figure 2 This is a flowchart illustrating the principle of the multi-channel data synchronous acquisition and transmission method of the present invention.

[0058] Figure 3 This is a diagram of the architecture of the multi-channel data synchronous acquisition and transmission system of the present invention. Detailed Implementation

[0059] Example 1:

[0060] Please see Figure 1 and Figure 2 The present invention provides an embodiment of a multi-channel data synchronous acquisition and transmission method, comprising the following steps:

[0061] S1: The FESA chip is used to build a multi-acquisition channel integrated acquisition architecture, and all analog nuclear signals output by the PET detector are connected to the FESA chip of the acquisition architecture one by one.

[0062] Furthermore, this embodiment takes 64 adjacent analog nuclear signal output channels in a PET detector ring array as an example to provide a detailed explanation of the construction of an integrated acquisition architecture for multiple acquisition channels and the signal access process. First, based on the transmission distance, impedance characteristics, and noise level of the 64 signals, the hardware configuration and parameter initialization of the FESA chip's internal acquisition channels were completed to ensure that the chip's internal circuitry matched the external signal link. Then, each analog nuclear signal was independently connected to the corresponding acquisition channel of the FESA chip via an impedance-matched differential signal link. The differential signal link adopted a 50Ω standard impedance design, which effectively suppressed common-mode noise and electromagnetic interference during transmission, preventing amplitude attenuation, waveform distortion, or timing offset of the analog nuclear signal during transmission. During signal access, the exclusive connection principle was strictly followed, meaning that one internal acquisition channel corresponds only to one analog nuclear signal output from the PET detector, without channel sharing, signal multiplexing, or multi-channel merging, ensuring the independence and integrity of each signal. After all signals were connected, a power-on self-test and link continuity test were performed on the entire acquisition architecture. By sending test commands to the FESA chip, it was checked whether each channel could receive analog signals normally and whether there were short circuits, open circuits, or channel adhesion problems. After passing the test, the signal acquisition preparation state was officially entered.

[0063] The specific steps of S1 include:

[0064] S1.1: Determine and configure the number of internal acquisition channels of the FESA chip based on the total number of gamma photon event output channels of the PET detector; the gamma photon event is a data entity of a single effective photon interaction detected by the PET detector, and is the smallest effective data unit;

[0065] Furthermore, the total number of gamma photon event output channels of a PET detector is determined by the detector's physical structure, the size of the scintillator array, and the number of photoelectric conversion devices. Different models and application scenarios of PET equipment have significantly different numbers of output channels, ranging from dozens to thousands. The FESA chip possesses flexible channel configuration capabilities, supporting various methods such as hardware jumper configuration, register writing configuration, and host computer software configuration to customize the number of internally available acquisition channels, adapting to the access needs of PET detectors of different sizes. During configuration, the total number of detector channels is first read from the PET equipment's main control system. This parameter is determined by factory calibration and on-site debugging, ensuring its fixedness and uniqueness. Then, the total number of detector channels is written into the FESA chip's channel configuration register. The FESA chip's internal channel management module automatically activates the corresponding number of acquisition channels based on the written value, closing unnecessary and unused channels to reduce chip power consumption and signal interference risks. Simultaneously, each activated acquisition channel is assigned a unique hardware address and a unique identifier ID. This identifier ID is used to distinguish the acquisition data from different channels, avoiding data confusion.

[0066] Furthermore, a gamma photon event, as the smallest effective data unit in PET imaging, represents a complete photon detection process. Specifically, a gamma photon is incident on a scintillator, and its energy is transferred to the scintillator through the photoelectric effect, Compton scattering, or pair production. The scintillator emits fluorescence, which is received by a photoelectric conversion device and converted into an analog electrical signal. This analog electrical signal is the physical carrier of the gamma photon event, and each gamma photon event contains unique information such as arrival time, pulse amplitude, and location of action. In this embodiment, each analog nuclear signal corresponds to an independent gamma photon event detection unit. When a gamma photon event occurs, the corresponding analog nuclear signal is immediately output and transmitted to the FESA chip. The chip processes this signal to extract the core features of the event, completing the conversion from physical signal to digital data.

[0067] Furthermore, in this embodiment, the PET detector has a total of 64 gamma photon event output channels. Therefore, the number of internal acquisition channels of the FESA chip is configured to 64 to ensure that the number of channels matches the number of signal outputs perfectly, with no redundancy or missing channels. After configuration, the FESA chip automatically allocates independent signal conditioning circuits, pulse detection units, time recording units, and data buffer spaces to the 64 acquisition channels. Each channel has equal hardware resources and processing permissions, with no priority differences or resource contention issues, ensuring the fairness and synchronization of multi-channel processing. At the same time, the FESA chip stores channel configuration information, unique identifier ID, hardware address, and other parameters in a non-volatile configuration memory. Even if the device is powered off and restarted, the configuration parameters remain unchanged, eliminating the need for reconfiguration.

[0068] S1.2: Connect the input terminal of each internal acquisition channel of the FESA chip to the corresponding analog nuclear signal output terminal of the PET detector through an impedance-matched differential signal link, so that each analog nuclear signal can be independently connected to the corresponding internal acquisition channel.

[0069] Furthermore, the differential signal link consists of a pair of differential signal lines, a signal driver chip, an impedance matching resistor, and a shielded cable. It can convert the single-ended analog nuclear signal output by the PET detector into a differential signal for transmission, improving the signal's anti-interference capability. During the connection process, the principle of one-to-one correspondence between channel numbers is strictly followed. The input terminal of the acquisition channel 1 inside the FESA chip is connected to the analog nuclear signal output terminal 1 of the PET detector, acquisition channel 2 is connected to output terminal 2, and so on, until all 64 channels are connected, ensuring that the signal transmission path is consistent with the channel identifier ID. The exclusive connection means that each analog nuclear signal has an independent physical transmission link from the detector output terminal to the FESA chip acquisition channel input terminal. It does not share lines with other signals, does not pass through multiplexers, and does not undergo combining processing, completely eliminating problems such as signal crosstalk, timing delay deviation, and amplitude mutual influence between channels. For analog nuclear signals, exclusive independent access can preserve the original waveform characteristics, arrival time information, and pulse amplitude information of the signal to the greatest extent.

[0070] S2: The FESA chip sequentially amplifies and pulses each analog core signal, synchronously collects the arrival time and pulse amplitude information of each analog core signal, calculates the time interval data between channels through the arrival time information, and completes multi-channel independent time measurement and front-end digital processing by combining preset time measurement parameters, and outputs multi-channel asynchronous digital event data to the PCB board.

[0071] The FESA chip sequentially amplifies and identifies the pulses of each analog core signal, and simultaneously acquires the arrival time and pulse amplitude information of each analog core signal, including:

[0072] S2.1: Allocate an independent preamplifier unit to each established internal acquisition channel in the FESA chip. Each preamplifier unit receives the analog core signal input from the corresponding internal acquisition channel, performs amplitude normalization amplification processing on the received analog core signal, and outputs an amplified core pulse signal with consistent amplitude.

[0073] Furthermore, the FESA chip integrates preamplifier units equal to the number of acquisition channels. Each preamplifier unit independently corresponds to one acquisition channel, possessing independent amplification gain, bias voltage, and filtering parameters, ensuring no interference between them. Since the amplitudes of analog nuclear signals output from different positions and channels of the PET detector naturally differ—some signals are stronger than others—direct pulse discrimination and sampling would lead to problems such as weak signal detection failure and large amplitude measurement errors. Therefore, the core objective of amplitude normalization amplification processing is to uniformly amplify the analog nuclear signals of different amplitudes across all channels, achieving amplitude consistency. The preamplifier unit employs a low-noise, high-bandwidth, and fast-response operational amplifier design, capable of completing signal amplification within nanoseconds without producing significant waveform distortion. To ensure the accuracy of signal arrival time and reduce time delay, in this embodiment, 64 preamplifier units start working synchronously. Each unit receives the analog core signal of the corresponding channel and automatically adjusts the amplification gain according to the original amplitude of the signal. For signals with smaller original amplitudes, a higher gain is used for amplification, and for signals with larger original amplitudes, a lower gain is used for amplification. Finally, the amplitude of the amplified core pulse signal output by all channels is stabilized between 0.5V and 1V, achieving complete amplitude uniformity. During the amplification process, the low-pass filter circuit built into the preamplifier unit filters out high-frequency noise in the signal, retains the original waveform characteristics of the core pulse, and avoids noise interference to subsequent pulse leading-edge detection and peak sampling. The amplitude-uniform amplified core pulse signal is transmitted to the dual-path parallel processor of the corresponding channel in real time.

[0074] S2.2: The amplitude-consistent amplified core pulse signal output by the preamplifier unit is transmitted in parallel to the dual-path parallel processor of each internal acquisition channel; the dual-path parallel processor includes a first path and a second path;

[0075] Furthermore, each acquisition channel is equipped with an independent dual-path parallel processor, with 64 processors operating synchronously without resource sharing or processing conflicts. The first path is dedicated to signal arrival time detection, and the second path is dedicated to pulse amplitude sampling. The two paths are physically independent and work synchronously, enabling the acquisition of time and amplitude information at the same time, eliminating the time deviation caused by sequential processing in a single path, and ensuring the synchronicity of multi-channel data acquisition. After the amplitude-consistent amplified core pulse signal enters the dual-path parallel processor, it will be simultaneously distributed to the first path and the second path. The first path and the second path independently execute processing operations according to their respective functional logic, without affecting or waiting for each other.

[0076] Furthermore, in this embodiment, after the amplified nuclear pulse signal is transmitted to the dual-path parallel processor, the pulse leading edge detection circuit of the first path and the peak sampling and holding circuit of the second path are started simultaneously. The processing clocks of the two paths are completely synchronized and are both provided by an external 100MHz temperature-controlled crystal oscillator, achieving a time resolution of 10 nanoseconds. This allows for precise capture of the leading edge and peak moments of the nuclear pulse. The dual-path parallel processing architecture avoids the delay errors caused by the traditional serial processing mode of measuring time first and then amplitude, ensuring that the time information and amplitude information correspond to the same nuclear pulse event, thus improving the correlation and accuracy of the data.

[0077] S2.3: The dual-path parallel processor obtains the voltage amplitude of the amplified core pulse signal through the pulse leading edge detection circuit set in the first path, and compares the voltage amplitude with the trigger threshold determined based on the channel background noise. When the voltage amplitude of the amplified core pulse signal exceeds the trigger threshold for the first time, the current time is recorded and the corresponding arrival timestamp is generated. The arrival timestamp is used as the arrival time information of the amplified core pulse signal.

[0078] Furthermore, the pulse leading edge detection circuit adopts a high-speed comparator design, which can monitor the voltage amplitude change of the amplified core pulse signal in real time, with a response time reaching the sub-nanosecond level, ensuring accurate capture of the rising edge of the signal. The trigger threshold is not a fixed value, but is dynamically generated based on the background noise level of each channel. Each channel monitors its own noise amplitude in real time, and takes 1.5 times the noise peak value as the trigger threshold, which ensures that the effective signal can be reliably triggered and avoids false triggering by noise signals. When the voltage amplitude of the amplified core pulse signal rises rapidly from a low level and exceeds the trigger threshold for the first time, the pulse leading edge detection circuit immediately sends a trigger signal to the timestamp recording component. The timestamp recording component uses the crystal oscillator clock as a reference to record the absolute time value of the current moment and generate an arrival timestamp. This arrival timestamp is based on the system global time and has uniqueness and comparability.

[0079] Furthermore, the specific steps in S2.3 include:

[0080] (1) The pulse leading edge detection circuit completes power-on initialization and parameter pre-configuration. After the system starts, the pulse leading edge detection circuit enters a stable working state. First, it completes the initialization operations of the internal high-speed comparator, clock synchronization component, threshold generation component and timestamp recording component. All components complete the reference calibration according to the preset parameters. The working bandwidth of the high-speed comparator is set to 500MHz and the response time is controlled within 100ps to ensure that the rapid leading edge change of the amplified core pulse signal can be accurately captured. The clock synchronization component is connected to an external 100MHz constant temperature crystal clock to lock the basic resolution of time measurement at 10ns to ensure that the time recording reference of all channels is completely consistent. The threshold generation component completes the initialization of the background noise monitoring circuit, prepares to collect the noise level of the current channel in real time and calculate the trigger threshold. The entire initialization process is completed in microseconds.

[0081] (2) Dynamically determine the trigger threshold, including: when there is no effective amplification core pulse signal input, the background noise monitoring circuit inside the pulse leading edge detection circuit continuously collects the real-time voltage fluctuation signal of the current channel, continuously collects 10,000 noise sampling points and calculates the average amplitude and peak amplitude of the noise, and takes 1.5 times the peak amplitude of the noise as the trigger threshold of the current channel. The trigger threshold will be updated in real time with the changes in channel ambient temperature, working voltage and device status, and the threshold will be refreshed once every 10ms to ensure that the trigger threshold is always adapted to the noise level of the current channel. In this embodiment, the peak amplitude of the background noise of the current channel is stable at 20mV, so the calculated trigger threshold is fixed at 30mV. This value is transmitted to the threshold input terminal of the high-speed comparator in real time as the benchmark for signal judgment.

[0082] (3) The amplitude-consistent amplified core pulse signal after being processed by the preamplifier unit is continuously input to the pulse leading edge detection circuit in the form of a continuous analog signal. First, it passes through the impedance matching circuit to ensure that the input impedance is completely matched with the internal impedance of the circuit, so as to avoid waveform distortion caused by signal reflection. The standard amplitude range of the amplified core pulse signal is stabilized between 0.5V and 1V, and the rise time of the signal leading edge is controlled within 20ns. The pulse leading edge detection circuit obtains the voltage amplitude of the signal in real time at a nanosecond sampling rate. The voltage value of the current signal is updated once every nanosecond, and the value is transmitted to the signal input terminal of the high-speed comparator in real time to maintain a synchronous comparison with the determined trigger threshold.

[0083] (4) The high-speed comparator receives two input signals at the same time. One is the real-time updated voltage amplitude of the amplified core pulse signal, and the other is the dynamically generated 30mV trigger threshold. The comparator performs the comparison operation at a frequency of once every 10ps. When the amplified core pulse signal has not arrived, the signal voltage amplitude is always lower than the 30mV trigger threshold. The high-speed comparator outputs a low level and does not trigger any action. When the amplified core pulse signal starts to rise, the signal voltage amplitude gradually increases. The high-speed comparator continuously tracks the amplitude change until the signal voltage amplitude rises to exceed the 30mV trigger threshold for the first time. The high-speed comparator immediately completes the level flip, switching from low level to high level. This level flip signal is transmitted synchronously to the timestamp recording component as a valid trigger instruction.

[0084] (5) After receiving a valid trigger command from the high-speed comparator, the timestamp recording component immediately pauses the internal clock counting and locks the current clock count value. The clock count value is based on an external 100MHz constant temperature crystal oscillator and is continuously accumulated from the start of the system. The minimum counting unit is 10ns. In this embodiment, when the valid trigger command arrives, the clock count value is 56320, which is the original time base of the current moment. The entire locking process is completed within 50ps and there is no time delay.

[0085] (6) The timestamp recording component encapsulates the locked clock count value to generate a 32-bit fixed-length arrival timestamp. The timestamp value directly corresponds to the locked time information and can completely reflect the arrival time of the nuclear pulse signal. In this embodiment, the locked clock count value is 56320, and the arrival timestamp generated after encapsulation is the corresponding value. The timestamp is based on the system's global unified time and has consistency in cross-channel comparison. It will not deviate due to differences in channel hardware.

[0086] (7) The pulse leading edge detection circuit transmits the generated standardized arrival timestamp to the data output port of the dual-path parallel processor. At the same time, it adds the current channel identification information to the timestamp to ensure that the timestamp is uniquely associated with the corresponding channel and the corresponding signal. After the transmission is completed, the arrival timestamp is formally defined as the arrival time information corresponding to the current amplification core pulse signal and is directly sent to the time measurement core processor of the FESA chip for inter-channel time interval calculation and time offset compensation.

[0087] S2.4: At the same time as the arrival timestamp is generated, the dual-path parallel processor captures the maximum voltage value of the amplified core pulse signal through the peak sample-and-hold circuit set in the second path, quantizes the captured maximum voltage value to form the corresponding pulse amplitude code, and uses the pulse amplitude code as the pulse amplitude information of the amplified core pulse signal.

[0088] Furthermore, the peak sample-and-hold circuit works synchronously with the pulse leading-edge detection circuit. At the same moment the timestamp is generated, the peak capture operation is initiated. The nuclear pulse signal is characterized by rapid rise and fall, with a duration of only tens of nanoseconds. The peak sample-and-hold circuit employs a high-speed sampling switch and holding capacitor design, enabling it to quickly capture the maximum voltage value of the signal and hold it stably until quantization is complete. Quantization uses a high-precision analog-to-digital converter circuit to convert continuous analog voltage maximum values ​​into discrete digital codes. The higher the number of bits in the code, the higher the amplitude measurement accuracy. This embodiment uses 12-bit quantization accuracy, which can divide the voltage range from 0V to 1V into 4096 levels, accurately reflecting the amplitude differences of the nuclear pulse and meeting the energy resolution requirements of PET imaging.

[0089] Furthermore, the specific steps in S2.4 include:

[0090] (1) After the system starts, the peak sampling and holding circuit enters the standby state and sequentially completes the initialization and reference calibration of the internal analog switch, holding capacitor, buffer amplifier and analog-to-digital conversion module. The conduction time of the analog switch is set to no more than 100ps to ensure that there is no distortion during the signal switching process. The capacitance value of the holding capacitor is fixed at 100pF to meet the requirements of fast sampling and stable holding. The buffer amplifier adopts a unity gain design and the working bandwidth is set to 500MHz to ensure that the amplitude does not attenuate during signal transmission. The analog-to-digital conversion module is set to 12-bit conversion accuracy during initialization. The input voltage range is set to 0V to 1V. The conversion clock is synchronously connected to an external 100MHz constant temperature crystal oscillator to ensure that it uses the same clock reference as the pulse leading edge detection circuit. The entire initialization process is completed in microseconds and keeps in a synchronized and ready state with the pulse leading edge detection circuit of the first path.

[0091] (2) The trigger signal of the peak sampling and holding circuit is the same as the trigger signal output by the first path pulse leading edge detection circuit. When the voltage amplitude of the amplified core pulse signal exceeds the trigger threshold for the first time and generates the arrival timestamp, the trigger signal is synchronously transmitted to the peak sampling and holding circuit. The peak sampling and holding circuit immediately switches from the standby state to the sampling state to ensure that the peak capture and timestamp generation are strictly synchronized and there is no time deviation. The transmission path of the trigger signal is designed with equal length wiring and the transmission delay is controlled within 50ps to ensure that the two operations start at the same time.

[0092] (3) After entering the sampling state, the analog switch inside the peak sampling and holding circuit is turned on instantly. The amplified core pulse signal is directly transmitted to the two ends of the holding capacitor after passing through the buffer amplifier. The holding capacitor is charged quickly following the signal voltage change. Since the amplified core pulse signal has the characteristics of rapid rise and rapid fall, the rise time of the signal front edge is controlled within 20ns, and the peak duration is about 50ns. The holding capacitor continuously tracks the voltage change during the signal rise phase. When the signal voltage rises to the highest point and is about to start falling, the analog switch is automatically turned off according to the internal peak detection logic. The response time of the turn-off action does not exceed 100ps. At this time, the voltage remaining on the holding capacitor is the maximum voltage of the amplified core pulse signal. In this embodiment, the maximum voltage of the amplified core pulse signal after the amplitude normalization processing of the preamplifier unit is stable between 0.6V and 0.9V. The holding capacitor can completely capture this voltage value and maintain it stably.

[0093] (4) After the analog switch is turned off, the holding capacitor enters the holding state and holds the captured maximum voltage value stably until the analog-to-digital conversion is completed. The holding time is set to no less than 500ns, which completely covers the time required for analog-to-digital conversion. The buffer amplifier continuously isolates the voltage on the holding capacitor by impedance and buffers the signal to avoid the subsequent analog-to-digital conversion module from having a load effect on the holding voltage, and ensures that the voltage value input to the quantization processing module is completely consistent with the captured maximum voltage value, without attenuation or fluctuation.

[0094] (5) Perform quantization processing on the stable maximum voltage according to preset parameters, including: the analog-to-digital conversion module performs quantization conversion on the input maximum voltage with 12-bit precision. The 12-bit quantization can divide the input range from 0V to 1V into 4096 equally spaced quantization levels. The voltage amplitude corresponding to each quantization level is about 0.244mV. The conversion process adopts the successive approximation algorithm. The comparison reference voltage inside the successive approximation algorithm decreases step by step. The initial value of the reference voltage is set to 0.5V. Then, each level of reference voltage is generated sequentially according to the ratio of 1 / 2 of the previous level until the 12-bit data is determined bit by bit. The entire quantization conversion process is completed within 200ns. The conversion clock frequency is 100MHz. Each clock cycle completes the determination of one bit of data. In this embodiment, when the captured maximum voltage is 0.7V, after quantization by the successive approximation algorithm, a corresponding 12-bit binary quantization result is generated. The binary quantization result is a digital sequence that uniquely matches the 0.7V voltage.

[0095] (6) The 12-bit quantization result output by the analog-to-digital conversion module is latched by the internal register, encapsulated according to the unified data format of the system, forming a pulse amplitude code, which is defined as the pulse amplitude information of the current amplification core pulse signal, and sent to the time measurement core processor of the FESA chip synchronously with the arrival time information.

[0096] The process of outputting the asynchronous digital event data includes:

[0097] S2.5: The time measurement core processor of the FESA chip obtains the arrival timestamps output by each internal acquisition channel, reads the arrival timestamps of each internal acquisition channel according to the preset polling order, and calculates the difference between the arrival timestamps of the current channel and the previous channel to obtain the time interval data between channels.

[0098] Furthermore, the time measurement core processor is the time management and data integration unit within the FESA chip. It is responsible for uniformly receiving and processing time information from all channels. A polling mechanism ensures the orderliness and fairness of data reading. The preset polling order follows the channel ID from smallest to largest, i.e., reading from channel 1 to channel 64 in a loop. The reading frequency is synchronized with the signal acquisition frequency, ensuring that each newly generated arrival timestamp is read in a timely manner. The inter-channel time interval data is obtained by calculating the difference in timestamps between adjacent reading channels, reflecting the time differences in gamma photon events between different channels, thus eliminating inter-channel timing discrepancies. In this embodiment, the time measurement core processor polls and reads the arrival timestamps of channels 1 to 64 in sequence at a frequency of 1MHz. After reading the arrival timestamp of each channel, it immediately performs a difference operation with the arrival timestamp of the previous channel to obtain the time interval data between channels. For example, if the arrival timestamp of channel 5 is 1000ns and the arrival timestamp of the previous channel 4 is 980ns, then the time interval between channel 5 and channel 4 is 20ns. All time interval data between channels are stored in real time in a temporary buffer area, waiting to be combined with the time measurement parameters for time offset compensation calculation.

[0099] S2.6: The time measurement core processor calculates the time offset compensation value independently for each internal acquisition channel based on the basic time reference provided by the external crystal oscillator, the time interval data between channels, and the preset time measurement parameters.

[0100] Furthermore, the specific steps in S2.6 include:

[0101] (1) The time measurement core processor completes the power-on initialization and clock reference locking. Specifically, after the system is powered on, the time measurement core processor first completes the initialization operation and enters a stable standby state; it connects to the clock signal output by the external 100MHz constant temperature crystal oscillator and uses the clock signal as the basic time reference for the entire calculation process. At this time, the minimum resolution unit of time measurement is locked at 10ns, and all time-related operations are carried out based on this reference; during the initialization phase, the preset time measurement parameters are loaded. The time measurement parameters include the inherent delay compensation value of the channel, the temperature drift correction coefficient, the time domain linear correction coefficient, and the allowable value of the reference deviation between channels. Among them, the inherent delay compensation value of the channel is set according to the factory calibration result of each channel, the temperature drift correction coefficient is set to 0.2ns / ℃, the time domain linear correction coefficient is set to 1, and the allowable value of the reference deviation between channels is set to 5ns. All parameters are fixed values.

[0102] (2) The time measurement core processor synchronously obtains the global base time reference value provided by the external crystal oscillator through the internal data bus. At the same time, it reads the original arrival timestamp generated and uploaded by the pulse leading edge detection circuit of each channel in the preset polling order from channel 1 to channel 64. The reading operation is performed at a clock frequency of 100MHz. The time taken for a single reading operation does not exceed 10ns, ensuring that the original arrival timestamps of all channels are read within the same time window, avoiding additional calculation errors caused by differences in reading timing. After reading, the original arrival timestamps of all channels are temporarily stored. Each arrival timestamp retains complete global time information and maintains a strict correspondence with the base time reference.

[0103] (3) The time measurement core processor retrieves all preset time measurement parameters and matches the parameters with the corresponding channels one by one according to the channel number. Each channel only calls its own exclusive parameters. The inherent delay compensation value of each channel is a fixed value obtained from the factory test. For example, the inherent delay compensation value of the first channel is set to -4ns, the inherent delay compensation value of the second channel is set to -3ns, and the inherent delay compensation value of the third channel is set to -5ns. The temperature drift correction coefficient is uniformly applied to all channels without distinguishing between channels, so it is still 0.2ns / ℃. The time domain linear correction coefficient and the allowable value of the reference deviation between channels are used as constraints in the calculation process.

[0104] (4) The time measurement core processor uses the global base time reference provided by the external crystal oscillator as the sole reference. It performs a difference operation between the original arrival timestamp of the current channel and the global base time reference to obtain the initial time deviation value of the channel relative to the global reference. Then, it adds the initial time deviation value to the inherent delay compensation value of the corresponding channel to complete the initial correction of the inherent hardware delay and obtain the initial calibration time deviation. In this embodiment, the difference between the original arrival timestamp of the first channel and the global base time reference is 6ns. After adding the inherent delay compensation value of -4ns, the initial calibration time deviation is 2ns.

[0105] (5) The time measurement core processor performs a weighted operation on the obtained preliminary calibration time deviation and the inter-channel time interval data corresponding to the current channel. The weighting coefficient is directly adopted by the preset time domain linear correction coefficient 1. After the operation, the time domain correction deviation value is obtained. Then, the time domain correction deviation value is added to the temperature drift deviation value calculated by the temperature drift correction coefficient. The temperature drift deviation value is obtained by multiplying the difference between the current working temperature and the room temperature of 25℃ by the temperature drift correction coefficient. In this embodiment, the current working temperature is 35℃, the difference is 10℃, and the temperature drift deviation value is 2ns. The value obtained at this time is the comprehensive time deviation including hardware delay, inter-channel time interval and environmental drift. The comprehensive time deviation must meet the constraint condition of the inter-channel reference deviation allowable value of 5ns. If it exceeds the range, it will be limited according to the upper or lower limit of the allowable value to ensure that the calculation result is within a reasonable range.

[0106] (6) The time measurement core processor inverts the sign of the comprehensive time deviation value after constraint and amplitude limiting. The converted value is the independent time offset compensation value of the current channel. In this embodiment, the comprehensive time deviation of the first channel is calculated to be 4ns, and the time offset compensation value obtained after sign conversion is -4ns. The comprehensive time deviation of the second channel is calculated to be 3ns, and the time offset compensation value obtained after sign conversion is -3ns. Each channel generates its own compensation value according to this logic.

[0107] (7) The time measurement core processor repeats (1)-(6) in the order from channel 1 to channel 64 to complete the calculation of time offset compensation value for all channels in sequence. After each channel's time offset compensation value is calculated, the time offset compensation value is immediately bound to the corresponding channel number and stored in the internal compensation value storage register to ensure that the data is not lost or confused. After all channels are calculated, a complete set of independent time offset compensation values ​​for 64 channels is formed.

[0108] S2.7: Use the time offset compensation value to perform linear time domain correction on the original arrival timestamps corresponding to each internal acquisition channel to obtain the corrected independent channel time stamps;

[0109] Furthermore, the linear time-domain correction adopts a simple and direct numerical superposition method, adding the original arrival timestamp to the corresponding channel's time offset compensation value to obtain the corrected independent channel timestamp. This correction method has high computational efficiency and strong real-time performance, and can complete the correction operation within nanoseconds without affecting the data processing flow. The corrected independent channel timestamp eliminates time errors caused by factors such as channel hardware differences, transmission delays, and temperature drift. The timestamp of each channel is based on a globally unified time, and has cross-channel comparability.

[0110] Furthermore, in this embodiment, the original arrival timestamp is added to the corresponding channel's time offset compensation value to obtain the corrected independent channel time stamp. For example, the original timestamp of channel 1 is 500ns, the time offset compensation value is -4ns, and the corrected time stamp is 496ns; the original timestamp of channel 2 is 503ns, the time offset compensation value is -3ns, and the corrected time stamp is 500ns. After correction, the deviation of the time stamps of each channel is greatly reduced.

[0111] S2.8: The time measurement core processor encapsulates the corrected independent channel time stamps, pulse amplitude codes, and unique channel identifiers corresponding to each internal acquisition channel into asynchronous digital event data.

[0112] Furthermore, asynchronous digital event data is the final output of the FESA chip's front-end digital processing. It is encapsulated using a standardized data frame format and includes three core fields: a corrected independent channel time stamp, pulse amplitude encoding, and a unique channel identifier. This results in a concise data structure and high transmission efficiency. Because the occurrence times of gamma photon events in each channel are random, the corrected independent channel time stamps are not perfectly synchronized. Therefore, this data is defined as asynchronous digital event data and requires timing lock-in calibration on the back-end PCB board to achieve multi-channel timing consistency. During the encapsulation process, the time measurement core processor adds a check bit to each event data point to ensure error-free data transmission and improve data reliability.

[0113] Furthermore, in this embodiment, the corrected independent channel time stamp, 12-bit pulse amplitude code, and 8-bit channel identifier ID of each channel are encapsulated into a 32-bit fixed-length asynchronous digital event data frame. The data frames of the 64 channels are synchronously output to the PCB board through a high-speed parallel interface, with a transmission rate of 1Gbps, ensuring real-time data transmission without congestion or data loss.

[0114] S3: The PCB board retrieves the preset timing phase-locking parameters, performs cross-channel timing phase-locking and phase deviation calibration on the multi-channel asynchronous digital event data, and generates a standardized imaging data stream with unified channel timing.

[0115] The specific steps of S3 include:

[0116] S3.1: The multi-channel timing calibration field-programmable gate array on the PCB board receives the asynchronous digital event data and reads the pre-stored timing phase-locked loop parameter set from the onboard non-volatile memory; the timing phase-locked loop parameter set contains the initial timing phase offset value corresponding to the unique channel identifier of each internal acquisition channel; the multi-channel timing calibration field-programmable gate array is configured with a distributed digital phase-locked loop array, and each phase-locked loop in the distributed digital phase-locked loop array uniquely corresponds to an internal acquisition channel;

[0117] Furthermore, the multi-channel timing calibration field-programmable gate array uses a Xilinx high-performance FPGA chip, equipped with 64 independent data receiving interfaces, capable of synchronously receiving asynchronous digital event data output by the FESA chip without data blocking or loss; the onboard non-volatile memory uses flash memory chips, with sufficient storage capacity to save the timing phase-locked loop parameters of all channels, offering fast read speed and strong stability; the initial timing phase offset value is a pre-calibrated phase compensation parameter for each channel, used to eliminate phase deviations caused by differences in PCB board links and interfaces; the distributed digital phase-locked loop array consists of 64 independent digital phase-locked loops, each corresponding to one acquisition channel, with independent phase detectors, loop filters, and digitally controlled oscillators, capable of independently completing phase calibration while accepting unified reference phase control to achieve cross-channel synchronous phase locking.

[0118] Furthermore, in this embodiment, the FPGA chip receives 64 channels of asynchronous digital event data in real time, and simultaneously reads a set of timing phase-locked loop parameters containing the initial timing phase offset values ​​of 64 channels from flash memory. The 64 phase-locked loops of the distributed digital phase-locked loop array correspond one-to-one with the 64 channels, waiting for the input of the reference phase signal and the phase signal to be calibrated, preparing to perform the phase calibration operation.

[0119] S3.2: The multi-channel timing calibration field programmable gate array determines the reference channel from all internal acquisition channels and uses the corrected independent channel time stamp corresponding to the reference channel as the reference time phase;

[0120] Furthermore, the selection of the reference channel follows the principle of optimal timing, that is, the channel with the most stable and smallest deviation after correction of the independent channel time stamp is selected as the reference from all channels. Usually, the channel with the middle channel ID and the best hardware state is selected. The corrected independent channel time stamp of the reference channel is used as the global reference time phase, and all other channels are phase aligned with this as the target to ensure the timing uniformity of the entire system. After the reference time phase is determined, it will be broadcast to all phase-locked loops of the distributed digital phase-locked loop array as the target reference for phase calibration.

[0121] Furthermore, in this embodiment, the FPGA chip selects channel 32 as the reference channel by analyzing the stability of the corrected time stamps of the 64 channels, uses its corrected independent channel time stamps as the reference time phase, and broadcasts them to the remaining 63 phase-locked loops in real time, providing a unified reference for phase comparison and calibration.

[0122] S3.3: Each phase-locked loop uses the independent channel time stamp after correction of the corresponding internal acquisition channel as the phase to be calibrated, compares it with the reference time phase, and calibrates and corrects its own channel phase in combination with the initial timing phase offset value.

[0123] When the distributed digital phase-locked loop array is calibrated and corrected, a master-slave synchronous cascaded structure is adopted, including:

[0124] S3.3.1: The distributed digital phase-locked loop array sets the channel with the smallest corrected independent channel time stamp as the master synchronization channel and the remaining channels as slave synchronization channels according to the corrected independent channel time stamp of each internal acquisition channel.

[0125] S3.3.2: Set the corrected independent channel time stamp corresponding to the main synchronization channel as the reference time phase, and send it to the corresponding digital phase-locked loop of each of the slave synchronization channels through the synchronization broadcast link;

[0126] Furthermore, the synchronous broadcast link is configured as follows: the broadcast data bit width is set to 32 bits, which is completely matched with the bit width of the corrected independent channel time stamp; the broadcast clock rate is kept consistent with the system operating clock and set to 100MHz; the single-bit data transmission time is controlled within 10ns; and the synchronous broadcast enable delay is set to 50ps to ensure that the broadcast start time is highly aligned with the reference phase latch time.

[0127] S3.3.3: Each digital phase-locked loop corresponding to the synchronization channel takes the corrected independent channel time stamp of its own channel as the phase to be calibrated, and inputs the phase to be calibrated as the phase feedback signal to the internal phase detector. The phase detector calculates the difference between the input phase feedback signal and the received reference time phase to obtain the instantaneous phase error.

[0128] Furthermore, a dedicated signal transmission path is established inside the digital phase-locked loop to directly send the calibrated phase to be calibrated to the phase feedback signal input pin of the phase detector in the form of a parallel level signal. The signal transmission path adopts an equal-length wiring design to ensure that the signal is without delay or distortion.

[0129] S3.3.4: The instantaneous phase error is superimposed with the initial timing phase offset value of the current channel to obtain the pre-corrected phase error signal;

[0130] S3.3.5: The pre-corrected phase error signal is input to the loop filter. The loop filter filters and processes the pre-corrected phase error signal, converts it into a frequency control word that can drive the subsequent circuit, and inputs the frequency control word to the internal numerically controlled oscillator. The numerically controlled oscillator adjusts its output phase according to the magnitude and direction of the frequency control word.

[0131] Furthermore, the specific steps in S3.3.5 include:

[0132] (1) The initialization parameters of the loop filter and the numerically controlled oscillator are configured from the digital phase-locked loop corresponding to the synchronous channel. The loop filter adopts a proportional-integral structure. After the system is powered on, the internal registers, arithmetic units and delay units of the loop filter are cleared first, and then the set arithmetic parameters are loaded. The proportional coefficient is set to 0.8, the integral coefficient is set to 0.2, the integral accumulation bit width is set to 32 bits, the integral saturation upper limit is set to 1000, and the integral saturation lower limit is set to -1000 to avoid integral overflow leading to control abnormality. The initialization of the numerically controlled oscillator is also completed at this time. The phase output bit width of the numerically controlled oscillator is set to 32 bits, the minimum phase adjustment step size is set to 1ns, the initial value of the output phase is set to 0ns, the working clock is kept in the same source as the phase detector and is set to 100MHz. All parameters remain fixed during system operation.

[0133] (2) The pre-corrected phase error signal obtained by superimposing the phase detector and the initial timing phase offset value is sent to the signal input terminal of the loop filter through a dedicated data path. The loop filter latches the pre-corrected phase error signal at the same rising edge of the 100MHz clock and stores it in the error input register. The signal transmission delay is controlled within 50ps to ensure that the pre-corrected phase error signal is stable and distortion-free. In this embodiment, the pre-corrected phase error value from the first synchronization channel is 6ns, the pre-corrected phase error value from the second synchronization channel is 11ns, and the pre-corrected phase error value from the third synchronization channel is -4ns. All values ​​are stably latched.

[0134] (3) The loop filter reads the pre-corrected phase error value from the error input register, multiplies the pre-corrected phase error value by the preset proportional coefficient 0.8 to obtain the proportional adjustment output value. The calculation process adopts fixed-point multiplication, and the calculation result is retained to two decimal places to ensure that the adjustment accuracy is sufficient to support the phase calibration requirements. In this embodiment, the first proportional adjustment output value of 4.8ns is obtained by multiplying 6ns from the synchronization channel by 0.8, the second proportional adjustment output value of 8.8ns is obtained by multiplying 11ns from the synchronization channel by 0.8, and the third proportional adjustment output value of -3.2ns is obtained by multiplying -4ns from the synchronization channel by 0.8.

[0135] (4) The loop filter multiplies the pre-corrected phase error value with the preset integral coefficient 0.2 to obtain the integral increment value of the current error. Then, it adds the integral increment value to the integral accumulation value stored in the integral register of the previous cycle to obtain the latest integral accumulation value. If the integral accumulation value exceeds the saturation range of 1000 or is lower than -1000, it is automatically limited to the saturation threshold to prevent integral saturation from causing adjustment failure. In this embodiment, the first integral increment value of 1.2ns is obtained by multiplying 6ns from the synchronization channel by 0.2. After adding it to the integral value of 0 of the previous cycle, the integral accumulation value is 1.2ns. The second integral increment value of 2.2ns is obtained by multiplying 11ns from the synchronization channel by 0.2. The integral accumulation value is 2.2ns. The third integral increment value of -0.8ns is obtained by multiplying -4ns from the synchronization channel by 0.2. The integral accumulation value is -0.8ns.

[0136] (5) The loop filter algebraically adds the result of the proportional term operation and the result of the integral term operation to obtain the total control quantity after filtering and smoothing. This total control quantity eliminates the high-frequency jitter and random noise in the pre-corrected phase error signal and outputs a stable and continuous control signal. In this embodiment, the first proportional term 4.8ns and the integral term 1.2ns from the synchronization channel are added together to obtain a total control quantity of 6ns. The second proportional term 8.8ns and the integral term 2.2ns from the synchronization channel are added together to obtain a total control quantity of 11ns. The third proportional term -3.2ns and the integral term -0.8ns from the synchronization channel are added together to obtain a total control quantity of -4ns.

[0137] (6) The loop filter quantizes the total control quantity in floating-point form into an integer frequency control word according to the input format requirements of the numerically controlled oscillator. The quantization method is to directly round down without rounding, so as to ensure that the control direction and the numerical trend are consistent. The bit width of the frequency control word is consistent with the phase adjustment bit width of the numerically controlled oscillator and is set to 32 bits. Positive numbers represent that the output phase needs to be reduced and negative numbers represent that the output phase needs to be increased. In this embodiment, the first step is to convert the total control quantity of the synchronous channel 6ns into the frequency control word 6, the second step is to convert the total control quantity of the synchronous channel 11ns into the frequency control word 11, and the third step is to convert the total control quantity of the synchronous channel -4ns into the frequency control word -4.

[0138] (7) After the frequency control word is generated, the loop filter sends it to the input interface of the numerically controlled oscillator through the parallel data port. The numerically controlled oscillator latches the frequency control word into the internal control register on the same clock edge to ensure that the frequency control word is stable and reliable and that there are no transmission errors or timing offsets.

[0139] (8) The numerically controlled oscillator reads the frequency control word in the control register, first identifies the sign bit to determine the adjustment direction. When the frequency control word is positive, it is determined to be the direction of phase decrease, and when the frequency control word is negative, it is determined to be the direction of phase increase. Then, it reads the value bit to determine the adjustment amplitude. The value represents the total number of adjustment steps. Each step corresponds to a phase change of 1ns. In this embodiment, the first synchronous channel frequency control word 6 represents an adjustment of 6ns in the direction of decrease, the second synchronous channel frequency control word 11 represents an adjustment of 11ns in the direction of decrease, and the third synchronous channel frequency control word -4 represents an adjustment of 4ns in the direction of increase.

[0140] (9) The numerically controlled oscillator adjusts the current output phase step by step according to the direction and step size obtained by analysis. Each clock cycle completes an adjustment of 1ns until the total adjustment step size is reached. The adjustment process is continuous and smooth, and there will be no phase jump. This ensures that the output phase is stably approaching the reference time phase. In this embodiment, the output phase from the first synchronous channel decreases by 6ns, the output phase from the second synchronous channel decreases by 11ns, and the output phase from the third synchronous channel increases by 4ns.

[0141] (10) After the phase adjustment is completed, the numerically controlled oscillator outputs the latest output phase signal as the current channel updated phase to be calibrated and sends it back to the phase feedback input of the phase detector.

[0142] S3.3.6: The adjusted output phase of the numerically controlled oscillator is used as the new phase to be calibrated for the current channel and sent back to the phase detector as a phase feedback signal until the instantaneous phase error is reduced to zero.

[0143] S3.4: After the phase deviation of all internal acquisition channels has been calibrated and corrected, the multi-channel timing calibration field programmable gate array merges the corrected independent channel timestamps of each internal acquisition channel in chronological order to form a standardized imaging data stream with unified channel timing.

[0144] Furthermore, after phase calibration, the time stamps of all channels are globally unified with no phase deviation. The FPGA chip sorts and merges the event data of all channels in chronological order, removes duplicate and invalid data, and forms a continuous, complete, and time-series unified standardized imaging data stream. It retains the corrected independent channel time stamps, pulse amplitude codes, channel identifiers and other core information, and the data format meets the input requirements of the PET imaging system.

[0145] S4: Determine the energy information of gamma photon events based on the pulse amplitude information in the standardized imaging data stream, combine it with the inter-channel time interval data to complete the coincidence event screening, and reconstruct the PET tomographic image.

[0146] The specific steps of S4 include:

[0147] S4.1: The digital signal processing component connected to the multi-channel timing calibration field programmable gate array parses the pulse amplitude code from the standardized imaging data stream and converts the pulse amplitude code into energy information corresponding to gamma photon events;

[0148] Furthermore, the specific steps of S4.1 include:

[0149] (1) After the system starts, the digital signal processing component completes the initialization operation first, all circuits enter a stable standby state, the data transmission interface is set to 32-bit parallel transmission mode, the interface working clock is set to 100MHz, and it is completely consistent with the front-end timing calibration circuit to ensure that the data transmission is without delay or misalignment; and during the initialization stage, the factory-calibrated energy conversion coefficient table is loaded, the value of the energy conversion coefficient table is fixed throughout the process, the bit width of the pulse amplitude code is set to 12 bits, the corresponding value range is set to 0 to 4095, the unit of energy information is set to kiloelectron volts, i.e. keV, and the target energy range is set to 0 to 800keV;

[0150] (2) The multi-channel timing calibration field programmable gate array will complete the phase calibration and timing integration of the standardized imaging data stream, and continuously send it to the digital signal processing component through the parallel data link. The digital signal processing component latches the input data stream at each rising edge of the 100MHz clock and stores the complete data frame in the internal data buffer unit. The latching delay is controlled within 50ps to ensure that the data frame is complete and not lost or misaligned. The standardized imaging data stream contains three core information: calibrated independent channel time stamp, pulse amplitude encoding, and unique channel identifier. The data frame structure is fixed and orderly.

[0151] (3) The digital signal processing component performs field-by-field splitting and positioning of the latched standardized imaging data stream. Specifically, it first identifies the frame header flag and channel identifier information, and then accurately positions the data segment where the pulse amplitude code is located according to the preset field offset position. The pulse amplitude code occupies a fixed 12 data bits in the data frame, located after the independent channel time mark and before the check bit. The parsing unit completes accurate extraction according to this fixed position without bit offset error. In this embodiment, the 12 pulse amplitude code values ​​located and extracted from the standardized imaging data stream are 2816, 3070, 2457, etc., and each code corresponds one-to-one with the unique channel identifier and time mark.

[0152] (4) Perform numerical range verification on the extracted 12-bit pulse amplitude code to determine whether the pulse amplitude code value is within the legal range of 0 to 4095. Codes that exceed the legal range are judged as invalid data, directly removed and an error flag is recorded. Codes within the legal range are judged as valid data. Execute (5). In this embodiment, all extracted pulse amplitude code values ​​are within the legal range, and all verification results are valid and can participate in energy conversion normally.

[0153] (5) The digital signal processing component retrieves the preset energy conversion parameters, wherein the full-scale voltage value corresponding to the 12-bit pulse amplitude encoding is set to 1V, the gamma photon energy value corresponding to the 1V voltage is set to 800keV, and the energy increment value corresponding to a single encoding step is fixed at 0.195keV. This increment value is calculated by dividing 800keV by 4096 encoding levels.

[0154] (6) The digital signal processing component multiplies the verified pulse amplitude code value with the energy increment value corresponding to a single code step to obtain the original energy value corresponding to the current pulse amplitude code. In this embodiment, when the pulse amplitude code is 2816, 2816 is multiplied by 0.195keV to obtain the original energy value of 549.12keV. When the pulse amplitude code is 3070, 3070 is multiplied by 0.195keV to obtain the original energy value of 598.65keV. When the pulse amplitude code is 2457, 2457 is multiplied by 0.195keV to obtain the original energy value of 479.12keV.

[0155] (7) The digital signal processing component retrieves the channel energy correction coefficient loaded during initialization. The channel energy correction coefficient is a fixed value calibrated at the factory for each channel, used to eliminate inherent system errors introduced by preamplifier, peak sampling, analog-to-digital conversion, etc. In this embodiment, the energy correction coefficient of all channels is uniformly set to 1.01. The correction method is to multiply the original energy value by the energy correction coefficient to obtain the corrected accurate energy value. In this embodiment, the original energy value of 549.12keV multiplied by 1.01 yields a corrected accurate energy value of 554.61keV, the original energy value of 598.65keV multiplied by 1.01 yields a corrected accurate energy value of 604.64keV, and the original energy value of 479.12keV multiplied by 1.01 yields a corrected accurate energy value of 483.91keV;

[0156] (8) The digital signal processing component will formally calibrate the energy value after error correction as the gamma photon event energy information corresponding to the current pulse amplitude encoding. The gamma photon event energy information directly reflects the amount of energy deposited after the gamma photon is incident on the PET detector. The numerical unit of the energy information is uniformly keV.

[0157] (9) The digital signal processing component rebinds the generated gamma photon event energy information with the independent channel time stamp and unique channel identifier in the same data frame to form complete event data containing time information, energy information and channel information, and stores it.

[0158] S4.2: The digital signal processing component extracts the corrected independent channel time stamps from the standardized imaging data stream, and filters out matching event pairs based on the corrected independent channel time stamps and energy information;

[0159] Furthermore, a coincident event pair refers to an event in which two gamma photons generated by the annihilation of positive and negative electrons are simultaneously detected by two different channels of a PET detector, with a very small arrival time difference and similar energies. The digital signal processing component determines the temporal correlation of events through time stamps and the energy matching of events through energy information. Only two events that simultaneously meet the time and energy conditions can be identified as coincident event pairs. The screening process is carried out in real time, which can quickly extract effective data from massive event data and improve image reconstruction efficiency.

[0160] The process of filtering matching event pairs based on the corrected independent channel timestamps and energy information employs a dual filtering mechanism of time windows and energy windows, including:

[0161] S4.2.1: The digital signal processing component obtains the preset coincidence time window width and the upper and lower limits of the coincidence energy window. In this embodiment, the preset coincidence time window width is 10 ns and the upper and lower limits of the coincidence energy window are 430 keV to 650 keV.

[0162] S4.2.2: Extract the corrected independent channel time stamps and energy information corresponding to all gamma photon events from the standardized imaging data stream;

[0163] S4.2.3: Calculate the absolute value of the time difference between the corrected independent channel time stamps corresponding to any two different gamma photon events;

[0164] S4.2.4: When the absolute value of the time difference is less than or equal to the width of the time window, and the energy information corresponding to the two gamma photon events is between the upper and lower limits of the energy window, the two gamma photon events are determined to be a pair of coincident events.

[0165] Furthermore, the dual screening mechanism simultaneously satisfies both time and energy conditions, improving the accuracy of event matching and effectively eliminating invalid data such as random matches, scattering matches, and noise events. Only two gamma photon events that pass the verification of both the time window and the energy window can be determined as valid matching event pairs for image reconstruction. In this embodiment, event pairs with an absolute time difference of less than or equal to 10 ns and an energy between 430 keV and 650 keV are determined as matching event pairs, while all other events are eliminated.

[0166] S4.3: The matching event pair is transmitted to the image reconstruction processor, which processes the matching event pair using a filtered back projection algorithm to generate a PET tomographic image.

[0167] Furthermore, the specific steps of S4.3 include:

[0168] (1) After the system is powered on, the image reconstruction processor clears all registers of the internal data receiving interface, projection data buffer unit, filtering operation unit, back projection operation unit and image output unit. Then it loads the algorithm running parameters. The matrix size of the reconstructed image is set to 128×128, the physical size of each pixel is set to 1.5×1.5 mm, the number of tomographic layers is set to 128, and the thickness of each tomographic layer is set to 2 mm. The total number of projection angles is set to 360, and the interval between adjacent projection angles is one degree. The filtering function is selected as the ramp filter function and paired with the Hanning window function. The cutoff frequency of the Hanning window function is set to 0.8 times the Nyquist frequency. The bit width of the projection data is set to 32 bits, and the quantization bit of the image pixel value is set to 16 bits. All parameters remain fixed during the reconstruction process.

[0169] (2) The image reconstruction processor receives coincidence event pair data from the digital signal processing component through the high-speed data receiving interface. Under the synchronization of the 100MHz working clock, each coincidence event pair is latched one by one and all coincidence event pairs are stored in a dedicated projection data buffer unit. Each coincidence event pair contains the number of two channels, the corresponding corrected independent channel time stamp, energy information, and the spatial position information of two response lines. The storage depth of the projection data buffer unit is set to 100,000 coincidence event pairs to ensure that all valid coincidence event pairs generated in a single scan can be completely stored. There is no loss or misalignment in the data receiving process, and the transmission delay is controlled within 50ps.

[0170] (3) Based on the physical position of the two channels corresponding to each pair of coincidence events, calculate the spatial angle and radial position of the response line corresponding to the pair of coincidence events. Accumulate the count of the pair of coincidence events into the projection data buffer unit corresponding to the projection angle and radial position. Traverse all pairs of coincidence events to complete the filling of all projection data and form a complete projection sine curve. In this embodiment, each projection angle corresponds to 128 radial sampling units, and the radial sampling interval is set to 2 mm. All pairs of coincidence events are accurately positioned in the corresponding projection data buffer unit, with no projection misalignment and no count omission.

[0171] Furthermore, the calculation process for the spatial angle and radial position of the response line corresponding to the event pair is as follows:

[0172] The image reconstruction processor extracts the numbers of the first and second channels from the event pair data. Based on the physical position parameter table of the PET detector ring array pre-stored in the system, it reads the polar coordinate positions of the two channels on the ring detector. In this embodiment, the PET detector is a complete ring structure with a fixed ring radius of 400 mm. The total number of detector channels is 64, which are evenly distributed on the entire circumference. Each channel corresponds to a fixed circumferential angle. The angle corresponding to channel one is 0 degrees, the angle corresponding to channel two is 5.625 degrees, and the remaining channels increase sequentially at fixed angle intervals of 5.625 degrees. The physical position parameters of all channels are calibrated and permanently stored when the system leaves the factory.

[0173] The image reconstruction processor substitutes the circumferential angle and annular radius of the first channel into the rectangular coordinate transformation relationship to calculate the x-coordinate and y-coordinate of that channel. The x-coordinate is equal to the annular radius multiplied by the cosine of the corresponding angle, and the y-coordinate is equal to the annular radius multiplied by the sine of the corresponding angle. The x-coordinate and y-coordinate of the second channel are calculated in the same way.

[0174] The slope and intercept of the response line are calculated based on the rectangular coordinates of the two channels. The slope is equal to the difference between the ordinate of the second channel and the ordinate of the first channel, divided by the difference between the abscissa of the second channel and the abscissa of the first channel. The intercept is equal to the product of the slope and the abscissa of the first channel, which is the ordinate of the first channel. Thus, the complete linear equation of the response line in the reconstruction plane is determined, and this line is the response line through which the gamma photon pair passes.

[0175] Based on the slope of the response line, calculate the angle between the response line and the horizontal coordinate axis of the reconstruction plane. This angle is the spatial angle of the response line. The spatial angle ranges from 0 degrees to 179 degrees. When calculating, first perform an arctangent operation on the slope to obtain the initial angle. If the response line crosses the left and right halves of the coordinate system, add 180 degrees to the initial angle. Finally, normalize the calculation result to a standard projection angle between 0 degrees and 179 degrees.

[0176] The vertical distance from the origin of the reconstructed plane coordinates to the response line is calculated. This vertical distance is the radial position of the response line. The radial position is calculated using the distance formula from a point to a line. The origin of the coordinates is substituted into the linear equation of the response line. The numerator is the absolute value of the intercept, and the denominator is the square root of the slope squared plus one. The two are divided to obtain the radial distance value. In this embodiment, the radial sampling interval is set to 2 mm. Therefore, the calculated radial distance is rounded according to the 2 mm interval to obtain the radial position number corresponding to the 128 radial sampling units, ensuring that the response line accurately matches the corresponding radial sampling unit.

[0177] The image reconstruction processor latches the rectified spatial angle and radial position number as the sole basis for the current coincidence event pair projection data to be placed. This angle and position directly correspond to a specific data unit in the projection sine graph, ensuring that the count value of the coincidence event pair can be accurately accumulated to the correct projection unit.

[0178] (4) The image reconstruction processor performs normalization correction on the filled projection sine curve. The correction method is to multiply the count value of each projection unit by the normalization correction coefficient of the corresponding channel. The normalization correction coefficient adopts the fixed value calibrated by the system factory, and the value range is 0.9~1.1. It is used to eliminate the projection error caused by the difference in detector channel sensitivity and geometric position deviation.

[0179] (5) The image reconstruction processor inputs the corrected one-dimensional projection data into the filtering operation unit in sequence. First, it performs a fast Fourier transform on the corrected one-dimensional projection data to convert the time-domain projection data to the frequency domain space. The number of points of the fast Fourier transform is set to 256. The transformation process is completed under the cooperation of hardware multipliers and adders. The fast Fourier transform is the prior art in this field and is not an inventive solution of this application. It will not be described in detail here.

[0180] (6) The filtering operation unit multiplies the frequency domain projection data with the pre-configured ramp filter function and Hanning window function point by point to complete the frequency domain filtering. The ramp filter function is used to enhance the high frequency components of the projection data and eliminate image edge blurring. The Hanning window function is used to suppress high frequency noise in the frequency domain and avoid ringing artifacts in the reconstructed image. The ramp filter function and Hanning window function are existing technologies in this field and are not the inventive solutions of this application. They will not be described in detail here.

[0181] (7) After filtering is completed, the filtering operation unit performs an inverse fast Fourier transform on the frequency domain projection data to convert the data from the frequency domain space back to the time domain space and obtain the filtered and corrected projection data. The number of points of the inverse transform is consistent with the previous fast Fourier transform and is set to 256 points.

[0182] (8) The back projection operation unit accumulates the values ​​of the projection data point by point into the corresponding pixels of the 128×128 reconstructed image matrix according to the path of the response line based on the filtered and corrected projection data and the corresponding spatial position of the response line. The back projection is performed sequentially according to the projection angle from 0 degrees to 359 degrees. All radial projection data of each angle completes a full matrix back projection accumulation. The back projection process adopts hardware parallel computing, and the time for a single back projection iteration does not exceed 1 millisecond.

[0183] (9) After all 360 projection angles have been filtered and corrected, the projection data have been back-projected and accumulated. The value of each pixel in the reconstructed image matrix reaches a stable state, forming the initial PET tomographic image. The pixel value reflects the distribution of radioactive tracer concentration at that location. The higher the value, the higher the metabolic level of the corresponding area.

[0184] (10) The image output unit converts the initial floating-point format image pixel values ​​into 16-bit integer format and performs linear normalization, mapping the pixel values ​​to the standard gray range of 0 to 65535. In this embodiment, the normalization coefficient is fixed at 0.0001 to ensure that the image brightness is moderate and the details are clearly distinguishable.

[0185] (11) The image output unit performs three-point neighborhood average smoothing on the normalized tomographic image. The smoothing window size is set to 3×3. Only adjacent pixels are weighted and averaged. The core structure and lesion information of the image are not changed. The processed image effectively reduces random noise and ring artifacts, and maintains edge sharpness and spatial resolution.

[0186] (12) The smoothed image is labeled as the final PET tomographic image and transmitted to the system display unit and data storage unit through the image output interface. The image format meets the medical equipment standard and can be directly used by doctors to read the images and make clinical diagnoses.

[0187] S5: Real-time detection of PET tomographic images. When the image quality is lower than the preset image quality threshold, the timing measurement parameters of the FESA chip or the timing lock parameters of the PCB board are adjusted through the closed loop of the system control link.

[0188] The specific steps of S5 include:

[0189] S5.1: Acquire PET tomographic images, calculate the contrast-to-noise ratio and uniformity index of the PET tomographic images, and obtain a real-time comprehensive image quality score;

[0190] Furthermore, the contrast-to-noise ratio reflects the distinction between lesions and normal tissues in an image. The higher the ratio, the clearer the image details. The uniformity index reflects the gray-level uniformity of the image. The closer the index is to 1, the fewer image artifacts and the better the quality. The contrast-to-noise ratio and the uniformity index are combined to obtain a comprehensive image quality score, which ranges from 0 to 100 points. The higher the score, the better the image quality.

[0191] Furthermore, the specific steps in S5.1 include:

[0192] (1) After the system is powered on, all registers are cleared to ensure that all circuits enter a stable standby state. The matrix size of the PET tomographic image is fixed at 128×128, the size of the region of interest is set to 30×30, the size of the background region is set to 20×20, the uniformity detection region is the image center region with a size of 60×60, the contrast-to-noise ratio calculation weight is set to 0.6, the uniformity index calculation weight is set to 0.4, and the full score of the comprehensive score is set to 100.

[0193] (2) The latest generated PET tomographic image is read from the output cache of the image reconstruction processor through a dedicated data reading interface. Under the synchronous drive of a 100MHz working clock, the pixel data of the entire image is completely latched. The latching delay is controlled within 50ps to ensure that all pixel data is not lost or misaligned. The image data is 16-bit quantized grayscale pixel value with a value range between 0 and 65535. Each pixel value corresponds to the distribution intensity of the radioactive tracer in the body.

[0194] (3) Select the high-count target area as the region of interest in the PET tomographic image. The location is fixed in the upper left of the image center and the size is strictly 30×30. At the same time, select the background area in the uniform low-count area far away from the target area. The location is fixed in the lower right corner of the image and the size is strictly 20×20. The two areas do not overlap or intersect to ensure that the calculation results are not interfered with each other.

[0195] (4) Traverse all 900 pixels in the region of interest row by row and column by column, read the gray value of each pixel in turn, sum all the values ​​to get the total pixel sum, and then divide the total pixel sum by the total number of pixels in the region of interest, 900, to get the average pixel value of the region of interest.

[0196] (5) Traverse all 400 pixels in the background area in the same way. First, accumulate all pixel values ​​and calculate the average pixel value of the background area. Then, calculate the difference between each pixel value and the average pixel value of the background area. Square the difference and accumulate the difference. Divide the difference by the total number of pixels 400 to get the variance. Take the square root of the variance to get the standard deviation of the background area.

[0197] (6) Subtract the average pixel value of the background region from the average pixel value of the region of interest to obtain the numerator value. Then divide the numerator value by the standard deviation of the background region. The final value is the contrast-to-noise ratio of the current PET tomographic image. This value is used to characterize the degree of distinction between the target region and the background region in the image and the level of noise suppression. The larger the value, the clearer the distinction between the target and the background and the better the image quality.

[0198] (7) In the central region of the PET tomographic image, select a uniformity detection area of ​​size 60×60. The uniformity detection area covers the most stable central part of the image, avoiding edge artifacts and counting distortion areas. Extract the gray values ​​of all 3600 pixels in the uniformity detection area row by row and column by column, and store them in a dedicated uniformity calculation cache to ensure that the data is complete and without omission.

[0199] (8) First, sum the 3600 pixel values ​​in the uniformity detection area, then divide by the total number of pixels to get the average pixel value of the area. Then, traverse all pixel values, find the maximum and minimum pixel values ​​in the area, subtract the minimum pixel value from the maximum pixel value to get the pixel range, and then divide the range by the average pixel value of the area to get the relative deviation value.

[0200] (9) Subtract the relative deviation value from 1 to obtain the uniformity index of the current image. The uniformity index is used to characterize the stability of the gray distribution of the entire image. The closer the index is to one, the more uniform the image count is, the fewer the ring artifacts and stripe artifacts are, and the higher the imaging stability.

[0201] (10) Standardize the contrast-to-noise ratio and convert it into a value in the range of 0 to 60. Standardize the uniformity index and convert it into a value in the range of 0 to 40. Then add the converted contrast-to-noise ratio and uniformity index directly to obtain the total score, which is the real-time image quality comprehensive score. The score range is 0 to 100. The higher the score, the better the image quality.

[0202] (11) The three data points obtained in this evaluation—contrast-to-noise ratio, uniformity index, and real-time image quality comprehensive score—are uniformly latched into the result register for comparison with the preset image quality threshold.

[0203] S5.2: Compare the real-time image quality comprehensive score with the preset image quality threshold. When the real-time image quality comprehensive score is lower than the preset image quality threshold, generate a parameter optimization request. The parameter optimization request carries parameter type identification information and parameter value information.

[0204] Furthermore, the preset image quality threshold is determined by clinical imaging standards. In this embodiment, it is set to 70 points. A score below this value indicates that the image quality cannot meet the diagnostic requirements. In this embodiment, when the real-time image quality comprehensive score drops to 65 points, which is below the 70-point threshold, the system immediately generates a parameter optimization request, indicating that the timing measurement parameters of the FESA chip and the initial timing phase offset value of the PCB board need to be adjusted, and carrying the specific adjustment value.

[0205] S5.3: The parameter optimization request is transmitted to the configuration register of the FESA chip and the parameter update interface of the PCB board through the system control link; the system control link uses an arbitration method based on message identifier to transmit the parameter optimization request.

[0206] Furthermore, the system control link is a high-speed serial bus with fast transmission speed and high reliability. It adopts a message identifier arbitration method to ensure that parameter optimization requests are transmitted first. The request instructions are sent to the configuration register of the FESA chip and the parameter update interface of the PCB board respectively. After receiving the request instructions, the parameter update interface responds immediately and performs parameter update operation. In this embodiment, the parameter optimization request is transmitted in real time through the system control link, and the message identifier is set to the highest priority to ensure that the instructions reach the target hardware quickly. The FESA chip and the PCB board receive the instructions at the same time and start parameter update synchronously.

[0207] S5.4: The configuration register of the FESA chip adjusts the timing measurement parameters according to the parameter optimization request, and the parameter update interface of the PCB board updates the initial timing phase offset value in the timing phase-locked loop parameter set according to the parameter optimization request.

[0208] Furthermore, the FESA chip configuration register directly writes the new timing measurement parameters, which take effect immediately, adjusting the timing measurement accuracy and compensation value. The PCB board parameter update interface writes the new initial timing phase offset value to the non-volatile memory, overwriting the original parameters. The next calibration process will automatically use the new parameters. After the parameter adjustment is completed, the system restarts the data acquisition, timing calibration, and image reconstruction processes. In this embodiment, the FESA chip adjusts the timing measurement parameters, the PCB board updates the initial timing phase offset value of each channel, and after the parameter update, data is reacquired. The real-time quality comprehensive score of the reconstructed image rises back to 88 points, returning to the normal level, and the closed-loop adjustment is completed.

[0209] Example 2:

[0210] Please see Figure 3 Another embodiment of the present invention provides a multi-channel data synchronous acquisition and transmission system, comprising:

[0211] The data acquisition module 10 is configured with internal acquisition channels according to the total number of PET detector channels. It is exclusively connected to the analog nuclear signal output terminal of the PET detector through a differential signal link with impedance matching. It has a built-in independent preamplifier unit, a dual-path parallel processor and a time measurement core processor to complete the amplification of analog nuclear signals, pulse discrimination, and synchronous acquisition of arrival time information and pulse amplitude information. It realizes multi-channel independent time measurement, time domain correction and multi-channel asynchronous digital event data encapsulation and output.

[0212] The timing calibration module 20 is equipped with a multi-channel timing calibration field-programmable gate array, onboard non-volatile memory and distributed digital phase-locked loop array. It is used to retrieve pre-stored timing phase-locked parameters, determine the reference channel and complete cross-channel timing phase-locking and phase deviation calibration in a master-slave synchronous cascade structure. It merges the channel time stamps after phase calibration and generates a standardized imaging data stream with unified channel timing.

[0213] Image reconstruction module 30 includes a digital signal processing component and an image reconstruction processor. The digital signal processing component parses the pulse amplitude code to obtain gamma photon energy information and uses a dual filtering mechanism of time window and energy window to complete the matching event filtering. The image reconstruction processor processes the matching event pairs through a filtering back projection algorithm to reconstruct and generate PET tomographic images.

[0214] The control and detection module 40 is used to detect the image quality of PET tomographic images in real time, calculate the contrast-to-noise ratio and uniformity index to obtain a comprehensive real-time image quality score. When the comprehensive real-time image quality score is lower than the preset image quality threshold, a parameter optimization request is sent to the FESA chip configuration register and PCB board parameter update interface through the system control link. The time measurement parameters and timing phase-locked parameters are adjusted in a closed loop to ensure stable system operation.

[0215] The embodiments of the present invention have been described above with reference to the accompanying drawings. However, the present invention is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments under the guidance of the present invention without departing from the spirit and scope of the present invention. All of these variations are within the protection scope of the present invention.

Claims

1. A multi-channel data synchronous acquisition and transmission method, characterized in that, include: S1: The FESA chip is used to build a multi-acquisition channel integrated acquisition architecture, and all analog nuclear signals output by the PET detector are connected to the FESA chip of the acquisition architecture one by one. S2: The FESA chip sequentially amplifies and pulses each analog core signal, synchronously collects the arrival time and pulse amplitude information of each analog core signal, calculates the time interval data between channels through the arrival time information, and completes multi-channel independent time measurement and front-end digital processing by combining preset time measurement parameters, and outputs multi-channel asynchronous digital event data to the PCB board. S3: The PCB board retrieves the preset timing phase-locking parameters, performs cross-channel timing phase-locking and phase deviation calibration on the multi-channel asynchronous digital event data, and generates a standardized imaging data stream with unified channel timing. S4: Determine the energy information of gamma photon events based on the pulse amplitude information in the standardized imaging data stream, combine it with the inter-channel time interval data to complete the coincidence event screening, and reconstruct the PET tomographic image. S5: Real-time detection of PET tomographic images. When the image quality is lower than the preset image quality threshold, the timing measurement parameters of the FESA chip or the timing lock parameters of the PCB board are adjusted through the closed loop of the system control link.

2. The multi-channel data synchronous acquisition and transmission method as described in claim 1, characterized in that, The specific steps of S1 include: Based on the total number of gamma photon event output channels of the PET detector, the number of internal acquisition channels of the FESA chip is determined and configured; the input terminal of each internal acquisition channel of the FESA chip is exclusively connected to a corresponding analog nuclear signal output terminal of the PET detector through an impedance-matched differential signal link, so that each analog nuclear signal can be independently accessed by the corresponding internal acquisition channel; the gamma photon event is a data entity of a single effective photon interaction detected by the PET detector, and is the smallest effective data unit.

3. The multi-channel data synchronous acquisition and transmission method as described in claim 2, characterized in that, The FESA chip sequentially amplifies and identifies the pulses of each analog core signal, and simultaneously acquires the arrival time and pulse amplitude information of each analog core signal, including: Each established internal acquisition channel in the FESA chip is assigned an independent preamplifier unit. Each preamplifier unit receives the analog core signal input from the corresponding internal acquisition channel, performs amplitude normalization amplification processing on the received analog core signal, and outputs an amplified core pulse signal with consistent amplitude. The amplitude-consistent amplified nuclear pulse signal output by the preamplifier unit is transmitted in parallel to the dual-path parallel processor of each internal acquisition channel; the dual-path parallel processor includes a first path and a second path. The dual-path parallel processor obtains the voltage amplitude of the amplified core pulse signal through the pulse leading edge detection circuit set in the first path, and compares the voltage amplitude with the trigger threshold determined based on the channel background noise. When the voltage amplitude of the amplified core pulse signal exceeds the trigger threshold for the first time, the current time is recorded and a corresponding arrival timestamp is generated. The arrival timestamp is used as the arrival time information of the amplified core pulse signal. The dual-path parallel processor, upon arrival at the time of timestamp generation, captures the maximum voltage value of the amplified core pulse signal through the peak sample-and-hold circuit set in the second path, quantizes the captured maximum voltage value to form a corresponding pulse amplitude code, and uses the pulse amplitude code as the pulse amplitude information of the amplified core pulse signal.

4. The multi-channel data synchronous acquisition and transmission method as described in claim 3, characterized in that, The process of outputting asynchronous digital event data includes: The FESA chip's time measurement core processor acquires the arrival timestamps output by each internal acquisition channel, reads the arrival timestamps of each internal acquisition channel according to a preset polling order, and calculates the difference between the arrival timestamps of the current channel and the previous channel to obtain the time interval data between channels. The time measurement core processor calculates time offset compensation values ​​independently for each internal acquisition channel based on the basic time reference provided by the external crystal oscillator, the time interval data between channels, and the preset time measurement parameters. The arrival timestamps of each internal acquisition channel are linearly corrected in the time domain using the time offset compensation value to obtain the corrected independent channel time stamps. The time measurement core processor encapsulates the corrected independent channel time stamps, pulse amplitude codes, and unique channel identifiers corresponding to each internal acquisition channel into asynchronous digital event data.

5. The multi-channel data synchronous acquisition and transmission method as described in claim 4, characterized in that, The specific steps of S3 include: The multi-channel timing calibration field-programmable gate array on the PCB receives the asynchronous digital event data and reads the pre-stored timing phase-locked loop parameter set from the onboard non-volatile memory; the timing phase-locked loop parameter set contains the initial timing phase offset value corresponding to the unique channel identifier of each internal acquisition channel; the multi-channel timing calibration field-programmable gate array is configured with a distributed digital phase-locked loop array, and each phase-locked loop in the distributed digital phase-locked loop array uniquely corresponds to one internal acquisition channel; The multi-channel timing calibration field-programmable gate array determines the reference channel from all internal acquisition channels and uses the corrected independent channel time stamp corresponding to the reference channel as the reference time phase. Each phase-locked loop uses the independent channel time stamp after correction of the corresponding internal acquisition channel as the phase to be calibrated, compares it with the reference time phase, and calibrates and corrects its own channel phase in combination with the initial timing phase offset value. Once the phase deviations of all internal acquisition channels have been calibrated and corrected, the multi-channel timing calibration field-programmable gate array merges the corrected independent channel timestamps of each internal acquisition channel in chronological order to form a standardized imaging data stream with unified channel timing.

6. The multi-channel data synchronous acquisition and transmission method as described in claim 5, characterized in that, When the distributed digital phase-locked loop array is calibrated and corrected, a master-slave synchronous cascaded structure is adopted, including: The distributed digital phase-locked loop array uses the corrected independent channel time stamps of each internal acquisition channel to designate the channel with the smallest corrected independent channel time stamp as the master synchronization channel and the remaining channels as slave synchronization channels. The corrected independent channel time stamp corresponding to the main synchronization channel is set as the reference time phase and sent to the digital phase-locked loops corresponding to each of the slave synchronization channels through the synchronization broadcast link. Each digital phase-locked loop corresponding to the synchronization channel takes the corrected independent channel time stamp of its own channel as the phase to be calibrated, and inputs the phase to be calibrated as the phase feedback signal to the internal phase detector. The phase detector compares the input phase feedback signal with the received reference time phase in real time to obtain the instantaneous phase error, and then adds the instantaneous phase error to the initial timing phase offset value of the current channel to obtain the pre-corrected phase error signal. The pre-corrected phase error signal is input to the loop filter. The loop filter filters and processes the pre-corrected phase error signal, converts it into a frequency control word, and inputs the frequency control word to the internal numerically controlled oscillator. The numerically controlled oscillator adjusts its output phase according to the magnitude and direction of the frequency control word. The adjusted output phase of the numerically controlled oscillator is used as the new phase to be calibrated for the current channel, and is sent to the phase detector as a phase feedback signal again until the instantaneous phase error is reduced to zero.

7. The multi-channel data synchronous acquisition and transmission method as described in claim 6, characterized in that, The specific steps of S4 include: A digital signal processing component connected to a multi-channel timing calibration field-programmable gate array parses the pulse amplitude code from the standardized imaging data stream and converts the pulse amplitude code into energy information corresponding to gamma photon events; The digital signal processing component extracts corrected independent channel time stamps from the standardized imaging data stream, and filters out matching event pairs based on the corrected independent channel time stamps and energy information; The matching event pairs are transmitted to the image reconstruction processor, which processes them using a filtered back projection algorithm to generate PET tomographic images.

8. The multi-channel data synchronous acquisition and transmission method as described in claim 7, characterized in that, The process of filtering matching event pairs based on the corrected independent channel timestamps and energy information employs a dual filtering mechanism of time windows and energy windows, including: The digital signal processing component acquires the preset coincidence time window width and coincidence energy window upper and lower limits; Extract corrected independent channel time stamps and energy information corresponding to all gamma photon events from the standardized imaging data stream; Calculate the absolute value of the time difference between the corrected independent channel time stamps corresponding to any two different gamma photon events; When the absolute value of the time difference is less than or equal to the width of the time window, and the energy information corresponding to the two gamma photon events is between the upper and lower limits of the energy window, the two gamma photon events are determined to be a pair of coincident events.

9. The multi-channel data synchronous acquisition and transmission method as described in claim 8, characterized in that, The specific steps of S5 include: Acquire PET tomographic images, calculate the contrast-to-noise ratio and uniformity index of the PET tomographic images, and obtain a real-time comprehensive image quality score; The real-time image quality comprehensive score is compared with a preset image quality threshold. When the real-time image quality comprehensive score is lower than the preset image quality threshold, a parameter optimization request is generated. The parameter optimization request carries parameter type identification information and parameter value information. The parameter optimization request is transmitted to the configuration register of the FESA chip and the parameter update interface of the PCB board via the system control link; the system control link uses an arbitration method based on message identifiers to transmit the parameter optimization request. The configuration register of the FESA chip adjusts the timing measurement parameters according to the parameter optimization request, and the parameter update interface of the PCB board updates the initial timing phase offset value in the timing phase-locked loop parameter set according to the parameter optimization request.

10. A multi-channel data synchronous acquisition and transmission system, used to implement the multi-channel data synchronous acquisition and transmission method according to any one of claims 1-9, characterized in that, include: The data acquisition module is configured with internal acquisition channels based on the total number of channels of the PET detector. It is exclusively connected to the analog nuclear signal output terminal of the PET detector through an impedance-matched differential signal link to complete the amplification of the analog nuclear signal, pulse discrimination, synchronous acquisition of arrival time information and pulse amplitude information, and output of multiple channels of asynchronous digital event data. The timing calibration module is used to retrieve pre-stored timing phase-locked parameters, determine the reference channel, and complete cross-channel timing phase-locked and phase deviation calibration in a master-slave synchronous cascade structure. It merges the phase-calibrated channel time stamps to generate a standardized imaging data stream. The image reconstruction module uses a dual filtering mechanism of time window and energy window to complete the screening of matching events, and processes the matching event pairs through a filtering back projection algorithm to generate PET tomographic images. The control and detection module is used to detect the image quality of PET tomographic images in real time, calculate the contrast-to-noise ratio and uniformity index to obtain a comprehensive real-time image quality score. When the comprehensive real-time image quality score is lower than the preset image quality threshold, a parameter optimization request is sent to the FESA chip configuration register and PCB board parameter update interface through the system control link to adjust the time measurement parameters and timing phase-locked loop parameters.

Images