Chip sorting test method, device and system

Abstract

A chip sorting test method, device and system are disclosed, which determines the use state of a test site and configuration information of the test site; determines a standby test site of a to-be-tested chip based on the use state of the test site and the configuration information of the test site; controls a mechanical hand to place the to-be-tested chip into the standby test site for testing; in response to the to-be-tested chip completing the test in the standby test site, and the test result and / or test progress of the to-be-tested chip indicating that the to-be-tested chip needs to be moved to a next standby test site for testing, iteratively performs the operation of controlling the mechanical hand to move the to-be-tested chip to the next standby test site for testing until the test result and / or test progress of the to-be-tested chip indicates that the to-be-tested chip does not need to be tested any more, thereby realizing continuous serial testing, efficient and accurate testing and optimized resource configuration of the to-be-tested chip between multiple test sites on a handler, and improving the test capacity and product yield.

Description

Technical Field

[0001] This disclosure relates to the field of chip testing technology, and in particular to a chip sorting and testing method, apparatus and system. Background Technology

[0002] The sorting machine is a core automated device for realizing chip electrical testing, performance classification, and defective product screening. Its testing efficiency and accuracy directly determine the packaging and testing capacity and product yield.

[0003] In related technologies, chip sorting machines can perform chip sorting tests through single-site independent testing or multi-site parallel testing. Single-site independent testing can only complete a single test item for one chip per test, resulting in a long testing cycle and failing to meet the needs of large-scale chip sorting testing. While multi-site parallel testing can simultaneously test multiple chips for the same test item, each test station needs to synchronously complete the entire process of pressure testing and data reading. This synchronization between multiple test stations is prone to interference, affecting test accuracy. Furthermore, different test items require step-by-step switching, further extending the testing cycle and making it difficult to meet the high-precision, high-efficiency packaging and testing requirements of semiconductor chips. Summary of the Invention

[0004] To address the aforementioned technical problems, this disclosure provides a chip sorting and testing method, apparatus, and system.

[0005] According to one aspect of the present disclosure, a chip sorting and testing method is provided, comprising: Determine the usage status and configuration information of the test site; Based on the usage status and configuration information of the test sites, the available test sites for the chip under test are determined. The robotic arm is controlled to place the chip under test into the test station for testing. In response to the chip under test completing the test at the available test site, and the test result and / or test progress of the chip under test indicating that the chip under test needs to be moved to the next available test site for testing, the operation of controlling the robot to move the chip under test to the next available test site for testing is iteratively executed until the test result and / or test progress of the chip under test indicate that the chip under test no longer needs to be tested.

[0006] According to another aspect of the present disclosure, a chip sorting and testing apparatus is provided, comprising: The first determination module is used to determine the usage status and configuration information of the test site; The second determining module is used to determine the test site to be used for the chip under test based on the usage status and configuration information of the test site. The testing module is used to control the robotic arm to place the chip under test into the test station for testing; The first moving module is configured to, in response to the chip under test completing the test at the designated test site and the test result and / or test progress indicating that the chip under test needs to be moved to the next designated test site for testing, iteratively execute the operation of controlling the robotic arm to move the chip under test to the next designated test site for testing, until the test result and / or test progress indicating that the chip under test no longer needs to be tested.

[0007] According to another aspect of the present disclosure, a chip sorting and testing system is provided, the system including a sorter and at least one test station for serial testing; The sorting machine is used to determine the usage status and configuration information of the test stations; based on the usage status and configuration information of the test stations, it determines the available test stations for the chip under test; it controls the robotic arm to place the chip under test into the available test station for testing; in response to the chip under test completing the test at the available test station, and the test result and / or test progress indicating that the chip under test needs to be moved to the next available test station for testing, iteratively executes the operation of controlling the robotic arm to move the chip under test to the next available test station for testing, until the test result and / or test progress indicating that the chip under test no longer needs to be tested.

[0008] Based on the embodiments of this disclosure, when performing chip sorting tests, the usage status and configuration information of each test station can be determined first. Based on the usage status and configuration information of the test stations, the candidate test station for the chip under test is then determined. The robot arm is controlled to place the chip under test into the candidate test station for testing. In response to the chip under test completing the test at the candidate test station, and the test result and / or test progress indicating that the chip under test needs to be moved to the next candidate test station for testing, the operation of controlling the robot arm to move the chip under test to the next candidate test station for testing is iteratively executed until the test result and / or test progress indicating that the chip under test no longer needs to be tested. This realizes continuous serial testing, efficient and accurate testing, and optimized resource allocation of the chip under test among multiple test stations on the sorting machine, improving packaging and testing capacity and product yield. Moreover, it avoids the problems of chip damage and test data incompatibility caused by transferring chips between different sorting machines, and can meet the needs of high-precision and high-efficiency packaging and testing.

[0009] The technical solutions of this disclosure will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0010] The above and other objects, features, and advantages of this disclosure will become more apparent from the more detailed description of the embodiments thereof in conjunction with the accompanying drawings. The drawings are provided to further illustrate the embodiments of this disclosure and form part of the specification. They are used together with the embodiments of this disclosure to explain the disclosure and do not constitute a limitation thereof. In the drawings, the same reference numerals generally represent the same components or steps.

[0011] This disclosure will become clearer with reference to the accompanying drawings and the following detailed description, wherein: Figure 1 A system architecture diagram applicable to the chip sorting and testing method disclosed herein; Figure 2 This is a schematic flowchart of one embodiment of the chip sorting and testing method disclosed herein; Figure 3 This is a flowchart illustrating step 203 of the chip sorting and testing method disclosed herein; Figure 4 This is a flowchart illustrating step 202 of the chip sorting and testing method disclosed herein; Figure 5 This is a schematic flowchart of another embodiment of the chip sorting and testing method disclosed herein; Figure 6 This is a structural diagram of one embodiment of the chip sorting and testing apparatus disclosed herein; Figure 7 This is a structural diagram of another embodiment of the chip sorting and testing apparatus disclosed herein; Figure 8 This is a structural diagram of an electronic device for chip sorting and testing according to the present disclosure. Detailed Implementation

[0012] Hereinafter, exemplary embodiments according to the present disclosure will be described in detail with reference to the accompanying drawings. Obviously, the described embodiments are merely some embodiments of the present disclosure, and not all embodiments of the present disclosure, and it should be understood that the present disclosure is not limited to the exemplary embodiments described herein.

[0013] It should be noted that, unless otherwise specifically stated, the relative arrangement, numerical expressions, and values ​​of the components and steps set forth in these embodiments do not limit the scope of this disclosure.

[0014] Those skilled in the art will understand that the terms "first," "second," etc., in the embodiments of this disclosure are only used to distinguish different steps, devices, or modules, and do not represent any specific technical meaning, nor do they indicate a necessary logical order between them.

[0015] It should also be understood that in the embodiments disclosed herein, "a plurality of" may refer to two or more, and "at least one" may refer to one, two or more.

[0016] It should also be understood that any component, data or structure mentioned in the embodiments of this disclosure can generally be understood as one or more unless expressly defined or given to the contrary in the context.

[0017] Furthermore, the term "and / or" in this disclosure is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / " in this disclosure generally indicates that the preceding and following related objects have an "or" relationship.

[0018] It should also be understood that the description of the various embodiments in this disclosure emphasizes the differences between the various embodiments, and the similarities or similarities can be referred to each other. For the sake of brevity, they will not be described in detail.

[0019] At the same time, it should be understood that, for ease of description, the dimensions of the various parts shown in the accompanying drawings are not drawn according to actual scale.

[0020] The following description of at least one exemplary embodiment is merely illustrative and is in no way intended to limit this disclosure or its application or use.

[0021] Techniques, methods, and equipment known to those skilled in the art may not be discussed in detail, but where appropriate, they should be considered part of the specification.

[0022] It should be noted that similar labels and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be discussed further in subsequent figures.

[0023] The embodiments disclosed herein can be applied to electronic devices such as terminal devices, computer systems, and servers, and can operate together with a wide range of other general-purpose or special-purpose computing system environments or configurations. Examples of well-known terminal devices, computing systems, environments, and / or configurations suitable for use with electronic devices such as terminal devices, computer systems, and servers include, but are not limited to: personal computer systems, server computer systems, thin clients, thick clients, handheld or laptop devices, microprocessor-based systems, set-top boxes, programmable consumer electronics, network PCs, minicomputer systems, mainframe computer systems, and distributed cloud computing environments including any of the above systems, etc.

[0024] Electronic devices such as terminal devices, computer systems, and servers can be described in the general context of computer system executable instructions (such as program modules) executed by a computer system. Typically, program modules can include routines, programs, object programs, components, logic, data structures, etc., which perform specific tasks or implement specific abstract data types. Computer systems / servers can be implemented in distributed cloud computing environments, where tasks are executed by remote processing devices linked through communication networks. In distributed cloud computing environments, program modules can reside on local or remote computing system storage media, including storage devices.

[0025] This disclosure outlines In developing this disclosure, the inventors discovered that neither single-site independent testing nor multi-site parallel testing can achieve continuous testing and transfer of chips between different testing stations on the same sorting machine when sorting and testing chips. When chips are upgraded or there are many chip test items, it is necessary to update the test programs at each testing station and build a new test platform to implement the new test items, which is costly; alternatively, the chip can be transferred to other sorting machines for testing other items. Transferring chips between different sorting machines can easily lead to problems such as solder ball damage and pin damage. Furthermore, test data cannot be linked and traced across multiple stations, resulting in a high risk of missed defective products and making it difficult to meet the high-precision, high-efficiency packaging and testing requirements of high-end semiconductor chips.

[0026] In order to solve the above-mentioned technical problems in chip sorting and testing, the inventors have proposed the technical solution disclosed herein.

[0027] Exemplary System Figure 1 This is a system architecture diagram applicable to the chip sorting and testing method disclosed herein. (See diagram below.) Figure 1 As shown, the system includes a sorting machine 110 and at least one test station 120 for serial testing. The sorting machine 110 includes a robotic arm 111, which can control the transfer of the chip under test 130 between different test stations 120, so as to complete multiple test items of the chip under test 130 through different test stations.

[0028] In the chip sorting and testing system, the sorter 110 is used to determine the usage status and configuration information of the test station 120. Based on the usage status and configuration information of the test station 120, the system determines the available test station for the chip under test 130. The system controls the robot arm 111 to place the chip under test 130 into the available test station for testing. In response to the chip under test 130 completing the test at the available test station, and the test result and / or test progress indicating that the chip under test needs to be moved to the next available test station for testing, the system iteratively executes the operation of controlling the robot arm 111 to move the chip under test 130 to the next available test station for testing, until the test result and / or test progress indicating that the chip under test no longer needs to be tested.

[0029] The system's test stations 120 can be configured according to business needs, and their number can be increased or decreased in real time based on the number and changes of the test items required for the chip under test. Different test stations can be configured with different test items; for example, one test station can be configured to test the chip's temperature control, while another can be configured to test the chip's power consumption.

[0030] In this embodiment of the disclosure, different test stations in the system can form one test path or multiple test paths. For example, it includes four test stations, each used to complete different electrical test items. The chip under test can complete all test items by passing through the four test stations. Alternatively, the system includes four test stations, which can form multiple test paths. Test stations 1 and 2 complete the same test items, and test stations 3 and 4 complete the same test items. Therefore, test stations 1 and 3 can form one test path, and test stations 2 and 4 can form another test path, or test stations 1 and 4 can form one test path, and test stations 2 and 3 can form another test path.

[0031] In this embodiment of the disclosure, the sorting machine 110 can control the robotic arm to move the chip under test between different test stations, and can obtain the chip under test from the feed tray and place it in different test stations for testing, thereby realizing continuous serial testing of the chip under test 130 between multiple test stations on the sorting machine 110.

[0032] In the chip sorting and testing system, when the chip under test 130 is moved to a test station at the end of the test path for testing, other chips under test can be tested at an unoccupied front-end test station to improve chip testing efficiency.

[0033] Exemplary methods Figure 2 This is a schematic flowchart of an embodiment of the chip sorting and testing method disclosed herein; the chip sorting and testing method can be applied in a sorting machine, such as... Figure 2 As shown, the sorting and testing method for this chip may include the following steps 201 to 204. Each step is explained below.

[0034] In step 201, the usage status and configuration information of the test site are determined.

[0035] The usage status of the test station indicates whether a chip under test is being tested at the test station. The usage status of the test station can include two states: not occupied by a chip and occupied by a chip.

[0036] The configuration information of the test site is used to indicate the test items, test sequence, and other information that the test site is configured to execute.

[0037] For example, the system has three test stations, which are used to perform DC parameter tests, AC parameter tests, breakdown tests, etc. The configuration information of the three test stations can be set according to the test sequence and test items. For example, test station 1 is numbered 1 and is used to perform the first test, such as DC parameter test; test station 2 is numbered 2 and is used to perform the second test, such as AC parameter test; and test station 3 is numbered 3 and is used to perform the third test, such as breakdown test.

[0038] In this embodiment, the test sequence of a test site can be identified by the site number. For example, if the site number of a test site is 1, it means that the test sequence is the first test.

[0039] In this embodiment, the configuration information of each test site can be pre-configured according to the testing requirements of the current batch of chips under test, and stored in the site configuration file.

[0040] In step 202, the test sites to be used for the chip under test are determined based on the usage status and configuration information of the test sites.

[0041] In this embodiment, when the sorting machine starts running, the robot arm can obtain the usage status of the test site and obtain the configuration information of the test site from the site configuration file. The configuration information includes the configuration number and the test items.

[0042] Specifically, the presence of a chip at a test station can be determined using a vacuum generator (vacuum pump) on the robotic arm. If a chip is occupied at a test station, the robotic arm picks it up and moves it to the receiving area. Alternatively, a prompt message can be generated to remind the tester to verify whether the chip at the test station should be placed in the qualified or unqualified area of ​​the receiving area and to move the chip accordingly. The station configuration file records the configuration information for each test station, including the test items configured to be executed at the test station and the test sequence.

[0043] When the sorting machine starts testing, if it is determined that the test site is not occupied by the chip, the configuration information of the test site can be used to indicate that the first test can be performed. For example, the test site with site number 1 can be identified as the test site to be used.

[0044] In this embodiment, during the sorting test, for example, when the chip under test has completed the test at test station 1 and it is necessary to determine the next test station to be used, the usage status of the test station after test station 1 can be determined by a robotic arm; or, the usage status of the test station can be queried through the station status record file.

[0045] The site status log file can record the usage status of each test site. During the chip testing process, the usage status of the test site can be updated in real time when the chip to be tested is placed on the test site and when the chip is removed from the test site.

[0046] Specifically, after the robotic arm places the chip under test into the test station for testing, the usage status of the test station can be updated in the station status log file to be occupied by the chip; after the robotic arm moves the chip under test to the next test station for testing, the usage status of the test station can be updated in the station status log file to be unoccupied by the chip.

[0047] In this embodiment, during the sorting test, if it is determined that the next test station after the current test station is not occupied by the chip, then the next test station can be determined as a standby test station; if it is determined that the next test station after the current test station is occupied by the chip, then when the next test station's usage status changes to not being occupied by the chip, it can be determined as a standby test station.

[0048] In step 203, the robot arm is controlled to place the chip under test into the test station for testing.

[0049] In some implementations, a robotic arm can use a vacuum pump to generate negative pressure to attract the chip surface, then move to the corresponding test station and release the chip, allowing it to slide into the test station.

[0050] In other implementations, the robotic arm can also gently grip the chip from both sides using servo-controlled flexible grippers (such as rubber clamping plates), then move it to the corresponding test station and release the chip, allowing it to slide into the test station.

[0051] In step 204, in response to the chip under test completing the test at the test site and the test result and / or test progress indicating that the chip under test needs to be moved to the next test site for testing, the operation of controlling the robot to move the chip under test to the next test site for testing is iteratively executed until the test result and / or test progress indicating that the chip under test no longer needs to be tested.

[0052] The test result for the chip under test at each test station can be either "pass" or "fail". The test progress is used to characterize the progress of the sorting test of the chip under test. For example, if the sorting test of the chip under test needs to be completed through 4 test stations, then the test progress is considered complete only if all 4 test stations have completed the test; otherwise, the test progress is considered incomplete.

[0053] In this embodiment, if the test result of the chip under test is "test passed" and the test progress indicates that the test is not completed, it can be determined that the chip under test needs to be moved to the next available test site for testing; otherwise, it indicates that the chip under test does not need to be moved to the next available test site for testing.

[0054] In this embodiment, by iteratively executing the operation of controlling the robot to move the chip under test to the next test station for testing, the chip under test can be tested for different test items in sequence at different test stations until the test results and / or test progress indicate that the chip under test does not need to be tested anymore, then the chip under test can be moved to the receiving area.

[0055] In this embodiment, in response to a test result indicating that the test has failed, the robot arm can be controlled to move the chip under test to the non-conforming area in the receiving area; in response to a test result indicating that the test has passed and a test progress indicating that the test has been completed, the robot arm can be controlled to move the chip under test to the conforming area in the receiving area, thereby completing the complete testing process of the chip from the picking area to the receiving area.

[0056] Based on the embodiments of this disclosure, when performing chip sorting tests, the usage status and configuration information of each test station can be determined first. Based on the usage status and configuration information of the test stations, the candidate test station for the chip under test is then determined. The robot arm is controlled to place the chip under test into the candidate test station for testing. In response to the chip under test completing the test at the candidate test station, and the test result and / or test progress indicating that the chip under test needs to be moved to the next candidate test station for testing, the operation of controlling the robot arm to move the chip under test to the next candidate test station for testing is iteratively executed until the test result and / or test progress indicating that the chip under test no longer needs to be tested. This realizes continuous serial testing, efficient and accurate testing, and optimized resource allocation of the chip under test among multiple test stations on the sorting machine, improving packaging and testing capacity and product yield. Moreover, it avoids the problems of chip damage and test data incompatibility caused by transferring chips between different sorting machines, and can meet the needs of high-precision and high-efficiency packaging and testing.

[0057] In some optional implementations, in response to the completion of testing of the chip under test at the test site, the test data of the chip under test at the test site can be stored in a local database and uploaded to the Manufacturing Execution System (MES).

[0058] In this implementation, by uploading the test data of the chip under test at each available test site to the MES, it is helpful to trace the chip test information, realize the accurate source of the problem of defective chips, facilitate process optimization, and reduce the false negative rate.

[0059] Figure 3 This is a flowchart illustrating step 203 of the chip sorting and testing method disclosed herein. Figure 3 As shown above, in the above Figure 2 Based on the illustrated embodiment, the specific implementation process of step 203 may include the following steps 231 to 233. Each step is described below.

[0060] In step 231, the usage status of the next test site to be used is determined.

[0061] In this embodiment, the usage status of test sites whose test sequence follows test site 1 can be determined by a robotic arm; alternatively, the usage status of test sites can be queried through a site status record file.

[0062] The site status log file can record the usage status of each test site. During the chip testing process, the usage status of the test site can be updated in real time when the chip to be tested is placed on the test site and when the chip is removed from the test site.

[0063] Furthermore, in response to the next standby test site being unoccupied by the chip, step 232 is executed; in response to the next standby test site being occupied by the chip, step 233 is executed.

[0064] In step 232, in response to the fact that the next standby test station is not occupied by a chip, the robot arm is controlled to move the chip under test to the next standby test station, and the next standby test station is controlled to test the chip under test.

[0065] In this embodiment, when it is determined that the next test station is not occupied by a chip, the robotic arm can be directly controlled to pick up the chip under test from the current test station and move it to the next test station, and the next test station can be controlled to test the chip under test.

[0066] In step 233, in response to the next standby test station being occupied by a chip, the robot arm is controlled to move the chip under test to the next standby test station after the chip at the next standby test station is removed, and the next standby test station is controlled to test the chip under test.

[0067] In this embodiment, when it is determined that the next standby test station is occupied by a chip, it can be determined that the next standby test station is performing tests on other chips under test. At this time, the usage status of the next standby test station can be determined again after a set time. If the usage status of the next standby test station changes to not being occupied by a chip, the robotic arm can be controlled to pick up the chip under test from the current standby test station and move it to the next standby test station, and the next standby test station can be controlled to test the chip under test.

[0068] Based on the embodiments of this disclosure, continuous serial testing and test site configuration between multiple test sites on the sorting machine for the chip under test are realized, thereby improving the packaging and testing capacity.

[0069] Figure 4 This is a flowchart illustrating step 202 of the chip sorting and testing method disclosed herein. Figure 4 As shown above, in the above Figure 2 Based on the illustrated embodiment, when the sorting machine starts running, the specific implementation process of step 202 may include the following steps 221 to 223. Each step is described below.

[0070] In step 221, the usage status of the test site is determined.

[0071] The specific method for determining the usage status of the test site in step 221 can be found in [link to relevant documentation]. Figure 2 The description of step 201 in the illustrated embodiment will not be repeated here to save space.

[0072] In step 222, in response to the test site being unoccupied by the chip, the test site with the initial configuration number is identified as the test site to be used.

[0073] In this embodiment, when the sorting machine starts running, if all test stations are in an unoccupied state, the test station with the initial configuration number can be directly identified as the test station to be used.

[0074] The initial number is used to identify the test item to be performed by the test station as the first test. When the sorting machine starts running, the test station with the initial number can be obtained from the site configuration file as the test station to be used to perform the first test on the chip under test.

[0075] In step 223, in response to the test station being occupied by a chip, the control robot removes the chip from the test station occupied by the chip or generates a prompt message to prompt the tester to remove the chip from the test station occupied by the chip, and determines the test station with the configuration number of the initial number as the test station to be used.

[0076] In this embodiment, when the sorting machine starts running, if any test station is occupied by a chip, the robotic arm can pick up the chip from the test station and move it to the receiving area; or a prompt message can be generated to remind the tester to verify whether the chip in the test station should be placed in the qualified area or the unqualified area in the receiving area, and then move the chip.

[0077] Based on the embodiments of this disclosure, when the sorting machine starts running, the test station with the initial number is used as the standby test station, which can significantly reduce the computational overhead of system scheduling and improve the response speed of the test process. When the test station is occupied, the chip is automatically removed by the robotic arm or the station is released by manual prompting. This can be adapted to fully automated mass production test lines, and the station can also be released by manual prompting in special scenarios such as robotic arm failure, thus improving the scenario adaptability of the solution.

[0078] Figure 5 This is a schematic flowchart illustrating another embodiment of the chip sorting and testing method disclosed herein. Figure 5 As shown, during the testing of the chip under test, the usage status of the upstream test station can also be determined, and based on the usage status, it can be determined whether other chips under test should be tested. This includes the following steps 501 to 503. Each step is explained below.

[0079] In step 501, it is determined whether the test site to be used has a preceding test site.

[0080] Among them, the front-end test site refers to the test site whose test sequence is before the test site to be used.

[0081] For example, if the test site to be used is site number 4, and the test timing is the fourth test site, then the preceding test sites of the test site to be used can be test sites with test timings of the third, second, and first. If the test site to be used is the test site with the first test timing, then there is no preceding test site.

[0082] In step 502, in response to the fact that the test site to be used has a front-end test site, the usage status of the front-end test site of the test site to be used is determined.

[0083] In this embodiment, the specific process for determining the usage status of the upstream test site can be found in [reference needed]. Figure 2 The description of step 202 in the illustrated embodiment will not be repeated here.

[0084] When determining the usage status of the front-end test station, you can first determine the usage status of the front-end test station adjacent to the test station to be used. If it is not occupied by the chip, you can then obtain the usage status of the front-end test station with a higher test timing.

[0085] In step 503, in response to the fact that the usage status of the front-end test station is not occupied by a chip, the target chip to be tested using the front-end test station is obtained, and the robot arm is controlled to move the target chip to the front-end test station for testing.

[0086] For example, if the test station to be used is test station number 4, then the usage status of test station with test timing number 3 can be determined. If it is not occupied by a chip, it can take material from test station with test timing number 2. If test station with test timing number 2 has no material (not occupied by a chip), it can take material from test station with test timing number 1. If test station with test timing number 1 has no material (not occupied by a chip), it can take material from the feed tray.

[0087] Based on the embodiments disclosed herein, by running multiple test sites simultaneously, the test linkage processing of multiple chips under test can be completed, with no test site resources idle, further improving test efficiency.

[0088] Exemplary device Figure 6 This is a structural diagram of one embodiment of the chip sorting and testing apparatus of this disclosure. The chip sorting and testing apparatus can be applied to a sorting machine, such as... Figure 6 As shown, the chip sorting and testing apparatus may include: The first determining module 61 is used to determine the usage status and configuration information of the test site; The second determining module 62 is used to determine the test site to be used for the chip under test based on the usage status and configuration information of the test site. Test module 63 is used to control the robotic arm to place the chip under test into the test station for testing; The first moving module 64 is used to respond to the chip under test completing the test at the test site and the test result and / or test progress indicating that the chip under test needs to be moved to the next test site for testing, and iteratively executes the operation of controlling the robot to move the chip under test to the next test site for testing, until the test result and / or test progress indicate that the chip under test no longer needs to be tested.

[0089] Figure 7 This is a structural diagram of another embodiment of the chip sorting and testing apparatus of this disclosure. Figure 7 As shown above, in the above Figure 6 Based on the illustrated embodiment, in some optional embodiments, the chip sorting and testing apparatus may further include: The second moving module 65 is used to control the robot to move the chip under test to the non-conforming area in the receiving area in response to the test result and / or test progress indicating that the chip under test does not need to be tested again and the test result indicates that the test failed. The third moving module 66 is used to control the robot to move the chip under test to the qualified area in the receiving area in response to the test result and / or test progress indicating that the chip under test no longer needs to be tested, and the test result indicating that the test is passed and the test progress indicating that the test is completed.

[0090] In some alternative implementations, test module 63 may include: The first determination submodule 631 is used to determine the usage status of the next test site to be used; The first test submodule 632 is used to control the robot arm to move the chip under test to the next test station in response to the next test station being unoccupied by the chip, and to control the next test station to test the chip under test. The second test submodule 633 is used to respond to the usage status of the next standby test station being occupied by a chip, control the robot arm to move the chip under test to the next standby test station after the chip at the next standby test station is removed, and control the next standby test station to test the chip under test.

[0091] In some alternative implementations, when the sorting machine starts running, the first determining module 61 may include: The first acquisition submodule 611 is used to acquire the usage status of the test site through a robotic arm; The second acquisition submodule 612 is used to obtain the configuration information of the test site from the site configuration file. The configuration information includes the configuration number and the test item.

[0092] In some alternative implementations, the second determining module 62 may include: The second determining submodule 621 is used to determine the test station with the initial configuration number as the test station to be used in response to the test station's usage status being unoccupied by the chip. The third determining submodule 622 is used to respond to the usage status of the test station being occupied by a chip, control the robot to remove the chip in the test station occupied by the chip or generate a prompt message to prompt the tester to remove the chip in the test station occupied by the chip, and determine the test station with the configuration number as the initial number as the standby test station.

[0093] In some optional implementations, the chip sorting and testing apparatus may further include: an update module 67, used to control the robot arm to place the chip under test into the test station for testing, and then update the usage status of the test station in the station status record file to be occupied by a chip; and to control the robot arm to move the chip under test to the next test station for testing, and then update the usage status of the test station in the station status record file to be unoccupied by a chip.

[0094] In some optional implementations, the chip sorting and testing apparatus may further include: a third determining module 68, used to determine the usage status of the preceding test station of the test station in response to the test station having a preceding test station during the testing process of the chip to be tested; The test module 63 is used to respond to the usage status of the front-end test station being unoccupied by a chip, obtain the target chip to be tested using the front-end test station, and control the robot arm to move the target chip to the front-end test station for testing.

[0095] In some optional implementations, the chip sorting and testing apparatus may further include: a storage module 69, used to store the test data of the chip under test at the test site in a local database, and upload the test data of the chip under test at the test site to the manufacturing execution system.

[0096] The modules and units in this device can be further divided into finer-grained units according to actual needs, and the specific configuration can be set according to actual requirements.

[0097] The apparatus of this disclosure can be used to implement the methods of the above embodiments of this disclosure. The two correspond to each other in specific implementation, and the specific implementation of related parts can be referred to each other, which will not be repeated here.

[0098] Exemplary electronic devices, computer program products, and computer-readable storage media This disclosure also provides a system including a sorting machine and at least one test station for cascade testing; the sorting machine is used to determine the usage status and configuration information of the test station; based on the usage status and configuration information of the test station, a candidate test station for the chip under test is determined; a robotic arm is controlled to place the chip under test into the candidate test station for testing; in response to the chip under test completing the test at the candidate test station, and the test result and / or test progress indicating that the chip under test needs to be moved to the next candidate test station for testing, the operation of controlling the robotic arm to move the chip under test to the next candidate test station for testing is iteratively executed until the test result and / or test progress indicating that the chip under test no longer needs to be tested.

[0099] This disclosure also provides an electronic device, including: a memory for storing a computer program; and a processor for executing the computer program stored in the memory, wherein when the computer program is executed, it implements the chip sorting and testing method of any of the above embodiments of this disclosure.

[0100] Below, for reference Figure 8 This describes an electronic device according to embodiments of the present disclosure, wherein apparatus for implementing methods according to embodiments of the present disclosure may be integrated. Figure 8 This is a structural diagram of an electronic device provided in an illustrative embodiment of the present disclosure, such as... Figure 8 As shown, the electronic device includes one or more processors 11, one or more memory 12 of computer-readable storage media, and a computer program stored in the memory and executable on the processor. When the program in the memory 12 is executed, the chip sorting test method described above can be implemented.

[0101] Specifically, in practical applications, the electronic device may also include components such as an input device 13 and an output device 14, which are interconnected via a bus system and / or other forms of connection mechanisms (not shown). Those skilled in the art will understand that... Figure 8 The structure of the electronic device shown does not constitute a limitation on the electronic device and may include more or fewer components than shown, or certain components, or different component arrangements. Wherein: The processor 11 may be a central processing unit (CPU) or other form of processing unit with chip sorting and / or instruction execution capabilities. It performs various functions and processes data by running or executing software programs and / or modules stored in the memory 12 and calling data stored in the memory 12, thereby providing overall monitoring of the electronic device.

[0102] The memory 12 can store one or more computer program products. The memory can include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. The volatile memory may include, for example, random access memory (RAM) and / or cache memory. The non-volatile memory may include, for example, read-only memory (ROM), hard disk, flash memory, etc. One or more computer program products can be stored on the computer-readable storage medium, and the processor 11 can run the computer program products to implement the chip sorting and testing methods of the various embodiments of this disclosure described above, and / or other desired functions.

[0103] The input device 13 can be used to receive input numerical or character information. The input device 13 may include a keyboard, mouse, joystick, etc., related to user settings and function control.

[0104] The output device 14 can output various information to the outside, including determined distance information, direction information, etc. The output device 14 may include, for example, a display, a speaker, a printer, and a communication network and its connected remote output devices, etc.

[0105] The electronic device may also include a power supply for powering various components, which can be logically connected to the processor 11 through a power management system, thereby enabling functions such as charging, discharging, and power consumption management through the power management system. The power supply may also include one or more DC or AC power supplies, recharging systems, power fault detection circuits, power converters or inverters, power status indicators, and any other components.

[0106] Of course, for the sake of simplicity, Figure 8 Only some of the components of the electronic device relevant to this disclosure are shown, omitting components such as buses, input / output interfaces, etc. In addition, the electronic device may include any other suitable components depending on the specific application.

[0107] In addition to the methods and apparatus described above, embodiments of this disclosure may also be computer program products comprising computer program instructions that, when executed by a processor, cause the processor to perform the steps in the methods for determining wafer yield according to various embodiments of this disclosure as described in the "Exemplary Methods" section of this specification.

[0108] Computer program products can be written in any combination of one or more programming languages ​​to perform the operations of embodiments of this disclosure. The programming languages ​​include object-oriented programming languages ​​such as Java and C++, as well as conventional procedural programming languages ​​such as C or similar languages. The program code can be executed entirely on a user's computing device, partially on a user's computing device, as a standalone software package, partially on a user's computing device and partially on a remote computing device, or entirely on a remote computing device or server.

[0109] Furthermore, embodiments of this disclosure may also be computer-readable storage media storing computer program instructions thereon, which, when executed by a processor, cause the processor to perform the steps in the methods for determining wafer yield according to various embodiments of this disclosure as described in the "Exemplary Methods" section above.

[0110] Computer-readable storage media may take the form of any combination of one or more readable media. A readable medium may be a readable signal medium or a readable storage medium. A readable storage medium may, for example, include, but is not limited to, electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatuses, or devices, or any combination thereof. More specific examples of readable storage media (a non-exhaustive list) include: electrical connections having one or more wires, portable disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof.

[0111] The basic principles of this disclosure have been described above with reference to specific embodiments. However, it should be noted that the advantages, benefits, and effects mentioned in this disclosure are merely examples and not limitations. These advantages, benefits, and effects should not be considered as essential features of each embodiment of this disclosure.

[0112] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For system embodiments, since they largely correspond to method embodiments, the description is relatively simple; relevant parts can be referred to the descriptions in the method embodiments.

[0113] Those skilled in the art will understand that all or part of the steps of the above method embodiments can be implemented by hardware related to program instructions. The aforementioned program can be stored in a computer-readable storage medium. When the program is executed, it performs the steps of the above method embodiments. The aforementioned storage medium includes various media that can store program code, such as ROM, RAM, magnetic disk, or optical disk.

[0114] The methods and apparatus of this disclosure may be implemented in many ways. For example, they may be implemented by software, hardware, firmware, or any combination of software, hardware, and firmware. The above-described order of steps for the method is for illustrative purposes only, and the steps of the method of this disclosure are not limited to the order specifically described above, unless otherwise specifically stated. Furthermore, in some embodiments, this disclosure may also be implemented as a program recorded on a recording medium, the program including machine-readable instructions for implementing the method according to this disclosure. Thus, this disclosure also covers recording media storing programs for performing the method according to this disclosure.

[0115] The description in this disclosure is provided for illustrative and descriptive purposes only and is not intended to be exhaustive or to limit the disclosure to its forms. Many modifications and variations will be apparent to those skilled in the art. The embodiments were chosen and described in order to better illustrate the principles and practical application of this disclosure and to enable those skilled in the art to understand this disclosure and to design various embodiments with various modifications suitable for a particular purpose.

Claims

1. A chip sorting and testing method, characterized in that, include: Determine the usage status and configuration information of the test site; Based on the usage status and configuration information of the test sites, the available test sites for the chip under test are determined. The robotic arm is controlled to place the chip under test into the test station for testing. In response to the chip under test completing the test at the available test site, and the test result and / or test progress of the chip under test indicating that the chip under test needs to be moved to the next available test site for testing, the operation of controlling the robot to move the chip under test to the next available test site for testing is iteratively executed until the test result and / or test progress of the chip under test indicate that the chip under test no longer needs to be tested.

2. The method according to claim 1, characterized in that, In response to the test results and / or test progress indicating that the chip under test no longer needs to be tested, the method further includes: In response to the test result indicating that the test failed, the robot arm is controlled to move the chip under test to the non-conforming area in the receiving area; In response to the test result indicating that the test has passed and the test progress indicating that the test has been completed, the robot arm is controlled to move the chip under test to the qualified area in the receiving area.

3. The method according to any one of claims 1-2, characterized in that, The step of controlling the robotic arm to move the chip under test to the next available test station for testing includes: Determine the usage status of the next available test site; In response to the fact that the next standby test station is not occupied by a chip, the robot arm is controlled to move the chip under test to the next standby test station, and the next standby test station is controlled to test the chip under test. In response to the fact that the next standby test station is occupied by a chip, the robot arm is controlled to move the chip under test to the next standby test station after the chip at the next standby test station is removed, and the next standby test station is controlled to test the chip under test.

4. The method according to claim 1, characterized in that, When the sorting machine starts running, determining the usage status and configuration information of the test site includes: The robotic arm is used to obtain the usage status of the test site. The configuration information of the test site is obtained from the site configuration file. The configuration information includes the configuration number and the test item.

5. The method according to claim 4, characterized in that, The step of determining the available test sites for the chip under test based on the usage status and configuration information of the test sites includes: In response to the fact that the usage status of the test site is not occupied by the chip, the test site with the initial configuration number is determined as the test site to be used. In response to the test station being occupied by a chip, the robot arm is controlled to remove the chip from the test station occupied by the chip or to generate a prompt message to remind the tester to remove the chip from the test station occupied by the chip, and the test station with the initial configuration number is identified as the standby test station.

6. The method according to claim 1, characterized in that, After the control robot places the chip under test into the test station for testing, the method further includes: updating the usage status of the test station to be occupied by the chip in the station status record file; After controlling the robotic arm to move the chip under test to the next available test station for testing, the method further includes: updating the usage status of the available test station to be unoccupied by a chip in the station status record file.

7. The method according to claim 6, characterized in that, Also includes: During the testing of the chip under test, in response to the fact that the test site to be used has a front-end test site, the usage status of the front-end test site of the test site to be used is determined. In response to the fact that the front-end test station is not occupied by a chip, the target chip to be tested using the front-end test station is obtained, and the robot arm is controlled to move the target chip to the front-end test station for testing.

8. The method according to claim 1, characterized in that, In response to the completion of testing of the chip under test at the test site, the method further includes: The test data of the chip under test at the test site is stored in the local database, and the test data of the chip under test at the test site is uploaded to the manufacturing execution system.

9. A chip sorting and testing apparatus, characterized in that, include: The first determination module is used to determine the usage status and configuration information of the test site; The second determining module is used to determine the test site to be used for the chip under test based on the usage status and configuration information of the test site. The testing module is used to control the robotic arm to place the chip under test into the test station for testing; The first moving module is configured to, in response to the chip under test completing the test at the designated test site and the test result and / or test progress indicating that the chip under test needs to be moved to the next designated test site for testing, iteratively execute the operation of controlling the robotic arm to move the chip under test to the next designated test site for testing, until the test result and / or test progress indicating that the chip under test no longer needs to be tested.

10. A chip sorting and testing system, characterized in that, The system includes a sorting machine and at least one test station for cascade testing; The sorting machine is used to determine the usage status and configuration information of the test stations; based on the usage status and configuration information of the test stations, it determines the available test stations for the chip under test; it controls the robotic arm to place the chip under test into the available test station for testing; in response to the chip under test completing the test at the available test station, and the test result and / or test progress indicating that the chip under test needs to be moved to the next available test station for testing, iteratively executes the operation of controlling the robotic arm to move the chip under test to the next available test station for testing, until the test result and / or test progress indicating that the chip under test no longer needs to be tested.

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