Screening method, screening device, electronic device, storage medium, and program product

Abstract

The present disclosure provides a screening method, a screening device, an electronic device, a storage medium and a program product, relating to the technical field of semiconductor technology. The chip reliability screening method comprises: dividing a wafer into a plurality of screening regions; evaluating the early death risk of the plurality of screening regions based on the quality monitoring data of the wafer, to divide the plurality of screening regions into different early death risk levels based on the evaluation results; setting corresponding reliability test conditions for the screening regions based on the early death risk levels, wherein the reliability test conditions include stress test parameters, and the early death risk level is positively correlated with the stress test parameters; and performing excitation test on the chips in the screening regions based on the reliability test conditions, to screen the chips excited to early death defects based on the test results. Through the technical scheme of the present disclosure, corresponding reliability test conditions are set for different regions to realize targeted excitation test on the chips.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a chip reliability screening method, a chip reliability screening device, an electronic device, a computer-readable storage medium, and a computer program product. Background Technology

[0002] For integrated circuit chips, burn-in (BI) testing is needed to accelerate the screening of chips that fail prematurely due to potential defects, in order to ensure chip quality and reliability. However, the current burn-in testing scheme sets only fixed and unique test conditions for a fixed chip / product. Since the defect levels and yield levels of different areas in the wafer are not consistent, the test can easily cause understress or overstress to the chip on the wafer. Understress cannot effectively stimulate premature failure defects in the chip, while overstress has an adverse effect on the reliability of the chip, thus affecting the test results.

[0003] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0004] The purpose of this disclosure is to provide a chip reliability screening method, screening device, electronic device, storage medium, and program product, which at least to some extent overcomes the problem of poor performance of chip aging tests in related technologies.

[0005] Other features and advantages of this disclosure will become apparent from the following detailed description, or may be learned in part from practice of this disclosure.

[0006] According to one aspect of this disclosure, a chip reliability screening method is provided, comprising: dividing a wafer into multiple screening regions; assessing the premature failure risk of the multiple screening regions based on quality monitoring data of the wafer, and classifying the multiple screening regions into different premature failure risk levels based on the assessment results; setting corresponding reliability test conditions for the screening regions based on the premature failure risk levels, wherein the reliability test conditions include stress test parameters, and the premature failure risk level is positively correlated with the stress test parameters; and performing excitation tests on chips in the screening regions based on the reliability test conditions, and screening chips that exhibit premature failure defects based on the test results.

[0007] In one embodiment of this disclosure, dividing a wafer into multiple screening regions includes: dividing the circumference of the wafer into multiple sector-shaped screening regions based on a set angular interval, with the center of the wafer as the dividing center; or dividing the wafer into a concentric circular screening region and multiple annular screening regions based on a configured successively increasing radius, with the center of the wafer as the dividing center; or dividing the wafer into multiple screening regions based on a grid; or dividing the wafer into multiple screening regions based on the detected defect distribution.

[0008] In one embodiment of this disclosure, the wafer quality monitoring data includes at least one of the following: defect detection data during the wafer manufacturing process, key process parameters, wafer acceptance test data, and CP test yield.

[0009] In one embodiment of this disclosure, the premature failure risk of the plurality of screening regions is assessed based on the wafer quality monitoring data, and the plurality of screening regions are divided into different premature failure risk levels based on the assessment results. This includes: assessing the premature failure risk of each screening region based on the defect detection data, the key process parameters, the wafer acceptance test data, and the CP test yield, to obtain a risk assessment value for each screening region; determining the risk level interval to which the risk assessment value belongs, and determining the premature failure risk level of the screening region based on the risk level interval to which it belongs.

[0010] In one embodiment of this disclosure, a premature failure risk assessment is performed on the defect detection data, key process parameters, wafer acceptance test data, and CP test yield of each screening region to obtain a risk assessment value for each screening region. This includes: for each screening region, determining the defect type and corresponding defect quantity and size based on the defect detection data; for each defect type, determining a defect score based on the defect type weight, the defect quantity, and the defect size; obtaining a defect assessment value based on the defect scores of multiple defect types; calculating the deviation between the key process parameters and the target process parameters to obtain a process control assessment value based on the deviation; determining the difference between the electrical performance parameters and design parameters of the devices within the screening region based on the wafer acceptance test data to obtain a performance assessment value based on the difference; and normalizing the defect assessment value, the process control assessment value, the performance assessment value, and the CP test yield to obtain the risk assessment value.

[0011] In one embodiment of this disclosure, the reliability test includes a high voltage stress test, wherein the stress test parameters include a first voltage value of dynamic voltage stress and a second voltage value of enhanced voltage stress applied within a stress cycle, a first duration of dynamic voltage stress and a second duration of enhanced voltage stress within the stress cycle, and the number of stress cycles.

[0012] In one embodiment of this disclosure, based on the pre-death risk level, corresponding reliability test conditions are set for the screening region, including: determining matching stress test parameters based on the pre-death risk level of the screening region, and alternately applying dynamic voltage stress and enhanced voltage stress based on the matching stress test parameters; and configuring at least one local test mode in the screening region that matches the pre-death risk level as the test condition, wherein the at least one local test mode operates when the dynamic voltage stress and / or the enhanced voltage stress are applied to the screening region, and the execution type of the local test mode is positively correlated with the pre-death risk level, wherein the local test mode is determined based on at least one type of test mode executed in at least one circuit characteristic region in the chip.

[0013] In one embodiment of this disclosure, the circuit characteristic region includes a digital region, an analog region, and a storage region. The local test mode includes a static power current test mode, a functional test mode, and a scan test mode performed by the digital region; the local test mode also includes the static power current test mode and the functional test mode performed by the analog region; and the local test mode also includes the static power current test mode, the functional test mode, and the memory built-in self-test mode performed by the storage region.

[0014] In one embodiment of this disclosure, based on the premature death risk level, corresponding reliability test conditions are set for the screening area, and the method further includes: based on the premature death risk level, determining the proportion of the chips in the screening area that execute the local test mode as the stress test parameter, wherein the proportion is positively correlated with the premature death risk level.

[0015] In one embodiment of this disclosure, the premature death risk level is positively correlated with the stress test parameters, including: the increment of the first voltage value corresponding to two adjacent premature death risk levels is a first fixed value or a variable, and the increment of the corresponding second voltage value is a second fixed value or a variable; the increment of the first duration corresponding to two adjacent premature death risk levels is a third fixed value or a variable, and the increment of the corresponding second duration is a fourth fixed value or a variable; the increment of the proportion corresponding to two adjacent premature death risk levels is a fifth fixed value or a variable.

[0016] In one embodiment of this disclosure, the maximum voltage values ​​of both the dynamic voltage stress and the enhanced voltage stress are less than the maximum operating voltage of the chip.

[0017] In one embodiment of this disclosure, performing excitation testing on the chip in the screening area based on the reliability test conditions includes: transmitting the reliability test conditions to a wafer testing machine, so that the wafer testing machine performs excitation testing on the screening area based on the corresponding reliability test conditions, and obtaining the test result.

[0018] According to one aspect of this disclosure, a chip reliability screening apparatus is provided, comprising: a division module for dividing a wafer into multiple screening regions; an evaluation module for evaluating the premature failure risk of the multiple screening regions based on quality monitoring data of the wafer, so as to classify the multiple screening regions into different premature failure risk levels based on the evaluation results; a setting module for setting corresponding reliability test conditions for the screening regions based on the premature failure risk levels, wherein the reliability test conditions include stress test parameters, and the premature failure risk level is positively correlated with the stress test parameters; and a screening module for performing excitation tests on chips in the screening regions based on the reliability test conditions, so as to screen chips that exhibit premature failure defects based on the test results.

[0019] According to another aspect of this disclosure, an electronic device is provided, comprising: a processor; and a memory for storing executable instructions of the processor; the processor being configured to perform the chip reliability screening method of the first aspect described above by executing the executable instructions.

[0020] According to another aspect of this disclosure, a computer-readable storage medium is provided having a computer program stored thereon, which, when executed by a processor, implements the chip reliability screening method described above.

[0021] According to another aspect of this disclosure, a computer program product is provided, on which a computer program is stored, which, when executed by a processor, implements the above-described chip reliability screening method.

[0022] The chip reliability screening scheme provided in the embodiments of this disclosure divides the wafer into multiple screening areas, assesses the premature failure risk of each area based on quality monitoring data and classifies them into levels, and sets corresponding reliability test conditions for different areas according to the positive correlation between premature failure risk level and stress test parameters, so as to achieve targeted excitation testing of the chip, which can reduce the probability of the chip generating under stress or over stress, prevent over-testing of low-risk areas and under-testing of high-risk areas under uniform test conditions, thereby improving the test effect and improving the test accuracy of chip premature failure defects.

[0023] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0024] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0025] Figure 1 A flowchart illustrating a chip reliability screening method according to an embodiment of this disclosure is shown.

[0026] Figure 2 A flowchart illustrating another chip reliability screening method in an embodiment of this disclosure is shown.

[0027] Figure 3 This diagram illustrates a method of partitioning a wafer according to an embodiment of the present disclosure.

[0028] Figure 4 This diagram illustrates another method of partitioning a wafer according to an embodiment of the present disclosure;

[0029] Figure 5 This diagram illustrates the detection results of another wafer defect detection embodiment of the present disclosure;

[0030] Figure 6 This diagram illustrates the detection results of another wafer defect detection embodiment of the present disclosure;

[0031] Figure 7 A flowchart illustrating another chip reliability screening method in an embodiment of this disclosure is shown.

[0032] Figure 8 A graph showing an applied stress voltage according to an embodiment of this disclosure is provided.

[0033] Figure 9 A flowchart illustrating yet another chip reliability screening method according to an embodiment of this disclosure is shown;

[0034] Figure 10 This diagram illustrates a chip reliability screening device according to an embodiment of the present disclosure.

[0035] Figure 11 A structural block diagram of an electronic device according to an embodiment of the present disclosure is shown. Detailed Implementation

[0036] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, they are provided so that this disclosure will be more comprehensive and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0037] Furthermore, the accompanying drawings are merely illustrative of this disclosure and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and therefore repeated descriptions of them will be omitted. Some block diagrams shown in the drawings are functional entities and do not necessarily correspond to physically or logically independent entities. These functional entities may be implemented in software, in one or more hardware modules or integrated circuits, or in different network and / or processor devices and / or microcontroller devices.

[0038] like Figure 1 As shown, a chip reliability screening method according to an embodiment of this disclosure includes:

[0039] Step S102: Wafer fabrication is complete (Wafer Fab-out).

[0040] Step S104, Wafer Acceptance Test (WAT).

[0041] Step S106: Chip Probe (CP) and High Voltage Stress Test (HVST).

[0042] Step S108: Assemble AOL (Assembly On Line).

[0043] Step S110, Final test.

[0044] In this embodiment, although WL (wafer level) HVST (high voltage stress) is used to replace the traditional Package burn-in, bringing BI stress forward to the CP stage of WL, higher stress voltage and temperature can be achieved in the wafer stage, and the time can be shortened to minutes or even seconds, eliminating the need for long oven baking and significantly reducing BI costs, the currently used wafer level HVST (Wafer level High Voltage Stress Test) only sets fixed and unique HVST conditions for a fixed chip / product, which cannot effectively cover the differences in process technology, defect level, and yield level between different wafers.

[0045] To address at least one of the aforementioned issues, a chip reliability screening scheme is proposed in this disclosure.

[0046] To facilitate understanding, the following is an explanation of several terms used in this application.

[0047] Defects inspection: This involves using inspection techniques to identify and locate physical defects on and inside a wafer. These defects include particulate contamination, scratches, voids, etc., which can be potential sources of chip failure.

[0048] Process inline SPC: In each process stage of wafer manufacturing, a series of process parameters are monitored in real time, such as the exposure dose of photolithography, the etching rate, and the thickness of thin film deposition. SPC (Statistical Process Control) technology is used to analyze the stability and variation trend of these parameters. If a certain process parameter exceeds the normal fluctuation range, it may indicate that there is a problem with the chip manufacturing quality in that area.

[0049] WAT data (Wafer Acceptance Test Data): WAT testing refers to a series of tests performed after wafer manufacturing is completed and before chip packaging, used to evaluate the electrical performance of basic components on the wafer (such as transistors, resistors, capacitors, etc.).

[0050] CP testing: CP testing is an electrical performance test performed on each chip on a wafer to determine whether the chip meets the design specifications.

[0051] IDDQ (Quiet Current) test pattern: This refers to designing a series of specific input stimuli to bring the circuit into various stable logic states, and monitoring the IDDQ in these states. If the detected IDDQ exceeds the normal range, it can be determined that there is a fault in the circuit.

[0052] Function test pattern: This refers to generating a series of input signals that cover all possible input conditions of the circuit. By observing whether the circuit's output matches the expected functional result, it is possible to verify whether the circuit can work normally according to the design requirements.

[0053] mbist test (Memory Built-in Self-Test) pattern: Based on a specific algorithm, read and write operations are performed on the storage cells in the memory to detect whether there are any faults in the storage cells.

[0054] Scan test pattern: The scan chain can be used to move test data into the flip-flops, change the state of the flip-flops, and thus affect the input of the combinational logic circuit. The output of the combinational logic circuit is fed back to the flip-flops, and the result is shifted out through the scan chain and compared with the expected value to detect logic faults inside the digital circuit.

[0055] like Figure 2 As shown, a chip reliability screening method according to an embodiment of this disclosure includes:

[0056] Step S202: Divide the wafer into multiple screening areas.

[0057] In some embodiments, the wafer is divided into multiple regions according to certain rules, and each region contains a certain number of chips to facilitate subsequent targeted evaluation, testing and screening of the chips. The screening region realizes the partition management of chips on the wafer.

[0058] Step S204: Based on wafer quality monitoring data, assess the premature failure risk of multiple screening areas, and classify the multiple screening areas into different premature failure risk levels based on the assessment results.

[0059] In some embodiments, wafer quality monitoring data includes at least one of the following: defect inspection data during wafer manufacturing, process inline spc (SPC) data, wafer acceptance test data (WAT) data, and CP test yield.

[0060] In some embodiments, premature failure risk assessment refers to analyzing and judging the possibility of premature failure of chips in the screening area during use based on wafer quality monitoring data, and the resulting premature failure risk level is used to reflect the risk status of each screening area.

[0061] Step S206: Based on the premature death risk level, set corresponding reliability test conditions for the screening area. The reliability test conditions include stress test parameters, and the premature death risk level is positively correlated with the stress test parameters.

[0062] In some embodiments, reliability testing conditions refer to specific parameters and environmental requirements for conducting reliability testing that match the premature death risk level of the screening area.

[0063] In some embodiments, stress test parameters include stress voltage and stress time applied to the chip.

[0064] The positive correlation between the premature death risk level and stress test parameters can be understood as follows: for screening areas with a higher premature death risk, stronger stress needs to be applied for testing in order to more effectively stimulate the possible premature death defects; while for screening areas with a lower premature death risk, relatively weaker stress can be applied for testing.

[0065] Step S208: Perform excitation tests on the chips in the screening area based on reliability test conditions, so as to screen chips that exhibit premature failure defects based on the test results.

[0066] In some embodiments, excitation testing refers to performing testing operations on chips in the screening area under set reliability test conditions to determine whether they have premature defects.

[0067] In this embodiment, by dividing the wafer into multiple screening areas, assessing the premature failure risk of each area based on quality monitoring data and classifying them into levels, and setting corresponding reliability test conditions for different areas according to the positive correlation between premature failure risk level and stress test parameters, targeted excitation testing of the chip can be achieved. This can reduce the probability of the chip experiencing understress or overstress, prevent overtesting of low-risk areas and undertesting of high-risk areas under uniform test conditions, thereby improving test results and enhancing the test accuracy of premature failure defects in the chip.

[0068] In one embodiment of this disclosure, one way to divide a wafer into multiple screening regions includes: dividing the circumference of the wafer based on a set angular interval, with the center of the wafer as the dividing center, to obtain multiple fan-shaped screening regions.

[0069] like Figure 3 As shown, the circumference of the wafer is divided based on a set angular interval to obtain 8 sector-shaped screening areas.

[0070] In this embodiment, because the sector area is divided in detail, targeted analysis can be performed on chips at different angles and positions, thereby improving detection accuracy.

[0071] In one embodiment of this disclosure, one method of dividing a wafer into multiple screening regions includes: using the center of the wafer as the dividing center, dividing the wafer into a concentric circular screening region and multiple annular screening regions based on a configured, successively increasing radius.

[0072] like Figure 4 As shown, the wafer is divided into a concentric circular screening region 1 and seven annular screening regions based on the successively increasing radii of the configuration.

[0073] In this embodiment, concentric circles and multiple annular screening areas are divided based on the center and successively increasing radii, which helps to discover performance differences at different locations from the center to the edge of the wafer.

[0074] In one embodiment of this disclosure, one way to divide a wafer into multiple screening regions includes: dividing the wafer based on a grid to obtain multiple screening regions.

[0075] In this embodiment, dividing the wafer based on a grid can achieve uniform and comprehensive coverage of the wafer surface.

[0076] In one embodiment of this disclosure, one way to divide a wafer into multiple screening regions includes: dividing the wafer based on the detected defect distribution to obtain multiple screening regions.

[0077] In this embodiment, dividing the wafer based on the detected defect distribution is more targeted. By focusing on monitoring areas with concentrated defects, the risk of premature chip failure in these areas can be analyzed more deeply.

[0078] In one embodiment of this disclosure, the premature failure risk of multiple screening regions is assessed based on wafer quality monitoring data, and the multiple screening regions are classified into different premature failure risk levels based on the assessment results, including:

[0079] Early failure risk assessments were performed on the defect detection data, key process parameters, wafer acceptance test data, and CP test yield of each screening area to obtain the risk assessment value for each screening area.

[0080] In some embodiments, based on the collected data, specific indicators for early failure risk assessment are determined. For example, the indicators for defect detection data can be defect density, the indicators for key process parameters can be the degree of deviation of key process parameters from standard values, the indicators for wafer acceptance test data can be the performance fluctuation range, and the indicators for CP test yield can be the yield level, etc.

[0081] In some embodiments, defect detection includes gate defects, contact defects, and first layer metal wiring (Metal1), and the distribution and proportion of these defect types vary in different screening areas on the wafer.

[0082] Figure 5 The test results for the full-pattern wafer are shown.

[0083] Figure 6 The distribution of CP test yield on the wafer is shown.

[0084] In some embodiments, for a single screening region, the corresponding weights of the above indicators are assigned based on the degree of impact on the risk of premature failure. Defect density may have a higher weight, while some relatively minor process parameters may have a relatively lower weight. Based on the indicators and their corresponding weights, the risk assessment value of each screening region can be determined.

[0085] Determine the risk level range to which the risk assessment value belongs, and then determine the premature death risk level of the screening area based on the risk level range to which it belongs.

[0086] In some embodiments, statistical parameters can be calculated based on historical assessment data. If the data shows a normal distribution, the risk level range can be divided with the mean as the center and the standard deviation as the standard deviation.

[0087] In some embodiments, based on data such as defects inspection, processinline SPC parameters, WAT data, and CP test yield obtained during wafer manufacturing, N different screening regions are divided into different early failure risk levels (1 to M), where 1 represents the lowest risk and the higher the number, the higher the risk. The early failure risk levels of different screening regions may be the same or different.

[0088] In this embodiment, by conducting early failure risk assessments on defect detection data, key process parameters, wafer acceptance test data, and CP test yield for each screening area, various factors affecting early chip failure can be comprehensively considered. This enables the mining and analysis of quality information at different levels of the wafer to calculate the risk assessment value for each screening area. Then, the risk level range to which the risk assessment value belongs is determined, and the early failure risk level is determined accordingly. This quantitative classification of early failure risk facilitates the subsequent configuration of different reliability test conditions based on different risk levels, thereby improving the targeting and effectiveness of testing.

[0089] like Figure 7 As shown, in one embodiment of this disclosure, a premature failure risk assessment is performed on the defect detection data, key process parameters, wafer acceptance test data, and CP test yield of each screening region to obtain a risk assessment value for each screening region, including:

[0090] Step S702: For each screening area, determine the defect type and corresponding defect quantity and defect size based on the defect detection data. For each defect type, determine the defect score based on the defect type weight, defect quantity and defect size. Based on the defect scores of multiple defect types, obtain the defect evaluation value.

[0091] In some embodiments, in terms of defect detection, the defect type, quantity, and size are determined based on defect detection data, and a defect score is calculated by combining the defect type weight, thereby obtaining a defect evaluation value, and realizing the assessment of the impact of different types of defects on the risk of premature chip failure.

[0092] Step S704: Calculate the deviation between the key process parameters and the target process parameters to obtain the process control evaluation value based on the deviation.

[0093] In some embodiments, by calculating the deviation between key process parameters and target process parameters, a process control evaluation value is obtained, thereby enabling the assessment of premature failure risk from the process level and timely detection of potential threats to chip quality from process fluctuations.

[0094] Step S706: Based on the wafer acceptance test data, determine the difference between the electrical performance parameters and design parameters of the devices in the screening area, so as to obtain a performance evaluation value based on the difference.

[0095] In some embodiments, the difference between the device's electrical performance parameters and design parameters is determined by accepting test data on the wafer, and a performance evaluation value is obtained to evaluate the chip quality from a performance perspective, ensuring that the chip performance meets the design requirements.

[0096] Step S708: Normalize the defect assessment value, process control assessment value, performance assessment value, and CP test yield to obtain the risk assessment value.

[0097] In this embodiment, based on defect detection data, the impact of different defects on the risk of premature chip failure can be quantified. By calculating the deviation between key process parameters and target values, process control evaluation values ​​are obtained, which can promptly identify potential risks caused by process fluctuations. Performance evaluation values ​​are obtained using wafer acceptance test data, and chip quality is controlled from the perspective of electrical performance. The above evaluation values ​​are normalized with the CP test yield to obtain risk evaluation values, effectively integrating multi-source data to comprehensively reflect the risk of premature failure in different screening areas.

[0098] In one embodiment of this disclosure, the reliability test includes a high voltage stress test, and the stress test parameters include a first voltage value of dynamic voltage stress and a second voltage value of enhanced voltage stress applied within a stress cycle, a first duration of dynamic voltage stress and a second duration of enhanced voltage stress within the stress cycle, and the number of stress cycles.

[0099] In some embodiments, in order to set different reliability test conditions for screening regions with different premature failure risk levels, it is necessary to first determine the corresponding reliability test item, namely high voltage stress test. According to the different premature failure risk levels, different wafer-level high voltage stress test (HVST) conditions are set for the chips in each wafer micro-region.

[0100] like Figure 8 As shown, the stress voltage includes DVS (Dynamic Voltage Stress) and EVS (Enhanced Voltage Stress). The stress test parameters include a first voltage value for dynamic voltage stress and a second voltage value for enhanced voltage stress. Within one stress cycle, a first duration is assigned to dynamic voltage stress and a second duration is assigned to enhanced voltage stress.

[0101] In some embodiments, reliability test conditions also include test patterns, namely the local test patterns described below.

[0102] In one embodiment of this disclosure, based on the premature death risk level, corresponding reliability test conditions are set for the screening area, including:

[0103] Based on the premature death risk level of the screening region, matching stress test parameters are determined, and dynamic voltage stress and enhanced voltage stress are applied alternately based on the matching stress test parameters; and at least one local test mode matching the premature death risk level of the chip in the screening region is configured as a test condition, wherein at least one local test mode is operated when dynamic voltage stress and / or enhanced voltage stress are applied to the screening region, and the execution type of the local test mode is positively correlated with the premature death risk level, wherein the local test mode is determined based on at least one type of test mode executed in at least one circuit characteristic region in the chip.

[0104] In some embodiments, the chip is composed of multiple circuit characteristic regions with different functions. Each region may have different functions and potential failure modes. Local test modes are determined based on at least one type of test mode performed in at least one circuit characteristic region in the chip. That is, targeted tests are performed for the characteristics of different regions to more accurately detect potential problems in each region of the chip and improve the accuracy and effectiveness of the test.

[0105] In some embodiments, configuring at least one local test mode in the screening area to match the chip's premature failure risk level includes: for screening areas with low risk levels, where the chip is less likely to have premature failure issues, fewer local test modes can be selected, for example, performing a static power current test mode only on the digital area, a functional test mode on the analog area, and a functional test mode on the memory area.

[0106] For medium-risk screening areas, the number of test modes can be increased. For example, in addition to the low-risk test modes, a scanning test mode for digital areas and a built-in self-test mode for memory in storage areas can be added.

[0107] For high-risk levels, all available local test modes can be executed to ensure comprehensive testing of all circuit characteristic areas and functions of the chip.

[0108] In this embodiment, stress testing mainly involves applying dynamic voltage stress and enhanced voltage stress to detect the overall reliability of the chip under different voltage conditions, while local testing mode is used to perform targeted functional tests on different circuit characteristic areas within the chip in order to more comprehensively test the chip.

[0109] In one embodiment of this disclosure, the circuit characteristic region includes a digital region, an analog region, and a storage region.

[0110] Local test modes include static power current test mode, functional test mode, and scan test mode performed in the digital area.

[0111] In some embodiments, performing static power current test mode, functional test mode and scan test mode on digital areas can detect digital circuits from multiple aspects such as current, function and logic structure, and promptly discover potential logic errors, leakage and other problems.

[0112] The local test modes also include static power current test mode and functional test mode performed in the simulated area.

[0113] In some embodiments, the analog area employs a static power supply current test mode and a functional test mode, which can effectively evaluate the current characteristics and signal processing functions of the analog circuit and ensure its normal operation.

[0114] Local test modes also include static power current test mode, functional test mode, and memory built-in self-test mode performed in the storage area.

[0115] In some embodiments, the storage area employs a static power current test mode, a functional test mode, and a built-in self-test mode to comprehensively test the storage function and data read / write accuracy of the memory.

[0116] In some embodiments, the local test mode includes IDDQ test patterns and function test patterns for digital regions, analog regions, and storage regions respectively, mbist test patterns for SRAM, scan test patterns for digital regions, etc., wherein one of the above test patterns can be selected for execution, or multiple test patterns can be selected for execution.

[0117] In this embodiment, by setting up specialized local test modes for different circuit characteristic areas (digital area, analog area, and memory area) of the chip, comprehensive and accurate testing of the chip is achieved. The differentiated test modes for different areas improve the pertinence and effectiveness of the test, and help to discover potential defects in various parts of the chip more comprehensively.

[0118] In one embodiment of this disclosure, based on the pre-death risk level, corresponding reliability test conditions are set for the screening area, and the method further includes: based on the pre-death risk level, determining the proportion of chips in the screening area that perform local test mode as stress test parameters, wherein the proportion is positively correlated with the pre-death risk level.

[0119] The chip ratio represents the coverage of the test pattern.

[0120] In some embodiments, based on the positive correlation between the risk level of premature death and the proportion of chips performing local testing mode, the proportion of chips corresponding to different risk levels is preset. A corresponding chip proportion can be set for different risk levels, and the higher the level, the larger the proportion value.

[0121] In this embodiment, by establishing a positive correlation between the early failure risk level and the proportion of chips performing local testing mode, the optimal allocation of testing resources is achieved. For screening areas with a low early failure risk level, the proportion of chips performing local testing mode is reduced, thereby reducing the testing workload and cost while ensuring a certain detection coverage. Conversely, for screening areas with a high early failure risk level, the proportion of chips performing local testing mode is increased, which can more comprehensively detect potential problematic chips and improve the accuracy and reliability of the test.

[0122] In one embodiment of this disclosure, the premature death risk level is positively correlated with stress test parameters, including: the increment of the first voltage value corresponding to two adjacent premature death risk levels is a first fixed value or a variable, and the increment of the corresponding second voltage value is a second fixed value or a variable; the increment of the first duration corresponding to two adjacent premature death risk levels is a third fixed value or a variable, and the increment of the corresponding second duration is a fourth fixed value or a variable; the increment of the proportion corresponding to two adjacent premature death risk levels is a fifth fixed value or a variable.

[0123] In some embodiments, Tables 1 and 2 show test schemes where the increment of the first voltage value is a first fixed value, the increment of the second voltage value is a second fixed value, the increment of the first duration is a third fixed value, or the increment of the second duration is a fourth fixed value.

[0124] Table 1

[0125] Risk level EVS voltage EVS time (ms) 1 1.2*vdd 1 2 1.2*vdd+50mV 1+0.1 3 1.2*vdd+100mV 1+0.2 n-1 1.2*vdd+50*(n-2)mV 1+0.1*(n-2) n 1.2*vdd+50*(n-1)mV 1+0.1*(n-1)

[0126] Table 2

[0127]

[0128]

[0129] In one embodiment of this disclosure, the maximum voltage values ​​of both dynamic voltage stress and enhanced voltage stress are less than the maximum operating voltage of the chip.

[0130] In some embodiments, the voltages of EVS(n) and DVS(n), 1.2*vdd+50*(n-1)mV, must not exceed the maximum operating voltage Vmax of the circuit / module / chip, otherwise it will cause hard breakdown of the chip.

[0131] In some embodiments, the maximum pattern coverage is 80% + (n-1)*2% ≤ 100%.

[0132] In one embodiment of this disclosure, stimulating a chip in a screening area based on reliability test conditions includes: transmitting the reliability test conditions to a wafer testing machine, so that the wafer testing machine can stimulate the screening area based on the corresponding reliability test conditions to obtain test results.

[0133] like Figure 9 As shown, a chip reliability screening scheme according to another embodiment of this disclosure includes:

[0134] Step S902: Divide the entire wafer into N different screening areas.

[0135] In some embodiments, the filtering regions are numbered 1, 2, ... N.

[0136] In some embodiments, the entire wafer is divided into several (N) different screening regions. The micro-regions can be divided by angle or by radius.

[0137] Step S904: Based on the quality monitoring data during the wafer manufacturing process, divide the N different screening areas into different chip premature failure risk levels.

[0138] Quality monitoring data includes information such as defect inspection, process inline SPC parameters, WAT data, and CP test yield.

[0139] Step S906: Based on the different early failure risk levels of each micro-region, different wafer level HVST conditions are set for the chips in the screening area of ​​each wafer as reliability test conditions.

[0140] The conditions include parameters such as stress voltage, stress time and number of cycles, test patterns, and test coverage of the patterns.

[0141] Stress voltage includes the magnitude of DVS (Dynamic Voltage Stress) and EVS (Enhanced Voltage Stress).

[0142] Stress time is the duration of stress applied by DVS and EVS, and the number of cycles.

[0143] Test patterns include IDDQ test patterns and function test patterns for digital areas, analog areas, and storage areas respectively, mbist test patterns for SRAM, scan test patterns for digital areas, etc., and can be one of them or a combination of several of them.

[0144] Step S908: According to the set wafer level HVST conditions, perform HVST on the chips in the screening areas of N different wafers in sequence on the wafer CP test machine to quickly excite chip premature defects.

[0145] In this embodiment, the wafer micro-region chip reliability screening scheme based on Wafer Level High Voltage Stress (HVST) can precisely and dynamically adjust the wafer level HVST conditions of each micro-region of each wafer according to the defect and yield distribution of the same wafer or different wafers. This allows for targeted measures to achieve the goal of balancing and rapidly stimulating chip premature defects, thereby preventing the chip from being affected by fluctuations in wafer fab manufacturing processes, defect levels, and chip yield.

[0146] It should be noted that the above figures are merely illustrative of the processes included in the method according to exemplary embodiments of the present invention, and are not intended to be limiting. It is readily understood that the processes shown in the above figures do not indicate or limit the temporal order of these processes. Furthermore, it is readily understood that these processes may, for example, be executed synchronously or asynchronously in multiple modules.

[0147] Those skilled in the art will understand that various aspects of the present invention can be implemented as systems, methods, or program products. Therefore, various aspects of the present invention can be specifically implemented in the following forms: entirely hardware implementations, entirely software implementations (including firmware, microcode, etc.), or implementations combining hardware and software aspects, collectively referred to herein as “circuits,” “modules,” or “systems.”

[0148] The following reference Figure 10 To describe the chip reliability screening device 1000 according to an embodiment of the present invention. Figure 10 The chip reliability screening device 1000 shown is merely an example and should not impose any limitations on the functionality and scope of use of the embodiments of the present invention.

[0149] The chip reliability screening device 1000 is implemented as a hardware module. Components of the chip reliability screening device 1000 may include, but are not limited to: a division module 1002 for dividing the wafer into multiple screening areas; an evaluation module 1004 for evaluating the premature failure risk of the multiple screening areas based on wafer quality monitoring data, and classifying the multiple screening areas into different premature failure risk levels based on the evaluation results; a setting module 1006 for setting corresponding reliability test conditions for the screening areas based on the existing premature failure risk levels, wherein the reliability test conditions include stress test parameters, and the premature failure risk level is positively correlated with the stress test parameters; and a screening module 1008 for performing excitation tests on the chips in the screening areas based on the reliability test conditions, and screening chips that exhibit premature failure defects based on the test results.

[0150] Those skilled in the art will understand that various aspects of the present invention can be implemented as systems, methods, or program products. Therefore, various aspects of the present invention can be specifically implemented in the following forms: entirely hardware implementations, entirely software implementations (including firmware, microcode, etc.), or implementations combining hardware and software aspects, collectively referred to herein as “circuits,” “modules,” or “systems.”

[0151] The following reference Figure 11 To describe an electronic device 1100 according to this embodiment of the present invention. Figure 11 The electronic device 1100 shown is merely an example and should not impose any limitations on the functionality and scope of use of the embodiments of the present invention.

[0152] like Figure 11 As shown, the electronic device 1100 is manifested in the form of a general-purpose computing device. The components of the electronic device 1100 may include, but are not limited to: at least one processing unit 1110, at least one storage unit 1120, and a bus 1130 connecting different system components (including storage unit 1120 and processing unit 1110).

[0153] The storage unit stores program code that can be executed by the processing unit 1110, causing the processing unit 1110 to perform the steps described in the "Exemplary Methods" section of this specification according to various exemplary embodiments of the present invention. For example, the processing unit 1110 can perform actions such as... Figure 1 The scheme described in steps S202 to S208 shown.

[0154] Storage unit 1120 may include a readable medium in the form of a volatile storage unit, such as random access memory (RAM) 11201 and / or cache memory 11202, and may further include a read-only memory (ROM) 11203.

[0155] Storage unit 1120 may also include a program / utility 11204 having a set (at least one) of program modules 11205, such program modules 11205 including but not limited to: operating system, one or more application programs, other program modules and program data, each or some combination of these examples may include an implementation of a network environment.

[0156] Bus 1130 can represent one or more of several types of bus structures, including a memory cell bus or memory cell controller, a peripheral bus, a graphics acceleration port, a processing unit, or a local bus using any of the various bus structures.

[0157] Electronic device 1100 can also communicate with one or more external devices 1170 (e.g., keyboard, pointing device, Bluetooth device, etc.), and with one or more devices that enable a user to interact with electronic device 1100, and / or with any device that enables electronic device 1100 to communicate with one or more other computing devices (e.g., router, modem, etc.). This communication can be performed via input / output (I / O) interface 1150. Furthermore, electronic device 1100 can also communicate with one or more networks (e.g., local area network (LAN), wide area network (WAN), and / or public networks, such as the Internet) via network adapter 1160. As shown, network adapter 1160 communicates with other modules of electronic device 1100 via bus 1130. It should be understood that, although not shown in the figures, other hardware and / or software modules can be used in conjunction with electronic device 1100, including but not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data backup storage systems.

[0158] From the above description of the embodiments, those skilled in the art will readily understand that the exemplary embodiments described herein can be implemented by software or by combining software with necessary hardware. Therefore, the technical solutions according to the embodiments of this disclosure can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (such as a CD-ROM, USB flash drive, external hard drive, etc.) or on a network, including several instructions to cause a computing device (such as a personal computer, server, terminal device, or network device, etc.) to execute the methods according to the embodiments of this disclosure.

[0159] In exemplary embodiments of this disclosure, a computer-readable storage medium is also provided, on which a program product capable of implementing the methods described above is stored. In some possible embodiments, various aspects of the invention may also be implemented as a program product comprising program code that, when the program product is run on an electronic device, causes the electronic device to perform the steps of the various exemplary embodiments of the invention described in the "Exemplary Methods" section above.

[0160] According to embodiments of the present invention, a program product for implementing the above-described method may employ a portable compact disc read-only memory (CD-ROM) and include program code, and may run on an electronic device, such as a personal computer. However, the program product of the present invention is not limited thereto. In this document, a readable storage medium may be any tangible medium containing or storing a program that may be used by or in conjunction with an instruction execution system, apparatus, or device.

[0161] The program product may employ any combination of one or more readable media. A readable medium may be a readable signal medium or a readable storage medium. A readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of readable storage media (a non-exhaustive list) include: an electrical connection having one or more wires, a portable disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof.

[0162] Computer-readable signal media may include data signals propagated in baseband or as part of a carrier wave, carrying readable program code. Such propagated data signals may take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. A readable signal medium may also be any readable medium other than a readable storage medium, capable of sending, propagating, or transmitting programs for use by or in conjunction with an instruction execution system, apparatus, or device.

[0163] The program code contained on the readable medium may be transmitted using any suitable medium, including but not limited to wireless, wired, optical fiber, RF, etc., or any suitable combination thereof.

[0164] Program code for performing the operations of this invention can be written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Java and C++, and conventional procedural programming languages ​​such as C or similar languages. The program code can execute entirely on the user's computing device, partially on the user's device, as a standalone software package, partially on the user's computing device and partially on a remote computing device, or entirely on a remote computing device or server. In cases involving remote computing devices, the remote computing device can be connected to the user's computing device via any type of network, including a local area network (LAN) or a wide area network (WAN), or it can be connected to an external computing device (e.g., via the Internet using an Internet service provider).

[0165] It should be noted that although several modules or units for the device used to perform actions have been mentioned in the detailed description above, this division is not mandatory. In fact, according to embodiments of this disclosure, the features and functions of two or more modules or units described above can be embodied in one module or unit. Conversely, the features and functions of one module or unit described above can be further divided and embodied by multiple modules or units.

[0166] Furthermore, although the steps of the method in this disclosure are described in a specific order in the accompanying drawings, this does not require or imply that the steps must be performed in that specific order, or that all the steps shown must be performed to achieve the desired result. Additional or alternative steps may be omitted, multiple steps may be combined into one step, and / or a step may be broken down into multiple steps.

[0167] From the above description of the embodiments, those skilled in the art will readily understand that the exemplary embodiments described herein can be implemented by software or by combining software with necessary hardware. Therefore, the technical solutions according to the embodiments of this disclosure can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (such as a CD-ROM, USB flash drive, external hard drive, etc.) or on a network, including several instructions to cause a computing device (such as a personal computer, server, mobile terminal, or network device, etc.) to execute the methods according to the embodiments of this disclosure.

[0168] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the appended claims.

Claims

1. A chip reliability screening method, characterized in that, include: Divide the wafer into multiple screening areas; Based on the quality monitoring data of the wafer, the risk of premature death of the multiple screening regions is assessed, and the multiple screening regions are divided into different premature death risk levels based on the assessment results. Based on the premature death risk level, corresponding reliability test conditions are set for the screening area, wherein the reliability test conditions include stress test parameters, and the premature death risk level is positively correlated with the stress test parameters; The chips in the screening area are subjected to excitation tests based on the reliability test conditions, so as to screen the chips that exhibit premature failure defects based on the test results.

2. The chip reliability screening method according to claim 1, characterized in that, The wafer is divided into multiple screening areas, including: Using the center of the wafer as the dividing point, the circumference of the wafer is divided at predetermined angular intervals to obtain multiple sector-shaped screening areas; or Using the center of the wafer as the dividing center, the wafer is divided into a concentric circular screening region and multiple annular screening regions based on successively increasing radii; or The wafer is divided into multiple screening regions based on a grid; or Based on the detected defect distribution, the wafer is divided to obtain the multiple screening regions.

3. The chip reliability screening method according to claim 1, characterized in that, The wafer quality monitoring data includes at least one of the following: defect detection data during wafer manufacturing, key process parameters, wafer acceptance test data, and CP test yield.

4. The chip reliability screening method according to claim 3, characterized in that, The risk of premature failure in the multiple screening regions is assessed based on the quality monitoring data of the wafers, and the multiple screening regions are divided into different premature failure risk levels based on the assessment results, including: A risk assessment of premature failure is performed on the defect detection data, key process parameters, wafer acceptance test data, and CP test yield of each screening region to obtain a risk assessment value for each screening region. Determine the risk level range to which the risk assessment value belongs, and determine the premature death risk level of the screening area based on the risk level range to which it belongs.

5. The chip reliability screening method according to claim 4, characterized in that, Early failure risk assessments are performed on the defect detection data, key process parameters, wafer acceptance test data, and CP test yield for each of the screening regions to obtain a risk assessment value for each screening region, including: For each of the filtering regions, the defect type and the corresponding number and size of defects are determined based on the defect detection data. For each defect type, a defect score is determined based on the weight of the defect type, the number of defects, and the size of defects. Based on the defect scores of multiple defect types, a defect evaluation value is obtained. Calculate the deviation between the key process parameters and the target process parameters, and obtain a process control evaluation value based on the deviation; Based on the wafer acceptance test data, the difference between the electrical performance parameters and design parameters of the devices in the screening area is determined, so as to obtain a performance evaluation value based on the difference; The defect assessment value, the process control assessment value, the performance assessment value, and the CP test yield are normalized to obtain the risk assessment value.

6. The chip reliability screening method according to claim 1, characterized in that, The reliability test includes a high voltage stress test, and the stress test parameters include a first voltage value of dynamic voltage stress and a second voltage value of enhanced voltage stress applied within a stress cycle, a first duration of dynamic voltage stress and a second duration of enhanced voltage stress within the stress cycle, and the number of stress cycles.

7. The chip reliability screening method according to claim 6, characterized in that, Based on the aforementioned early death risk level, corresponding reliability test conditions are set for the screening area, including: Based on the premature death risk level of the screened region, matching stress test parameters are determined to alternately apply the dynamic voltage stress and enhanced voltage stress based on the matching stress test parameters; and Configure at least one local test mode in the screening area that matches the premature death risk level as the test condition. The at least one local test mode is operated when the dynamic voltage stress and / or the enhanced voltage stress are applied to the screening area. The execution type of the local test mode is positively correlated with the premature death risk level. The local test mode is determined based on at least one type of test mode executed in at least one circuit characteristic region in the chip.

8. The chip reliability screening method according to claim 7, characterized in that, The circuit characteristic region includes a digital region, an analog region, and a storage region, wherein, The local test modes include the static power current test mode, the functional test mode, and the scan test mode performed in the digital area; The local test mode also includes the static power current test mode and the functional test mode performed in the simulated area; The local test mode also includes the static power current test mode, the functional test mode, and the memory built-in self-test mode performed in the storage area.

9. The chip reliability screening method according to claim 7, characterized in that, Based on the aforementioned early death risk level, corresponding reliability test conditions are set for the screening area, including: Based on the premature death risk level, the proportion of the chips performing the local testing mode in the screening area is determined as the stress testing parameter, wherein the proportion is positively correlated with the premature death risk level.

10. The chip reliability screening method according to claim 9, characterized in that, The risk level of premature death is positively correlated with the stress test parameters, including: The increment of the first voltage value corresponding to two adjacent premature death risk levels is a first fixed value or a variable, and the increment of the corresponding second voltage value is a second fixed value or a variable; The increment of the first duration corresponding to two adjacent premature death risk levels is a third fixed value or a variable, and the increment of the corresponding second duration is a fourth fixed value or a variable; The increment of the proportion corresponding to two adjacent premature death risk levels is a fifth fixed value or a variable.

11. The chip reliability screening method according to claim 6, characterized in that, The maximum voltage values ​​of both the dynamic voltage stress and the enhanced voltage stress are less than the maximum operating voltage of the chip.

12. The chip reliability screening method according to claim 1, characterized in that, The chips in the screening area are subjected to excitation testing based on the aforementioned reliability test conditions, including: The reliability test conditions are transmitted to a wafer testing machine, which then performs excitation tests on the selected area based on the corresponding reliability test conditions to obtain the test results.

13. A chip reliability screening device, characterized in that, include: The partitioning module is used to divide the wafer into multiple screening areas; An evaluation module is used to assess the premature death risk of the multiple screening regions based on the quality monitoring data of the wafer, and to classify the multiple screening regions into different premature death risk levels based on the evaluation results; The setting module is used to set corresponding reliability test conditions for the screening area based on the existing premature death risk level, wherein the reliability test conditions include stress test parameters, and the premature death risk level is positively correlated with the stress test parameters; A screening module is used to perform excitation tests on the chips in the screening area based on the reliability test conditions, so as to screen the chips that exhibit premature failure defects based on the test results.

14. An electronic device, characterized in that, include: processor; as well as Memory for storing the executable instructions of the processor; The processor is configured to execute the chip reliability screening method according to any one of claims 1 to 12 by executing the executable instructions.

15. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the chip reliability screening method according to any one of claims 1 to 12.

16. A computer program product having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the chip reliability screening method according to any one of claims 1 to 12.

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