Screening method, screening device, electronic device, storage medium, and program product

Abstract

The present disclosure provides a screening method, a screening device, an electronic device, a storage medium and a program product, relating to the technical field of semiconductor. Wherein, the chip screening method comprises: determining a first group of test items for reliability screening in the test of a chip; determining a second group of test items related to the first group of test items in the wafer level test of a wafer on which the chip is located; obtaining target test data detected by a plurality of test units located on the wafer, the test units being configured based on the second group of test items, and the plurality of test units being arranged along the circumference of the chip; predicting a test prediction value of the first group of test items based on the target test data; and performing outlier screening on the actual test value of the first group of test items based on the test prediction value to screen out risk chips. Through the technical scheme of the present disclosure, the detection capability of potential defects of the chip can be improved, and the reliability of defect chip detection can be improved.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a chip screening method, a chip screening device, an electronic device, a computer-readable storage medium, and a computer program product. Background Technology

[0002] Because chips need to operate stably in extreme environments, including high and low temperatures and humidity, chip reliability is an important indicator affecting chip performance. In order to improve reliability, after completing routine testing, the test results need to be further screened to remove outliers. Currently, the data used for screening is directly obtained circuit-level test data. Although this data can find obvious functional faults, it is difficult to detect subtle potential defects that do not affect the current basic function implementation but may cause problems in long-term use or under special conditions, resulting in low accuracy and efficiency of screening.

[0003] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0004] The purpose of this disclosure is to provide a chip screening method, a chip screening device, an electronic device, a computer-readable storage medium, and a computer program product, which at least to some extent overcome the problem of low accuracy and efficiency in chip outlier screening in related technologies.

[0005] Other features and advantages of this disclosure will become apparent from the following detailed description, or may be learned in part from practice of this disclosure.

[0006] According to one aspect of this disclosure, a chip screening method is provided, comprising: determining a first set of test items for reliability screening in the testing of the chip; determining a second set of test items related to the first set of test items in wafer-level testing of the wafer on which the chip is located; acquiring target test data detected by a plurality of test units located on the wafer, the test units being configured based on the second set of test items, the plurality of test units being arranged circumferentially along the chip; predicting test prediction values ​​of the first set of test items based on the target test data; and performing outlier screening on the actual test values ​​of the first set of test items based on the test prediction values ​​to screen out risky chips.

[0007] In one embodiment of this disclosure, a dicing channel is provided between adjacent chips. For a single chip, test units are respectively provided on at least two dicing channels outside the chip, and the second set of test items in each test unit are arranged along the extension direction of the dicing channel.

[0008] In one embodiment of this disclosure, the second set of test items is arranged from the center of the cutting channel to both sides based on position sensitivity.

[0009] In one embodiment of this disclosure, the method further includes: the second set of test items includes a plurality of second target test items; for a single second target test item, a first test point and a second test point on the wafer with a distance less than a distance threshold are determined to obtain a first test result of the second target test item at the first test point and a second test result of the second target test item at the second test point; the degree of deviation of the second test result relative to the first test result is determined as the position sensitivity of the second target test item.

[0010] In one embodiment of this disclosure, acquiring target test data detected by a plurality of test units located on the wafer includes: the second group of test items includes a plurality of second target test items, and for a single second target test item, the average of a plurality of test values ​​obtained by the plurality of test units is determined as the corresponding target test data.

[0011] In one embodiment of this disclosure, determining a second set of test items related to the first set of test items in wafer-level testing of the wafer containing the chip includes: acquiring first test data of the first set of test items in multiple batches, and second test data of wafer test items in the wafer-level testing; selecting sample data of chips within the preset range from the second test data based on the selection operation of the chip within the preset range of test points in the wafer-level testing; using the wafer test items as first input items, and each first target test item of the first set of test items as output items, to train a first machine learning model based on the sample data and the first test data until the deviation of the first prediction result of the first target test item relative to the corresponding first test data is less than a preset difference, thereby obtaining a first prediction model; obtaining the importance of each wafer test item to the first prediction result based on the first prediction model, and selecting candidate wafer test items from the wafer test items based on the importance; verifying the correlation between the candidate wafer test items and the first set of test items, and filtering out the second set of test items from the candidate wafer test items based on the verification results.

[0012] In one embodiment of this disclosure, obtaining the importance of each of the wafer test items to the first prediction result, and selecting candidate wafer test items from the wafer test items based on the importance, includes: extracting an importance attribute array from the first machine learning model, the importance attribute array representing the importance of multiple wafer test items to the first prediction result; sorting the importance attribute array, and selecting the candidate wafer test items based on the sorting result.

[0013] In one embodiment of this disclosure, the correlation verification of the candidate wafer test items with the first group of test items is performed to select the second group of test items from the candidate wafer test items based on the verification results. This includes: analyzing the correlation of the candidate wafer test items with the first group of test items in terms of circuit function based on the circuit structure of the chip to obtain an initial screening result for the candidate wafer test items based on the analysis results; constructing a verification model based on a second machine learning model to verify the second prediction result for the first group of test items when the initial screening result is used as the second input item; and selecting the second group of test items from the initial screening result based on the second prediction result.

[0014] In one embodiment of this disclosure, predicting the test prediction value of the first group of test items based on the target test data includes: training a third machine learning model based on the actual test value of the first group of test items and the target test data to obtain a second prediction model; and inputting the target test data into the second prediction model to obtain the test prediction value of the first group of test items.

[0015] In one embodiment of this disclosure, outlier screening is performed on the actual test values ​​of the first group of test items based on the test prediction values ​​to screen out risky chips. This includes: constructing a dataset based on the actual test values ​​and the test prediction values; the first group of test items includes multiple first target test items, and a mean vector is generated based on the mean of each first target test item in the dataset; calculating the Mahalanobis distance between the actual test values ​​and the corresponding mean vector; identifying chips whose Mahalanobis distance is greater than a distance threshold as risk-marked chips; and performing reliability verification on the risk-marked chips to determine whether the risk-marked chips belong to the risky chips or not based on the verification results.

[0016] In one embodiment of this disclosure, reliability verification of the risk marker chip includes: verifying the reliability of the risk marker chip based on early failure rate testing and / or high-temperature operating life testing.

[0017] In one embodiment of this disclosure, it further includes at least one of the following: updating the first set of test items, the second set of test items, the method for predicting the first set of test items, and the outlier screening method based on the reliability verification results.

[0018] In one embodiment of this disclosure, determining a first set of test items for reliability screening during chip testing includes: performing deductive reasoning based on collected chip design information and reliability failure information to deduce the reliability failure mechanism of the chip, and determining a first set of candidate test items for detecting the failure mechanism; performing inductive reasoning based on chi-square test on collected chip test data and failure records to statistically identify a second set of candidate test items related to reliability failure; and mutually verifying the first set of candidate test items and the second set of candidate test items to obtain the first set of test items based on the verification results.

[0019] In one embodiment of this disclosure, the testing of the chip includes chip probe testing and / or finished product testing.

[0020] According to one aspect of this disclosure, a chip screening apparatus is provided, comprising: a first determining module for determining a first set of test items for reliability screening during chip testing; a second determining module for determining a second set of test items related to the first set of test items at the wafer level of the wafer on which the chip is located; an acquiring module for acquiring target test data detected by a plurality of test units located on the wafer, the test units being configured based on the second set of test items, the plurality of test units being arranged circumferentially along the chip; a prediction module for predicting test prediction values ​​of the first set of test items based on the target test data; and a screening module for performing outlier screening on the actual test values ​​of the first set of test items based on the test prediction values ​​to screen out risky chips.

[0021] According to another aspect of this disclosure, an electronic device is provided, comprising: a processor; and a memory for storing executable instructions of the processor; the processor being configured to perform the chip screening method of the first aspect described above by executing the executable instructions.

[0022] According to another aspect of this disclosure, a computer-readable storage medium is provided having a computer program stored thereon, which, when executed by a processor, implements the chip screening method described above.

[0023] According to another aspect of this disclosure, a computer program product is provided, on which a computer program is stored, which, when executed by a processor, implements the chip screening method described above.

[0024] The chip screening scheme provided in the embodiments of this disclosure involves setting test units around the chip on the wafer. When determining wafer-level test items related to chip-level test items, the wafer-level test items of the chip are tested based on the test units to obtain target test data. By introducing the target test data of wafer-level testing, the test results of chip-level testing are predicted to obtain the predicted test results for the first set of test items. Then, based on the relationship between the predicted test value and the actual test value, chips with potential risks are screened out. The introduction of target test data of wafer-level testing helps to identify subtle potential defects that, although they do not affect the current basic function implementation, may cause problems under long-term use or special conditions. This is conducive to improving the detection capability of potential chip defects, thereby improving the reliability of defective chip detection.

[0025] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0026] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0027] Figure 1 A schematic flowchart of a chip screening method according to an embodiment of this disclosure is shown;

[0028] Figure 2 This diagram illustrates a test unit disposed on a wafer in an embodiment of the present disclosure;

[0029] Figure 3 This diagram illustrates the arrangement of test subunits in the test unit of an embodiment of this disclosure.

[0030] Figure 4 A flowchart illustrating another chip screening method in an embodiment of this disclosure is shown;

[0031] Figure 5 A flowchart illustrating another chip screening method according to an embodiment of this disclosure is shown.

[0032] Figure 6 A flowchart illustrating yet another chip screening method according to an embodiment of this disclosure is shown;

[0033] Figure 7 A flowchart illustrating yet another chip screening method according to an embodiment of this disclosure is shown;

[0034] Figure 8A flowchart illustrating yet another chip screening method according to an embodiment of this disclosure is shown;

[0035] Figure 9 This diagram illustrates the test points set in an embodiment of the present disclosure.

[0036] Figure 10 A graph showing the correlation between predicted test values ​​and actual test values ​​in an embodiment of this disclosure is provided.

[0037] Figure 11 A schematic diagram illustrating outliers in an embodiment of this disclosure is shown;

[0038] Figure 12 This diagram illustrates a chip screening device according to an embodiment of the present disclosure;

[0039] Figure 13 A structural block diagram of an electronic device according to an embodiment of the present disclosure is shown. Detailed Implementation

[0040] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, they are provided so that this disclosure will be more comprehensive and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0041] Furthermore, the accompanying drawings are merely illustrative of this disclosure and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and therefore repeated descriptions of them will be omitted. Some block diagrams shown in the drawings are functional entities and do not necessarily correspond to physically or logically independent entities. These functional entities may be implemented in software, in one or more hardware modules or integrated circuits, or in different network and / or processor devices and / or microcontroller devices.

[0042] Automotive-grade chips refer to integrated circuit chips used in automotive electronic systems. Therefore, they have strict requirements for reliability. After testing, outliers are removed by screening based on the test results, thereby improving the reliability of automotive-grade chips.

[0043] In some embodiments, chip screening can be based on Dynamic Part Averaging (DPAT), Principal Component Analysis (PCA), or machine learning. These methods can be categorized into two types based on the parameters used to construct the screening model:

[0044] The first type directly uses test data obtained from tests such as WAT (Wafer Acceptance Test), CP (Chip Probing), and FT (Final Test) to build models for screening. However, since these data are all from the circuit level, it is difficult to find subtle potential defects, resulting in insufficient screening accuracy and low efficiency.

[0045] The second type involves setting up on-chip detectors to collect various types of information from the chip and building a screening model based on the collected chip information. This type of solution has a high screening cost because it occupies chip area and adds a lot of extra test items.

[0046] To address at least one of the aforementioned problems, a chip screening scheme is proposed in this disclosure.

[0047] To facilitate understanding, the following is an explanation of several terms used in this application.

[0048] WAT data (Wafer Acceptance Test Data): WAT testing refers to a series of tests performed after wafer manufacturing is completed and before chip packaging, used to evaluate the electrical performance of basic components on the wafer (such as transistors, resistors, capacitors, etc.).

[0049] CP testing: CP testing is an electrical performance test performed on each chip on a wafer to determine whether the chip meets the design specifications.

[0050] Final Test (FT): This is a comprehensive test conducted on a chip after semiconductor manufacturing is completed. It covers functional testing (such as instruction set, module and system function testing) and performance testing (such as speed, power consumption and stability testing).

[0051] like Figure 1 As shown, a chip screening method according to an embodiment of this disclosure includes:

[0052] Step S102: Determine the first set of test items used for reliability screening in the chip testing.

[0053] In some embodiments, chip testing includes chip probe testing and / or finished product testing, with the first set of test items being chip-level test items.

[0054] In some embodiments, the first set of test items may be key CP and / or FT test items, including V min I DDQ (Quiescent Power Supply Current) and F max wait.

[0055] Step S104: Determine the second set of test items related to the first set of test items in the wafer-level test of the wafer where the chip is located.

[0056] In some embodiments, wafer-level testing refers to testing performed before the chip is cut off from the wafer, used to identify problematic chip areas on the wafer in advance. The second set of test items can be used to make a certain prediction of the final reliability of the chip at the wafer-level stage, and both the first set of test items and the second set of test items are used for reliability screening.

[0057] In some embodiments, the second set of test items includes key test items in the WAT test items that are related to chip probe testing and / or finished product testing.

[0058] In some embodiments, reliability screening includes a screening method that uses analysis methods such as specific type failure analysis and reliability analysis to improve chip yield. The first group of test items and the second group of test items are related. It can also be understood as the most relevant chip-level test items and wafer-level test items found in order to improve yield, perform specific type failure analysis and reliability analysis, so as to implement the testing of the second group of test items based on subsequent test units.

[0059] Step S106: Obtain target test data detected by multiple test units located on the wafer. The test units are configured based on the second set of test items, and the multiple test units are set along the circumference of the chip.

[0060] In one embodiment of this disclosure, the wafer structure of the wafer on which the chip is located includes: a chip array including multiple chips; and a test unit arranged along the circumference of the chips. The test unit is configured based on a second set of test items related to a first set of test items. The first set of test items are test items used for reliability screening in the testing of the chip, and the second set of test items belongs to wafer-level testing of the wafer.

[0061] In some embodiments, a test unit refers to a functional entity constructed to complete specified tests on a chip, while a test item is a specific test item set for specified functions and performance of the chip. The test unit is used to provide the necessary conditions and means for the execution of the test items.

[0062] In some embodiments, one implementation of the test unit based on the configuration of the second set of test items includes: the test unit includes multiple test subunits, each test subunit corresponds to a test item, that is, each test subunit is responsible for testing a test item, the multiple test subunits can be set based on position sensitivity, so for each second target test item in the second set of test items, multiple test values ​​can be obtained, and the average of the multiple test values ​​is determined as the target test data corresponding to the second target test item.

[0063] In some embodiments, another implementation of the test unit based on the second set of test items includes: the test unit may include one or more test sub-units, multiple test sub-units corresponding to the same second set of test items, multiple test sub-units may be set in different positions, for example, arranged along the extension direction of the cutting channel, or designed with different structural parameters, for example, the structural size of multiple test sub-units arranged along the direction of the cutting channel gradually increases.

[0064] In some embodiments, another implementation of the test unit based on the second set of test items includes: the test unit refers to a test subunit, which corresponds to multiple sets of second set of test items, and the multiple sets of second set of test items can be tested on the test unit in turn.

[0065] In some embodiments, dicing channels are provided between adjacent chips. For a single chip, test units are provided on at least two dicing channels outside the chip, and test sub-units in each test unit are arranged along the extension direction of the dicing channel.

[0066] In some embodiments, target test data refers to test data obtained by testing the second set of test items.

[0067] Step S108: Predict the test prediction value of the first group of test items based on the target test data.

[0068] In some embodiments, the relationship between the target test data and the test values ​​of the first set of test items can be established by learning from a large amount of historical test data. Based on this relationship, the test prediction value of the first set of test items can be predicted using the currently acquired target test data. The test prediction value of the first set of test items can be understood as a reference test result for the chip if there is no risk or the risk is small.

[0069] Step S110: Based on the test prediction values, outlier screening is performed on the actual test values ​​of the first group of test items to screen out risky chips.

[0070] In some embodiments, after the chip is manufactured, the first set of test items are actually tested to obtain the actual test value. The actual test value is compared with the previously predicted test value, and a reasonable threshold range is set. If the actual test value deviates from the predicted test value by more than a certain threshold, the chip is determined to be an outlier, that is, a chip that may have potential risks.

[0071] In this embodiment, by setting test units around the chip on the wafer, when determining the wafer-level test items related to chip-level test items, the wafer-level test items of the chip are tested based on the test units to obtain target test data. By introducing the target test data of wafer-level testing, the test results of chip-level testing are predicted to obtain the predicted test results for the first set of test items. Then, based on the relationship between the predicted test value and the actual test value, chips with potential risks are screened out. The introduction of target test data of wafer-level testing helps to identify subtle potential defects that, although they do not affect the current basic function implementation, may cause problems in long-term use or under special conditions. This is conducive to improving the detection capability of potential chip defects, thereby improving the reliability of defective chip detection.

[0072] In addition, setting test units along the circumference of the chip eliminates the need to integrate monitoring circuits inside the chip. This allows for wafer-level testing while reducing chip area and lowering testing costs.

[0073] In one embodiment of this disclosure, dicing channels are provided between adjacent chips on a wafer. For a single chip, test units are provided on at least two dicing channels outside the chip, and a second set of test items in each test unit is arranged along the extension direction of the dicing channel.

[0074] In some embodiments, for square chips, a set of test units can be set around each chip.

[0075] In this embodiment, dicing channels are provided between adjacent chips on the wafer, and test units are provided on at least two dicing channels outside a single chip. The second set of test items in each test unit is arranged along the extension direction of the dicing channel. The dicing channel serves as a reserved area for chip separation. Setting test units here will not affect the function and performance of the chip itself. At the same time, it facilitates the layout and wiring of the test units and effectively utilizes space resources. Setting test units on at least two dicing channels can obtain test data of the wafer area around the chip from multiple angles, which helps to obtain wafer-level test data more accurately.

[0076] In one embodiment of this disclosure, the second set of test items is arranged from the center of the cutting channel outwards to both sides based on position sensitivity.

[0077] In some embodiments, the test unit includes test sub-units, and the distribution of the test sub-units can be determined based on position sensitivity. Position sensitivity can be understood as the fact that, under the same close-range conditions, if the deviation of the test values ​​obtained by two identical first test sub-units is greater than the deviation of the test values ​​obtained by two identical second test sub-units, then the first test sub-unit has stronger position sensitivity.

[0078] In this embodiment, the center position of the dicing channel can be understood as the center position of the outer edge of the chip adjacent to the dicing channel. Based on position sensitivity, the second set of test items are arranged from the center position of the dicing channel to both sides. The test items with higher position sensitivity are set closer to the center position of the dicing channel, while the test items with lower position sensitivity can be set along the center position of the dicing channel to both sides, which is beneficial for the test units to obtain more accurate target test data.

[0079] In one embodiment of this disclosure, the method further includes: a second set of test items including a plurality of second target test items; for a single second target test item, determining a first test point and a second test point on the wafer at a distance less than a distance threshold, to obtain a first test result of the second target test item at the first test point and a second test result of the second target test item at the second test point; and determining the degree of deviation of the second test result relative to the first test result as the position sensitivity of the second target test item.

[0080] In this embodiment, by quantifying the performance differences of the second target test item at different locations on the wafer, the degree of influence of the test item on the location factor can be intuitively reflected, thereby ensuring the rationality of the arrangement of multiple second group test items in the test unit.

[0081] In some embodiments, multiple second target test items belong to test sub-units. A test sub-unit refers to a set of circuit structures specifically designed on a semiconductor wafer for testing and characterizing the performance of semiconductor devices and processes. The second target test items are the key WAT test items.

[0082] In one embodiment of this disclosure, acquiring target test data detected by a plurality of test units located on a wafer includes:

[0083] The second set of test items includes multiple second target test items. For a single second target test item, the average of the multiple test values ​​obtained from multiple test units is determined as the corresponding target test data.

[0084] like Figure 2 As shown, in some embodiments, except for the chip dies at the edge, each chip die is surrounded by dicing channels. Test units are set on the dicing channels. There are at least four sets of test values ​​of the second set of test items around the chip die that can be used as a reference. By calculating the average of the test values ​​of the four test sub-units testkey around a chip die (1, 2, 3, and 4), the target test data of the chip is used. This helps to more accurately characterize the information of each chip die and provides reference information for subsequent modeling.

[0085] In this embodiment, multiple test units collect data at different locations. Individual test values ​​may fluctuate due to local interference or minor process differences. By averaging, the final target test data can be made more stable and reliable, and more accurately reflect the overall characteristics of the second target test item on the wafer.

[0086] like Figure 3 As shown, in some embodiments, on the cutting track, position-sensitive test keys are placed in the middle area, while those with low position sensitivity are placed on both sides, or insensitive test keys are placed in the corners. The WAT test items include a ring oscillator (RO), metal resistance, and saturation drain current I0. dsat RC_FV type, capacitor type, inversion layer thickness and inverter, etc.

[0087] In some embodiments, the first set of test items includes HSI (High Speed ​​Interface) in the CP test, with a predicted value showing a correlation of 95%+ with the measured value, indicating good prediction results. The relevant second set of test items includes RC_FV_V1, RC_FV_V2, TXI_N (negative terminal of differential signal), TXI_P (positive terminal of differential signal), and I... dsat When excluding HSI-type defects, the above-mentioned test items should be prioritized in the test unit.

[0088] In some embodiments, the test unit may include transistors and labeling units, etc.

[0089] like Figure 4 As shown, in one embodiment of this disclosure, a second set of test items related to the first set of test items is determined in the wafer-level testing of the wafer containing the chip, including:

[0090] Step S402: Obtain the first test data of the first group of test items in multiple batches, and the second test data of the wafer test items in the wafer-level test.

[0091] In some embodiments, the second set of test items consists of one or more wafer test items.

[0092] Step S404: Based on the selection operation of chips within a preset range of test points in wafer-level testing, sample data of chips within the preset range are selected from the second test data.

[0093] In some embodiments, a test point can be understood as a location point set during wafer-level testing to obtain chip or wafer-related performance data. A preset range refers to a specific spatial area defined on the wafer with a certain test point as the center or reference. By limiting the preset range, since WAT generally only tests 5 to 9 test points, the M nearest chips around each test point are obtained as samples. Only the chips closest to the site have the most similar process conditions and parameters, making the sample data of chips within the preset range selected from the second test data more reliable.

[0094] Step S406: Take the wafer test item as the first input item, and take each first target test item of the first group of test items as the output item. Train the first machine learning model based on the sample data and the first test data until the deviation of the first prediction result of the first target test item relative to the corresponding first test data is less than the preset difference, and obtain the first prediction model.

[0095] In some embodiments, a model learns the intrinsic relationship between wafer test items and a first target test item using a large amount of data to obtain a first prediction model, which is used to predict the results of a first set of test items using data from the wafer test items.

[0096] In some embodiments, the first machine learning model may be a decision tree model, a random forest model, or a neural network model, etc.

[0097] Step S408: Based on the first prediction model, obtain the importance of each wafer test item to the first prediction result, so as to select candidate wafer test items from the wafer test items based on the importance.

[0098] In some embodiments, importance reflects the relative contribution of each wafer test item to the model prediction process. By analyzing the internal structure and parameters of the model, such as decision trees and random forests, the importance scores of features can be directly output. Obtaining the importance of each wafer test item helps to select test items that have a greater impact on the prediction results of the first group of test items from multiple wafer test items as candidate wafer test items.

[0099] Step S410: Verify the correlation between the candidate wafer test items and the first group of test items, so as to select the second group of test items from the candidate wafer test items based on the verification results.

[0100] In some embodiments, correlation verification refers to examining and confirming the degree of correlation between candidate wafer test items and the first set of test items. Feature selection methods in machine learning can be used to determine the correlation by evaluating the dependency between features (candidate wafer test items) and targets (first set of test items). Through correlation verification, it can be ensured that the second set of test items can truly reflect the relevant information of the first set of test items.

[0101] In this embodiment, data from multiple batches is analyzed, and chip sample data from specific areas of the wafer are selected to comprehensively reflect the characteristics of chips under different production conditions. By training a machine learning model, the complex potential relationships between wafer test items and the first set of test items are uncovered to improve the accuracy of predicting potential chip defects. Furthermore, by combining importance analysis and correlation verification, a second set of test items related to the first set of test items is selected. This allows the focus to be placed on subtle potential defects that may cause problems under long-term or special conditions during the wafer-level testing stage. This effectively utilizes the target test data obtained from wafer-level testing to predict chip-level test results, ensuring the effectiveness of chip reliability screening.

[0102] In one embodiment of this disclosure, obtaining the importance of each wafer test item to a first prediction result, and selecting candidate wafer test items from the wafer test items based on the importance, includes:

[0103] An importance attribute array is extracted from the first machine learning model. The importance attribute array represents the importance of multiple wafer test items to the first prediction result. The importance attribute array is sorted so that candidate wafer test items can be selected based on the sorting results.

[0104] In this embodiment, by extracting the importance attribute array from the first machine learning model, the importance of each wafer test item to the first prediction result can be clearly quantified. The importance attribute array is sorted, and candidate wafer test items are selected based on the sorting results to determine the test items that have a greater impact on the prediction result. This ensures the screening efficiency and effect of the second group of test items, and also ensures the correlation between the selected candidate wafer test items and the prediction of the first group of test items.

[0105] like Figure 5 As shown, in one embodiment of this disclosure, the correlation between candidate wafer test items and a first group of test items is verified, so as to select a second group of test items from the candidate wafer test items based on the verification results, including:

[0106] Step S502: Based on the circuit structure of the chip, analyze the correlation between the candidate wafer test items and the first group of test items in terms of circuit function, so as to obtain the preliminary screening results of the candidate wafer test items based on the analysis results.

[0107] In some embodiments, the circuit structure of a chip refers to the various electronic components (such as transistors, resistors, capacitors, inductors, etc.) that constitute the chip, as well as their connection methods and layout. The correlation between the candidate wafer test items and the first group of test items in terms of circuit function refers to the degree of correlation between the candidate wafer test items and the first group of test items in terms of the functions implemented by the chip circuit.

[0108] Step S504: Construct a validation model based on the second machine learning model to validate the second prediction result for the first set of test items when the initial screening result is used as the second input item.

[0109] In some embodiments, the second machine learning model may be a neural network model, a decision tree model, or a support vector machine, etc.

[0110] Step S506: Select the second set of test items from the initial screening results based on the second prediction results.

[0111] In this embodiment, the second machine learning model is used to make a second prediction on the first set of test items using the initial screening results as input. Through model learning and reasoning, it can discover the potential correlations and patterns between the candidate wafer test items and the first set of test items, and help determine whether the correlation between each item in the initial screening results and the first set of test items meets the requirements, so as to further screen out the second set of test items.

[0112] In one embodiment of this disclosure, predicting the test prediction value of the first set of test items based on target test data includes:

[0113] The third machine learning model is trained based on the actual test values ​​of the first set of test items and the target test data to obtain the second prediction model; the target test data is then input into the second prediction model to obtain the test prediction values ​​of the first set of test items.

[0114] In some embodiments, the third machine learning model can be a linear regression model, a decision tree model, or a neural network model, etc., which constructs a second prediction model by learning the relationship between the actual test values ​​of the first set of test items and the target test data.

[0115] In this embodiment, a second prediction model is obtained by training a third machine learning model to uncover the potential relationship between the target test data and the actual test values ​​of the first set of test items. This enables accurate prediction of the test prediction values ​​of the first set of test items based on the target test data, ensuring the effectiveness of the screening operation by using the test prediction values ​​as reference data for chip outlier screening.

[0116] like Figure 6 As shown, in one embodiment of this disclosure, outlier screening is performed on the actual test values ​​of the first group of test items based on the test prediction values ​​to screen out risky chips, including:

[0117] Step S602: Construct a dataset based on the actual test values ​​and the test prediction values.

[0118] In some embodiments, the actual test values ​​and the predicted test values ​​are organized and combined to form a dataset according to certain rules and formats.

[0119] Step S604: The first set of test items includes multiple first target test items. A mean vector is generated based on the mean of each first target test item in the dataset.

[0120] In some embodiments, when the first set of test items contains multiple first target test items, the mean value of each first target test item in the dataset is calculated, and these mean values ​​are arranged in a certain order to form a vector to represent the average level of the data in multiple dimensions.

[0121] Step S606: Calculate the Mahalanobis distance between the actual test value and the corresponding mean vector.

[0122] In some embodiments, Mahalanobis distance takes into account the covariance structure of the data and is used to measure the distance between a data point and a distribution.

[0123] Step S608: Chips with a Mahalanobis distance greater than the distance threshold are identified as risk-marked chips.

[0124] Risk-marked chips refer to chips whose actual test values ​​deviate significantly from the overall average level, indicating a high potential risk based on data performance, but further verification is needed to determine whether they actually have reliability issues.

[0125] Step S610: Perform reliability verification on the risk-marking chip to determine whether the risk-marking chip is a risk chip or not based on the verification results.

[0126] In this embodiment, by constructing a dataset, calculating the mean vector based on the dataset, and performing operations such as calculating the Mahalanobis distance between the actual test value and the corresponding mean vector, chips that may pose risks, i.e. risk-marked chips, can be effectively identified. This provides accurate screening targets for subsequent reliability verification, improving screening efficiency and accuracy. Furthermore, by performing reliability verification on risk-marked chips, the accuracy of the finally screened risk chips is ensured, enabling timely detection and handling of chips with reliability problems, and reducing the risk of failure during use.

[0127] In one embodiment of this disclosure, reliability verification of the risk marker chip includes: verifying the reliability of the risk marker chip based on early failure rate testing and / or high-temperature operating life testing.

[0128] In this embodiment, the Early Life Failure Rate (ELFR) test is used to measure the reliability performance of the chip in the initial stage of its use, and the High Temperature Operating Life Test (HTOL) test is used to determine the product reliability by accelerating the thermal activation failure mechanism.

[0129] In one embodiment of this disclosure, it further includes at least one of the following: updating the first set of test items, the second set of test items based on the reliability verification results, the method for predicting the first set of test items, and the outlier screening method.

[0130] like Figure 7 As shown, in one embodiment of this disclosure, a first set of test items for reliability screening in the testing of the chip is determined, including:

[0131] Step S702: Based on the collected chip design information and reliability failure information, deductive reasoning is performed to deduce the chip reliability failure mechanism and determine the first set of candidate test items for detecting the failure mechanism.

[0132] In some embodiments, chip design information refers to data generated during the chip design process, including but not limited to chip architecture, functional modules, and process parameters. Reliability failure information is used to record relevant data on reliability problems that occur during chip use, including the time of failure, the chip's operating conditions at the time of failure (such as temperature, voltage, load, etc.), and the specific manifestations of the failure.

[0133] In some embodiments, based on the chip's design information and reliability failure information, and in accordance with relevant theoretical knowledge, the causes and ways in which the chip may have reliability problems are analyzed, thereby deriving the chip's reliability failure mechanism. The reliability failure mechanism describes the specific processes and mechanisms that lead to chip performance degradation or functional loss, and determines a first set of candidate test items for detecting these failure mechanisms.

[0134] Step S704: Based on the chi-square test, inductive reasoning is performed on the collected chip test data and failure records to statistically identify a second set of candidate test items related to reliability failures.

[0135] In some embodiments, the chi-square test is used to test whether there is a significant association between two categorical variables. In the analysis of chip test data and failure records, the chip test results (such as passing or failing a test) are used as one categorical variable, and the failure records (such as failing or not failing) are used as another categorical variable. By calculating the chi-square value, it is determined whether there is a correlation between the two variables.

[0136] Step S706: Verify the first group of candidate test items and the second group of candidate test items against each other, so as to obtain the first group of test items based on the verification results.

[0137] In some embodiments, since the first set of candidate test items is derived from theoretical deductive reasoning and the second set of candidate test items is derived from inductive reasoning based on actual data, they are mutually verified to verify their consistency. Through this mutual verification, test items that may be inaccurate or redundant can be removed, and more reliable and representative test items can be retained, thus ultimately determining the first set of test items.

[0138] In this embodiment, through deductive reasoning based on design information and reliability failure information, the potential reliability failure mechanism of the chip is deeply explored. The chi-square test is used to summarize and reason about the actual test data and failure records, and test items that are significantly related to reliability failure are found from a large amount of data. By starting from the two levels of chip design principles and actual failure data, the first set of test items for reliability screening is determined, which improves the accuracy and reliability of the determined first set of test items.

[0139] like Figure 8 As shown, a chip screening method according to another embodiment of this disclosure includes:

[0140] Step S802: Based on the chip design and known failure information, the relationship between known failure mechanisms and testing is determined through forward analysis, and highly significant test items are determined through reverse analysis using chi-square test. The key CP and / or FT test items are selected through mutual verification of forward and reverse analysis, and used as the first set of test items for reliability screening.

[0141] Step S804: Establish the connection between the WAT test items and the CP and / or FT test items to obtain the key WAT test items as the second set of test items.

[0142] In some embodiments, the implementation process of step S802 includes:

[0143] (1) Obtain the CP and / or FT test values ​​and WAT test values ​​of N batches of chips.

[0144] (2) The WAT test includes 5 to 9 test points, such as... Figure 9 As shown, the horizontal and vertical axes can represent the x and y coordinates, respectively. The black dots in the figure are test points, that is, there are 9 test points. The M nearest chips around each test point, that is, the shaded area around the test point, are taken as samples. Only the chips closest to the test point have the most similar process conditions and parameters, which helps to improve the prediction accuracy.

[0145] (3) Input the WAT test value and establish the key CP and / or FT test items in the model prediction step S802 in sequence. The first prediction model can be established by using the random forest algorithm. Adjust the model hyperparameters until the predicted value and the measured value in the test group show a high correlation (>0.95).

[0146] like Figure 10 As shown, the horizontal axis represents the test value and the vertical axis represents the predicted value. The data points are relatively concentrated and distributed around a straight line or a certain curve. For positive correlation, these points are roughly distributed in a straight line from the lower left to the upper right, indicating that as the test value increases, the predicted value also increases.

[0147] (4) Based on the first prediction model, extract the top A input parameters with high importance as candidate wafer test items.

[0148] (5) Based on the circuit design structure, the B items related to the CP and / or FT test items in the A key input parameters are analyzed in a positive direction as the initial screening result. For example, the resistance and capacitance values ​​in the HSI circuit are highly correlated with those in the WAT.

[0149] (6) Use a neural network to predict the corresponding CP and / or FT tests using the key WAT test items in item B, check the prediction results, and perform cross-validation with the above process to obtain the key WAT test items, i.e. the second set of test items.

[0150] Step S806: Based on the WAT testkey setting method, test units are arranged in the wafer dicing channel and target test data is acquired.

[0151] Each chip corresponds to a set of target test data. For example, the average of the test values ​​of the four sets around each chip is used as the target test data for that chip.

[0152] Step S808: Construct a second prediction model based on machine learning algorithms, and use the new WAT features of each chip to predict the test value of CP / FT to obtain the test prediction value.

[0153] Step S810: Identify outliers by comparing the prediction results with the actual test values ​​of CP and / or FT, and use them as risk-marked chips.

[0154] In some embodiments, since the predicted values ​​obtained by the model are highly correlated with the measured values, and since the chip yield is very high and most samples are good products, samples that tend to the distribution center and have similar characteristics are considered to be high-reliability samples, while outliers with large differences in characteristics are considered to be defective products. In other words, samples whose measured values ​​differ too much from the predicted values ​​have reason to be considered to have potential risks.

[0155] In some embodiments, Mahalanobis distance is suitable for handling correlated data. During its calculation, it eliminates the correlation and variance differences between data dimensions and can accurately identify outliers. Therefore, Mahalanobis distance can be used to mark samples that deviate too much as low reliability.

[0156] like Figure 11 As shown, the horizontal axis represents the test value, the vertical axis represents the predicted value, and the points on the outer ring are considered outliers, i.e., marked as low reliability.

[0157] In some embodiments, methods such as SVM can also be used to identify outliers.

[0158] In step S812, the tagged risk chip undergoes reliability verification through ELFR / HTOL testing to determine whether it is a risk chip.

[0159] Step S814: Use the results of the reliability verification to update the first set of test items and the second set of test items, as well as to adjust the model parameters and optimize the outlier judgment criteria.

[0160] In some embodiments, by setting the testkey of the key WAT test item to characterize the chip's features, it can help determine process corners, Monte Carlo simulation points, and RC models, etc.

[0161] In some embodiments, the value of the test subunit Testkey is the statistics of the target test data. It can use the mean / median of the surrounding four groups, or it can be extended to the outermost test groups and weighted to achieve good screening effect and reduce false positive rate.

[0162] In this embodiment, compared to setting up an on-chip monitor, there is no need to increase the chip area and test items. Existing test data can be fully utilized, which can reduce test costs. In addition, it can be continuously iterated based on newly manufactured chips to achieve higher screening efficiency. This chip screening scheme has strong applicability. For example, it can continuously accumulate chip test data to continuously improve chip reliability.

[0163] It should be noted that the above figures are merely illustrative of the processes included in the method according to exemplary embodiments of the present invention, and are not intended to be limiting. It is readily understood that the processes shown in the above figures do not indicate or limit the temporal order of these processes. Furthermore, it is readily understood that these processes may, for example, be executed synchronously or asynchronously in multiple modules.

[0164] Those skilled in the art will understand that various aspects of the present invention can be implemented as a system, method, or programmable chip. Therefore, various aspects of the present invention can be specifically implemented in the following forms: a completely hardware implementation, a completely software implementation (including firmware, microcode, etc.), or a combination of hardware and software aspects, collectively referred to herein as a "circuit," "module," or "system."

[0165] The following reference Figure 12 To describe the chip screening apparatus 1200 according to an embodiment of the present invention. Figure 12 The chip screening device 1200 shown is merely an example and should not impose any limitations on the functionality and scope of use of the embodiments of the present invention.

[0166] The chip screening device 1200 is manifested as a hardware module. Components of the chip screening device 1200 may include, but are not limited to: a first determining module 1202, used to determine a first set of test items for reliability screening during chip testing; a second determining module 1204, used to determine a second set of test items related to the first set of test items at the wafer level of the wafer where the chip is located; an acquisition module 1206, used to acquire target test data detected by multiple test units located on the wafer, the test units being configured based on the second set of test items, and the multiple test units being arranged along the circumference of the chip; a prediction module 1208, used to predict the test prediction values ​​of the first set of test items based on the target test data; and a screening module 1210, used to perform outlier screening on the actual test values ​​of the first set of test items based on the test prediction values, in order to screen out risky chips.

[0167] Those skilled in the art will understand that various aspects of the present invention can be implemented as a system, method, or programmable chip. Therefore, various aspects of the present invention can be specifically implemented in the following forms: a completely hardware implementation, a completely software implementation (including firmware, microcode, etc.), or a combination of hardware and software aspects, collectively referred to herein as a "circuit," "module," or "system."

[0168] The following reference Figure 13 To describe an electronic device 1300 according to this embodiment of the present invention. Figure 13 The electronic device 1300 shown is merely an example and should not impose any limitations on the functionality and scope of use of the embodiments of the present invention.

[0169] like Figure 13 As shown, the electronic device 1300 is manifested in the form of a general-purpose computing device. The components of the electronic device 1300 may include, but are not limited to: at least one processing unit 1310, at least one storage unit 1320, and a bus 1330 connecting different system components (including storage unit 1320 and processing unit 1310).

[0170] The storage unit stores program code that can be executed by the processing unit 1310, causing the processing unit 1310 to perform the steps described in the "Exemplary Methods" section of this specification according to various exemplary embodiments of the present invention. For example, the processing unit 1310 can perform actions such as... Figure 1 The scheme described in steps S102 to S110 shown.

[0171] Storage unit 1320 may include readable media in the form of volatile storage units, such as random access memory (RAM) 13201 and / or cache memory 13202, and may further include read-only memory (ROM) 13203.

[0172] Storage unit 1320 may also include a program / utility 13204 having a set (at least one) of program modules 13205, such program modules 13205 including but not limited to: operating system, one or more application programs, other program modules and program data, each or some combination of these examples may include an implementation of a network environment.

[0173] Bus 1330 can represent one or more of several types of bus structures, including a memory cell bus or memory cell controller, a peripheral bus, a graphics acceleration port, a processing unit, or a local bus using any of the various bus structures.

[0174] Electronic device 1300 can also communicate with one or more external devices 1370 (e.g., keyboard, pointing device, Bluetooth device, etc.), and with one or more devices that enable a user to interact with electronic device 1300, and / or with any device that enables electronic device 1300 to communicate with one or more other computing devices (e.g., router, modem, etc.). This communication can be performed via input / output (I / O) interface 1350. Furthermore, electronic device 1300 can also communicate with one or more networks (e.g., local area network (LAN), wide area network (WAN), and / or public networks, such as the Internet) via network adapter 1360. As shown, network adapter 1360 communicates with other modules of electronic device 1300 via bus 1330. It should be understood that, although not shown in the figures, other hardware and / or software modules can be used in conjunction with electronic device 1300, including but not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data backup storage systems.

[0175] From the above description of the embodiments, those skilled in the art will readily understand that the exemplary embodiments described herein can be implemented by software or by combining software with necessary hardware. Therefore, the technical solutions according to the embodiments of this disclosure can be embodied in the form of a software chip, which can be stored in a non-volatile storage medium (such as a CD-ROM, USB flash drive, external hard drive, etc.) or on a network, and includes several instructions to cause a computing device (such as a personal computer, server, terminal device, or network device, etc.) to execute the methods according to the embodiments of this disclosure.

[0176] In exemplary embodiments of this disclosure, a computer-readable storage medium is also provided, having stored thereon a program chip capable of implementing the methods described above. In some possible implementations, various aspects of the invention may also be implemented as a program chip including program code that, when run on an electronic device, causes the electronic device to perform the steps described in the "Exemplary Methods" section of this specification according to various exemplary embodiments of the invention.

[0177] According to embodiments of the present invention, a programmable chip for implementing the above-described method may employ a portable compact disc read-only memory (CD-ROM) and include program code, and may run on an electronic device, such as a personal computer. However, the programmable chip of the present invention is not limited thereto. In this document, a readable storage medium may be any tangible medium containing or storing a program that may be used by or in conjunction with an instruction execution system, apparatus, or device.

[0178] The program chip can take the form of any combination of one or more readable media. The readable media can be a readable signal medium or a readable storage medium. The readable storage medium can be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of readable storage media (a non-exhaustive list) include: electrical connections with one or more wires, portable disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof.

[0179] Computer-readable signal media may include data signals propagated in baseband or as part of a carrier wave, carrying readable program code. Such propagated data signals may take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. A readable signal medium may also be any readable medium other than a readable storage medium, capable of sending, propagating, or transmitting programs for use by or in conjunction with an instruction execution system, apparatus, or device.

[0180] The program code contained on the readable medium may be transmitted using any suitable medium, including but not limited to wireless, wired, optical fiber, RF, etc., or any suitable combination thereof.

[0181] Program code for performing the operations of this invention can be written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Java and C++, and conventional procedural programming languages ​​such as C or similar languages. The program code can execute entirely on the user's computing device, partially on the user's device, as a standalone software package, partially on the user's computing device and partially on a remote computing device, or entirely on a remote computing device or server. In cases involving remote computing devices, the remote computing device can be connected to the user's computing device via any type of network, including a local area network (LAN) or a wide area network (WAN), or it can be connected to an external computing device (e.g., via the Internet using an Internet service provider).

[0182] It should be noted that although several modules or units for the device used to perform actions have been mentioned in the detailed description above, this division is not mandatory. In fact, according to embodiments of this disclosure, the features and functions of two or more modules or units described above can be embodied in one module or unit. Conversely, the features and functions of one module or unit described above can be further divided and embodied by multiple modules or units.

[0183] Furthermore, although the steps of the method in this disclosure are described in a specific order in the accompanying drawings, this does not require or imply that the steps must be performed in that specific order, or that all the steps shown must be performed to achieve the desired result. Additional or alternative steps may be omitted, multiple steps may be combined into one step, and / or a step may be broken down into multiple steps.

[0184] From the above description of the embodiments, those skilled in the art will readily understand that the exemplary embodiments described herein can be implemented by software or by combining software with necessary hardware. Therefore, the technical solutions according to the embodiments of this disclosure can be embodied in the form of a software chip, which can be stored in a non-volatile storage medium (such as a CD-ROM, USB flash drive, external hard drive, etc.) or on a network, and includes several instructions to cause a computing device (such as a personal computer, server, mobile terminal, or network device, etc.) to execute the methods according to the embodiments of this disclosure.

[0185] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the appended claims.

Claims

1. A chip screening method, characterized in that, include: Identify the first set of test items used for reliability screening in the chip testing process; Identify the second set of test items related to the first set of test items in the wafer-level testing of the wafer containing the chip; Acquire target test data detected by a plurality of test units located on the wafer, the test units being configured based on the second set of test items, the plurality of test units being arranged along the circumference of the chip; Based on the target test data, predict the test prediction value of the first group of test items; Outlier screening is performed on the actual test values ​​of the first group of test items based on the predicted test values ​​to identify risky chips.

2. The chip screening method according to claim 1, characterized in that, A dicing channel is provided between adjacent chips. For a single chip, a test unit is provided on at least two dicing channels outside the chip. The second set of test items in each test unit is arranged along the extension direction of the dicing channel.

3. The chip screening method according to claim 2, characterized in that, Based on position sensitivity, the second set of test items are arranged from the center of the cutting channel outwards to both sides.

4. The chip screening method according to claim 3, characterized in that, Also includes: The second set of test items includes multiple second target test items. For a single second target test item, a first test point and a second test point on the wafer with a distance less than a distance threshold are determined to obtain a first test result of the second target test item at the first test point and a second test result of the second target test item at the second test point. The degree of deviation of the second test result from the first test result is determined as the position sensitivity of the second target test item.

5. The chip screening method according to claim 1, characterized in that, Acquiring target test data detected by multiple test units located on the wafer, including: The second set of test items includes multiple second target test items. For a single second target test item, the average of multiple test values ​​obtained from multiple test units is determined as the corresponding target test data.

6. The chip screening method according to claim 1, characterized in that, The second set of test items related to the first set of test items is determined in the wafer-level testing of the wafer containing the chip, including: Acquire first test data for the first group of test items in multiple batches, and second test data for the wafer test items in the wafer-level test; Based on the selection operation of the chip within a preset range of test points in the wafer-level test, sample data of the chip within the preset range are selected from the second test data; The wafer test item is used as the first input item, and each first target test item of the first group of test items is used as the output item. The first machine learning model is trained based on the sample data and the first test data until the deviation of the first prediction result of the first target test item relative to the corresponding first test data is less than a preset difference, and the first prediction model is obtained. Based on the first prediction model, the importance of each wafer test item to the first prediction result is obtained, so as to select candidate wafer test items from the wafer test items based on the importance. The candidate wafer test items are subjected to correlation verification with the first group of test items, so as to select the second group of test items from the candidate wafer test items based on the verification results.

7. The chip screening method according to claim 6, characterized in that, Obtaining the importance of each of the wafer test items to the first prediction result, and selecting candidate wafer test items from the wafer test items based on the importance, includes: Extract the importance attribute array from the first machine learning model, wherein the importance attribute array represents the importance of multiple wafer test items to the first prediction result; The importance attribute array is sorted, and the candidate wafer test items are selected based on the sorting results.

8. The chip screening method according to claim 6, characterized in that, The candidate wafer test items are subjected to correlation verification with the first group of test items, and the second group of test items is selected from the candidate wafer test items based on the verification results, including: Based on the circuit structure of the chip, the correlation between the candidate wafer test items and the first group of test items in terms of circuit function is analyzed, so as to obtain the initial screening results of the candidate wafer test items based on the analysis results. A validation model is constructed based on the second machine learning model to verify the second prediction result of the first set of test items when the initial screening result is used as the second input item. The second group of test items is selected from the initial screening results based on the second prediction results.

9. The chip screening method according to claim 1, characterized in that, Based on the target test data, predict the test prediction value of the first set of test items, including: Based on the actual test values ​​of the first set of test items and the target test data, the third machine learning model is trained to obtain the second prediction model. The target test data is input into the second prediction model to obtain the test prediction value of the first set of test items.

10. The chip screening method according to claim 1, characterized in that, Outlier screening is performed on the actual test values ​​of the first group of test items based on the predicted test values ​​to identify risky chips, including: A dataset is constructed based on the actual test values ​​and the predicted test values; The first set of test items includes multiple first target test items, and a mean vector is generated based on the mean of each first target test item in the dataset; Calculate the Mahalanobis distance between the actual test value and the corresponding mean vector; Chips whose Mahalanobis distance is greater than the distance threshold are identified as risk-marked chips; The risk labeling chip is subjected to reliability verification in order to determine whether the risk labeling chip belongs to the risk chip or not based on the verification results.

11. The chip screening method according to claim 10, characterized in that, The reliability verification of the risk marker chip includes: The reliability of the risk-marked chip is verified based on early failure rate testing and / or high-temperature operating life testing.

12. The chip screening method according to claim 10, characterized in that, Also includes: Based on the reliability verification results, at least one of the following is updated: the first set of test items, the second set of test items, the method for predicting the first set of test items, and the outlier screening method.

13. The chip screening method according to claim 1, characterized in that, The first set of test items used for reliability screening in the chip testing is determined, including: Based on the collected design information and reliability failure information of the chip, deductive reasoning is performed to deduce the reliability failure mechanism of the chip and determine the first set of candidate test items for detecting the failure mechanism. Based on the chi-square test, inductive reasoning is performed on the collected test data and failure records of the chip to statistically identify a second group of candidate test items related to reliability failures. The first group of candidate test items and the second group of candidate test items are mutually verified to obtain the first group of test items based on the verification results.

14. The chip screening method according to any one of claims 1 to 13, characterized in that, Testing of the chip includes chip probe testing and / or finished product testing.

15. A chip screening device, characterized in that, include: The first determining module is used to determine the first set of test items used for reliability screening in the testing of the chip; The second determining module is used to determine a second set of test items related to the first set of test items at the wafer level of the wafer where the chip is located; An acquisition module is used to acquire target test data detected by a plurality of test units located on the wafer, the test units being configured based on the second set of test items, and the plurality of test units being arranged along the circumference of the chip; The prediction module is used to predict the test prediction value of the first group of test items based on the target test data; The filtering module is used to perform outlier filtering on the actual test values ​​of the first group of test items based on the test prediction values, so as to filter out risky chips.

16. An electronic device, characterized in that, include: processor; as well as Memory for storing the executable instructions of the processor; The processor is configured to execute the chip screening method of any one of claims 1 to 14 by executing the executable instructions.

17. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the chip screening method according to any one of claims 1 to 14.

18. A computer program product having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the chip screening method according to any one of claims 1 to 14.

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