Resistance measurement method and device of circuit layout and storage medium

Abstract

A resistance measurement method and device of a circuit layout and a storage medium are disclosed. The method comprises: reading a circuit design file to obtain circuit design information; performing circuit geometric modeling based on the circuit design information, and performing mesh partitioning to determine mesh data; constructing a first improved node analysis equation set based on the mesh data, layering data, and network data; adding an equipotential constraint relationship based on preset short circuit configuration information to determine a second improved node analysis equation set; obtaining to-be-measured port information, and determining a first node and a second node in the mesh data based on the to-be-measured port information; applying a port excitation between the first node and the second node to the second improved node analysis equation set and solving to determine a first node voltage of the first node and a second node voltage of the second node; and calculating an equivalent resistance between the first node and the second node. The application has the technical effect of improving the equivalent resistance measurement efficiency of the circuit board layout.

Description

Technical Field

[0001] This disclosure relates to the field of electronic design automation technology, and more particularly to a method, apparatus, and storage medium for measuring the resistance of a circuit layout. Background Technology

[0002] In high-speed electronic circuit systems, the stability of the Power Delivery Network (PDN) is a critical factor in ensuring normal system operation. The PDN is used to deliver electrical energy from the power module to various functional modules. However, traces, copper traces, vias, pads, and interconnect structures in the circuit board or integrated circuit package all introduce resistance along the transmission path. When load current flows through these transmission paths, a DC voltage drop occurs, causing the actual supply voltage at the load end to deviate from the design value, thus affecting the operational stability of the devices and the reliability of the system.

[0003] Therefore, in the design, verification, and debugging of circuit boards and integrated circuit packages, it is necessary to accurately evaluate the equivalent resistance between power modules and load modules, as well as between any critical nodes. While existing electronic design automation (EDA) software can provide some DC resistance measurement capabilities, it typically focuses more on extracting resistance between device pins, making it difficult to flexibly support resistance analysis between arbitrary measurement points in the layout. In loop resistance measurement scenarios, it often relies on specific models such as voltage regulation modules for short-circuit settings. For non-voltage regulation module networks or complex short-circuit requirements, users may need to manually modify circuit connections, which is complex and error-prone. Therefore, how to flexibly implement resistance measurement and short-circuit configuration between arbitrary nodes in circuit layout analysis, and improve the extraction efficiency of local and loop resistances, is a problem that needs to be solved in power integrity analysis. Summary of the Invention

[0004] In view of this, embodiments of this application provide a method, apparatus and storage medium for measuring the resistance of a circuit layout, with the aim of constructing an improved set of node analysis equations based on circuit design information, and achieving efficient measurement of the equivalent resistance between target nodes in the circuit layout through short-circuit configuration and port excitation. In a first aspect, a method for measuring the resistance of a circuit layout is provided, comprising: reading a circuit design file and parsing it to obtain circuit design information, the circuit design information including layer stacking data for characterizing the structure and materials of the circuit board under test, geometric data for characterizing the shape of conductive structures in the circuit board under test, terminal data for characterizing devices and pins, and network data for characterizing electrical connection relationships; performing circuit geometric modeling based on the circuit design information and performing mesh generation to determine mesh data; constructing a first improved node analysis equation set based on the mesh data, layer stacking data, and network data; adding equipotential constraints to the first improved node analysis equation set based on preset short-circuit configuration information to determine a second improved node analysis equation set, the equipotential constraints being used to ensure that at least two nodes corresponding to the preset short-circuit configuration information are equivalently short-circuited during the solution process; obtaining the port information to be tested and determining a first node and a second node in the mesh data based on the port information to be tested; applying port excitation acting between the first node and the second node to the second improved node analysis equation set and solving it to determine the first node voltage of the first node and the second node voltage of the second node; and calculating the equivalent resistance between the first node and the second node based on the first node voltage, the second node voltage, and the port excitation.

[0005] The above-described resistance measurement method for circuit layouts can establish grid data suitable for numerical solutions and improve the set of node analysis equations based on circuit design information. It then provides an equivalent expression for preset short-circuit configurations at the equation level, and calculates the equivalent resistance by applying port excitation to the corresponding nodes of the port under test and solving for the node voltage. Compared to methods that require repeated modifications to the underlying geometric model or circuit connection topology, this application improves the flexibility of short-circuit configurations and port measurements during circuit layout analysis. Furthermore, this method transforms the resistance measurement problem in the circuit layout into an equation-solving problem, which is beneficial for improving the automation of local and loop resistance measurements and providing a more efficient and accurate resistance evaluation method for power integrity analysis and system debugging.

[0006] Optionally, the stack-up data includes: dielectric layer information, metal layer information, thickness information, and material property information; geometric data includes: polygonal geometric data used to characterize the trace shape and copper foil shape; terminal data includes: component information, pin location information, and the node number corresponding to the pin; network data includes: network information to which the pin belongs and network connection relationship.

[0007] Optionally, circuit geometry modeling is performed based on circuit design information, and meshing is performed to determine mesh data, including: constructing a circuit geometry model based on stacked data and geometric data; determining the computational region in the circuit geometry model based on network data; and meshing the computational region based on a preset meshing method to generate mesh data.

[0008] Optionally, based on mesh data, stacked data, and network data, a first improved set of node analysis equations is constructed, including: generating an improved node analysis matrix based on the material properties in the mesh data and stacked data to characterize the relationship between node voltage and branch current in the circuit layout; constructing the first improved set of node analysis equations based on the improved node analysis matrix; wherein the improved node analysis matrix includes a conductance matrix block and a voltage source constraint equation block and / or a current source constraint equation block.

[0009] Optionally, the preset short-circuit configuration information includes at least one of short-circuit node configuration information and port aggregation configuration information. The short-circuit node configuration information includes at least one of netlist short-circuit relationships, user-defined short-circuit relationships, and voltage regulation module short-circuit relationships. The short-circuit node configuration information is used to indicate at least two nodes that need to be equivalently shorted, and the port aggregation configuration information is used to indicate nodes corresponding to multiple pins that need to be aggregated into the same port. Based on the preset short-circuit configuration information, an equipotential constraint relationship is added to the first improved node analysis equation set, including: adding an equipotential constraint relationship to the first improved node analysis equation set to constrain the node voltages of at least two nodes to be equal, according to the short-circuit node configuration information; and / or adding an equipotential constraint relationship to the first improved node analysis equation set to constrain the node voltages of multiple pins corresponding to the nodes to be equal, according to the port aggregation configuration information.

[0010] Optionally, an equipotential constraint relationship is added to the first improved nodal analysis equation set, including: adding auxiliary branch variables to the first improved nodal analysis equation set; and adding voltage constraint equations to the first improved nodal analysis equation set based on the auxiliary branch variables; wherein the voltage constraint equations are used to ensure that nodes constrained by the equipotential constraint relationship have the same nodal voltage during the solution process.

[0011] Optionally, the second improved nodal analysis equation set includes a matrix part and a right-hand vector; applying port excitation acting between the first node and the second node to the second improved nodal analysis equation set includes: obtaining a preset current value corresponding to the port excitation; increasing the element in the right-hand vector corresponding to the first node by the preset current value, and decreasing the element in the right-hand vector corresponding to the second node by the preset current value; wherein, before and after applying the port excitation, the dimension and sparse structure of the matrix part of the second improved nodal analysis equation set remain unchanged.

[0012] Optionally, when measuring the resistance of multiple ports under test, the method further includes: performing matrix decomposition on the matrix part of the second improved nodal analysis equation set to obtain the matrix decomposition result; modifying the right-hand vector of the second improved nodal analysis equation set for different ports under test, and solving based on the matrix decomposition result to obtain the equivalent resistance corresponding to different ports under test; wherein, the multiple ports under test include at least one of the following: ports under test between centralized ports, ports under test between single ports, and ports under test between centralized ports.

[0013] Secondly, a resistance measurement device for a circuit layout is provided, comprising: a parsing unit for reading a circuit design file and parsing it to obtain circuit design information, the circuit design information including layer stacking data characterizing the structure and materials of the circuit board under test, geometric data characterizing the shape of conductive structures in the circuit board under test, terminal data characterizing devices and pins, and network data characterizing electrical connections; a mesh determination unit for performing circuit geometric modeling based on the circuit design information and performing mesh partitioning to determine mesh data; a first equation set construction unit for constructing a first improved node analysis equation set based on the mesh data, layer stacking data, and network data; and a second equation set construction unit for constructing a second equation set based on preset short-circuit configuration information in the second... An improved set of nodal analysis equations is constructed by adding equipotential constraints to determine a second improved set of nodal analysis equations. The equipotential constraints are used to ensure that at least two nodes corresponding to the preset short-circuit configuration information are equivalently short-circuited during the solution process. A node determination unit is used to acquire the information of the port to be measured and determine the first node and the second node in the mesh data based on the information of the port to be measured. A solution unit is used to apply the port excitation acting between the first node and the second node to the second improved set of nodal analysis equations and solve for the first node voltage of the first node and the second node voltage of the second node. A resistance calculation unit is used to calculate the equivalent resistance between the first node and the second node based on the first node voltage, the second node voltage, and the port excitation.

[0014] Thirdly, a computer-readable storage medium is provided having a computer program stored thereon, which, when executed by a processor, implements a resistance measurement method based on a circuit layout as provided in the first aspect. Attached Figure Description

[0015] The accompanying drawings used in the description of the embodiments of this disclosure are briefly introduced below: Figure 1 A schematic flowchart of a resistance measurement method for a circuit layout provided in some embodiments of this application is shown. Figure 2 A flowchart illustrating a method for determining grid data provided in some embodiments of this application is shown; Figure 3 A schematic diagram of the structure of a resistance measuring device with a circuit layout provided in some embodiments of this application is shown. Detailed Implementation

[0016] To more clearly illustrate the technical solutions in the embodiments of this disclosure, examples of implementation methods of this disclosure will be described below with reference to the accompanying drawings. The accompanying drawings described below are merely some embodiments of this disclosure. For those skilled in the art, other drawings and other implementation methods can be obtained based on these drawings without creative effort. Adjustments and improvements made without departing from the concept of this disclosure are all within the protection scope of this disclosure.

[0017] To keep the drawings simple, each figure only schematically shows the parts relevant to the embodiment, and they do not represent the actual structure of the product. In addition, for the sake of clarity and ease of understanding, some figures only schematically show parts of components with the same structure or function, and there may actually be more or fewer components with the same structure or function.

[0018] In this disclosure, unless otherwise expressly specified and limited, ordinal numbers, such as “first”, “second”, etc., are used only to distinguish and describe related objects, and should not be construed as indicating or implying the relative importance or order between related objects; furthermore, they do not represent the quantity of related objects. “Multiple” includes two or more, and other quantifiers are similar. “ / ” is used to describe the relationship between related objects, indicating an “or” relationship between them. “And / or” is used to describe the relationship between related objects, including any combination relationship between them, such as “a and / or b” including: “a alone”, “b alone”, or “a and b”. “One or more” or “at least one” of multiple objects refers to any object or any combination of multiple objects, such as “one or more of a1, a2, a3” or “at least one of a1, a2, a3” including: “a1 alone”, “a2 alone”, “a3 alone”, “a1 and a2”, “a1 and a3”, “a2 and a3”, or “a1, a2 and a3”.

[0019] In high-speed electronic circuit systems, the power distribution network (PDN) is used to transmit electrical energy output from the power module to the processor, memory, interface chips, and other functional modules. With increasing system integration, operating frequency, and load current requirements, the stability of the PDN has a more significant impact on system reliability. The conductive structures in circuit boards and integrated circuit packages, such as traces, copper foil, vias, pads, and package interconnects, are not ideal conductors and all create resistance along the power transmission path. When load current flows through these paths, a DC voltage drop occurs, causing a difference between the actual voltage received at the load and the output voltage of the power module. If the DC voltage drop is too large, the load voltage may be lower than the voltage required for normal device operation, leading to device malfunctions, logic errors, or decreased system stability. Furthermore, an improperly designed power network can also cause the load power supply state to deviate from the design expectations, thus affecting device reliability.

[0020] Therefore, accurately assessing the equivalent resistance between the power module and the load module, as well as between critical nodes, during the design and debugging phases of circuit boards or integrated circuit packages is crucial for determining the rationality of the power path, locating local impedance anomalies, and verifying the reliability of the PDN design. Typically, electronic design automation (EDA) software can analyze the stack-up structure, material properties, conductive geometry, component pins, and network connections based on the circuit layout design file, and obtain DC resistance or related power integrity analysis results through numerical solutions. Through this type of analysis, designers can determine whether there are problems in the power supply path such as excessively narrow copper traces, insufficient vias, unreasonable return paths, or local connection anomalies.

[0021] However, existing resistance measurement methods still have shortcomings in terms of flexibility and adaptability to complex measurement scenarios. On the one hand, some electronic design automation tools mainly provide resistance extraction between device pins, and the measurement objects are usually limited to predefined device terminals or ports. When designers need to locate local resistance near copper traces, traces, vias, or other critical locations on the layout, existing tools cannot directly support resistance analysis between arbitrary measurement points. On the other hand, in loop resistance measurement scenarios, existing tools often require setting up voltage regulation modules and short-circuiting them to form a specific measurement loop. For non-voltage regulation module networks, multi-point shorting, centralized port aggregation, or other complex short-circuit requirements, users may need to manually adjust the circuit connection relationships, which is cumbersome and prone to human error. In addition, in complex circuit board or package layouts, the number of nodes to be tested is large, and the combination of measurement ports is complex. If each resistance measurement requires modifying the underlying geometry model, readjusting the mesh topology, or repeatedly building the solution matrix, it will significantly increase the computational cost and affect the efficiency of single-port resistance measurement. Therefore, this application provides a resistance measurement method, apparatus, and storage medium, aiming to provide more flexible and accurate analysis means for PDN reliability assessment and circuit layout debugging.

[0022] The following description is in conjunction with the accompanying drawings: Figure 1 The diagram illustrates a flow chart of a resistance measurement method for a circuit layout according to some embodiments of this application. This resistance measurement method can be applied to power integrity analysis scenarios of circuit boards or integrated circuit packages, and includes at least the following steps: S110: Read the circuit design file and parse the circuit design information. The circuit design information includes layer stacking data to characterize the layer structure and materials of the board under test, geometric data to characterize the shape of the conductive structure in the board under test, terminal data to characterize the devices and pins, and network data to characterize the electrical connection relationships. S120: Perform circuit geometry modeling based on circuit design information, and perform mesh generation to determine mesh data; S130: Based on grid data, stacked data, and network data, construct the first improved set of node analysis equations; S140: Based on the preset short-circuit configuration information, add equipotential constraint relationship to the first improved node analysis equation set to determine the second improved node analysis equation set. The equipotential constraint relationship is used to make at least two nodes corresponding to the preset short-circuit configuration information be equivalently short-circuited during the solution process. S150: Obtain the information of the port under test, and determine the first node and the second node in the grid data based on the information of the port under test; S160: Apply port excitation acting between the first node and the second node to the second improved nodal analysis equations and solve for the first node voltage of the first node and the second node voltage of the second node. S170: Calculate the equivalent resistance between the first node and the second node based on the first node voltage, the second node voltage, and the port excitation.

[0023] In the above embodiments, the circuit layout may include conductive structures for forming a power distribution network, such as traces, copper pads, solder pads, vias, and connection structures associated with device pins. Since these conductive structures are not ideal conductors in actual circuits, different conductive paths will generate corresponding resistances during the power supply process from the power module to the load module. Therefore, by calculating the equivalent resistance between the ports under test in the circuit layout, a basis can be provided for power path evaluation, local resistance anomaly location, and loop resistance analysis. Before performing resistance measurements, the circuit design file can be read, and circuit design information can be parsed from the circuit design file. The circuit design information can be used to describe the layer structure, materials, conductive structure shapes, devices and pins, and electrical connections of the layout under test. For example, the circuit design information may include stack-up data, geometric data, terminal data, and network data. Layer stack-up data can be used to describe the dielectric layers, metal layers, and their corresponding thicknesses and material properties in the circuit diagram under test, thus providing a basis for determining the electrical characteristics of different conductive structures. Geometric data can be used to describe the shape of conductive structures such as traces and copper foil, thus providing a basis for constructing a circuit geometric model and determining the computational region. Terminal data can be used to describe the positions of components and pins, as well as the node numbers corresponding to the pins, thus providing a basis for subsequently determining the nodes corresponding to the ports under test. Network data can be used to describe the networks to which pins belong and the network connection relationships, thus providing a basis for determining the electrical connection relationships in the circuit layout. Based on this information, the circuit structure, which originally exists in the form of a layout, can be converted into a computational object suitable for numerical analysis. Furthermore, circuit geometric modeling can be performed based on circuit design information. Circuit geometric modeling can be understood as forming a geometric model to describe the region to be analyzed based on the shape of the conductive structures, layer structure, and connection relationships in the circuit diagram under test. This geometric model can reflect the position, shape, and relative relationships between different structures of the conductive regions in the circuit layout. Then, the computational region corresponding to the circuit geometric model is meshed to obtain mesh data. Mesh data can discretize a continuous conductive region into multiple nodes and mesh cells that can participate in numerical solutions, enabling the subsequent establishment of electrical solution equations based on these nodes and mesh cells.

[0024] After obtaining the mesh data, the first improved set of nodal analysis equations can be constructed by combining the overlay data and the network data. During the construction process, the overlay data provides information related to the structure and materials of the circuit board under test (DUT), while the network data provides information related to electrical connections. The first improved set of nodal analysis equations describes the constraints between node voltages, branch currents, and electrical connections in the DUT, thus transforming the DC resistance analysis problem in the circuit layout into a linear equation solving problem. This allows for subsequent numerical solutions to obtain the voltage information of the nodes under test.

[0025] In some measurement scenarios, to perform loop resistance measurements, simulate specific electrical short-circuit conditions, or meet port aggregation requirements, it is necessary to configure the node relationships in the equation set before resistance measurement. This application, based on preset short-circuit configuration information, can add equipotential constraints to the first improved node analysis equation set, ensuring that at least two nodes corresponding to the preset short-circuit configuration are considered equivalently short-circuited during the solution process. For example, for nodes that need to be electrically short-circuited, it is not necessary to modify the underlying geometric model or regenerate the mesh; instead, corresponding equipotential constraints can be added at the equation set level to ensure these nodes satisfy the equipotential relationship during the solution process. Therefore, the determined second improved node analysis equation set can reflect the short-circuit condition required for the current resistance measurement while retaining the original layout modeling results.

[0026] The port-to-test (UTP) information in this application indicates the two measurement terminals of interest in this resistance measurement. Based on the UTP information, a first node and a second node can be determined in the grid data. The first and second nodes correspond to the two ends of the UTP, respectively; they can be nodes corresponding to device pins or nodes in the layout under test corresponding to the measurement location. By assigning the UTP to specific nodes in the grid data, subsequent port excitation and node voltage extraction have a clear computational target. Subsequently, a port excitation acting between the first and second nodes can be applied to the second improved node analysis equations, creating a measurement perturbation between the first and second nodes, resulting in a voltage difference between the first and second nodes that can be used to calculate the equivalent resistance. After applying the port excitation, solving the second improved node analysis equations yields the first node voltage of the first node and the second node voltage of the second node. Since the second improved node analysis equations already reflect the electrical characteristics of the layout under test and the equipotential relationship corresponding to the preset short-circuit configuration, the first and second node voltages can reflect the potential state at both ends of the UTP under the current measurement conditions. Furthermore, combined with the port excitation, the equivalent resistance between the first and second nodes can be calculated. Therefore, the resistance measurement results between the ports under test can be obtained under the current short-circuit configuration and layout model.

[0027] The circuit layout resistance measurement method provided in this embodiment can establish grid data and improved node analysis equations suitable for numerical solutions based on circuit design information. It also provides an equivalent expression for preset short-circuit configurations at the equation level, and calculates the equivalent resistance by applying port excitation to the corresponding nodes of the port under test and solving for the node voltage. Compared to methods that require repeated modifications to the underlying geometric model or circuit connection topology, this embodiment improves the flexibility of short-circuit configuration and port measurement during circuit layout analysis. Furthermore, this method transforms the resistance measurement problem in the circuit layout into an equation-solving problem, which is beneficial for improving the automation of local resistance and loop resistance measurements, providing a more efficient and accurate resistance evaluation method for power integrity analysis and system debugging.

[0028] Figure 2 The diagram illustrates a flowchart of a method for determining mesh data provided in some embodiments of this application. Step S120 involves performing circuit geometry modeling based on circuit design information and mesh generation to determine the mesh data, including: S210: Constructing a circuit geometric model based on stacked data and geometric data; S220: Determine the computational region in the circuit geometric model based on network data; S230: The computational domain is meshed based on a preset meshing method to generate mesh data.

[0029] Mesh data can convert the layout structure in a circuit design file into discretized data that can be used for resistance calculations. When constructing the circuit geometry model, the spatial relationships between metal layers, dielectric layers, and different layers in the layout under test can be determined based on the stack-up data. Furthermore, the shape and location of conductive structures such as traces, copper pads, solder pads, and vias can be determined based on the geometric data. The resulting circuit geometry model reflects the distribution of conductive structures in the layout under test, allowing subsequent resistance analysis to be modeled not only based on the abstract connections between device pins but also on the actual shapes of the conductive structures within the layout.

[0030] When determining the computational region, network data can be used to identify electrical networks relevant to the current resistance measurement. For example, when performing DC resistance analysis on a power distribution network, the computational region can be defined as the conductive area that has an electrical connection to the power network under test, ground network, port under test, or related load pins. This avoids including all layout areas unrelated to the current measurement in the calculation, thereby reducing unnecessary calculations and focusing subsequent meshing on conductive paths related to the resistance under test.

[0031] When meshing the computational domain, continuous conductive areas can be divided into multiple mesh cells according to a preset meshing method, generating corresponding mesh nodes. The preset meshing method can be determined based on the modeling dimensions and computational accuracy requirements of the layout under test. For example, in the analysis of planar or near-planar conductive areas, a triangular mesh can be used to mesh the computational domain; when considering three-dimensional structures, a tetrahedral mesh can be used. For areas with significant current distribution changes, such as device pins, pads, vias, and connections between traces and copper foil, the mesh density can be increased to enhance the computational accuracy in these areas. For areas with more regular shapes and gentler current distribution changes, a relatively sparse mesh can be used to reduce the overall computational load.

[0032] Through the above processing, the generated mesh data can include mesh nodes, mesh cells, and the connection relationships between mesh nodes. This preserves the geometric features of the conductive structure in the circuit layout under test and provides a discretization basis for the subsequent construction of improved node analysis equations, enabling the continuous conductive structure in the circuit layout to be converted into a solvable node network.

[0033] In some embodiments of this application, a first improved node analysis equation set is constructed based on mesh data, stacked data, and network data, including: generating an improved node analysis matrix based on the material properties in the mesh data and stacked data to characterize the relationship between node voltage and branch current in the circuit layout; constructing the first improved node analysis equation set based on the improved node analysis matrix; wherein the improved node analysis matrix includes a conductance matrix block and a voltage source constraint equation block and / or a current source constraint equation block.

[0034] The first improved nodal analysis equation set can transform the meshed circuit layout into a solvable linear system. The mesh data provides the nodes and mesh cells involved in the calculation, the material properties in the stacked data provide parameters such as the conductivity of the conductive material, and the network data provides the electrical connections between different conductive structures and device pins. Based on the above data, an improved nodal analysis matrix describing the relationship between node voltage and branch current can be assembled, and the first improved nodal analysis equation set can be further formed, as shown in Equation 1 below: Formula 1 Where G is the conductance matrix, B and C are the correlation matrices of voltage source branches and / or current source branches, V is the node voltage vector, and I is the branch current vector. S For the current source term, V SThe above matrix relationships are used to characterize the relationships between node voltages, branch currents, and source constraints in the circuit layout. When constructing the first improved nodal analysis equation set, the conductivity relationships formed by the corresponding conductive structures can be determined based on each grid node and its connection relationships in the grid data, combined with the material properties in the stacked data, and these conductivity relationships are written into the conductivity matrix. For cases with voltage source branches and / or current source branches, the connection relationships between source branches and nodes can be represented by an correlation matrix, and the excitations or constraints corresponding to the source branches can be represented by current source terms and voltage source terms. Thus, the conductive structures, electrical connections, and source constraints in the circuit layout can be unified into the improved nodal analysis equation set for solution. The first improved nodal analysis equation set can be used for subsequent short-circuit configuration, port excitation, and node voltage solutions. Since the first improved nodal analysis equation set already includes the node voltage variables and branch current variables obtained from the discretization of the circuit layout, the node voltage of the node under test under specified measurement conditions can be obtained by configuring constraints and excitations in this equation set during subsequent resistance measurements.

[0035] In some embodiments of this application, the preset short-circuit configuration information includes at least one of short-circuit node configuration information and port aggregation configuration information. The short-circuit node configuration information includes at least one of netlist short-circuit relationships, user-defined short-circuit relationships, and voltage regulation module short-circuit relationships. The short-circuit node configuration information is used to indicate at least two nodes that need to be equivalently shorted, and the port aggregation configuration information is used to indicate nodes corresponding to multiple pins that need to be aggregated into the same port. Based on the preset short-circuit configuration information, an equipotential constraint relationship is added to the first improved node analysis equation set, including: adding an equipotential constraint relationship to the first improved node analysis equation set to constrain the node voltages of at least two nodes to be equal, according to the short-circuit node configuration information; and / or adding an equipotential constraint relationship to the first improved node analysis equation set to constrain the node voltages of multiple pin-corresponding nodes to be equal, according to the port aggregation configuration information.

[0036] The preset short-circuit configuration information is used to configure the node potential relationships in the first improved node analysis equation set before applying port excitation. The preset short-circuit configuration information may include at least one of short-circuit node configuration information and port aggregation configuration information. Specifically, the short-circuit node configuration information can be used to indicate nodes that need to be equivalently shorted during resistance measurement. This short-circuit node configuration information can originate from the netlist short-circuit relationships in the circuit design file, from short-circuit relationships set by the user according to measurement requirements, or from the short-circuit settings for the voltage regulation module in loop resistance measurement. For example, in a loop resistance measurement scenario, to form the corresponding measurement loop, the nodes corresponding to the relevant ports of the voltage regulation module can be configured as equivalent short-circuited nodes.

[0037] When performing equipotential configuration based on short-circuit node configuration information, equipotential constraints can be added to the first improved node analysis equation set to ensure equal node voltages. For example, if the node voltages of two nodes requiring equivalent short-circuiting are V1 and V2, a constraint V1-V2=0 can be added to the first improved node analysis equation set. This indicates that the two nodes have the same node voltage during the equation solution process, thus achieving an equivalent short circuit in electrical terms. In this way, the short-circuit relationship indicated by the short-circuit node configuration information can be reflected in the improved node analysis equation set without directly modifying the circuit geometry model or re-meshing.

[0038] Port aggregation configuration information is used to indicate the nodes corresponding to multiple pins that need to be aggregated into the same port. In centralized port measurement scenarios, one measurement port may correspond to multiple physical pins. To make these physical pins behave as the same electrical port during resistance measurement, multiple equipotential constraints can be added to the first improved node analysis equation set based on the port aggregation configuration information, so that multiple pin nodes corresponding to the same centralized port have the same node voltage. For example, a centralized port corresponds to three pin nodes with node voltages V0, V1, and V2. One of the nodes can be selected as the aggregation reference node, for example, the node with node voltage V0 can be selected as the aggregation reference node, and constraints V1-V0=0 and V2-V0=0 can be added. Through the above constraints, multiple pin nodes with node voltages V0, V1, and V2 are constrained to the same potential during the solution process, thereby forming an electrical aggregation relationship corresponding to the centralized port in the first improved node analysis equation set.

[0039] Therefore, by adding equipotential constraints to the first improved node analysis equation set based on the preset short-circuit configuration information, the second improved node analysis equation set can be determined. Compared to the first improved node analysis equation set, the second improved node analysis equation set further includes the equivalent short-circuit relationship corresponding to the short-circuit node configuration information, and / or the pin aggregation relationship corresponding to the port aggregation configuration information. Therefore, when applying port excitation and solving the equations based on the second improved node analysis equation set, the obtained node voltage can reflect the circuit state under the current short-circuit configuration or port aggregation configuration.

[0040] In some embodiments of this application, adding equipotential constraints to the first improved nodal analysis equation set includes: adding auxiliary branch variables to the first improved nodal analysis equation set; and adding voltage constraint equations to the first improved nodal analysis equation set based on the auxiliary branch variables; wherein the voltage constraint equations are used to ensure that nodes constrained by the equipotential constraint have the same nodal voltage during the solution process.

[0041] Auxiliary branch variables can be used as additional solution variables in the first improved nodal analysis equation set to represent short-circuited branches between nodes constrained by equipotential constraints, in conjunction with the voltage constraint equations. That is, in addition to the node voltage variables and branch current variables included in the original first improved nodal analysis equation set, auxiliary branch variables corresponding to the equipotential constraint can be added, allowing the equipotential constraint to be incorporated into the improved nodal analysis equation set through equation constraints.

[0042] When adding voltage constraint equations, constraints can be established to ensure equal node voltages for nodes bound by equipotential relationships. If the two constrained nodes are node j and node k, with node voltage Vj for node j and node voltage Vk for node k, then the voltage constraint equations in Formula 2 can be added as follows: Formula 2: Vj-Vk=0 The voltage constraint equation is used to ensure that nodes j and k have the same node voltage during the solution process. Auxiliary branch variables are used to allow this voltage constraint equation to participate in the solution as a constraint branch in the improved nodal analysis equation set.

[0043] In some examples, auxiliary branch variables and voltage constraint equations can be added to the first improved nodal analysis equation set in matrix expansion form. Specifically, coefficients of auxiliary branch variables can be introduced into the equation positions corresponding to nodes j and k, and constraint rows corresponding to the voltage constraint equations can be added, so that the coefficients corresponding to node j and node k in the newly added constraint rows are opposite, thereby forming an equipotential constraint of Vj-Vk=0.

[0044] When there are two or more nodes constrained by equipotential constraints, the voltage relationship between different nodes can be defined separately using multiple voltage constraint equations. For example, one node can be selected as a reference node, and voltage constraint equations can be established between the other nodes and the reference node, thus ensuring that multiple nodes maintain the same potential during the solution process. By adding auxiliary branch variables and voltage constraint equations to the first improved node analysis equation set, a second improved node analysis equation set containing equipotential constraints can be formed, making the constrained nodes appear as equivalent short-circuited states during resistance measurement.

[0045] In some implementations, the second improved node analysis equation set includes a matrix part and a right-hand vector; applying a port excitation acting between the first node and the second node to the second improved node analysis equation set includes: obtaining a preset current value corresponding to the port excitation; increasing the element in the right-hand vector corresponding to the first node by the preset current value, and decreasing the element in the right-hand vector corresponding to the second node by the preset current value; wherein, before and after applying the port excitation, the dimension and sparse structure of the matrix part of the second improved node analysis equation set remain unchanged.

[0046] The second improved nodal analysis equations can be represented as a linear relationship between the matrix part and the right-hand vector. The matrix part characterizes the node voltages, branch currents, and constraint relationships of the circuit layout under the current short-circuit configuration, while the right-hand vector characterizes the excitation terms applied to the equations. When applying port excitation between the first and second nodes, the matrix part of the second improved nodal analysis equations can be left unchanged; instead, the measurement current can be injected by adjusting the right-hand vector.

[0047] Specifically, the preset current value can be the excitation current value used for resistance measurement. In one example, the preset current value can be set to 1A. If it is necessary to apply a current source excitation corresponding to this preset current value between the first node and the second node, the preset current value can be increased in the element corresponding to the first node in the right-hand vector, and the preset current value can be decreased in the element corresponding to the second node in the right-hand vector. Thus, the first node is equivalent to being injected with the measurement current, and the second node is equivalent to flowing out the same amount of measurement current, thereby forming a port excitation for resistance measurement between the first node and the second node.

[0048] Since port excitation is achieved by adjusting the right-hand vector, the matrix portion of the second improved nodal analysis equations does not require the addition of new rows or columns before and after applying the port excitation; the dimension and sparse structure of the matrix portion can remain unchanged. Thus, after completing the short-circuit configuration, resistance measurements at different ports under test can be achieved by adjusting the right-hand vector without reconstructing the matrix portion for each port excitation. This approach helps reduce disturbances to the original equation structure and provides a basis for subsequent reuse of matrix decomposition results for multiple resistance measurements.

[0049] After solving the second improved nodal analysis equations after applying port excitation, a solution vector containing the voltages of each node can be obtained. Based on this solution vector, the first node voltage corresponding to the first node and the second node voltage corresponding to the second node can be extracted. Since a known preset current value is applied between the first and second nodes, the equivalent resistance between the first and second nodes can be calculated based on the voltage difference between the first and second node voltages and this preset current value. For example, if the node voltage of the first node s1 is Vs1 and the node voltage of the second node s2 is Vs2, the voltage difference between the two nodes can be expressed as: ΔV = Vs1 - Vs2. If the preset current value corresponding to the port excitation is I, then according to Ohm's law, the equivalent DC resistance between the two can be expressed as R = ΔV / I. Here, R represents the equivalent DC resistance between the first node s1 and the second node s2, ΔV represents the voltage difference between the first node s1 and the second node s2, and I represents the excitation current injected between the first node s1 and the second node s2.

[0050] In some embodiments, when measuring the resistance of multiple ports under test, the method further includes: performing matrix decomposition on the matrix part of the second improved nodal analysis equation set to obtain the matrix decomposition result; modifying the right-hand vector of the second improved nodal analysis equation set for different ports under test, and solving based on the matrix decomposition result to obtain the equivalent resistance corresponding to different ports under test; wherein, the multiple ports under test include at least one of the following: ports under test between centralized ports, ports under test between single ports, and ports under test between centralized ports.

[0051] After completing the short-circuit configuration, if the matrix portion of the second improved nodal analysis equations remains unchanged due to the measurement port variation, the differences among multiple ports under test mainly lie in the different excitation positions in the right-hand vector. That is, the first and second nodes corresponding to different ports under test are different. Consequently, the elements in the right-hand vector that have had their preset current values ​​increased or decreased differ, but the matrix portion describing the electrical relationships and short-circuit configuration relationships of the circuit layout can remain consistent. Therefore, the matrix portion of the second improved nodal analysis equations can be decomposed during the first measurement, and the resulting matrix decomposition can be saved. When measuring the resistance of other ports under test subsequently, it is not necessary to decompose the matrix portion again. Instead, the right-hand vector is updated according to the new port under test, and the saved matrix decomposition results are used for back-substitution. After solving, the node voltages at both ends of the new port under test can be extracted from the solution vector, and the corresponding equivalent resistance can be calculated accordingly.

[0052] In the above process, centralized port, single-port, and combined measurements can all be transformed into excitation configuration and voltage extraction for the corresponding nodes or node groups. For centralized ports formed by port aggregation, their multiple pin nodes have already been constrained to the same potential in the second improved node analysis equation set. For single-port measurements, the right-hand vector can be updated according to the excitation settings corresponding to each measurement node. Thus, resistance measurements under different port combinations can be completed using the same solution framework. Therefore, since the main changes during batch measurements are concentrated in the right-hand vector, and there is no need to repeatedly rebuild or decompose the matrix, the computational overhead of multiple resistance measurements can be reduced, and the efficiency of batch extraction of local resistance and loop resistance can be improved.

[0053] Figure 3The diagram illustrates a schematic of a resistance measurement device for a circuit layout provided in some embodiments of this application. The resistance measurement device 300 includes: a parsing unit 310, used to read circuit design files and parse them to obtain circuit design information, including layer stacking data characterizing the structure and materials of the circuit board under test, geometric data characterizing the shape of conductive structures in the circuit board under test, terminal data characterizing devices and pins, and network data characterizing electrical connections; a mesh determination unit 320, used to perform circuit geometric modeling based on the circuit design information and to perform mesh partitioning to determine mesh data; a first equation set construction unit 330, used to construct a first improved node analysis equation set based on the mesh data, layer stacking data, and network data; and a second equation set construction unit 340, used to construct a first improved node analysis equation set based on preset short-circuit configuration information in the first improved node... An equipotential constraint relationship is added to the point analysis equation set to determine the second improved node analysis equation set. The equipotential constraint relationship is used to ensure that at least two nodes corresponding to the preset short-circuit configuration information are equivalently short-circuited during the solution process. The node determination unit 350 is used to acquire the port information to be tested and determine the first node and the second node in the grid data based on the port information to be tested. The solution unit 360 is used to apply the port excitation acting between the first node and the second node to the second improved node analysis equation set and solve it to determine the first node voltage of the first node and the second node voltage of the second node. The resistance calculation unit 370 is used to calculate the equivalent resistance between the first node and the second node based on the first node voltage, the second node voltage and the port excitation.

[0054] Based on the same technical concept, this application also provides a computer-readable storage medium storing a computer program thereon, which, when executed by a processor, implements a resistance measurement method for the circuit layout provided in the above embodiments.

[0055] In the above embodiments, the descriptions of each embodiment have their own emphasis. Parts not described in detail or in a particular embodiment can be referred to in the relevant descriptions of other embodiments. Furthermore, the above embodiments can be freely combined as needed.

Claims

1. A method for measuring the resistance of a circuit layout, characterized in that, include: The circuit design file is read and parsed to obtain circuit design information, which includes layer stacking data for characterizing the structure and materials of the board under test, geometric data for characterizing the shape of the conductive structure in the board under test, terminal data for characterizing the devices and pins, and network data for characterizing the electrical connection relationships. Based on the circuit design information, perform circuit geometric modeling and mesh generation to determine the mesh data; Based on the grid data, the stacked data, and the network data, a first improved set of node analysis equations is constructed. Based on the preset short-circuit configuration information, an equipotential constraint relationship is added to the first improved node analysis equation set to determine the second improved node analysis equation set. The equipotential constraint relationship is used to make at least two nodes corresponding to the preset short-circuit configuration information equivalently short-circuited during the solution process. Obtain the information of the port to be tested, and determine the first node and the second node in the grid data based on the information of the port to be tested; Apply port excitation acting between the first node and the second node to the second improved nodal analysis equations and solve for the first node voltage of the first node and the second node voltage of the second node. Calculate the equivalent resistance between the first node and the second node based on the first node voltage, the second node voltage, and the port excitation.

2. The resistance measurement method for circuit layout according to claim 1, characterized in that, The stack-up data includes: dielectric layer information, metal layer information, thickness information, and material property information; The geometric data includes: polygonal geometric data used to characterize the trace shape and the copper foil shape; The terminal data includes: component information, pin location information, and the node number corresponding to the pin; The network data includes: information about the network to which the pin belongs and the network connection relationship.

3. The resistance measurement method for circuit layout according to claim 2, characterized in that, Based on the circuit design information, circuit geometry modeling is performed, and mesh generation is conducted to determine the mesh data, including: A circuit geometric model is constructed based on the stacked data and the geometric data; The computational region in the circuit geometric model is determined based on the network data; The computational region is meshed according to a preset meshing method to generate the mesh data.

4. The resistance measurement method for circuit layout according to claim 3, characterized in that, Based on the grid data, the stacked data, and the network data, a first improved set of node analysis equations is constructed, including: Based on the mesh data and the material properties in the stacked data, an improved node analysis matrix is ​​generated to characterize the relationship between node voltage and branch current in the circuit layout. The first improved node analysis equation set is constructed based on the improved node analysis matrix; The improved node analysis matrix includes a conductance matrix block and a voltage source constraint equation block and / or a current source constraint equation block.

5. The method for measuring resistance in a circuit layout according to claim 1, characterized in that, The preset short-circuit configuration information includes at least one of short-circuit node configuration information and port aggregation configuration information, and the short-circuit node configuration information includes at least one of netlist short-circuit relationship, user-defined short-circuit relationship and voltage regulation module short-circuit relationship. The short-circuit node configuration information is used to indicate at least two nodes that need to be equivalently shorted, and the port aggregation configuration information is used to indicate nodes corresponding to multiple pins that need to be aggregated into the same port. The step of adding equipotential constraint relationships to the first improved node analysis equation set based on preset short-circuit configuration information includes: Based on the short-circuit node configuration information, an equipotential constraint relationship is added to the first improved node analysis equation set to constrain the node voltages of the at least two nodes to be equal. And / or, Based on the port aggregation configuration information, an equipotential constraint relationship is added to the first improved node analysis equation set to constrain the node voltages of the nodes corresponding to the multiple pins to be equal.

6. The resistance measurement method for circuit layout according to claim 5, characterized in that, Add equipotential constraints to the first improved set of nodal analysis equations, including: Add auxiliary branch variables to the first improved node analysis equation set; Based on the auxiliary branch variables, voltage constraint equations are added to the first improved node analysis equation set. The voltage constraint equation is used to ensure that nodes constrained by the equipotential constraint relationship have the same node voltage during the solution process.

7. The resistance measurement method for circuit layout according to claim 1, characterized in that, The second improved nodal analysis equation set includes a matrix part and a right-hand vector; Applying port excitation acting between the first node and the second node to the second improved nodal analysis equations includes: Obtain the preset current value corresponding to the port excitation; The element corresponding to the first node in the right-end vector is increased by the preset current value, and the element corresponding to the second node in the right-end vector is decreased by the preset current value. Before and after applying the port excitation, the dimension and sparse structure of the matrix part of the second improved node analysis equation set remain unchanged.

8. The resistance measurement method for circuit layout according to claim 7, characterized in that, When measuring the resistance of multiple ports under test, the method further includes: The matrix part of the second improved node analysis equation set is decomposed to obtain the matrix decomposition result; For different ports under test, the right-hand vector of the second improved node analysis equation system is modified respectively, and the solution is performed based on the matrix decomposition result to obtain the equivalent resistance corresponding to the different ports under test; The plurality of ports to be tested includes at least one of the following: ports to be tested between centralized ports, ports to be tested between single ports, and ports to be tested between centralized ports.

9. A resistance measuring device for a circuit layout, characterized in that, include: The parsing unit is used to read the circuit design file and parse it to obtain the circuit design information. The circuit design information includes layer stacking data for characterizing the layer structure and material of the board under test, geometric data for characterizing the shape of the conductive structure in the board under test, terminal data for characterizing the devices and pins, and network data for characterizing the electrical connection relationship. The mesh determination unit is used to perform circuit geometric modeling based on the circuit design information, and to perform mesh subdivision to determine the mesh data; The first equation system construction unit is used to construct a first improved node analysis equation system based on the grid data, the stacked data, and the network data. The second equation set construction unit is used to add equipotential constraint relationships to the first improved node analysis equation set based on preset short-circuit configuration information, and determine the second improved node analysis equation set. The equipotential constraint relationships are used to make at least two nodes corresponding to the preset short-circuit configuration information be equivalently short-circuited during the solution process. A node determination unit is used to acquire information about the port to be tested, and to determine a first node and a second node in the grid data based on the information about the port to be tested. The solving unit is used to apply port excitation acting between the first node and the second node to the second improved nodal analysis equations and to solve the equations to determine the first node voltage of the first node and the second node voltage of the second node. The resistance calculation unit is used to calculate the equivalent resistance between the first node and the second node based on the first node voltage, the second node voltage, and the port excitation.

10. A computer-readable storage medium, characterized in that, It stores a computer program that, when executed by a processor, implements a resistance measurement method for a circuit layout as described in any one of claims 1 to 8.

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