A chip interconnect package analysis method based on signal integrity

Abstract

The application discloses a chip interconnection packaging analysis method based on signal integrity, and relates to the technical field of chip packaging. The method comprises the following steps: collecting basic packaging data, dividing an interconnection analysis section according to a conduction sequence, establishing a structure homology section graph and determining a structure homology healthy reference section; comparing signal integrity data, extracting a signal integrity deviation and generating a standardized signal integrity abnormality fingerprint, screening a suspected abnormal section and recording a time domain position parameter; replacing a local frequency domain response of the suspected abnormal section to form a counterfactual channel response, determining a counterfactual recovery ratio, a counterfactual recovery fingerprint and a leading abnormal section; and combining packaging defect types in a flip-chip packaging defect type library and a structure application range to determine a final mapping defect type and generate a chip interconnection packaging analysis record. The application improves the consistency of packaging defect positioning and type mapping.

Description

Technical Field

[0001] This invention relates to the field of chip packaging technology, and in particular to a chip interconnect packaging analysis method based on signal integrity. Background Technology

[0002] As high-speed chip packaging evolves towards high-density bump arrays, thin-line width heavy routing layers, and multi-layer package substrate interconnects, the transmission path from chip pads to external solder balls gradually exhibits characteristics such as multiple structural layers, complex return paths, and enhanced proximity coupling. In chip interconnect package analysis, conventional methods typically collect package layout, stack-up structure, network connectivity, and signal integrity test or simulation data. By analyzing indicators such as insertion loss, return loss, impedance continuity, crosstalk, and eye diagram margin of the target high-speed signal network, the electrical transmission status of the package interconnect channel is evaluated.

[0003] In existing analysis processes, signal integrity metrics are usually evaluated on the entire channel as a whole. The correspondence between anomaly metrics and specific interconnect structure segments is not direct enough, making it difficult to distinguish the contributions of bump connections, redistribution layer traces, package substrate vias, solder ball connections, and ground return paths to the anomaly results. In addition, conventional defect judgment lacks counterfactual verification of channel response changes before and after replacing anomaly segments, resulting in insufficient correlation between defect type mapping and the actual applicable scope of the structure. Summary of the Invention

[0004] In view of the aforementioned existing problems, the present invention is proposed.

[0005] Therefore, this invention provides a chip interconnect packaging analysis method based on signal integrity to solve the problems of unclear correspondence between abnormal indicators and specific interconnect structure segments and insufficient correlation between defect type mapping and the applicable scope of actual structure in the prior art.

[0006] To solve the above-mentioned technical problems, the present invention provides the following technical solution:

[0007] This invention provides a chip interconnect package analysis method based on signal integrity, comprising: collecting basic package data of flip-chip packages; dividing interconnect analysis segments according to the conductivity sequence from chip pads to external solder balls; establishing a structural homology segmentation diagram and determining a structural homology healthy reference segment for each interconnect analysis segment; comparing the signal integrity data of each interconnect analysis segment with the signal integrity data of the corresponding structural homology healthy reference segment; extracting the signal integrity deviation of each interconnect analysis segment; converting the signal integrity deviation according to the corresponding calibration boundary to generate a standardized signal integrity anomaly fingerprint; screening out suspected anomaly segments and recording their time-domain location parameters; and further analyzing the suspected anomaly segments. The local frequency domain response of the abnormal segment is replaced with the local frequency domain response of the corresponding structurally homologous healthy reference segment. The target interconnect path is re-cascaded to form a counterfactual channel response. The counterfactual recovery ratio and counterfactual recovery fingerprint are determined based on the counterfactual channel response, and the dominant abnormal segment is determined based on the counterfactual recovery ratio. A flip-chip package defect type library is established. The package defect types and their structural applicability ranges in the flip-chip package defect type library are read. Combined with the standardized signal integrity abnormal fingerprint, counterfactual recovery fingerprint, time-domain location parameters, and structural applicability range of the dominant abnormal segment, the final mapped defect type is determined, and a chip interconnect package analysis record is generated.

[0008] As a preferred embodiment of the chip interconnect package analysis method based on signal integrity described in this invention, the step of dividing the interconnect analysis segment according to the conductivity sequence from the chip pad to the external solder ball includes: reading conductive connection records along the connection direction of chip pads, bumps, redistribution layers, vias on the package substrate, traces on the package substrate, and external solder balls in the target high-speed signal network; setting segment boundaries at locations where the structure type changes, the metal layer changes, there is a via layer change, there is a reference ground switch, the adjacent coupling relationship changes, and the solder ball connection area is entered, thereby dividing the target high-speed signal network into several interconnect analysis segments.

[0009] As a preferred embodiment of the chip interconnect packaging analysis method based on signal integrity described in this invention, the establishment of the structural homogeneous segmentation diagram includes: forming a node set based on interconnect analysis segments; forming a conductive connection edge set based on the conductive connection relationship between adjacent interconnect analysis segments in the same target interconnect path; forming a coupling edge set based on the proximity coupling relationship between the target interconnect analysis segment and the interfering interconnect analysis segment; and forming a return edge set based on the ground return relationship between the target interconnect analysis segment and the ground return path segment; and combining the node set, conductive connection edge set, coupling edge set, and return edge set to generate the structural homogeneous segmentation diagram.

[0010] As a preferred embodiment of the chip interconnect package analysis method based on signal integrity described in this invention, the step of determining the structurally homogeneous healthy reference segment for each interconnect analysis segment includes: determining candidate healthy interconnect analysis segments according to structural reference priority; when there are several candidate healthy interconnect analysis segments within the same reference source, determining the structural homogeneity adaptation value based on structural hard constraint markers, local port consistency markers, health status markers, and geometric similarity, and determining the candidate healthy interconnect analysis segment with the largest structural homogeneity adaptation value as the structurally homogeneous healthy reference segment; the structural reference priority includes a first structural reference priority, a second structural reference priority, and a third structural reference priority, where the first structural reference priority corresponds to a qualified interconnect analysis segment in the same package layout, the second structural reference priority corresponds to an interconnect analysis segment in the same batch of qualified samples, and the third structural reference priority corresponds to a healthy interconnect analysis segment in the package design baseline data.

[0011] As a preferred embodiment of the chip interconnect packaging analysis method based on signal integrity described in this invention, the step of comparing the signal integrity data of each interconnect analysis segment with the signal integrity data of the corresponding structurally homologous healthy reference segment to extract the signal integrity deviation of each interconnect analysis segment includes: reading the signal integrity data of each interconnect analysis segment and the signal integrity data of the corresponding structurally homologous healthy reference segment according to the interconnect segment structural homologous record and local port definition; comparing the signal integrity data of each interconnect analysis segment with the signal integrity data of the corresponding structurally homologous healthy reference segment, and extracting the signal integrity deviation according to the direction of signal integrity degradation.

[0012] As a preferred embodiment of the chip interconnect packaging analysis method based on signal integrity described in this invention, the step of converting the signal integrity deviation according to the corresponding calibration boundary to generate a standardized signal integrity anomaly fingerprint, screening out suspected anomaly segments, and recording time-domain location parameters includes: configuring a corresponding calibration boundary for each type of signal integrity deviation; converting the signal integrity deviation according to the corresponding calibration boundary into a standardized anomaly intensity; arranging the corresponding standardized anomaly intensities according to a fixed order of each signal integrity deviation to form a standardized signal integrity anomaly fingerprint; when there is at least one standardized anomaly intensity greater than zero corresponding to an applicable signal integrity index in the standardized signal integrity anomaly fingerprint, marking the corresponding interconnect analysis segment as a suspected anomaly segment; comparing the time-domain impedance data of the suspected anomaly segment with the time-domain impedance data of the corresponding structurally homogeneous healthy reference segment to determine the impedance anomaly time window; and recording the time-domain location parameters according to the impedance anomaly time window.

[0013] As a preferred embodiment of the chip interconnect package analysis method based on signal integrity described in this invention, the step of replacing the local frequency domain response of the suspected abnormal segment with the local frequency domain response of the corresponding structurally homologous healthy reference segment, and re-cascading the target interconnect path to form a counterfactual channel response includes: reading the local frequency domain response data of the suspected abnormal segment and the local frequency domain response data of the corresponding structurally homologous healthy reference segment according to the suspected abnormal segment record, segment-level signal integrity record, interconnect segment structural homologous record, and local port definition; forming a local port correspondence relationship based on input port, output port, reference ground port, adjacent coupling port, and port arrangement order; replacing the cascaded transmission matrix obtained by converting the local frequency domain response of the suspected abnormal segment with the cascaded transmission matrix of the corresponding structurally homologous healthy reference segment; for interconnect analysis segments in the target interconnect path whose conductive connection sequence number is not equal to the conductive connection sequence number of the suspected abnormal segment, keeping the corresponding cascaded transmission matrix unchanged, and re-cascading the target interconnect path according to the conductive sequence from the chip pad to the external solder ball of the package to form a counterfactual channel response.

[0014] As a preferred embodiment of the chip interconnect packaging analysis method based on signal integrity described in this invention, the step of determining the counterfactual recovery ratio and counterfactual recovery fingerprint based on the counterfactual channel response, and determining the dominant anomalous segment based on the counterfactual recovery ratio, includes: recording the target interconnect path response without replacing the suspected anomalous segment as the original channel response; recording the channel response formed when each interconnect analysis segment in the target interconnect path adopts a corresponding structurally homologous healthy reference segment as the healthy reference channel response; determining the counterfactual recovery ratio based on the difference energy between the original channel response and the healthy reference channel response, and the difference energy between the counterfactual channel response and the healthy reference channel response; generating a counterfactual standardized anomalous intensity corresponding to the current replacement action based on the counterfactual channel response formed after the suspected anomalous segment is replaced, and comparing the counterfactual standardized anomalous intensity with the standardized anomalous intensity before replacement to form a counterfactual recovery fingerprint; comparing the counterfactual recovery ratios of each suspected anomalous segment, and selecting the suspected anomalous segment with the largest counterfactual recovery ratio as the dominant anomalous segment.

[0015] As a preferred embodiment of the chip interconnect packaging analysis method based on signal integrity described in this invention, the step of establishing a flip-chip packaging defect type library and reading the packaging defect types and their structural applicability ranges from the library includes: reading the process failure analysis records, packaging design rule documents, failure sample cross-section analysis records, electrical test anomaly records, and signal integrity calibration records from the R&D stage of the flip-chip package; establishing a flip-chip packaging defect type library and creating a packaging defect type record for each type; establishing the structural applicability range of the packaging defect type based on the structural category of the interconnect analysis segment; and recording the packaging defect type number, packaging defect type name, structural applicability range, anomaly reference fingerprint, recovery reference fingerprint, recovery ratio reference value, time domain location applicability range, and defect type sorting in the packaging defect type record.

[0016] As a preferred embodiment of the chip interconnect packaging analysis method based on signal integrity described in this invention, the step of determining the final mapped defect type and generating a chip interconnect packaging analysis record by combining the standardized signal integrity anomaly fingerprint, counterfactual recovery fingerprint, time-domain location parameters, and structural applicability range of the dominant anomaly segment with the packaging defect type includes: reading the segment type, layer number, bump array region, solder ball escape direction, ground return relationship, standardized signal integrity anomaly fingerprint, counterfactual recovery fingerprint, and time-domain location parameters of the dominant anomaly segment; determining the structural applicability mark based on the structural data of the dominant anomaly segment and the structural applicability range of the packaging defect type; and determining the structural applicability mark based on the time-domain location parameters of the dominant anomaly segment and the packaging defect type. The temporal location applicability range of the trap type is determined by the temporal location consistency marker. The counterfactual fingerprint mapping algorithm is used to calculate the defect mapping adaptation value by combining the structural applicability marker, the temporal location consistency marker, the standardized signal integrity anomaly fingerprint, the counterfactual recovery fingerprint, the anomaly reference fingerprint, the recovery reference fingerprint, and the recovery ratio reference value. The package defect type with the largest defect mapping adaptation value is determined as the final mapped defect type. When no less than two package defect types have the same maximum defect mapping adaptation value, the final mapped defect type is determined by combining the structural applicability marker, the temporal location consistency marker, the difference between the recovery ratio reference value and the counterfactual recovery ratio of the dominant anomaly segment, and the defect type ranking, and a chip interconnect package analysis record is generated.

[0017] The beneficial effects of this invention are as follows: by forming a counterfactual channel response, the correspondence between the dominant abnormal segment and the channel recovery contribution is realized, which facilitates the screening of the dominant abnormal segment from the suspected abnormal segments; by establishing a flip-chip package defect type library and determining the final mapped defect type, the chip interconnect package analysis record can simultaneously reflect the source of the anomaly, the recovery contribution and the defect attribution, thereby improving the consistency of package defect location and type mapping. Attached Figure Description

[0018] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the following description of the embodiments will be briefly introduced. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a flowchart of a chip interconnect packaging analysis method based on signal integrity.

[0020] Figure 2 This is a flowchart for segmenting structures with similar origins.

[0021] Figure 3 This is a flowchart for generating abnormal fingerprints.

[0022] Figure 4 A flowchart for mapping defect types.

[0023] Figure 5 This is a standardized fingerprint distribution map of signal integrity anomalies.

[0024] Figure 6 A comparison chart of counterfactual recovery ratio and defect mapping fit value. Detailed Implementation

[0025] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0026] Many specific details are set forth in the following description in order to provide a full understanding of the invention. However, the invention may also be practiced in other ways different from those described herein, and those skilled in the art can make similar extensions without departing from the spirit of the invention. Therefore, the invention is not limited to the specific embodiments disclosed below.

[0027] Secondly, the term "one embodiment" or "embodiment" as used herein refers to a specific feature, structure, or characteristic that may be included in at least one implementation of the present invention. The phrase "in one embodiment" appearing in different places in this specification does not necessarily refer to the same embodiment, nor is it a single or selective embodiment that is mutually exclusive with other embodiments.

[0028] Reference Figures 1-6 This is one embodiment of the present invention, which provides a chip interconnect package analysis method based on signal integrity, including the following steps:

[0029] S1. Collect basic packaging data of flip-chip, divide interconnect analysis segments according to the conductivity sequence from chip pads to external solder balls, establish structural homogeneous segmentation diagrams, and determine structural homogeneous health reference segments for each interconnect analysis segment.

[0030] S1.1 Read and unify the basic encapsulation data to form encapsulation analysis records.

[0031] It should be noted that the basic package data includes package layout data, package stack-up data, bump array data, solder ball array data, network connection data, and ground return path data.

[0032] Furthermore, package layout data is read from the layout design file of the flip-chip, package stack-up data is read from the package stack-up design file, bump array data is read from the chip pad and bump correspondence file, solder ball array data is read from the package substrate solder ball allocation file, network connection data is read from the package netlist file, and ground return path data is read from the package ground design file and reference ground connection record. Package analysis records are then established for the flip-chip.

[0033] It should be noted that the package layout data includes chip pad coordinates, bump coordinates, redistribution layer trace coordinates, package substrate via coordinates, package substrate trace coordinates, and solder ball coordinates; the package stack-up data includes redistribution layer metal thickness, redistribution layer dielectric thickness, package substrate conductor layer thickness, dielectric material dielectric constant, dielectric loss tangent, conductor material conductivity, and reference ground plane location; the bump array data includes bump number, bump pitch, bump diameter, bump material, corresponding chip pad number, and signal network to which the bump belongs; the solder ball array data includes solder ball number, solder ball pitch, solder ball diameter, corresponding package substrate network, and solder ball attributes; the network connection data includes signal network name, differential network pairing relationship, parallel network relationship within the same group, and port connection relationship; the ground return path data includes ground bump location, ground solder ball location, ground via location, reference ground plane connectivity, and the location of the nearest return point of the signal path.

[0034] It should be noted that the packaging analysis record includes the package product number, package batch number, chip pad coordinate source, bump array data source, redistribution layer data source, package substrate data source, solder ball array data source, network connection data source, ground return path data source, and data acquisition time.

[0035] Furthermore, the basic packaging data is standardized in terms of name and coordinates. The signal network names in the packaging layout data, network connection data, bump array data, and solder ball array data are compared for consistency. When the names of the same signal network are inconsistent in different data sources, the actual conductive connection relationship from the chip pad to the solder ball outside the package is used to form a unified network name. The coordinates of the chip pad, bump, redistribution layer, package substrate via, package substrate trace, and solder ball are converted to the same packaging coordinate reference, and the layer number in the packaging layout data is used as the layer index.

[0036] It should be noted that when the coordinates of the same conductive structure differ in different data sources, the geometric coordinates in the package layout data are used as the basis, and the conductive connection relationships in the network connection data are used as the verification basis to form a conductive connection record of the target high-speed signal network. The conductive connection record includes the name of the target high-speed signal network, chip pad number, bump number, redistribution layer trace number, package substrate via number, package substrate trace number, solder ball number, and corresponding layer number.

[0037] S1.2 Set segment boundaries according to the conductivity sequence to form the target interconnection path.

[0038] Furthermore, interconnect analysis segments are divided according to the conductivity sequence from the chip pads to the external solder balls. For any target high-speed signal network, conductive connection records are sequentially read along the connection direction of the chip pads, bumps, redistribution layers, vias on the package substrate, traces on the package substrate, and external solder balls. Segment boundaries are set at locations where the structure type changes, the metal layer changes, vias are used for layer switching, reference grounds are switched, adjacent coupling relationships change, and the network enters the solder ball connection area. The target high-speed signal network is divided into several interconnect analysis segments, and these segments together constitute the target interconnect path according to their connection sequence.

[0039] It should be noted that a change in structure type refers to a switch in the structure category between chip pads, bumps, redistribution layer traces, redistribution layer replacement structures, package substrate vias, package substrate traces, solder ball connection structures, and ground return paths; a change in the metal layer refers to the target high-speed signal network moving from one redistribution layer to another, or from one package substrate conductor layer to another; a change in reference ground refers to a change in the connection objects in the reference ground layer, ground via path, and ground bump path corresponding to the target high-speed signal network; and a change in adjacent coupling relationships refers to a change in at least one of the following: the number of adjacent interfering interconnect analysis segments, adjacent line spacing, and interlayer overlap relationships of the target high-speed signal network.

[0040] Furthermore, the interconnect analysis segment is divided into chip pad segment, bump connection segment, redistribution layer fan-out segment, redistribution layer main trace segment, redistribution layer layer change segment, package substrate via segment, package substrate trace segment, solder ball connection segment, and ground return path segment.

[0041] It should be noted that the chip pad segment corresponds to the conductive structure between the chip pad and the bump connection start point; the bump connection segment corresponds to the bump conductive structure between the chip pad and the package side connection structure; the redistribution layer fan-out segment, the redistribution layer main trace segment, and the redistribution layer layer change segment correspond to the conductors led outward from the bump connection area, the traces with stable reference ground relationship and stable adjacent coupling relationship, and the position where the layer change is completed between redistribution layers, respectively; the package substrate via segment and the package substrate trace segment correspond to the vertical conductive connection and horizontal conductive path in the package substrate, respectively; the solder ball connection segment corresponds to the conductive connection between the package substrate conductor and the solder ball outside the package; and the ground return path segment corresponds to the return path formed by the reference ground layer, ground via, ground bump, and ground solder ball of the target high-speed signal network.

[0042] Furthermore, for differential signal networks, interconnection analysis segments are established for differential positive paths and differential negative paths, and differential pairing relationships are established between similar interconnection analysis segments in differential positive paths and differential negative paths.

[0043] The differential pairing record records the correspondence between the differential positive and differential negative paths in the chip pad segment, bump connection segment, redistribution layer fan-out segment, redistribution layer main trace segment, redistribution layer layer change segment, package substrate via segment, package substrate trace segment, and solder ball connection segment.

[0044] Furthermore, for adjacent high-speed signal networks that have at least one of the following relationships with the target high-speed signal network: adjacent parallel routing, interlayer overlap, and parallel relationship within the same group, a proximity coupling relationship is established between the target interconnect analysis segment and the intrusive interconnect analysis segment; for locations where the target interconnect analysis segment has at least one of the following conditions: reference layer switching, grounding via spacing change, and grounding return path detour, a grounding return relationship is established between the target interconnect analysis segment and the grounding return path segment.

[0045] It should be noted that when the conductive connection record in the target high-speed signal network is missing any content such as endpoint coordinates, layer number, or connection object, the current conductive connection record is marked as a record with missing structural data, and the record with missing structural data will not enter the interconnect analysis segment division process; when there are branch connections in the target high-speed signal network, the main transmission path from the chip pad to the external solder ball of the target package is used as the target interconnect path, and the branch connection is recorded as an adjacent coupling relationship or a ground return relationship.

[0046] S1.3 Analyze the connection relationships of interconnected segments and establish a structurally homogeneous segmentation diagram.

[0047] Furthermore, using interconnection analysis segments as nodes and conductive connection relationships, proximity coupling relationships, and ground return relationships as edges, a structural homogeneous segmentation graph is established. The structural homogeneous segmentation graph includes a set of nodes, a set of conductive connection edges, a set of coupling edges, and a set of return edges.

[0048] It should be noted that the node set is the set formed by all interconnect analysis segments; the conductive connection edge set is the set of conductive connection relationships between adjacent interconnect analysis segments in the same target interconnect path, and is used to record the cascading order of the target interconnect path; the coupling edge set is the set of electromagnetic coupling relationships between the target interconnect analysis segment and the intrusive interconnect analysis segment, and is used to record the intrusive interconnect analysis segment that has a neighboring coupling relationship with the target interconnect path; the return edge set is the set of return relationships between the target interconnect analysis segment and the ground return path segment, and is used to record the ground return path segment in the target interconnect path.

[0049] Furthermore, in the structural homogeneous segmentation diagram, two adjacent interconnection analysis segments within the same target interconnection path are associated through conductive connection edges; the target interconnection analysis segment is associated with an intrusive interconnection analysis segment that satisfies at least one of the following conditions: adjacent parallelism, interlayer overlap, and parallelism within the same group, through coupling edges; the target interconnection analysis segment is associated with the ground return path segment formed by the corresponding reference layer, ground via, ground bump, and ground solder ball through return edges; after the structural homogeneous segmentation diagram is established, valid relationship terms in the conductive connection pre-sequence segment, conductive connection post-sequence segment, coupling intrusion segment, and ground return segment are recorded for each interconnection analysis segment.

[0050] It should be noted that for the first interconnection analysis segment of the target interconnection path, the pre-conductive connection segment is recorded as empty; for the last interconnection analysis segment of the target interconnection path, the post-conductive connection segment is recorded as empty; the empty pre-conductive connection segment or the empty post-conductive connection segment does not affect the establishment of the structural homogeneous segmentation diagram; for interconnection analysis segments without adjacent coupling relationships, the coupling interference segment is recorded as empty; for interconnection analysis segments where the ground return relationship is provided by a continuous reference stratum and there is no independent grounding via record, the ground return segment is recorded according to the reference stratum corresponding to the current interconnection analysis segment.

[0051] S1.4 Extract the structural parameters of the interconnection analysis segment and establish the structural signature.

[0052] Furthermore, a structural signature is established for each interconnection analysis segment in the structural homogeneous segmentation diagram, wherein the interconnection analysis segment number is denoted as... .

[0053] It should be noted that the structural signature includes segment type, layer number, conductor length, conductor width, conductor thickness, adjacent line spacing, interlayer spacing, number of vias, bump location, solder ball location, ground return distance, reference ground continuity mark, differential pairing mark, and parallel mark in the same group.

[0054] Among them, the segment type records the structural category of the interconnect analysis segment, the layer number records the metal layer or package substrate conductor layer where the interconnect analysis segment is located, the conductor length, conductor width and conductor thickness record the geometric dimensions of the interconnect analysis segment, the adjacent line spacing and interlayer distance record the coupling conditions between the interconnect analysis segment and the interfering interconnect analysis segment, the number of vias records the number of vertical conductive connections contained in the interconnect analysis segment, the bump position and solder ball position record the structural position of the interconnect analysis segment in the flip package array, the ground return distance records the distance from the interconnect analysis segment to the nearest continuous ground return path, the reference ground continuity mark records whether it is continuous or discontinuous, the differential pair mark records whether it is paired or unpaired, and the same group parallel mark records whether there is a same group parallel relationship or not.

[0055] Furthermore, conductor length, conductor width, conductor thickness, adjacent line spacing, interlayer distance, number of vias, bump position, solder ball position, and ground return distance are obtained from package layout data, package stack-up data, bump array data, solder ball array data, and ground return path data, or are read or converted from these data. Based on any of the following conditions—windowing, switching, or breakpoints—the reference ground continuity marker is recorded as discontinuous for the corresponding reference ground layer of the interconnect analysis segment; when the reference ground layer of the interconnect analysis segment is continuous and the ground return path does not detour, the reference ground continuity marker is recorded as continuous. Differential pairing markers are determined based on the differential network pairing relationships in the network connection data, and parallel markers are determined based on the same group of parallel network relationships in the network connection data and the adjacent relationships in the package layout data.

[0056] It should be noted that the ground return distance is recorded according to the shortest geometric distance from the center line of the interconnect analysis segment to the nearest continuous ground return path; the differential pairing mark is recorded as paired or unpaired according to the correspondence between the interconnect analysis segment and the corresponding differential interconnect analysis segment; the parallel mark of the same group is recorded as having a parallel relationship or not having a parallel relationship according to the parallel relationship between the interconnect analysis segment and the high-speed signal path of the same group recorded in the network connection data.

[0057] It should be noted that when the first When an interconnect analysis segment lacks any of the following information: layer number, conductor length, endpoint coordinates, or local port definition, the first... Each interconnect analysis segment is recorded as a segment with missing structure data. Signal integrity anomaly fingerprint extraction is not performed on segments with missing structure data.

[0058] S1.5. Based on the structural reference priority, candidate healthy interconnect analysis segments are determined, and the structural homogeneity adaptation algorithm is used to determine the structural homogeneity healthy reference segments.

[0059] Furthermore, based on structural reference priority, structurally homogeneous health reference segments are determined for interconnect analysis segments.

[0060] It should be noted that structural reference priorities include structural reference first priority, structural reference second priority, and structural reference third priority. The order of structural reference priorities is set according to the similarity of the structural source between the reference object and the current interconnect analysis segment. Structural reference first priority corresponds to qualified interconnect analysis segments in the same package layout, structural reference second priority corresponds to interconnect analysis segments in the same batch of qualified samples, and structural reference third priority corresponds to healthy interconnect analysis segments in the package design baseline data. Structural reference first priority is an interconnect analysis segment in the same package layout that has the same segment type, the same metal layer, the same bump array area, and the same solder ball escape direction as the current interconnect analysis segment and has been determined to be qualified. When structural reference first priority does not obtain a candidate healthy interconnect analysis segment, structural reference second priority is used. Structural reference second priority is an interconnect analysis segment in the same batch of qualified samples that has the same structural signature category as the current interconnect analysis segment. When structural reference second priority does not obtain a candidate healthy interconnect analysis segment, structural reference third priority is used. Structural reference third priority is a healthy interconnect analysis segment generated in the package design baseline data according to design rules, material parameters, and stack-up structure. The reference source record for structurally homogeneous healthy reference segments is structural reference first priority, structural reference second priority, or structural reference third priority.

[0061] It should be noted that the bump array region is determined based on the row and column number of the bump in the bump array data, the signal network to which the bump belongs, and the distribution of adjacent ground bumps; the solder ball escape direction is determined based on the extension direction of the solder ball to the starting point of the package substrate trace, and is recorded as one of the following: escape towards the edge of the package substrate, escape towards the center of the package substrate, or escape along the same layer transition direction of the package substrate; the structural signature category is formed based on the segment type, layer number, conductor width range, via number range, adjacent line spacing range, and ground return distance range. Among them, the conductor width range, adjacent line spacing range, and ground return distance range are set according to the design nominal values ​​in the package design rule file and the upper and lower limits of the process tolerance in the package process calibration file, and the via number range is set according to the number of similar via structures recorded in the package layout data.

[0062] It should be noted that qualified interconnect analysis segments in the same package layout are obtained through design rule checks, signal integrity benchmark simulations, and process manufacturability checks; interconnect analysis segments of the same structural signature category in the same batch of qualified samples are obtained through electrical test qualification records, appearance inspection qualification records, and sampling section verification records in the same package batch; healthy interconnect analysis segments in the package design benchmark data are obtained through package design rules, material parameters, stack-up structure, target impedance requirements, and simulation calibration records.

[0063] It should be noted that the candidate healthy interconnect analysis segment consists of qualified interconnect analysis segments or healthy interconnect analysis segments obtained under the first priority of structural reference, the second priority of structural reference, and the third priority of structural reference. The structural homology healthy reference segment is the candidate healthy interconnect analysis segment determined by the structural homology adaptation algorithm.

[0064] Furthermore, when several candidate health interconnect analysis segments exist within the same reference source, the candidate health interconnect analysis segment numbers are denoted as... The structural homology adaptation algorithm is used, and the calculation number is... Interconnection analysis segment and numbered The structural homology fit values ​​between candidate healthy interconnect segments are analyzed.

[0065] It should be noted that the structural homology adaptation algorithm is expressed as: ;

[0066] in, Indicates the number is Interconnection analysis segment and numbered Structural homology fit values ​​between candidate healthy interconnect segments. Indicates a hard constraint marker for the structure. Indicates a local port consistency flag. Indicates health status marker, Indicates the number is The conductor length of the interconnect analysis segment, Indicates the number is Conductor length of candidate healthy interconnect analysis segments, Indicates the number is The conductor width of the interconnect analysis segment, Indicates the number is The conductor width of the candidate healthy interconnect segment. Indicates the number is The spacing between adjacent lines in the interconnect analysis segment. Indicates the number is The adjacent line spacing of the candidate healthy interconnect analysis segment. Indicates the number is The ground return distance of the interconnection analysis segment. Indicates the number is The ground return distance of the candidate healthy interconnect analysis segment.

[0067] It should be noted that the structural hard constraint is marked in the numbered... Interconnection analysis segment and numbered The candidate healthy interconnect analysis segments are set to 1 if they have the same segment type, the same metal layer, the same bump array region, and the same solder ball escape direction; otherwise, they are set to 0. The local port consistency flag is set to numbered... Interconnection analysis segment and numbered The health status flag is set to 1 when candidate health interconnection analysis segments have the same number of ports and the same port arrangement order, and to 0 when the port consistency condition is not met; the health status flag is set to 0 when the number is 1. The candidate health interconnect analysis segment is set to 1 when it is obtained through qualified sample test records or package design benchmark data, and to 0 when there are no qualified source records.

[0068] It should be noted that the structural hard constraint marker, local port consistency marker, and health status marker block candidate healthy interconnect analysis segments that do not meet the structural homology condition, port consistency condition, and health origin condition. , , as well as Commonly characterizing candidate health interconnection analysis segments and numbered The relative geometric differences between interconnected segments.

[0069] Furthermore, within the same reference source, the candidate healthy interconnect analysis segment with the largest structural homology fit value is selected as the segment numbered... For interconnection analysis segments, if there is no candidate healthy interconnection analysis segment with a structural homology adaptation value greater than zero in the first priority of structural reference, the process proceeds to the second priority of structural reference. If there is no candidate healthy interconnection analysis segment with a structural homology adaptation value greater than zero in the second priority of structural reference, the process proceeds to the third priority of structural reference. After determining the structural homology healthy reference segment according to the structural reference priority, the structural homology healthy reference segment number, reference source, and structural homology adaptation value are written into the interconnection segment structural homology record.

[0070] It should be noted that when participating in the calculation of structural homology fit values... , , as well as When any value in the table lacks a valid positive value, the number is 1. Candidate healthy interconnect analysis segments are not included in the structural homology fit value calculation; when they are included in the structural homology fit value calculation... , , as well as When any value in the table lacks a valid positive value, the number is 1. Interconnection analysis segments are recorded as segments with missing structural parameters, and segments with missing structural parameters are not included in the structural homogeneity health reference segment determination process. For interconnection analysis segments without adjacent coupling relationships, the adjacent line spacing is not included in the structural homogeneity adaptation value calculation, and the structural homogeneity health reference segment is determined by segment type, metal layer, conductor length, conductor width, ground return distance, local port consistency, and health status. For interconnection analysis segments where the ground return relationship is directly provided by the continuous reference ground layer and no independent ground return distance is formed, the ground return distance is not included in the structural homogeneity adaptation value calculation, and the structural homogeneity health reference segment is determined by segment type, metal layer, conductor length, conductor width, adjacent line spacing, local port consistency, and health status.

[0071] S1.6 Configure local port definitions and generate interconnect segment structure same-source records.

[0072] Furthermore, establish common-origin records for interconnect segment structures, when the number is When the interconnect analysis segment and the structurally homologous health reference segment have the same number of ports and the same port arrangement order, the structurally homologous health reference segment is marked as a replaceable reference segment. When the number is... When the interconnect analysis segment and the candidate healthy interconnect analysis segment have any discrepancy in the number of ports or the port arrangement order, the local port consistency flag is set to 0, and the candidate healthy interconnect analysis segment is not considered as numbered... The interconnection analysis segment is a structurally homologous healthy reference segment.

[0073] It should be noted that the interconnection segment structure homogeneity record includes the interconnection analysis segment number, structure signature, structure homogeneity health reference segment number, reference source, structure homogeneity adaptation value, conductive connection pre-sequence segment, conductive connection post-sequence segment, coupling interference segment, ground return segment, differential pairing segment, and local port definition.

[0074] The local port definition includes input ports, output ports, reference ground ports, adjacent coupled ports, and the port arrangement order.

[0075] It should be noted that the input and output ports record the signal transmission direction of the interconnect analysis segment in the target interconnect path; the reference ground port records the signal return path corresponding to the interconnect analysis segment; the adjacent coupling port records the coupling response between the interconnect analysis segment and the intrusive interconnect analysis segment; and the port arrangement order records the port correspondence between the interconnect analysis segment and the structurally homologous healthy reference segment.

[0076] S2. Compare the signal integrity data of each interconnect analysis segment with the signal integrity data of the corresponding structurally homogeneous healthy reference segment, extract the signal integrity deviation of each interconnect analysis segment, convert the signal integrity deviation according to the corresponding calibration boundary, generate a standardized signal integrity anomaly fingerprint, screen out suspected anomaly segments and record the time domain location parameters.

[0077] S2.1 Read the signal integrity data of the interconnection analysis segment and form a segment-level signal integrity record.

[0078] Furthermore, based on the interconnection segment structure homogeneity record and local port definition, the signal integrity data of each interconnection analysis segment and the corresponding structural homogeneity health reference segment are read. The signal integrity data includes insertion loss data, return loss data, time domain impedance data, crosstalk data, eye diagram margin data, edge crossing time data, and local frequency domain response data.

[0079] It should be noted that insertion loss data and return loss data are read in the priority order of vector network analysis test records, packaged electromagnetic simulation records, and channel simulation records; time-domain impedance data are read in the priority order of time-domain reflection test records and frequency-domain response data conversion results; crosstalk data is read from near-end crosstalk records and far-end crosstalk records of adjacent high-speed signal networks; eye diagram margin data is read in the priority order of receiver eye diagram test records, protocol conformance test records, and high-speed channel simulation records; edge crossing time data is read in the priority order of oscilloscope sampling records, bit error rate tester sampling records, and simulation waveform records; and local frequency domain response data is read from the scattering parameter records of the corresponding local ports of the interconnect analysis section.

[0080] Furthermore, the local port definitions of the interconnect analysis segment are mapped to the local port definitions of the structurally similar healthy reference segment. Signal integrity data is read according to the order of input port, output port, reference ground port, adjacent coupling port, and port arrangement. When the frequency sampling points of the interconnect analysis segment and the structurally similar healthy reference segment are inconsistent, the frequency sampling points of the interconnect analysis segment are used as the reference to interpolate and align the frequency domain data of the structurally similar healthy reference segment. When the time domain sampling points of the interconnect analysis segment and the structurally similar healthy reference segment are inconsistent, the time domain sampling points of the interconnect analysis segment are used as the reference to interpolate and align the time domain data of the structurally similar healthy reference segment.

[0081] It should be noted that when the reference source for the structurally homologous health reference segment is the design baseline reference, the signal integrity data of the structurally homologous health reference segment is read from the packaged electromagnetic simulation record, channel simulation record, and signal integrity calibration record during the R&D phase. When the packaged electromagnetic simulation record, channel simulation record, and signal integrity calibration record during the R&D phase do not provide signal integrity data for the structurally homologous health reference segment, the corresponding interconnect analysis segment is recorded as a health reference data missing segment, and signal integrity deviation extraction is not performed on the health reference data missing segment.

[0082] It should be noted that the segment-level signal integrity record includes the interconnect analysis segment number, the structurally homogeneous health reference segment number, the local port definition, the frequency sampling point, the time domain sampling point, the insertion loss data, the return loss data, the time domain impedance data, the crosstalk data, the eye diagram margin data, the edge crossing time data, and the local frequency domain response data.

[0083] S2.2 Compare the signal integrity data of the interconnection analysis segment and the structurally homologous healthy reference segment, and extract the signal integrity deviation.

[0084] Furthermore, the signal integrity data of each interconnect analysis segment is compared with the signal integrity data of the corresponding structurally homogeneous healthy reference segment, and non-negative signal integrity deviations are extracted according to the direction of signal integrity degradation. The signal integrity deviations include insertion loss deviation, return loss deviation, local impedance change, crosstalk deviation, eye diagram compression deviation, and timing offset.

[0085] It should be noted that the insertion loss deviation is extracted based on the difference in insertion loss between the interconnect analysis segment and the structurally similar healthy reference segment within the target operating frequency band; the return loss deviation is extracted based on the difference in return loss between the interconnect analysis segment and the structurally similar healthy reference segment within the target operating frequency band; the local impedance abrupt change is extracted based on the difference in impedance abrupt change between the interconnect analysis segment and the structurally similar healthy reference segment in the time-domain impedance curve; the crosstalk deviation is extracted based on the near-end crosstalk difference and far-end crosstalk difference between the interconnect analysis segment and the intruding interconnect analysis segment; the eye diagram compression deviation is extracted based on the degree of compression of the corresponding receiver eye height margin and eye width margin of the interconnect analysis segment relative to the structurally similar healthy reference segment; and the timing offset is extracted based on the degree of offset of the edge crossing time of the interconnect analysis segment relative to the edge crossing time of the structurally similar healthy reference segment.

[0086] The target operating frequency band is determined based on the corresponding interface protocol file, package design constraint file, and high-speed signal network operating rate record of the flip-chip. When the frequency band ranges in the interface protocol file, package design constraint file, and high-speed signal network operating rate record are inconsistent, the frequency band range defined in the package design constraint file shall be used as the target operating frequency band.

[0087] Furthermore, the insertion loss deviation, return loss deviation, local impedance change, crosstalk deviation, eye diagram compression deviation, and timing offset are written into the segment-level deviation record. The segment-level deviation record is then associated with the interconnect analysis segment number, the structural homogeneous health reference segment number, and the local port definition.

[0088] It should be noted that when the current interconnect analysis segment lacks any applicable data among insertion loss data, return loss data, time domain impedance data, crosstalk data, eye diagram margin data, and edge crossing time data, the current interconnect analysis segment will be recorded as a signal integrity data missing segment. The signal integrity data missing segment will not perform standardized signal integrity anomaly fingerprint generation.

[0089] S2.3. Convert the signal integrity deviation according to the corresponding calibration boundary and generate a standardized signal integrity anomaly fingerprint.

[0090] Furthermore, a corresponding calibration boundary is configured for each type of signal integrity deviation, and the signal integrity deviation is converted into a standardized anomaly intensity according to the corresponding calibration boundary; the signal integrity index is numbered as follows. ,in, Corresponding insertion loss deviation. Corresponding return loss deviation. Corresponding to the local impedance abrupt change, Corresponding crosstalk deviation, Corresponding eye diagram compression deviation. Corresponding timing offset.

[0091] It should be noted that the calibration boundaries are set based on the packaging design specifications, protocol conformance test requirements, statistical records of qualified samples from the same batch, and signal integrity calibration records from the R&D phase, and are recorded as valid positive values; the calibration boundary corresponding to the insertion loss deviation is set based on the insertion loss tolerance within the target operating frequency band, with a value range of 0.6 to 1.5 times the insertion loss tolerance; the calibration boundary corresponding to the return loss deviation is set based on the return loss tolerance within the target operating frequency band, with a value range of 0.7 to 1.8 times the return loss tolerance; and the calibration boundary corresponding to the local impedance mutation is set based on the target impedance allowable deviation, with a value range of [missing value]. The allowable deviation is 0.5 to 1.2 times; the calibration boundary corresponding to the crosstalk deviation is set according to the crosstalk limit of the adjacent high-speed signal network, and the value range is 0.8 to 1.6 times the crosstalk limit; the calibration boundary corresponding to the eye diagram compression deviation is calculated based on the lower limit of the eye diagram margin at the receiving end, and the value range is 0.6 to 1.4 times the eye diagram compression tolerance; the calibration boundary corresponding to the timing offset is set according to the edge timing tolerance in the interface protocol, and the value range is 0.5 to 1.0 times the edge timing tolerance; the specific value of each calibration boundary is determined by the signal integrity calibration record during the R&D stage and the statistical record of the operation of qualified samples in the same batch within the corresponding value range.

[0092] Furthermore, an anomaly boundary compression transformation method is adopted to transform the numbered... The interconnection analysis segment is numbered The signal integrity deviation under the signal integrity index is converted into standardized anomaly intensity.

[0093] It should be noted that the abnormal boundary compression conversion method is expressed as follows:

[0094] ;

[0095] in, Indicates the number is The interconnection analysis segment is numbered Standardized anomaly intensity under signal integrity metrics, Indicates the number is The interconnection analysis segment is numbered The signal integrity deviation under the signal integrity index. Indicates the number is The interconnection analysis segment is numbered The calibration boundaries under the signal integrity index.

[0096] Furthermore, following a fixed order of insertion loss deviation, return loss deviation, local impedance abrupt change, crosstalk deviation, eye diagram compression deviation, and timing offset, the six standardized anomaly intensities are arranged to form a standardized signal integrity anomaly fingerprint.

[0097] It should be noted that the standardized signal integrity anomaly fingerprint is represented as follows:

[0098] ;

[0099] in, Indicates the number is The standardized signal integrity anomaly fingerprint of the interconnect analysis segment.

[0100] It should be noted that when the number is The signal integrity index is applicable to the numbered The interconnection analysis segment, and When there is a missing available calibration record, the value is empty, or the value is not greater than 0, the number is... The interconnection analysis segment is recorded as a calibration boundary missing segment. Standardized signal integrity anomaly fingerprint generation is not performed on segments with missing calibration boundaries; when the number is... The signal integrity index is applicable to the numbered The interconnection analysis segment, and When an available deviation record is missing, the number is: The interconnection analysis segment is recorded as a segment with missing deviation; segments with missing deviation do not undergo standardized signal integrity anomaly fingerprint generation; when the number is When the signal integrity metrics are not applicable to the current interconnect analysis segment, Record it as 0, and record the reason for inapplicability in the segment-level deviation record.

[0101] S2.4. Screening suspected abnormal segments based on standardized signal integrity anomaly fingerprints.

[0102] Furthermore, suspected anomalous segments are screened based on the standardized signal integrity anomaly fingerprint. The screening of suspected anomalous segments is not configured with a screening boundary independent of the standardized anomaly strength. When there is a standardized anomaly strength greater than 0 corresponding to at least one applicable signal integrity index in the standardized signal integrity anomaly fingerprint, the corresponding interconnect analysis segment is marked as a suspected anomalous segment. When the standardized anomaly strengths corresponding to all applicable signal integrity indices in the standardized signal integrity anomaly fingerprint are equal to 0, the corresponding interconnect analysis segment is recorded as an interconnect analysis segment that has not triggered anomaly boundary.

[0103] It should be noted that the suspected abnormal segment record includes the suspected abnormal segment number, the structurally homologous healthy reference segment number, the standardized signal integrity abnormal fingerprint, the signal integrity index number that triggers the abnormal boundary, and the corresponding signal integrity deviation.

[0104] Furthermore, a correspondence is established between the local frequency domain response data of the suspected abnormal segment, the local frequency domain response data of the structurally homologous healthy reference segment, the standardized signal integrity anomaly fingerprint, and the segment-level deviation record, and the local port correspondence between the suspected abnormal segment and the structurally homologous healthy reference segment is recorded.

[0105] S2.5. Record the time-domain location parameters based on the time-domain impedance data.

[0106] Furthermore, the time-domain impedance data of the suspected abnormal segment is compared with the time-domain impedance data of the corresponding structurally homologous healthy reference segment to determine the impedance anomaly time window, and the time-domain location parameters are recorded according to the impedance anomaly time window; the time-domain location parameters include the start point, end point, midpoint, width, and peak time of the impedance anomaly time window.

[0107] It should be noted that the impedance anomaly time window is determined based on the time-domain impedance difference between the suspected anomaly segment and the structurally healthy reference segment. When the impedance difference of continuous time-domain sampling points exceeds the calibration boundary corresponding to the local impedance mutation, the time range corresponding to the continuous time-domain sampling points is recorded as the impedance anomaly time window. When there are multiple impedance anomaly time windows, the impedance anomaly time window containing the largest impedance difference is selected as the source of the time-domain location parameter of the suspected anomaly segment.

[0108] Furthermore, the midpoint between the start and end of the impedance anomaly time window is recorded as the midpoint of the time-domain impedance time window, the time difference between the end and start of the impedance anomaly time window is recorded as the width of the time-domain impedance time window, and the time corresponding to the sampling point with the largest impedance difference within the impedance anomaly time window is recorded as the peak impedance anomaly time.

[0109] It should be noted that when time-domain impedance data is missing for a suspected anomaly segment, the time-domain location parameter is recorded as a state of missing time-domain data; when the time-domain impedance data of a suspected anomaly segment does not form an impedance anomaly time window, the time-domain location parameter is recorded as a state of no time-domain anomaly window formed; the states of missing time-domain data and no time-domain anomaly window formed do not affect the standardized signal integrity anomaly fingerprint recording.

[0110] In this embodiment, to verify the characterization of abnormal distributions in the target interconnect path by the standardized signal integrity anomaly fingerprint, chip pad segments, bump connection segments, redistribution layer fan-out segments, redistribution layer main trace segments, redistribution layer layer change segments, package substrate via segments, package substrate trace segments, solder ball connection segments, and ground return path segments are included in the same comparison sequence, such as... Figure 5 The standardized signal integrity anomaly fingerprint distribution map shown is in Figure 5In the data, the normalized anomaly intensity of the via segments and trace segments of the packaging substrate is greater than 0, while the normalized anomaly intensity of the chip pad segments, bump connection segments, redistribution layer fan-out segments, redistribution layer main trace segments, redistribution layer layer change segments, solder ball connection segments, and ground return path segments is equal to 0. The distribution results correspond to the concentrated positions of local impedance mutations and insertion loss deviations in the segment-level deviation records, indicating that the normalized signal integrity anomaly fingerprint can reflect the segment-level distribution of the degree of anomaly in the target interconnect path and provide data basis for suspected anomaly segment records and time-domain location parameter records.

[0111] S3. Replace the local frequency domain response of the suspected abnormal segment with the local frequency domain response of the corresponding structurally homologous healthy reference segment, re-cascade the target interconnection path to form a counterfactual channel response, determine the counterfactual recovery ratio and counterfactual recovery fingerprint based on the counterfactual channel response, and determine the dominant abnormal segment based on the counterfactual recovery ratio.

[0112] S3.1 Read the local frequency domain response of the suspected abnormal segment to form a counterfactual substitution record.

[0113] Furthermore, based on the suspected abnormal segment records, segment-level signal integrity records, interconnection segment structural homology records, and local port definitions, the local frequency domain response data of each suspected abnormal segment is read, and the local frequency domain response data of the corresponding structural homology healthy reference segment is also read. The local frequency domain response data of the suspected abnormal segment and the local frequency domain response data of the structural homology healthy reference segment are matched according to the input port, output port, reference ground port, adjacent coupling port, and port arrangement order to form a counterfactual replacement record.

[0114] It should be noted that the counterfactual replacement record includes the suspected anomalous segment number, the structurally homologous healthy reference segment number, the target interconnect path number, the frequency sampling point, the local frequency domain response data of the suspected anomalous segment, the local frequency domain response data of the structurally homologous healthy reference segment, the local port correspondence, and the replaceable reference segment marker.

[0115] Furthermore, when the frequency sampling point of the suspected abnormal segment is inconsistent with the frequency sampling point of the structurally homologous healthy reference segment, the local frequency domain response data of the structurally homologous healthy reference segment is interpolated and aligned based on the frequency sampling point of the suspected abnormal segment; when the suspected abnormal segment and the structurally homologous healthy reference segment have any inconsistency in the number of ports or the port arrangement order, the suspected abnormal segment is recorded as a port inconsistency segment, and the local frequency domain response replacement is not performed on the port inconsistency segment.

[0116] It should be noted that interpolation alignment is performed using frequency sampling points within the target operating frequency band. The target operating frequency band is determined based on the interface protocol file, package design constraint file, and high-speed signal network operating rate record corresponding to the flip-chip. When the frequency band ranges in the interface protocol file, package design constraint file, and high-speed signal network operating rate record are inconsistent, the frequency band range defined in the package design constraint file is used as the target operating frequency band. When the structurally homogeneous healthy reference segment lacks local frequency domain response data within the target operating frequency band, the suspected abnormal segment is recorded as a healthy local response missing segment, and the counterfactual channel response formation is not performed on the healthy local response missing segment.

[0117] S3.2 Replace the local frequency domain response and re-cascade the target interconnect path to form a counterfactual channel response.

[0118] Furthermore, according to the conductivity sequence from the chip pads to the external solder balls of the package, the local frequency domain response data of each interconnect analysis segment in the target interconnect path is read, and the local frequency domain response data of each interconnect analysis segment is converted into a cascaded transfer matrix; the cascaded transfer matrix of the suspected abnormal segment is replaced with the cascaded transfer matrix of the corresponding structurally homologous healthy reference segment; for the interconnect analysis segment in the target interconnect path whose conductivity connection sequence number is not equal to the conductivity connection sequence number of the suspected abnormal segment, the corresponding cascaded transfer matrix is ​​kept unchanged, and the target interconnect path is re-cascaded to form a counterfactual cascaded matrix.

[0119] It should be noted that the frequency sampling point number is denoted as The conductive connection sequence number of the suspected abnormal segment in the target interconnect path is recorded as follows: The total number of interconnect analysis segments participating in cascading according to the conductive connection order within the target interconnect path is denoted as . , will be numbered The interconnection analysis segment is numbered The cascaded transfer matrix at the frequency sampling points is denoted as The conductive connection sequence is numbered as follows The suspected abnormal segment corresponds to a structurally homologous healthy reference segment in the numbered section. The cascaded transfer matrix at the frequency sampling points is denoted as The conductive connection sequence is numbered as follows The counterfactual cascade matrix after the suspected anomalous segment is replaced is denoted as .

[0120] It should be noted that the counterfactual cascade matrix is ​​represented as:

[0121] ;

[0122] It should be noted that, according to Increasing from 1 to Execute matrix concatenation sequentially. according to from Increment to Execute matrix concatenation sequentially; when hour, Not participating in matrix cascading; when hour, It does not participate in matrix cascading.

[0123] Furthermore, the counterfactual cascade matrix is ​​converted into scattering parameter form, and the counterfactual channel response is extracted according to the input and output ports of the target interconnection path. The target interconnection path response when the suspected abnormal segment is not replaced is recorded as the original channel response, and the channel response formed when each interconnection analysis segment in the target interconnection path adopts the corresponding structural homogeneous healthy reference segment is recorded as the healthy reference channel response.

[0124] It should be noted that the conductive connection sequence is numbered as follows: The counterfactual channel response formed after the suspected anomalous segment is replaced is denoted as The original channel response is denoted as Record the health reference channel response as ,in, Indicates a health reference.

[0125] It should be noted that when there is local frequency domain response data in the target interconnect path that cannot be converted into a concatenated transmission matrix, the corresponding suspected abnormal segment will be recorded as a counterfactual concatenated missing segment, and the counterfactual recovery ratio calculation will not be performed on the counterfactual concatenated missing segment; when there is an interconnect analysis segment in the target interconnect path with an incomplete port arrangement order, the corresponding suspected abnormal segment will be recorded as a port concatenated missing segment, and the counterfactual channel response formation will not be performed on the port concatenated missing segment.

[0126] S3.3. Compare the counterfactual channel response with the healthy reference channel response to determine the counterfactual recovery ratio.

[0127] Furthermore, the original channel response, counterfactual channel response, and healthy reference channel response are compared within the target operating frequency band to calculate the original channel difference energy and the counterfactual channel difference energy. The original channel difference energy records the degree of difference between the target interconnect path and the healthy reference channel response when the suspected abnormal segment is not replaced, while the counterfactual channel difference energy records the degree of difference between the target interconnect path and the healthy reference channel response after the suspected abnormal segment is replaced.

[0128] It should be noted that the calculation of the original channel difference energy and the counterfactual channel difference energy is expressed as follows:

[0129] ;

[0130] ;

[0131] in, This represents the original channel difference energy. The conductive connection sequence number is indicated as follows: The counterfactual channel difference energy after the suspected anomalous segment is replaced This indicates the total number of frequency sampling points within the target operating frequency band.

[0132] Furthermore, the counterfactual recovery ratio is determined based on the original channel difference energy and the counterfactual channel difference energy. When the counterfactual channel difference energy is less than the original channel difference energy after replacing the suspected abnormal segment, the counterfactual recovery ratio is recorded according to the degree of reduction in difference energy. When the counterfactual channel difference energy is greater than or equal to the original channel difference energy, the counterfactual recovery ratio is recorded as 0.

[0133] It should be noted that when and At that time, the counterfactual restoration ratio is expressed as:

[0134] ;

[0135] It should be noted that when or At that time, the counterfactual restoration ratio is expressed as:

[0136] ;

[0137] in, The conductive connection sequence number is indicated as follows: The counterfactual recovery rate of suspected abnormal segments.

[0138] It should be noted that when the original channel difference energy is equal to 0, the degree of difference energy reduction is not calculated, and the counterfactual recovery ratio is recorded as 0; when the healthy reference channel response is missing, the suspected abnormal segment is recorded as the healthy channel response missing segment, and the counterfactual recovery ratio is not calculated for the healthy channel response missing segment.

[0139] S3.4. Based on the standardized anomaly intensity changes, a counterfactual recovery fingerprint is formed.

[0140] Furthermore, they are numbered according to the conductive connection sequence. The counterfactual channel response formed after the suspected abnormal segment is replaced is used to extract the counterfactual signal integrity deviation of the target interconnect path. According to the rule that the signal integrity deviation exceeds the corresponding calibration boundary, logarithmic compression transformation is performed, and the signal integrity deviation is recorded as 0 when it does not exceed the corresponding calibration boundary, the counterfactual standardized anomaly intensity corresponding to the current replacement action is generated. The counterfactual standardized anomaly intensity is compared with the standardized anomaly intensity before replacement to determine the recovery component of each signal integrity index.

[0141] It should be noted that the conductive connection sequence is numbered as follows: After the suspected abnormal segment was replaced, in segment numbered The counterfactual normalized anomaly intensity formed under the signal integrity index is denoted as The conductive connection sequence is numbered as follows The suspected abnormal segment is numbered The recovered component under the signal integrity index is denoted as .

[0142] It should be noted that the recovery component is represented as:

[0143] ;

[0144] in, The conductive connection sequence number is indicated as follows: After the suspected abnormal segment was replaced, in segment numbered The counterfactual standardized anomaly strength formed under the signal integrity index, The conductive connection sequence number is indicated as follows: The suspected abnormal segment is numbered The recovered component under the signal integrity index.

[0145] Furthermore, the counterfactual recovery ratio and the recovery components of each signal integrity index are arranged in a fixed order to form a counterfactual recovery fingerprint; the fixed order is counterfactual recovery ratio, insertion loss recovery component, return loss recovery component, local impedance recovery component, crosstalk recovery component, eye diagram recovery component, and timing recovery component.

[0146] It should be noted that counterfactual fingerprint recovery is represented as follows:

[0147] ;

[0148] in, The conductive connection sequence number is indicated as follows: Counterfactual recovery fingerprint of suspected abnormal segments.

[0149] It should be noted that when the number is The signal integrity index is recorded in the segment-level deviation record as not applicable to the conductive connection sequence number. When a suspected abnormal segment is encountered, The record is 0, and the reason for inapplicability is retained in the counterfactual recovery fingerprint record; when the counterfactual normalized anomaly strength lacks available calculation records, the conductive connection sequence is numbered as follows. The suspected abnormal segment record is the fingerprint missing segment recovery, and the fingerprint missing segment recovery does not enter the main abnormal segment determination process.

[0150] S3.5. Screen suspected abnormal segments based on the counterfactual recovery ratio and determine the dominant abnormal segment.

[0151] Furthermore, the counterfactual recovery ratios of each suspected anomaly segment are compared, and the suspected anomaly segment with the largest counterfactual recovery ratio is selected as the dominant anomaly segment. When at least two suspected anomaly segments have the same maximum counterfactual recovery ratio, the suspected anomaly segment with the most signal integrity indicators with a recovery component greater than 0 in the counterfactual recovery fingerprint is selected as the dominant anomaly segment. When the number of signal integrity indicators with a recovery component greater than 0 is still the same, the suspected anomaly segment with a conductive connection sequence closer to the chip pad in the target interconnect path is selected as the dominant anomaly segment.

[0152] It should be noted that the dominant anomaly segment record includes the dominant anomaly segment number, the corresponding structural homologous healthy reference segment number, the counterfactual channel response, the counterfactual recovery ratio, the counterfactual recovery fingerprint, the standardized signal integrity anomaly fingerprint, and the time-domain location parameters.

[0153] Furthermore, when none of the suspected abnormal segments have achieved a counterfactual recovery ratio, the target interconnect path is recorded as having insufficient counterfactual recovery. When the target interconnect path is recorded as having insufficient counterfactual recovery, the standardized signal integrity anomaly fingerprint, time-domain location parameters, and local frequency-domain response data of each suspected abnormal segment are retained, and the insufficient counterfactual recovery state is written into the chip interconnect package analysis record.

[0154] S4. Establish a flip-chip package defect type library, read the package defect types and their structural applicability ranges from the flip-chip package defect type library, combine the standardized signal integrity anomaly fingerprint, counterfactual recovery fingerprint, time-domain location parameters, and structural applicability range of the dominant anomaly segment to determine the final mapped defect type, and generate chip interconnect package analysis records.

[0155] S4.1 Establish a flip-chip packaging defect type library to form packaging defect type records.

[0156] Furthermore, the process failure analysis records, packaging design rule documents, failure sample cross-section analysis records, electrical test anomaly records, and signal integrity calibration records during the R&D phase of the flip-chip are read to establish a flip-chip defect type library, and a packaging defect type record is generated for each type of packaging defect.

[0157] It should be noted that the types of packaging defects include bump cracking defects, bump solder joint defects, bump bridging defects, redistribution layer open circuit defects, redistribution layer necking defects, redistribution layer short circuit defects, via void defects in the packaging substrate, via high resistance defects in the packaging substrate, trace impedance abrupt change defects in the packaging substrate, solder ball void defects, solder ball crack defects, ground return path discontinuity defects, and missing reference ground shielding defects.

[0158] It should be noted that the encapsulation defect type record includes the encapsulation defect type number, encapsulation defect type name, structural applicable scope, anomaly reference fingerprint, recovery reference fingerprint, recovery ratio reference value, time domain location applicable scope, and defect type sorting.

[0159] Furthermore, based on the structural categories of interconnect analysis segments, the applicable structural scope of packaging defect types is established: the applicable structural scope of bump cracking defects, bump solder joint defects, and bump bridging defects corresponds to bump connection segments; the applicable structural scope of redistribution layer open circuit defects, redistribution layer necking defects, and redistribution layer short circuit defects corresponds to redistribution layer fan-out segments, redistribution layer main trace segments, and redistribution layer layer replacement segments; the applicable structural scope of packaging substrate via void defects and packaging substrate via high resistance defects corresponds to packaging substrate via segments; the applicable structural scope of packaging substrate trace impedance abrupt change defects corresponds to packaging substrate trace segments; the applicable structural scope of solder ball void defects and solder ball crack defects corresponds to solder ball connection segments; the applicable structural scope of ground return path discontinuity defects and reference ground shielding missing defects corresponds to ground return path segments, and the interconnect analysis segments marked as discontinuous based on reference ground continuity are recorded.

[0160] It should be noted that the anomaly reference fingerprint is generated from known defective samples in the process failure analysis record, defective injected samples in the packaging electromagnetic simulation record, and signal integrity calibration record during the R&D phase; the recovery reference fingerprint is generated from the recovery component record formed after performing local frequency domain response health replacement on the known defective sample; the recovery ratio reference value is generated from the counterfactual recovery ratio running statistics record of the known defective sample; the applicable range of the time domain position is generated by conversion based on the conductive length of the interconnect analysis segment, the medium propagation conditions, and the time domain reflection calibration record; the defect type is sorted from high to low according to the process failure analysis statistical frequency of the same package product type.

[0161] S4.2 Read the structural data of the dominant anomaly segment and determine the applicable structural marker and the time-domain position consistent marker.

[0162] Furthermore, based on the dominant anomaly segment record, interconnection segment structure homogeneity record, and segment-level deviation record, the segment type, layer number, bump array region, solder ball escape direction, ground return relationship, differential pairing mark, parallel group mark, standardized signal integrity anomaly fingerprint, counterfactual recovery fingerprint, and time-domain location parameters of the dominant anomaly segment are read, and a correspondence is established with the packaging defect type record in the flip-chip packaging defect type library.

[0163] It should be noted that the time-domain location parameters of the dominant anomaly segment include the start point, end point, midpoint, width, and peak time of the time-domain impedance time window. When the dominant anomaly segment is recorded as either a time-domain data missing state or a state where no time-domain anomaly window has been formed, the dominant anomaly segment is synchronously recorded as a time-domain location missing state, and a time-domain location consistency marker is determined based on the time-domain location missing state.

[0164] Furthermore, the conductive connection sequence number of the dominant abnormal segment in the target interconnect path is retained and denoted as... The packaging defect type number is recorded as Based on the segment type, layer number, bump array region, solder ball escape direction, and ground return relationship of the dominant anomaly segment, the conductive connection sequence number is determined as follows: The dominant anomaly segment relative to the numbered The structure of the encapsulation defect type is subject to the applicable marker; when the structure data of the dominant exception segment falls into the numbered When determining the applicable scope of the encapsulation defect type, the applicable structure flag is recorded as 1. If the structural data of the dominant anomaly segment does not fall within the numbered range... When the structure applicable to the encapsulation defect type is within its scope, the structure applicable flag is recorded as 0.

[0165] It should be noted that the conductive connection sequence is numbered as follows: The dominant anomaly segment relative to the numbered The structural designation applicable to the type of encapsulation defect is denoted as... .

[0166] Furthermore, based on the temporal location parameters and numbering of the dominant anomaly segment... The applicable range of the time-domain location for the encapsulation defect type is determined, and a consistent time-domain location marker is established; when any time in the impedance anomaly peak time or the midpoint of the time-domain impedance time window falls within the numbered... When the time-domain location of the encapsulation defect type is within the applicable range, the time-domain location is consistently marked as 1; when neither the peak time of the impedance anomaly nor the midpoint of the time-domain impedance time window falls within the range numbered... When the time-domain location of the encapsulation defect type is within the applicable range, the time-domain location is marked as 0.

[0167] It should be noted that the conductive connection sequence is numbered as follows: The dominant anomaly segment relative to the numbered The temporal location consistency marker for the encapsulation defect type is denoted as When the dominant anomaly segment is recorded as having a missing time-domain location, Record it as 1, and record the missing time domain location in the chip interconnect package analysis record.

[0168] S4.3. Combine the abnormal fingerprint and the recovered fingerprint to calculate the defect mapping adaptation value.

[0169] Furthermore, the standardized anomaly intensity corresponding to each signal integrity index is read from the standardized signal integrity anomaly fingerprint of the dominant anomaly segment; the counterfactual recovery ratio and the recovery components corresponding to each signal integrity index are read from the counterfactual recovery fingerprint of the dominant anomaly segment; and the numbered... The encapsulation defect type corresponds to the anomaly reference fingerprint, recovery reference fingerprint, and recovery ratio reference value. A reverse fact fingerprint mapping algorithm is used to calculate the defect mapping adaptation value. When the structure applicability flag is 0 or the temporal location consistency flag is 0, the number is... The defect mapping adapter value for the encapsulation defect type is recorded as 0, and the number is... The encapsulation defect type is recorded as a structural location mismatch defect type; when the applicable structural marker is 1 and the temporal location is also marked as 1, the reserved number is... Defect mapping adapter value for encapsulation defect type.

[0170] It should be noted that the counterfactual fingerprint mapping algorithm is expressed as:

[0171] ;

[0172] ;

[0173] ;

[0174] in, The conductive connection sequence number is indicated as follows: The dominant anomaly segment relative to the numbered The consistency factor of the abnormal fingerprint of the encapsulation defect type. The conductive connection sequence number is indicated as follows: The dominant anomaly segment relative to the numbered Recovery fingerprint consistency factor for encapsulation defect types, Indicates the number is The packaging defect type is numbered as follows: Abnormal reference components under the signal integrity index Indicates the number is The packaging defect type is numbered as follows: The recovery reference component under the signal integrity index, Indicates the number is The recovery ratio reference value for the type of packaging defect. The conductive connection sequence number is indicated as follows: The dominant anomaly segment relative to the numbered Defect mapping adapter value for encapsulation defect type.

[0175] It should be noted that the abnormal reference component, recovery reference component, and recovery ratio reference value are all read from the packaging defect type record in the flip-chip packaging defect type library, and the value range is 0 to 1; when the number is When the signal integrity index is recorded in the segment-level deviation record as not applicable to the dominant abnormal segment. and All are recorded as 1, and the reason for inapplicability is recorded in the chip interconnect packaging analysis record; when any record of the abnormal reference component, recovery reference component, and recovery ratio reference value is missing, the packaging defect type with the number is not used as the final mapping defect type determination object, and the reason for the missing reference record is recorded in the chip interconnect packaging analysis record.

[0176] It should be noted that the components involved in the defect mapping fit value calculation are... , , , , as well as All values ​​are read from the standardized signal integrity anomaly fingerprint, counterfactual recovery fingerprint, and flip-chip package defect type library. When any value involved in the calculation does not fall within the range of 0 to 1, the corresponding package defect type is not used as the final mapping defect type determination object, and the reason for the abnormal value is recorded in the chip interconnect package analysis record.

[0177] S4.4 Compare the defect mapping fit values ​​to determine the final mapped defect type.

[0178] Furthermore, for each package defect type in the flip-chip package defect type library, the defect mapping adaptation value is calculated one by one. When the structure applicability mark is 0 or the temporal location consistency mark is 0, the defect mapping adaptation value of the corresponding package defect type is recorded as 0, and the corresponding package defect type is recorded as a structure location mismatch defect type. Configure the defect mapping adaptation lower limit threshold. From the package defect types with a structure applicability mark of 1, a temporal location consistency mark of 1, and a defect mapping adaptation value not lower than the defect mapping adaptation lower limit threshold, select the package defect type with the largest defect mapping adaptation value as the final mapped defect type. When there is no package defect type with a defect mapping adaptation value not lower than the defect mapping adaptation lower limit threshold, the final mapped defect type is recorded as an unmatched defect type, and the standardized signal integrity anomaly fingerprint, counterfactual recovery fingerprint, temporal location parameters, and defect mapping adaptation values ​​of each package defect type of the dominant anomaly segment are retained in the chip interconnect package analysis record.

[0179] It should be noted that the lower limit threshold for defect mapping adaptation is determined based on the distribution of defect mapping adaptation values ​​for known defective samples and the distribution of defect mapping adaptation values ​​for non-defective samples, and the value range is from 0.30 to 0.80.

[0180] It should be noted that when at least two encapsulation defect types have the same maximum defect mapping fit value, the encapsulation defect types with the same maximum defect mapping fit value and the structural applicability mark 1 and the temporal location consistent mark 1 are selected from the encapsulation defect types with the same maximum defect mapping fit value; when only one encapsulation defect type is retained after selection, the encapsulation defect type retained after selection is determined as the final mapping defect type; when at least two encapsulation defect types still meet the conditions after selection, the encapsulation defect type with the smallest difference between the recovery ratio reference value and the counterfactual recovery ratio of the dominant anomaly segment is selected as the final mapping defect type; when at least two encapsulation defect types still meet the conditions, the final mapping defect type is determined according to the defect type sorting in the flip-chip encapsulation defect type library.

[0181] Furthermore, a correspondence is established between the final mapped defect type and the dominant abnormal segment number, the structural homology healthy reference segment number, the standardized signal integrity abnormal fingerprint, the counterfactual recovery fingerprint, the temporal location parameter, the structural applicability mark, the temporal location consistency mark, and the defect mapping adaptation value, forming a defect mapping result record.

[0182] S4.5 Summarize the defect mapping results and process records to generate chip interconnect packaging analysis records.

[0183] Furthermore, based on the packaging analysis record, interconnect segment structure homogeneity record, segment-level signal integrity record, segment-level deviation record, suspected abnormal segment record, dominant abnormal segment record, and defect mapping result record, a chip interconnect packaging analysis record is generated.

[0184] It should be noted that the chip interconnect package analysis record includes the package product number, package batch number, target high-speed signal network name, target interconnect path number, dominant anomaly segment number, dominant anomaly segment segment type, structural homogeneous health reference segment number, standardized signal integrity anomaly fingerprint, counterfactual channel response, counterfactual recovery ratio, counterfactual recovery fingerprint, time-domain location parameters, final mapping defect type, defect mapping adaptation value, structural applicability mark, time-domain location consistency mark, structural data missing status, health reference data missing status, calibration boundary missing status, deviation missing status, time-domain data missing status, counterfactual cascade missing status, health channel response missing status, recovery fingerprint missing status, and missing reason code.

[0185] It should be noted that the missing reason code is used to record the source of data missing in the chip interconnect package analysis record. When any content in the layer number, conductor length, endpoint coordinates, or local port definition of the interconnect analysis segment is missing, the structural data missing status is recorded as 1, and the missing reason code is recorded as structural data missing. When the signal integrity data of the structural homogeneous healthy reference segment is missing, the healthy reference data missing status is recorded as 1, and the missing reason code is recorded as healthy reference data missing. When the calibration boundary lacks available calibration records, has an empty value, or has a value not greater than 0, the calibration boundary missing status is recorded as 1, and the missing reason code is recorded as calibration boundary missing. When the signal integrity deviation lacks available deviation records, the deviation missing status is recorded as 1, and the missing reason code is recorded as deviation. Data loss is recorded as follows: When time-domain impedance data is missing in a suspected anomaly segment, the time-domain data loss status is recorded as 1, and the loss reason code is recorded as time-domain data loss; when there is local frequency-domain response data in the target interconnect path that cannot be converted into a cascaded transmission matrix, the counterfactual cascade loss status is recorded as 1, and the loss reason code is recorded as counterfactual cascade loss; when the healthy reference channel response is missing, the healthy channel response loss status is recorded as 1, and the loss reason code is recorded as healthy channel response loss; when the counterfactual normalized anomaly strength lacks available calculation records, the recovery fingerprint loss status is recorded as 1, and the loss reason code is recorded as recovery fingerprint loss; when there is no data loss in the chip interconnect package analysis record, all loss statuses are recorded as 0, and the loss reason code is recorded as no loss.

[0186] Furthermore, when the final mapped defect type is an unmatched defect type, the standardized signal integrity anomaly fingerprint, counterfactual recovery fingerprint, time-domain location parameters, structural data of the dominant anomaly segment, defect mapping adaptation values ​​for each package defect type, and defect mapping adaptation lower limit threshold of the dominant anomaly segment are retained in the chip interconnect package analysis record. When the target interconnect path has recorded a counterfactual recovery insufficiency state, the counterfactual recovery insufficiency state is written into the chip interconnect package analysis record. When the final mapped defect type is a package defect type in the flip package defect type library, the package defect type number, package defect type name, and structural applicable scope corresponding to the final mapped defect type are written into the chip interconnect package analysis record.

[0187] In this embodiment, to verify the data correlation of counterfactual channel responses in the defect type mapping, bump solder joint defects, redistribution layer necking, high via resistance of the package substrate, abrupt impedance changes in the package substrate traces, solder ball cracks, and discontinuities in the ground return path are included in the same comparison sequence, such as... Figure 6 The comparison chart shown here, comparing the counterfactual recovery ratio with the defect mapping fit value, is in... Figure 6 In the comparison, the counterfactual recovery ratio and defect mapping adaptation value corresponding to high via resistance of the package substrate ranked first among the six types of comparative defects, while the counterfactual recovery ratio and defect mapping adaptation value corresponding to abrupt change in trace impedance of the package substrate ranked second. The defect mapping adaptation value of high via resistance of the package substrate was higher than that of bump solder joint failure, necking of redistribution layer, abrupt change in trace impedance of package substrate, solder ball crack, and discontinuity of ground return path, respectively. Moreover, the structural applicability range of high via resistance of the package substrate matched the segment type of the dominant anomaly segment. The results show that there is a consistent correspondence between the local frequency domain response replacement result of the dominant anomaly segment, the counterfactual recovery fingerprint, and the structural applicability range in the flip-chip package defect type library, which can provide a basis for the final determination of the mapped defect type.

[0188] In summary, this invention achieves the correspondence between the dominant anomaly segment and the channel recovery contribution by forming a counterfactual channel response, which facilitates the screening of the dominant anomaly segment from the suspected anomaly segments; and by establishing a flip-chip package defect type library and determining the final mapped defect type, the chip interconnect package analysis record can simultaneously reflect the anomaly source, recovery contribution, and defect attribution, thereby improving the consistency of package defect location and type mapping.

[0189] It should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.

Claims

1. A chip interconnect packaging analysis method based on signal integrity, characterized in that, include: Collect basic packaging data of flip-chip, divide interconnect analysis segments according to the conductivity sequence from chip pads to external solder balls, establish structural homology segmentation diagrams, and determine structural homology health reference segments for each interconnect analysis segment; The signal integrity data of each interconnect analysis segment is compared with the signal integrity data of the corresponding structurally homogeneous healthy reference segment. The signal integrity deviation of each interconnect analysis segment is extracted, and the signal integrity deviation is converted according to the corresponding calibration boundary to generate a standardized signal integrity anomaly fingerprint. Suspected anomaly segments are screened out and their time-domain location parameters are recorded. The local frequency domain response of the suspected anomalous segment is replaced with the local frequency domain response of the corresponding structurally homologous healthy reference segment. The target interconnect path is re-cascaded to form a counterfactual channel response. The counterfactual recovery ratio and counterfactual recovery fingerprint are determined based on the counterfactual channel response, and the dominant anomalous segment is determined based on the counterfactual recovery ratio. Establish a flip-chip package defect type library, read the package defect types and their structural applicability ranges from the library, combine the standardized signal integrity anomaly fingerprint, counterfactual recovery fingerprint, time-domain location parameters, and structural applicability ranges of the dominant anomaly segment to determine the final mapped defect type, and generate chip interconnect package analysis records.

2. The chip interconnect packaging analysis method based on signal integrity as described in claim 1, characterized in that, The method of dividing interconnect analysis segments according to the conductivity sequence from the chip pads to the external solder balls of the package includes: Read conductive connection records along the connection direction of chip pads, bumps, redistribution layers, package substrate vias, package substrate traces, and external solder balls in the target high-speed signal network. Segmentation boundaries are set at locations where the structure type changes, the metal layer changes, vias are used for layer replacement, reference grounds are switched, adjacent coupling relationships change, and solder ball connection areas are entered, dividing the target high-speed signal network into several interconnection analysis segments.

3. The chip interconnect packaging analysis method based on signal integrity as described in claim 1, characterized in that, The establishment of the structural homology segmentation diagram includes: A set of nodes is formed by interconnection analysis segments, a set of conductive connection edges is formed by the conductive connection relationship between adjacent interconnection analysis segments in the same target interconnection path, a set of coupling edges is formed by the proximity coupling relationship between the target interconnection analysis segment and the intruding interconnection analysis segment, and a set of return edges is formed by the ground return relationship between the target interconnection analysis segment and the ground return path segment. By combining the set of nodes, the set of conductive connection edges, the set of coupling edges, and the set of return edges, a structurally homogeneous segmented graph is generated.

4. The chip interconnect packaging analysis method based on signal integrity as described in claim 1, characterized in that, The process of determining a structurally homogeneous health reference segment for each interconnect analysis segment includes: Candidate healthy interconnect analysis segments are determined based on structural reference priority; When there are several candidate healthy interconnect analysis segments within the same reference source, the structural homology fit value is determined based on the structural hard constraint flag, local port consistency flag, health status flag, and geometric similarity, and the candidate healthy interconnect analysis segment with the largest structural homology fit value is determined as the structural homology healthy reference segment; The structural reference priority includes structural reference first priority, structural reference second priority, and structural reference third priority. Structural reference first priority corresponds to the qualified interconnect analysis segment in the same package layout, structural reference second priority corresponds to the interconnect analysis segment in the same batch of qualified samples, and structural reference third priority corresponds to the healthy interconnect analysis segment in the package design baseline data.

5. The chip interconnect packaging analysis method based on signal integrity as described in claim 1, characterized in that, The step of comparing the signal integrity data of each interconnect analysis segment with the signal integrity data of the corresponding structurally homogeneous healthy reference segment, and extracting the signal integrity deviation of each interconnect analysis segment, includes: Based on the interconnection segment structural homogeneity record and local port definition, read the signal integrity data of each interconnection analysis segment and the signal integrity data of the corresponding structural homogeneity health reference segment; The signal integrity data of each interconnect analysis segment is compared with the signal integrity data of the corresponding structurally homogeneous healthy reference segment, and the signal integrity deviation is extracted according to the direction of signal integrity degradation.

6. The chip interconnect packaging analysis method based on signal integrity as described in claim 5, characterized in that, The process of converting the signal integrity deviation according to the corresponding calibration boundary, generating a standardized signal integrity anomaly fingerprint, filtering out suspected anomaly segments, and recording time-domain location parameters includes: For each type of signal integrity deviation, a corresponding calibration boundary is configured. The signal integrity deviation is converted into a standardized anomaly intensity according to the corresponding calibration boundary. The standardized anomaly intensities are arranged according to the fixed order of each signal integrity deviation to form a standardized signal integrity anomaly fingerprint. When there is a standardized anomaly strength greater than zero for at least one applicable signal integrity index in the standardized signal integrity anomaly fingerprint, the corresponding interconnect analysis segment is marked as a suspected anomaly segment. The time-domain impedance data of the suspected abnormal segment is compared with the time-domain impedance data of the corresponding structurally healthy reference segment to determine the impedance anomaly time window, and the time-domain location parameters are recorded according to the impedance anomaly time window.

7. The chip interconnect packaging analysis method based on signal integrity as described in claim 6, characterized in that, The step of replacing the local frequency domain response of the suspected abnormal segment with the local frequency domain response of the corresponding structurally homologous healthy reference segment, and re-cascading the target interconnect path to form a counterfactual channel response includes: Based on the suspected abnormal segment records, segment-level signal integrity records, interconnection segment structure homogeneity records, and local port definitions, read the local frequency domain response data of the suspected abnormal segment and the local frequency domain response data of the corresponding structural homogeneity healthy reference segment; A local port correspondence is formed based on the input port, output port, reference ground port, adjacent coupled ports, and the port arrangement order. The cascaded transfer matrix obtained by transforming the local frequency domain response of the suspected abnormal segment is replaced with the cascaded transfer matrix of the corresponding structurally homologous healthy reference segment. For the interconnect analysis segment in the target interconnect path where the conductive connection sequence number is not equal to the conductive connection sequence number of the suspected abnormal segment, the corresponding cascaded transfer matrix remains unchanged, and the target interconnect path is re-cascaded according to the conductive sequence from the chip pad to the external solder ball of the package to form a counterfactual channel response.

8. The chip interconnect packaging analysis method based on signal integrity as described in claim 7, characterized in that, The process of determining the counterfactual recovery ratio and counterfactual recovery fingerprint based on the counterfactual channel response, and determining the dominant anomaly segment based on the counterfactual recovery ratio, includes: The response of the target interconnect path when the suspected abnormal segment is not replaced is recorded as the original channel response. The channel response formed when each interconnect analysis segment in the target interconnect path adopts the corresponding structural homogeneous healthy reference segment is recorded as the healthy reference channel response. The counterfactual recovery ratio is determined based on the difference energy between the original channel response and the healthy reference channel response, and the difference energy between the counterfactual channel response and the healthy reference channel response. Based on the counterfactual channel response formed after the suspected anomaly segment is replaced, the counterfactual standardized anomaly intensity corresponding to the current replacement action is generated, and the counterfactual standardized anomaly intensity is compared with the standardized anomaly intensity before the replacement to form a counterfactual recovery fingerprint. The counterfactual recovery rates of each suspected outlier segment are compared, and the suspected outlier segment with the highest counterfactual recovery rate is selected as the dominant outlier segment.

9. The chip interconnect packaging analysis method based on signal integrity as described in claim 1, characterized in that, The establishment of the flip-chip package defect type library, and the reading of the package defect types and their applicable structural scopes from the library, include: Read the process failure analysis records, packaging design rule documents, failure sample cross-section analysis records, electrical test anomaly records, and signal integrity calibration records during the R&D stage of the flip-chip package, establish a flip-chip package defect type library, and generate a packaging defect type record for each type of packaging defect; Based on the structural category of the interconnect analysis segment, establish the structural applicable scope of the encapsulation defect type, and record the encapsulation defect type number, encapsulation defect type name, structural applicable scope, anomaly reference fingerprint, recovery reference fingerprint, recovery ratio reference value, time domain location applicable scope, and defect type sorting in the encapsulation defect type record.

10. The chip interconnect packaging analysis method based on signal integrity as described in claim 8 or 9, characterized in that, The process of combining the standardized signal integrity anomaly fingerprint, counterfactual recovery fingerprint, temporal location parameters, and the structural applicability range of the packaging defect type with the dominant anomaly segment to determine the final mapped defect type and generate a chip interconnect packaging analysis record includes: Read the segment type, layer number, bump array area, solder ball escape direction, ground return relationship, standardized signal integrity anomaly fingerprint, counterfactual recovery fingerprint, and time domain location parameters of the dominant anomaly segment; The structural applicability mark is determined based on the structural data of the dominant anomaly segment and the structural applicability range of the encapsulation defect type, and the temporal location consistency mark is determined based on the temporal location parameters of the dominant anomaly segment and the temporal location applicability range of the encapsulation defect type. A counterfactual fingerprinting algorithm is used, which combines structural applicability markers, temporal location consistency markers, standardized signal integrity anomaly fingerprints, counterfactual recovery fingerprints, anomaly reference fingerprints, recovery reference fingerprints, and recovery ratio reference values ​​to calculate defect mapping fit values. The package defect type with the largest defect mapping adaptation value is determined as the final mapped defect type. When no fewer than two package defect types have the same maximum defect mapping adaptation value, the final mapped defect type is determined by combining the structure applicability mark, the time domain position consistency mark, the difference between the recovery ratio reference value and the counterfactual recovery ratio of the dominant anomaly segment, and the defect type sorting, and a chip interconnect package analysis record is generated.

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