Array substrate, display panel and display device

Abstract

Embodiments of the present disclosure provide an array substrate, a display panel and a display device, and relate to the technical field of display, and are used for improving the problem of obvious color deviation of display picture under oblique viewing angle. The array substrate comprises pixels, gate lines, data lines and discharge signal lines. Each pixel comprises two sub-pixels, each sub-pixel comprises a pixel electrode, a first transistor and a second transistor, the second electrode of the first transistor is electrically connected with the first electrode of the second transistor, and the pixel electrode is electrically connected with the second electrode of the first transistor. In the same pixel, the control electrodes of the two first transistors and the control electrodes of the two second transistors are electrically connected with the same gate line. In the same pixel, the first electrodes of the two first transistors are electrically connected with at least one data line. In the same pixel, the second electrodes of the two second transistors are respectively electrically connected with one discharge signal line. The present application is used for displaying images.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and more particularly to an array substrate, a display panel, and a display device. Background Technology

[0002] With the rapid development of display technology, display devices have gradually become ubiquitous in people's lives. Among them, liquid crystal displays (LCDs) are widely used in smart products such as mobile phones, televisions, and laptops due to their advantages such as small size, low power consumption, low cost, high brightness, and high reliability.

[0003] In related technologies, when the LCD liquid crystal display panel involves the display of mixed high and low grayscale, there is still a significant color shift problem in the display image at an oblique viewing angle. Summary of the Invention

[0004] The purpose of this disclosure is to provide an array substrate, a display panel, and a display device to improve the problem of significant color shift in the display image at oblique viewing angles.

[0005] To achieve the above objectives, the embodiments of this disclosure provide the following technical solutions: On one hand, an array substrate is provided. The array substrate includes pixels, gate lines, data lines, and discharge signal lines. Each pixel includes two sub-pixels, each sub-pixel including a pixel electrode, a first transistor, and a second transistor. The second electrode of the first transistor is electrically connected to the first electrode of the second transistor, and the pixel electrode is electrically connected to the second electrode of the first transistor. In the same pixel, the control electrodes of the two first transistors and the two second transistors are electrically connected to the same gate line. In the same pixel, the first electrodes of the two first transistors are electrically connected to at least one data line. In the same pixel, the second electrodes of the two second transistors are each electrically connected to a discharge signal line.

[0006] In the aforementioned array substrate, each pixel comprises two sub-pixels: a first sub-pixel and a second sub-pixel. The pixel electrode of the first sub-pixel is called the first pixel electrode, and the pixel electrode of the second sub-pixel is called the second pixel electrode. Both the first and second sub-pixels are electrically connected to an independent discharge signal line. The discharge signal line connected to the first sub-pixel is called the first discharge signal line, and the discharge signal line connected to the second sub-pixel is called the second discharge signal line. In this configuration, both the first and second sub-pixels can achieve independent brightness adjustment. This allows for differentiated optimization based on different products or application scenarios, such as high-end displays (pursuing high image quality) and portable devices (pursuing high brightness), thereby enhancing the product's market competitiveness and usability. For example, in height mode, the voltage of the first discharge signal line can be adjusted to the highest level to minimize the impact of the first discharge signal line on the pixel voltage of the first pixel electrode, achieving peak transmittance. In low color shift mode, the voltages of the first and second discharge signal lines can be adjusted to be lowered in tandem, so that the voltage of the second discharge signal line is lower than that of the first discharge signal line. By finely adjusting the voltage difference between the two, the optimal color shift compensation effect at different gray levels can be achieved, thus improving the problem of obvious color shift in the display image at oblique viewing angles.

[0007] In some embodiments, two sub-pixels of the pixel are arranged along a first direction, and the pixel electrode includes a main body and two first protrusions. Along a second direction, the two first protrusions are located on opposite sides of the main body and on opposite sides of a midline extending from the main body along the second direction. The first direction and the second direction intersect.

[0008] In some embodiments, the array substrate further includes a first storage line, which is at least partially located on opposite sides of the pixel electrode along the second direction, and the first protrusion and the first storage line at least partially overlap in a direction perpendicular to the array substrate.

[0009] In some embodiments, in orthographic projection onto a reference plane, the data line is located between two pixel electrodes, and the reference plane is the plane containing the non-light-emitting surface of the array substrate. In orthographic projection onto the reference plane, the discharge signal line is at least partially located between the corresponding pixel electrode and the corresponding data line.

[0010] In some embodiments, two sub-pixels of the pixel are arranged along a first direction. In orthographic projection onto a reference plane, the discharge signal line overlaps with the centerline of the corresponding sub-pixel extending along a second direction. The first direction and the second direction intersect, and the reference plane is the plane containing the surface of the non-light-emitting side of the array substrate.

[0011] In some embodiments, the array substrate further includes a first discharge connection line, the first discharge connection line including a first overlap portion and a first connection segment connected together, at least a portion of the first overlap portion forming the second electrode of the second transistor, and the first connection segment being electrically connected to the discharge signal line. The first connection segment overlaps with the centerline of the corresponding sub-pixel extending along the first direction.

[0012] In some embodiments, the array substrate further includes a second discharge connection line, the second discharge connection line including a second overlap portion, a second connection segment, and a third connection segment connected in sequence, at least a portion of the second overlap portion forming the second electrode of the second transistor, and the third connection segment being electrically connected to the discharge signal line. Along the first direction, at least a portion of the second connection segment is located between the corresponding pixel electrode and the data line. Along the second direction, the third connection segment is located on one side of the pixel electrode.

[0013] In some embodiments, along the second direction, the second connection segment is at least partially opposite the data line in the second direction.

[0014] In some embodiments, two sub-pixels of the pixel are arranged along a first direction. The pixel electrode includes a main body and two first protrusions. Along a second direction, the two first protrusions are located on opposite sides of the main body and on opposite sides of the centerline extending from the main body along the second direction. The third connecting segment is located between the first protrusions and the corresponding data lines.

[0015] In some embodiments, in the same pixel, the first electrodes of the two first transistors are electrically connected to the same data line; in orthographic projection onto a reference plane, the data line is located between the corresponding two pixel electrodes, and the reference plane is the plane containing the surface of the non-light-emitting side of the array substrate.

[0016] Two sub-pixels in the pixel are arranged along a first direction. The data line includes multiple trace segments, including multiple first trace segments and multiple second trace segments. Along a second direction, the first trace segments and the second trace segments are at least partially offset, and one first trace segment and one second trace segment are alternately connected. The second direction intersects the first direction. Along the first direction, the side of the first trace segment closer to the second trace segment is the first side, and the pixel electrode located on the first side of the first trace segment is the first pixel electrode. The first trace segment is electrically connected to the first pixel electrode through a first transistor. Along the first direction, the side of the second trace segment closer to the first trace segment is the second side, and the pixel electrode located on the second side of the second trace segment is the second pixel electrode. The second trace segment is electrically connected to the second pixel electrode through a first transistor.

[0017] In some embodiments, the channel portion of the first transistor is a first channel portion, and the channel portion of the second transistor is a second channel portion. The array substrate further includes a first active portion, which includes the first channel portion, the second channel portion, and a first ohmic contact portion. Along the first direction, the first channel portion and the second channel portion are at least partially opposite to each other and connected through the first ohmic contact portion.

[0018] In some embodiments, the channel portion of the first transistor is a first channel portion, and the channel portion of the second transistor is a second channel portion. The array substrate further includes a second active portion, which includes a second ohmic contact portion and two first channel portions. Along the first direction, the two first channel portions are at least partially opposite to each other and connected through the second ohmic contact portion. The third active portion includes the second channel portion. Along the second direction, the second channel portion is at least partially opposite to the first channel portion.

[0019] In some embodiments, the data line further includes an extension located between the trace segment and the pixel electrode, and connected to an end of the trace segment. Along the first direction, a second ohmic contact and two first channel portions are located between the extension and one of the trace segments.

[0020] In some embodiments, one of the two sub-pixels of the pixel is a first sub-pixel, and the other is a second sub-pixel. The pixel electrode of the first sub-pixel is a first pixel electrode, and the pixel electrode of the second sub-pixel is a second pixel electrode. The two sub-pixels are electrically connected to two data lines, respectively. The data line electrically connected to the first sub-pixel is a first data line, and the data line electrically connected to the second sub-pixel is a second data line. The first sub-pixel and the second sub-pixel are arranged along a first direction. Along the first direction, the first data line is located on the side of the first pixel electrode away from the second pixel electrode, and the second data line is located between the first pixel electrode and the second pixel electrode.

[0021] In some embodiments, the array substrate includes a display area, a bonding area, and a first border area, wherein the bonding area and the first border area are located on opposite sides of the display area, and the pixels are located in the display area. The array substrate also includes data connection lines disposed in the first border area. The first data line and the second data line are electrically connected via the data connection lines.

[0022] In some embodiments, two sub-pixels of the pixel are arranged along a first direction. The array substrate further includes a shielding line, which, in its orthographic projection onto a reference plane, at least partially overlaps with a data line and is at least partially located between the data line and the pixel electrode. The reference plane is the plane containing the surface of the non-light-emitting side of the array substrate. The distance between the shielding line near the pixel electrode and the data line near the pixel electrode is greater than or equal to 1.5 μm.

[0023] In some embodiments, the array substrate further includes a first storage line along the second direction, the first storage line being at least partially located on opposite sides of the pixel electrode, and the shielding line being electrically connected to the first storage line.

[0024] In some embodiments, one of the two discharge signal lines corresponding to the two pixel electrodes is electrically connected to the shielding line.

[0025] In some embodiments, the array substrate includes a display area, a bonding area, and a first border area, wherein the bonding area and the first border area are located on opposite sides of the display area, and the pixels are located in the display area. The array substrate also includes a discharge signal bus, which is at least partially disposed in the first border area. The discharge signal line is electrically connected to the discharge signal bus in the first border area.

[0026] In some embodiments, the gate line extends along a first direction, and in a direction perpendicular to the array substrate, the gate line overlaps with the centerline of the pixel electrode extending along the first direction. At least one of the two pixel electrodes has a larger dimension along the first direction than its dimension along the second direction. The first direction and the second direction intersect.

[0027] In some embodiments, two sub-pixels of the pixel are arranged along a first direction. A plurality of pixels, including a first pixel, a second pixel, and a third pixel of different corresponding colors, are arranged in a row along the first direction: the plurality of first pixels, the plurality of second pixels, and the plurality of third pixels are arranged in a row. Along a second direction, a row of first pixels, a row of second pixels, and a row of third pixels are arranged sequentially.

[0028] In some embodiments, one of the two sub-pixels of the pixel is a first sub-pixel and the other is a second sub-pixel; the ratio of the area of ​​the first sub-pixel to the area of ​​the second sub-pixel is 1 to 2.5, and the display brightness corresponding to the electrode of the first sub-pixel is less than the display brightness corresponding to the second sub-pixel.

[0029] On the other hand, a display panel is provided. The display panel includes an array substrate, an opposing substrate, and a liquid crystal layer. The array substrate is an array substrate as described in any of the above embodiments. The opposing substrate is disposed opposite to the array substrate, and the liquid crystal layer is disposed between the array substrate and the opposing substrate.

[0030] In another aspect, a display device is provided. The display device includes a display panel and a backlight module, wherein the display panel is the display panel as described in any of the above embodiments, and the backlight module is disposed on the backlight side of the display panel.

[0031] The above-described display panel and display device have the same structure and beneficial technical effects as the array substrate provided in some of the above embodiments, and will not be described again here. Attached Figure Description

[0032] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual flow of the method, the actual timing of the signals, etc. involved in the embodiments of this disclosure.

[0033] Figure 1 This is a structural diagram of a display device according to some embodiments; Figure 2 for Figure 1 A sectional view along section line AA'; Figure 3 This is a top view of a display panel according to some embodiments; Figure 4 for Figure 3 A sectional view along the section line BB'; Figure 5 This is a structural layout of an array substrate according to some embodiments; Figure 6 This is a structural layout of another array substrate according to some embodiments; Figure 7 A circuit diagram of pixels of an array substrate according to some embodiments; Figure 8 This is a structural diagram of a display panel according to some embodiments; Figure 9 This is a structural layout of another array substrate according to some embodiments; Figure 10 This is a diagram showing the positional relationship between pixel electrodes and dark lines on an array substrate according to some embodiments; Figure 11 This is a structural diagram of a pixel electrode of an array substrate according to some embodiments; Figure 12 This is a structural layout of another array substrate according to some embodiments; Figure 13 This is a structural layout of another array substrate according to some embodiments; Figure 14 for Figure 13 The diagram shows the structural layout of the array substrate after removing the film layer containing the pixel electrodes. Figure 15 This is a structural layout of another array substrate according to some embodiments; Figure 16 This is a structural layout of another array substrate according to some embodiments; Figure 17 This is a structural layout of another array substrate according to some embodiments; Figure 18 This is a structural layout of another array substrate according to some embodiments; Figure 19 This is a circuit diagram of pixels on another array substrate according to some embodiments. Detailed Implementation

[0034] The technical solutions in some embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.

[0035] Unless the context otherwise requires, throughout the specification and claims, the term "comprise" and its other forms, such as the third-person singular "comprises" and the present participle "comprising," are interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiments," "example," "specific example," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0036] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more.

[0037] In describing some embodiments, the term "connection" and its derivative expressions may be used. The term "connection" should be interpreted broadly; for example, "connection" can be a mechanical connection or an electrical connection; it can be a fixed connection or a detachable connection, or an integral connection; it can be a direct connection or an indirect connection through an intermediate medium; it can be a connection within two components. Those skilled in the art will understand the specific meaning of the above terms herein based on the specific circumstances.

[0038] "At least one of A, B and C" has the same meaning as "at least one of A, B or C", both including the following combinations of A, B and C: only A, only B, only C, combinations of A and B, combinations of A and C, combinations of B and C, and combinations of A, B and C.

[0039] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0040] As used herein, "perpendicular" and "equal" include the described situation and situations that are similar to the described situation, within an acceptable deviation range, which is determined by those skilled in the art taking into account the measurement under discussion and the error associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, "perpendicular" includes absolute perpendicularity and approximate perpendicularity, where the acceptable deviation range for approximate perpendicularity could be, for example, a deviation within 5°. "Equal" includes absolute equality and approximate equality, where the acceptable deviation range for approximate equality could be, for example, a difference between the two equalities less than or equal to 5% of either one.

[0041] The term "relative" means that the first element can be directly or indirectly relative to the second element. In the case where the third element is between the first and second elements, although they are still relative to each other, the first and second elements can be understood as being indirectly relative to each other.

[0042] It should be understood that when a layer or element is referred to as being on another layer or substrate, it can mean that the layer or element is directly on another layer or substrate, or that there is an intermediate layer between the layer or element and another layer or substrate.

[0043] This document describes exemplary embodiments with reference to cross-sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as being limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched areas shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the areas of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0044] like Figure 1As shown, some embodiments of this disclosure provide a display device 1000, which can be any device that displays either moving (e.g., video) or stationary (e.g., still image) content, and whether it is text or an image. Exemplarily, the display device 1000 can be any product or component with display functionality, such as a television, laptop, tablet, mobile phone, personal digital assistant (PDA), navigator, in-vehicle display, in-flight display, wearable device, virtual reality (VR) device, augmented reality (AR) device, mixed reality (MR) device, signboard, electronic billboard, and shopping mall display. For example, the display device 1000 can be... Figure 1 The television set shown.

[0045] In some embodiments, see Figure 2 The display device 1000 includes a display panel 100 and a circuit board 200. The circuit board 200 is connected to the display panel 100 and is used to transmit control signals to the display panel 100 to drive the display panel 100 to display images. The circuit board 200 may include, for example, a timing controller (TCON), a power management chip (DC / DC), and an adjustable resistor voltage divider circuit (generating Vcom), etc. Of course, the circuit board 200 may also include other circuit structures, which will not be listed here.

[0046] Please continue reading. Figure 2 The display device 1000 may further include a frame 300 and a cover plate 400. The longitudinal section of the frame 300 is, for example, U-shaped. The display panel 100 and the circuit board 200 may be disposed within the frame 300, and the cover plate 400 is disposed at the opening of the frame 300. Of course, the display device 1000 may also exclude the cover plate 400, and this disclosure does not specifically limit this aspect.

[0047] In some embodiments, see Figure 2 The display device 1000 is a liquid crystal display (LCD). In this case, the display device 1000 may also include a backlight side disposed on the display panel 100. Figure 2The backlight module 500 (located on the lower side of the display panel 100) can be positioned, for example, on the side of the display panel 100 away from the cover plate 400, with the circuit board 200 disposed on the side of the backlight module 500 away from the cover plate 400. The backlight module 500 can be a direct-lit backlight module or an edge-lit backlight module, etc., and is used to provide a light source for the display panel 100. The display panel 100 adjusts the amount of light passing through it to display different gray levels, thereby achieving the purpose of image display. In addition, the display device 1000 may also include a touch structure, an under-display camera, and an under-display fingerprint sensor, enabling the display device 1000 to perform various functions such as touch control, photography, video recording, or fingerprint recognition, which will not be listed here.

[0048] Please continue reading. Figure 2 The display panel 100 is a liquid crystal display panel, meaning it may include an array substrate 10 and a counter substrate 20 disposed opposite each other, and a liquid crystal layer 30 disposed between the array substrate 10 and the counter substrate 20. The array substrate 10 and the counter substrate 20 can be bonded together by an adhesive 350, thereby confining the liquid crystal molecules of the liquid crystal layer 30 within the area enclosed by the adhesive 350. The counter substrate 20 may also be called a color filter substrate or an encapsulation substrate. The counter substrate 20 can filter incoming light to emit multiple colors of light (such as red, green, or blue) to achieve color display. Alternatively, the array substrate 10 can filter incoming light to emit multiple colors of light (such as red, green, or blue) to achieve color display; this embodiment does not specifically limit the specific application of this method.

[0049] The display panel 100 can be, for example, a vertical alignment (VA) type. For instance, pixel electrodes are disposed on the array substrate 10, and a common electrode is disposed on the opposing substrate 20. A vertical electric field is generated between the pixel electrodes and the common electrode, driving the liquid crystal molecules to deflect along the direction of the electric field, resulting in advantages such as high contrast and wide viewing angle. Alternatively, the display panel 100 can be, for instance, an advanced super-dimensional switch (ADS) type or a high-aperture-ratio high-advanced-dimensional switch (HADS) type. For instance, both the common electrode and pixel electrodes are disposed on the array substrate 10. A multi-dimensional electric field is formed by the electric field generated at the edge of the slit electrodes in the same plane and the electric field generated between the slit electrode layer and the plate electrode layer. This allows all oriented liquid crystal molecules between the slit electrodes and directly above the electrodes to rotate, thereby improving the liquid crystal working efficiency and increasing the light transmittance. It also offers advantages such as high resolution, high transmittance, low power consumption, wide viewing angle, high aperture ratio, low color difference, and no extrusion water ripples. HADS technology is an important implementation of ADS technology, and it has a higher aperture ratio.

[0050] In addition, see Figure 3 and Figure 4 The opposing substrate 20 can also filter the incident light to emit light of various colors (such as red, green, or blue) to achieve color display. For example, the opposing substrate 20 includes a second substrate 210 and a filter layer 230 disposed on the second substrate 210. The filter layer 230 is used to filter the light incident on the opposing substrate 20 to emit light of various colors (such as red, green, or blue), thereby enabling the display panel 100 to achieve color display. In addition, the opposing substrate 20 can also include a black matrix 240 disposed on the second substrate 210. The black matrix 240 can be used to isolate crosstalk between different colors of light and cover transistors and signal lines (including gate lines, data lines, etc.) on the array substrate 10 to block stray light from escaping from the gap between the pixel electrode 120 and the signal lines and to avoid signal line reflection interference with the display, thereby improving the contrast of the display panel 100. Of course, in other feasible embodiments, the array substrate 10 can filter the incident light to emit light of multiple colors (such as red, green or blue) to achieve color display. That is, the array substrate 10 includes a filter layer and a black matrix. The embodiments disclosed herein are not specifically limited.

[0051] The following describes some embodiments of this disclosure using a VA type display panel 100 as an example. However, the embodiments of this disclosure are not limited to this, and ADS type, HADS type, or any other suitable display panel 100 can also be considered, as long as the same technical concept is applied.

[0052] For example, such as Figure 3 and Figure 4 As shown, the array substrate 10 includes a first substrate 110 and pixel electrodes 120 disposed on the first substrate 110, and the opposing substrate 20 includes a second substrate 210 and a common electrode 220 disposed on the second substrate 210. The pixel electrodes 120 are spaced apart, and the common electrode 220 is a continuous, full-surface structure (i.e., the common electrode 220 does not have vias or slits). In this configuration, the electric field generated between the common electrode 220 and the pixel electrodes 120 causes the liquid crystal molecules within the liquid crystal layer 30 to rotate.

[0053] In related technologies, when the display panel is viewed from an oblique angle and the image involves a mixture of high and low grayscale, there is still a noticeable color shift problem.

[0054] To solve the above technical problems, please refer to Figure 3 In some embodiments of the present disclosure, the display panel 100 includes an array substrate 10 that may include a first substrate 110 and a plurality of pixels P disposed on one side of the first substrate 110. Each pixel P includes two sub-pixels P0 with different transmittances. One of the two sub-pixels P0 is a first sub-pixel P1, and the other is a second sub-pixel P2. The first sub-pixel P1 and the second sub-pixel P2 exhibit different light emission brightness under the same driving voltage. For example, the display brightness corresponding to the first sub-pixel P1 is less than the display brightness corresponding to the second sub-pixel P2. Thus, the first sub-pixel P1 can be called a dark pixel, and the second sub-pixel P2 can be called a bright pixel. In this case, on the one hand, the second sub-pixel P2 can ensure the brightness and transparency of the display when viewed directly, thus ensuring normal display quality; on the other hand, the first sub-pixel P1 can suppress the ineffective light leakage at the pixel edges and liquid crystal areas, reduce the brightness in dark states, effectively improve the static contrast and the purity of the dark field image, compensate for the optical deviation of the side viewing angle, improve the uniformity of the display across the entire viewing angle, and enhance the image quality and display stability.

[0055] Combination Figure 3 , Figure 4 , Figure 5 and Figure 6 The array substrate 10 also includes gate lines 40, data lines 50, and discharge signal lines 60. Figure 3(Not shown in the diagram), the gate line 40, the data line 50, and the discharge signal line 60 can be disposed on the same side of the first substrate 110. For example, the gate line 40 can be located between the data line 50 and the first substrate 110, and the discharge signal line 60 can be made of the same material as the data line 50 and disposed in the same layer.

[0056] Based on this, combined Figure 5 , Figure 6 and Figure 7 Each sub-pixel P0 includes a pixel electrode 120, a first transistor 31, and a second transistor 32. The second electrode of the first transistor 31 is electrically connected to the first electrode of the second transistor 32, and the pixel electrode 120 is electrically connected to the second electrode of the first transistor 31. In the same pixel P, the control electrodes of the two first transistors 31 and the two second transistors 32 are electrically connected to the same gate line 40 to receive the scan signal transmitted by the gate line 40. The first electrodes of the two first transistors 31 are electrically connected to at least one data line 50 to receive the data signal transmitted by the data line 50. The second electrodes of the two second transistors 32 are respectively electrically connected to a discharge signal line 60 to receive the discharge control signal transmitted by the discharge signal line 60. At this time, the pixel electrode 120 and the common electrode 220 form a liquid crystal capacitor Clc. The sub-pixel P0 may also include a storage capacitor Cst, which may be formed by the pixel electrode 210 and the discharge signal line 60 and / or other signal lines transmitting a common voltage signal (such as the first storage line 71, the second storage line 72, and the shield line 101 mentioned below).

[0057] Optionally, the multiple pixels P may include a first pixel R, a second pixel G, and a third pixel B, where the first pixel R corresponds to the color red, the second pixel G corresponds to the color green, and the third pixel B corresponds to the color blue, to achieve color display. In this case, the same pixel P mentioned above can be any one of the first pixel R, the second pixel G, and the third pixel B. Alternatively, the multiple pixels P may also include a fourth pixel, where the color corresponding to the fourth pixel can be any color other than red, green, and blue, such as white, cyan, or yellow. This disclosure does not specifically limit this aspect.

[0058] In this design, the pixel electrode 120 of the first sub-pixel P1 is called the first pixel electrode 121, and the pixel electrode 120 of the second sub-pixel P2 is called the second pixel electrode 122. The first sub-pixel P1 and the second sub-pixel P2 are each electrically connected to an independent discharge signal line 60. The discharge signal line 60 connected to the first sub-pixel P1 is called the first discharge signal line 61, and the discharge signal line 60 connected to the second sub-pixel P2 is called the second discharge signal line 62. In this configuration, both the first sub-pixel P1 and the second sub-pixel P2 can achieve independent brightness adjustment. This allows for differentiated optimization based on different products or application scenarios, such as high-end displays (pursuing high image quality) and portable devices (pursuing high brightness), thereby enhancing the product's market competitiveness and usability. For example, the display panel 100, including the array substrate 10, has a height mode and a low color shift mode. In height mode, the voltage of the first discharge signal line 61 can be adjusted to the highest level, minimizing the impact of the first discharge signal line 61 on the pixel voltage of the first pixel electrode 121 and achieving peak transmittance. In low color shift mode, the voltages of the first discharge signal line 61 and the second discharge signal line 62 can be adjusted to be lower, so that the voltage of the second discharge signal line 62 is less than the voltage of the first discharge signal line 61. By finely adjusting the voltage difference between the two, the optimal color shift compensation effect at different gray levels can be achieved, thus improving the problem of obvious color shift in the display at different viewing angles.

[0059] Optionally, the ratio of the area of ​​the first sub-pixel P1 to the area of ​​the second sub-pixel P2 is 1 to 2.5. For example, the ratio of the area of ​​the first sub-pixel P1 to the area of ​​the second sub-pixel P2 can be any one of 1, 1.2, 1.5, 1.6, 1.8, 2, 2.1, 2.2, 2.3, 2.4, and 2.5. These ratios are not listed exhaustively in this embodiment. The closer the ratio of the area of ​​the first sub-pixel P1 to the area of ​​the second sub-pixel P2 is to 1, the higher the transmittance. The closer the ratio is to 2.5, the better the wide-viewing-angle display effect. In some feasible implementations, the maximum size of the first sub-pixel P1 and the second sub-pixel P2 in the second direction Y can be equal, and the ratio of the size of the first sub-pixel P1 and the second sub-pixel P2 in the first direction X can be 1 to 2.5. This allows the first sub-pixel P1 and the second sub-pixel P2 to form an optimal area ratio, suppressing dark-state light leakage, improving contrast, ensuring brightness when viewed directly, and optimizing viewing angle performance. Optionally, in this case, the display brightness corresponding to the second sub-pixel P2 is higher than the display brightness of the first sub-pixel P1, that is, the second sub-pixel P2 is a bright pixel and the first sub-pixel P1 is a dark pixel. Optionally, the voltage value of the first discharge signal line 61 is lower than the voltage value of the second discharge signal line 62, so that the voltage difference between the second pixel electrode 122 and the common electrode 220 is greater than the voltage difference between the first pixel electrode 121 and the common electrode 220, thereby achieving different liquid crystal deflections corresponding to bright and dark pixels.

[0060] In some embodiments, see Figure 3 The array substrate 10 includes a display area AA and a peripheral area BB disposed on at least one side of the display area AA. Figure 3 Taking the peripheral area BB surrounding the display area AA as an example, the display area AA is the area for displaying images, and is configured to set up pixels P and signal lines (including but not limited to gate line 40 and data line 50); the peripheral area BB is the area that is not displayed, and is configured to set up various driving circuits (including but not limited to gate driving circuit 600 and source driving circuit 700) and control signal lines (including but not limited to clock signal lines and power signal lines).

[0061] Please continue reading. Figure 3 Multiple pixels P can be disposed in the display area AA. Pixels P can be arranged in multiple rows and columns, with one row including multiple pixels P arranged along a first direction X and one column including multiple pixels P arranged along a second direction Y. In this document, the first direction X and the second direction Y intersect; for example, the first direction X and the second direction Y are perpendicular. To achieve color display, the multiple pixels P can include a first pixel R, a second pixel G, and a third pixel B corresponding to different colors. Color display is achieved through the mixing of different colors of light (e.g., red, green, and blue). Of course, the multiple pixels P in the display area AA can also correspond to more colors, such as white, yellow, cyan, or other colors; the embodiments disclosed herein are not limited to this.

[0062] For example, such as Figure 3 As shown, along the first direction X, multiple first pixels R are arranged in one row, multiple second pixels G are arranged in one row, and multiple third pixels B are arranged in one row; along the second direction Y, one row of first pixels R, one row of second pixels G, and one row of third pixels B are arranged sequentially. At this time, first sub-pixels P1 and second sub-pixels P2 can be arranged along the first direction X. The ratio of the size of pixel P in the first direction X to the size of pixel P in the second direction Y can be 3. Thus, along the second direction Y, three adjacent pixels P that emit light of the first color, the second color, and the third color respectively form a pixel that is approximately square, preventing image distortion. With this configuration, the number of data lines 50 is reduced, which can decrease the number of channels for transmitting data signals in the source drive circuit 700 or the number of source drive circuits 700 themselves. Figure 8 The array substrate 10 shown includes four source drive circuits 700, which have a low cost.

[0063] Alternatively, along the second direction Y, multiple first pixels R are arranged in one column, multiple second pixels G in one column, and multiple third pixels B in one column; along the first direction X, a column of first pixels R, a column of second pixels G, and a column of third pixels B are arranged sequentially, forming a second arrangement. In this case, the first sub-pixel P1 and the second sub-pixel P2 can be arranged along the second direction Y. Furthermore, the ratio of the size of pixel P in the first direction X to the size of pixel P in the second direction Y can be 1 / 3. Thus, along the first direction X, a pixel formed by three adjacent pixels P emitting light of the first color, the second color, and the third color respectively is approximately square, preventing image distortion. With this arrangement, the number of grid lines 40 is reduced, the charging speed of sub-pixel P0 can be improved, and the pixel is charged more fully.

[0064] Please continue reading. Figure 3 , Figure 5 and Figure 6 The gate line 40 can extend along the first direction X, and multiple gate lines 40 can be arranged at intervals in the second direction Y. The gate line 40 can form the control electrode of the first transistor 31 and the control electrode of the second transistor 32. The gate drive circuit 600 is electrically connected to the control electrode of the first transistor 31 and the control electrode of the second transistor 32 through the gate line 40 (which can also be referred to as an integrated structure) to control the conduction and cutoff of the first transistor 31 and the second transistor 32. The gate line 40 can be a straight line or a broken line in its extension direction, and the embodiments of this disclosure do not specifically limit it in this way.

[0065] Please continue reading. Figure 3 , Figure 5 and Figure 6 The data line 50 can extend along the second direction Y, and multiple data lines 50 are arranged at intervals along the first direction X. The source drive circuit 700 is electrically connected to the first electrode of the first transistor 31 through the data line 50 to provide data signals to the pixel electrode 120. The data line 50 can be a straight line or a broken line in its extension direction, and this embodiment does not specifically limit it.

[0066] Please continue reading. Figure 5 and Figure 6 The discharge signal line 60 can extend along the second direction Y as a whole, and multiple discharge signal lines 60 are arranged at intervals along the first direction X. The discharge signal line 60 can be a straight line or a broken line in its extension direction, and the embodiments disclosed herein do not specifically limit this.

[0067] Among them, combined Figure 5 , Figure 6 and Figure 8The array substrate 10 also includes a discharge signal bus 6, which is disposed in the peripheral region BB and electrically connected through the second electrode of the second transistor 32 corresponding to the discharge signal line 60. Optionally, the discharge signal bus 6 can be made of the same material as the gate line 40 and disposed on the same layer. For example, see [reference needed]. Figure 8 and Figure 9 The peripheral area BB includes a bonding area C1 and a first border area C2. Along the second direction Y, the bonding area C1 and the first border area C2 are located on opposite sides of the display area AA. Circuit board 200 (see...) Figure 2 The discharge signal bus 6 can be electrically connected to the array substrate 10 through the bonding area C1. At this time, the discharge signal bus 6 is at least partially located in the first border area C2, and the discharge signal line 60 is electrically connected to the discharge signal bus 6 in the first border area C2. This reduces signal interference and crosstalk caused by circuit wiring and improves signal transmission quality. It should be understood that since the voltages of the first discharge signal line 61 and the second discharge signal line 62 can be independently adjusted, the array substrate 10 includes two discharge signal buses 6, namely the first discharge signal bus 61 and the second discharge signal bus 62. The first discharge signal line 61 is electrically connected to the first discharge signal bus 61, and the second discharge signal line 62 is electrically connected to the second discharge signal bus 62.

[0068] In addition, the array substrate 10 may also include a first common voltage signal bus 131 and a compensation signal line 133 located in the peripheral area BB. The first common voltage signal bus 131 includes a transition part 132, which is electrically connected to the common electrode 220 of the opposing substrate 20. Optionally, the transition part 132 can achieve conduction with the common electrode 220 through a conductive ball, such as a conductive gold ball. The conductive gold ball can be disposed in the frame adhesive. The compensation signal line 133 is used to connect the compensation voltage to perform potential compensation on the common electrode 220 located in the second frame area C2 to improve the voltage uniformity of the common electrode 220. Optionally, the compensation signal line 133 can also play a feedback role, such as detecting the voltage of the first common voltage signal bus 131 at the far end (second frame area C2 in the peripheral area BB) and providing feedback.

[0069] Please continue reading. Figure 5 , Figure 6 and Figure 7Each gate line 40 can be electrically connected to a row of pixels P, that is, each gate line 40 is electrically connected to the control electrode of the first transistor 31 and the control electrode of the second transistor 32 of a row of pixels P. Each data line 50 is electrically connected to a column of pixels P, that is, each data line 50 is electrically connected to the first electrode of all the first transistors 31 of a column of pixels P, or each data line 50 is electrically connected to the first electrode of the first transistor 31 of a column of first sub-pixels P1 or second sub-pixels P2. Each first discharge signal line 61 can be electrically connected to the second electrode of the second transistor 32 of a column of first sub-pixels P1, and each second discharge signal line 62 can be electrically connected to the second electrode of the second transistor 32 of a column of second sub-pixels P2. The structure is simple. Of course, the connection architecture between the gate line 40, data line 50, discharge signal line 60 and pixel P can also be in other suitable forms, and the embodiments disclosed herein are not limited to this.

[0070] Based on this, the first sub-pixel P1 and the second sub-pixel P2 can be arranged along the first direction X. Within the same pixel P, at least one of the two pixel electrodes 120 has a dimension along the first direction X that is larger than its dimension along the second direction Y. For example, the dimension D1 of the first pixel electrode 121 along the first direction X is larger than its dimension D2 along the second direction Y, and the dimension D3 of the second pixel electrode 122 along the first direction X is greater than or equal to its dimension D4 along the second direction Y. In this case, multiple pixels P can be arranged using... Figure 3 The arrangement shown is simple in structure.

[0071] In this document, the dimension of pixel electrode 120 in the first direction X can refer to the minimum dimension of pixel electrode 120 in the first direction X, and the dimension in the second direction Y can refer to the maximum dimension of pixel electrode 120 in the second direction Y. At this time, the dimension of pixel electrode 120 in the first direction X at the via position electrically connected to the second electrode of the first transistor 31 (e.g., via position H1 electrically connected to the second electrode of the first transistor 31) can be greater than the minimum dimension of pixel electrode 120 in the first direction X; the dimension of pixel electrode 120 in the second direction Y at the via position electrically connected to the second electrode of the first transistor 31 (e.g., via position H1 electrically connected to the second electrode of the first transistor 31) can be smaller than the maximum dimension of pixel electrode 120 in the second direction Y.

[0072] It should be understood that the tilting of all liquid crystal molecules in the same direction leads to problems such as large viewing angle differences and severe color distortion in the display panel 100. Therefore, the display panel 100 can be a multi-domain vertical alignment (MVA) type display panel, where a single pixel can include multiple domain regions with different liquid crystal orientations. The optical complementarity of these multiple domain regions compensates for color differences and light leakage defects caused by viewing angle differences, thereby improving the display quality. Optionally, the display panel 100 can employ ultraviolet-induced multi-domain vertical alignment (UV... 2 A) Photoalignment processes such as process technology or Super Ultraviolet Induced Multi-domain Vertical Alignment (SUVA) are used to define domains with different orientations within pixels through photoalignment, thereby optimizing the 100-degree viewing angle characteristics and display effect of the display panel.

[0073] It should be noted that a domain region is an independent region in which liquid crystal molecules have a uniform tilt or deflection direction. It can also be called an alignment domain or liquid crystal domain, meaning that the liquid crystal molecules in each domain region have the same tilt direction.

[0074] For example, see Figure 6 and Figure 10 Each sub-pixel P0 of the array substrate 10 includes four domain regions F. The four domain regions F are arranged in two rows and two columns along the first direction X and the second direction Y. The four domain regions F in each sub-pixel P0 are equal in size in the first direction X and equal in size in the second direction Y. In this case, the four domain regions F can achieve optical compensation in all directions (up, down, left, and right), effectively widening the viewing angle, significantly suppressing color shift under different viewing angles, optimizing the uniformity of light transmission across the entire area, and ensuring that the image maintains uniform brightness and stable color from all viewing positions, significantly improving the overall display quality and visual experience.

[0075] The following describes some embodiments of this disclosure by taking an example where each sub-pixel P0 of the array substrate 10 includes four domain regions F. However, the embodiments of this disclosure are not limited to this, and it is also possible for the sub-pixel P0 to include two, six, or more domain regions F, as long as the same technical concept is applied. In this case, the domain regions can be formed by aligning different domains through the alignment of the alignment film, or by slits in different extension directions of the pixel electrode, or by simultaneously aligning different domains through the alignment method of the alignment film and the different extension directions of the pixel electrode.

[0076] It should be understood that due to the differences in the alignment direction of liquid crystal molecules in different domain regions F, the transmittance of the boundary region between two adjacent domain regions F is significantly reduced due to the disordered arrangement of liquid crystal molecules. Dark lines may appear in the boundary region between two adjacent domain regions F in a bright state. For example, if the angle between the liquid crystal molecules of two adjacent domain regions F is large, such as greater than 90°, dark lines will appear in the boundary region between the two adjacent domain regions F in a bright state. Figure 9 As shown, the boundaries of the four domain regions F of sub-pixel P0 will form a dark line L in the shape of a swastika.

[0077] At this time, as Figure 5 , Figure 6 and Figure 10 As shown, the gate line 40 extends along the first direction X, and in the direction perpendicular to the array substrate 10, the gate line 40 overlaps with the center line (including the center line and the area where the center line is located) of the pixel electrode 120 extending along the first direction X. In this case, the gate line 40 can overlap with the boundary region between two adjacent domain regions F in the second direction Y, that is, the gate line 40 can overlap with the dark line L extending along the first direction X and located between domain regions F. For example, the gate line 40 is located within the dark line L extending along the first direction X and located between domain regions F. In this way, the gate line 40 does not need to be additionally blocked by the black matrix, which is beneficial to improving the transmittance of the display panel 100.

[0078] In some embodiments, see Figure 5 , Figure 6 , Figure 10 and Figure 11 Two sub-pixels P0 in pixel P are arranged along a first direction X. Pixel electrode 120 includes a main body 211 and two first protrusions 212 along a second direction Y. The two first protrusions 212 are located on opposite sides of the main body 211 and on opposite sides of the centerline extending from the main body 211 along the second direction Y. Based on this, each of the two first protrusions 212 can correspond to a dark line L extending along the first direction X and located at the boundary of sub-pixel P0, causing the dark line L extending along the first direction X and located at the boundary of sub-pixel P0 to shift towards the pixels P. This hides the dark line L extending along the first direction X and located at the boundary of sub-pixel P0 between the pixels P, thereby improving the transmittance of pixel P and increasing the overall brightness of the display panel 100.

[0079] Please continue reading. Figure 5 , Figure 6 , Figure 10 and Figure 11The two first protrusions 212 can have the same size in the first direction X and the same size in the second direction Y. In addition, the array substrate 10 also includes a first storage line 71, which can be made of the same material as the gate line 40 and disposed in the same layer. The first storage line 71 can extend along the first direction X; along the second direction Y, the first storage line 71 is at least partially located on opposite sides of the pixel electrode 120. The first storage line 71 can be used to transmit a common voltage signal to reduce coupling between the pixel electrodes 120, reduce signal interference, and improve brightness uniformity and image display quality. In the direction perpendicular to the array substrate 10, the first protrusions 212 and the first storage line 71 at least partially overlap. In this case, the storage capacitor Cst formed by the overlap of the pixel electrode 120 and the first storage line 71 (see...) Figure 7 The overlap area caused by the misalignment of the two first protrusions 212 with the first storage line 71 is reversed, thus achieving mutual compensation. That is, when a misalignment occurs in the second direction Y during the process, the overlap area between one of the first protrusions 212 and the first storage line 71 in the pixel electrode 120 increases, while the overlap area between the other first protrusion 212 and the first storage line 71 decreases, resulting in a decrease in the overall total storage capacitance Cst (see...). Figure 7 This can maintain stability, thereby reducing the impact of process deviations and improving yield and image display uniformity. At this point, refer to... Figure 7 The array substrate 10 may also include a second common voltage signal bus 70 located in the peripheral area BB, and the first storage line 71 may be electrically connected to the second common voltage signal bus 70 to receive the common voltage signal.

[0080] In addition, see Figure 6 , Figure 10 and Figure 11 The pixel electrode 120 may further include a second protrusion 213. Along the first direction X, the second protrusion 213a of the first pixel electrode 121 is located on the side of the main body 211 away from the second pixel electrode 122, and the second protrusion 213b of the second pixel electrode 122 is located on the side of the main body 211 away from the first pixel electrode 121. The second protrusion 213a and the second protrusion 213b are located on opposite sides of the centerline extending along the first direction X of the main body 211. Based on this, the second protrusion 213a and the second protrusion 213b may each correspond to a dark line L extending along the second direction Y and located at the boundary of the sub-pixel P0 away from the data line 50, so that the dark line L extending along the second direction Y and located at the boundary of the sub-pixel P0 away from the data line 50 is shifted towards the pixels P. In this way, the dark line L extending along the second direction Y and located at the boundary of the sub-pixel P0 away from the data line 50 can be hidden between the pixels P, thereby improving the transmittance of the pixels P and increasing the overall brightness of the display panel 100.

[0081] In some embodiments, see Figure 5 , Figure 6 and Figure 9 In the orthographic projection onto the reference plane, the data line 50 is located between two pixel electrodes 120. This allows full utilization of the gap between pixels P, which is beneficial for improving the overall transmittance of the display panel 100 and simplifies the structure. In this paper, the reference plane is the plane containing the surface of the non-light-emitting side of the array substrate 10.

[0082] Please continue reading. Figure 5 , Figure 6 and Figure 9 In the orthographic projection onto the reference plane, the discharge signal line 60 is at least partially located between the corresponding pixel electrode 120 and the corresponding data line 50. This allows the discharge signal line 60 to further reduce the coupling between the data line 50 and the pixel electrode 120, minimizing signal interference, improving brightness uniformity in the second direction Y, and enhancing brightness uniformity and image display quality. For example, as... Figure 5 and Figure 6 As shown, within the same pixel P, two sub-pixels P0 are electrically connected to the same data line 50. At this time, the first discharge signal line 61 is located between the data line 50 and the first pixel electrode 121, and the second discharge signal line 62 is located between the data line 50 and the second pixel electrode 121. Optionally, the first discharge signal line 61 at least partially overlaps with the first pixel electrode 121, and the second discharge signal line 62 at least partially overlaps with the second pixel electrode 122. For example, as... Figure 9 As shown, the two sub-pixels P0 are electrically connected to two data lines 50, respectively. The data line 50 electrically connected to the first sub-pixel P1 is the first data line 51, and the data line 50 electrically connected to the second sub-pixel P2 is the second data line 52. Along the first direction X, the first data line 51 is located on the side of the first pixel electrode 121 away from the second pixel electrode 122, and the second data line 52 is located between the first pixel electrode 121 and the second pixel electrode 122. At this time, the first discharge signal line 61 is located between the first data line 51 and the first pixel electrode 121, and the second discharge signal line 62 is located between the second data line 52 and the second pixel electrode 121.

[0083] In other embodiments, see Figure 12 and Figure 13 Two sub-pixels P0 in pixel P are arranged along the first direction X. In the orthographic projection onto the reference plane, the discharge signal line 60 overlaps with the centerline (including the centerline and the area where the centerline is located) extending along the second direction Y of the corresponding sub-pixel P0. In this case, combined with Figure 10The discharge signal line 60 can overlap with the boundary region between two adjacent domain regions F in the first direction X. That is, the discharge signal line 60 can overlap with the dark line L extending along the second direction Y and located between domain regions F. For example, the discharge signal line 60 is located within the dark line L extending along the second direction Y and located between domain regions F. In this way, the discharge signal line 60 does not need to be additionally blocked by the black matrix, which is beneficial to improving the transmittance of the display panel 100.

[0084] Please continue reading at this point. Figure 12 and Figure 13 The array substrate 10 also includes a discharge connection line 80, through which the discharge signal line 60 is electrically connected to the second electrode of the second transistor 32. The discharge connection line 80 may be made of the same material as the data line 50 and be disposed on the same layer.

[0085] In some examples, such as Figure 12 As shown, the discharge connection line 80 includes a first discharge connection line 81, which includes a first overlapping portion 811 and a first connecting segment 812 connected together. At least a portion of the first overlapping portion 811 forms the second electrode of the second transistor 32, and the first connecting segment 812 is electrically connected to the discharge signal line 60. The first connecting segment 812 overlaps with the centerline extending along the first direction X of the corresponding sub-pixel P0. Thus, the first connecting segment 812 can overlap with the boundary region between two adjacent domain regions F in the second direction Y. That is, the first connecting segment 812 can overlap with the dark line L extending along the first direction X and located between domain regions F. For example, the first connecting segment 812 is located within the dark line L extending along the first direction X and located between domain regions F. Therefore, the first connecting segment 812 does not require additional black matrix occlusion, which helps to improve the transmittance of the display panel 100.

[0086] In other examples, such as Figure 13 and Figure 14 As shown, the discharge connection line 80 includes a second discharge connection line 82, which includes a second overlapping portion 821, a second connecting segment 822, and a third connecting segment 823 connected in sequence. At least a portion of the second overlapping portion 821 forms the second electrode of the second transistor 32, and the third connecting segment 823 is electrically connected to the discharge signal line 60. Along the first direction X, at least a portion of the second connecting segment 822 is located between the corresponding pixel electrode 120 and the data line 50, and the second connecting segment 822 extends along the second direction Y. Along the second direction Y, the third connecting segment 823 is located on one side of the pixel electrode 120, and the third connecting segment 823 extends along the first direction X. This allows the second connecting segment 822 and the third connecting segment 823 to fully utilize the gap between pixels P, which is beneficial for improving the overall transmittance of the display panel 100 and has a simple structure. In the direction perpendicular to the first substrate 110, the third connecting segment 823 at least partially overlaps with the first storage line 71.

[0087] Based on this, such as Figure 13 and Figure 14 As shown, the second connecting segment 822 can be at least partially opposite to the data line 50 in the second direction Y. For example, the boundary of the second connecting segment 822 near the corresponding pixel electrode 120 is flush with the boundary of the data line 50 near the corresponding pixel electrode 120. In this way, the second connecting segment 822 and the data line 50 can make full use of the gap between adjacent pixel electrodes 120 in the first direction X, resulting in a compact arrangement that helps improve the overall transmittance of the display panel 100 and has a simple structure. Furthermore, combined with Figure 11 In the case where the pixel electrode 120 includes a main body 211 and two first protrusions 212, along the first direction X, the third connecting segment 823 is located between the first protrusion 212 and the corresponding data line 50. In this way, the gap between two adjacent pixel electrodes 120 in the second direction Y, the third connecting segment 823 and the first protrusion 212 are arranged along the first direction X, which can make full use of the gap between adjacent pixel electrodes 120 in the second direction Y, the arrangement is compact, which is conducive to improving the overall transmittance of the display panel 100 and the structure is simple.

[0088] In some embodiments, see Figure 5 , Figure 6 and Figure 13 In the same pixel P, the first electrodes of the two first transistors 31 are electrically connected to the same data line 50. In the orthographic projection onto the reference plane, the data line 50 is located between the corresponding two pixel electrodes 120. This makes full use of the gap between pixels P, which helps to improve the overall transmittance of the display panel 100 and has a simple structure.

[0089] In this configuration, two sub-pixels P0 in pixel P are arranged along the first direction X. The data line 50 includes multiple trace segments 510, each of which includes multiple first trace segments 511 and multiple second trace segments 512. Both the first trace segment 511 and the second trace segment 512 extend along the second direction Y. Along the second direction Y, the first trace segment 511 and the second trace segment 512 are at least partially staggered, and one first trace segment 511 and one second trace segment 512 are alternately connected.

[0090] Please continue reading. Figure 5 , Figure 6 and Figure 13Along the first direction X, the side of the first trace segment 511 closest to the second trace segment 512 is called the first side. The pixel electrode 120 located on the first side of the first trace segment 511 is called the first pixel electrode 121. The first trace segment 511 is electrically connected to the first pixel electrode 121 through a first transistor 31. In this way, the first trace segment 511 is electrically connected to the adjacent and far pixel electrode 120 (first pixel electrode 121) in the first direction X through the first transistor 31. The distance between the first trace segment 511 and the first pixel electrode 121 is large. The first transistor 31 can be located between the first trace segment 511 and the first pixel electrode 121, which has a compact structure and is conducive to improving the overall transmittance of the display panel 100.

[0091] Please continue reading. Figure 5 , Figure 6 and Figure 13 Along the first direction X, the side of the second trace segment 512 closest to the first trace segment 511 is the second side. The pixel electrode 120 located on the second side of the second trace segment 512 is the second pixel electrode 122. The second trace segment 512 is electrically connected to the second pixel electrode 122 through a first transistor 31. In this way, the second trace segment 512 is electrically connected to the adjacent and far pixel electrode 120 (second pixel electrode 122) in the first direction X through the first transistor 31. The distance between the second trace segment 512 and the second pixel electrode 122 is large. The first transistor 31 can be located between the second trace segment 512 and the second pixel electrode 122, which has a compact structure and is conducive to improving the overall transmittance of the display panel 100.

[0092] It should be noted that, for reference Figure 13 and Figure 14 The multiple trace segments 510 of the data cable 50 may also include a connecting trace segment 513, which extends along a first direction X. The first trace segment 511 and the second trace segment 512 can be connected through the connecting trace segment 513. (See also...) Figure 5 and Figure 6 The first routing segment 511 and the second routing segment 512 can also be directly connected. For example, the ends of the first routing segment 511 and the second routing segment 512 that are close to each other are adjacent to the boundary in the first direction X. The implementation of this disclosure is not limited to this.

[0093] It should be understood that in the same pixel P, when the first poles of the two first transistors 31 are electrically connected to the same data line 50, the arrangement of the first transistors 31 and the second transistors 32 is not unique. Two examples are given below, but the embodiments disclosed herein are not limited to these.

[0094] Example 1, see Figure 15 and Figure 16The channel portion of the first transistor 31 is a first channel portion 31-1, and the channel portion of the second transistor 32 is a second channel portion 32-1. At this time, the array substrate 10 also includes a first active portion 91, which includes a first channel portion 31-1, a second channel portion 32-1, and a first ohmic contact portion 31-2. Along the first direction X, the first channel portion 31-1 and the second channel portion 32-1 are at least partially opposite to each other and connected through the first ohmic contact portion 31-2. Thus, the first transistor 31 and the second transistor 32 are arranged along the first direction X, and the via position of the pixel electrode 120 can be at least partially opposite to the first active portion 91 in the second direction Y. For example, the via position H1 of the second pixel electrode 122 is at least partially opposite to a corresponding first active portion 91 in the second direction Y. At this time, the pixel electrode 120 can be electrically connected to the first ohmic contact 31-2 through the first connection trace 11 extending along the second direction Y. The first connection trace 11 can be made of the same material as the data line 50 and set in the same layer. This arrangement structure is compact and helps to improve the overall transmittance of the display panel 100. It should be noted that the first connection trace 11 can be widened at the via position of the pixel electrode 120.

[0095] Example 2, see Figure 17 The channel portion of the first transistor 31 is a first channel portion 31-1, and the channel portion of the second transistor 32 is a second channel portion 32-1. At this time, the array substrate 10 also includes a second active portion 92, which includes a second ohmic contact portion 31-3 and two first channel portions 31-1. Along the first direction X, the two first channel portions 31-1 are at least partially opposite to each other and connected through the second ohmic contact portion 31-3. In this way, the first transistor 31 adopts a dual-channel structure, which can be equivalent to two transistors arranged in series. This can effectively suppress leakage current, improve the stability of the first transistor 31, and improve the display quality. Based on this, the array substrate 10 also includes a third active portion 93, which includes a second channel portion 32-1 along the second direction Y. The second channel portion 32-1 is at least partially opposite to the first channel portion 31-1. Thus, the two first channel portions 31-1 of the first transistor 31 are arranged along the first direction X, and the second transistor 32 and the first transistor 31 are arranged along the second direction Y. This arrangement structure is compact and helps to improve the overall transmittance of the display panel 100.

[0096] Optional, such as Figure 17 As shown, the data line 50 also includes an extension 53, which is located between the trace segment 510 and the pixel electrode 120 and is connected to the end of the trace segment 510. Along the first direction X, the second ohmic contact portion 31-3 and two first channel portions 31-1 are located between the extension segment 53 and one trace segment 510. This arrangement is compact and helps to improve the overall transmittance of the display panel 100.

[0097] In addition, please continue to refer to Figure 17 The via positions of the third active portion 93 and the pixel electrode 120 can be at least partially opposite to the second active portion 92 in the second direction Y. For example, the via position H1 of the second pixel electrode 122 and the corresponding third active portion 93 are at least partially opposite to a corresponding second active portion 92 in the second direction Y. In this case, the third active portion 93 and the pixel electrode 120 can be electrically connected to the second ohmic contact portion 31-3 through the same second connection trace 12 extending along the second direction Y. This second connection trace 12 can be made of the same material as the data line 50 and disposed in the same layer, resulting in a compact arrangement that improves the overall transmittance of the display panel 100. It should be noted that the second connection trace 12 can be widened at the via position of the pixel electrode 120. (Reference) Figure 17 The first channel portion 31-1, the second channel portion 32-1, the via position H1 of the second pixel electrode 122, and the via position H2 of the shield line 101 electrically connected to the first storage line 71 are arranged adjacently, such as between the first trace segment 511 and the second discharge signal line 62 of the data line 50, with a compact arrangement to improve the aperture ratio.

[0098] In other embodiments, see Figure 9 and Figure 12 The first sub-pixel P1 and the second sub-pixel P2 are arranged along the first direction X. Along the first direction X, the first data line 51 is located on the side of the first pixel electrode 121 away from the second pixel electrode 122, and the second data line 52 is located between the first pixel electrode 51 and the second pixel electrode 122. At this time, the first transistor 31 and the second transistor 32 can be disposed between the data line 50 and the corresponding pixel electrode 120. Along the first direction X, the width of the portion of the data line 50 opposite to the corresponding first transistor 31 and second transistor 32 can be reduced to reduce the gap between sub-pixels P0 and improve transmittance. That is, the first sub-pixel P1 and the second sub-pixel P2 are each electrically connected to a data line 50, and each data line 50 is disposed in the gap between two adjacent pixel electrodes 120 in the first direction X. This increases the width of the data line 50 in the first direction X without reducing transmittance, reduces the impedance of the data line 50, thereby improving the charging rate of the pixel electrode 120 and improving display quality.

[0099] Please continue reading. Figure 9 The array substrate 10 also includes a data connection line 54, through which the first data line 51 and the second data line 52 are electrically connected. Optionally, the data connection line 54 may be made of the same material as the data line 50 and disposed in the same layer. For example, combined with... Figure 8 and Figure 9The peripheral area BB includes a bonding area C1 and a first border area C2. Along the second direction Y, the bonding area C1 and the first border area C2 are located on opposite sides of the display area AA. The circuit board 200 can be electrically connected to the array substrate 10 through the bonding area C1. At this time, the data connection line 54 is at least partially disposed in the first border area C2. The first data line 51 and the second data line 52 are electrically connected in the first border area C2 through the data connection line 54. This can reduce signal interference and crosstalk caused by circuit wiring and improve signal transmission quality.

[0100] In some embodiments, see Figure 12 , Figure 15 , Figure 16 and Figure 17 The array substrate 10 may further include a shielding line 101, which may be made of the same material as the pixel electrode 120 and disposed in the same layer. The shielding line 101 can be used to transmit a common voltage signal to reduce coupling between the pixel electrodes 120. In orthographic projection onto the reference plane, the shielding line 101 at least partially overlaps with the data line 50, thus reducing the overall area occupied by the shielding line 101 and the data line 50. This compact arrangement helps improve the overall transmittance of the display panel 100. Furthermore, the shielding line 101 is at least partially located between the data line 50 and the pixel electrode 120 to reduce coupling between them, decrease signal interference, improve brightness uniformity in the second direction Y, and enhance brightness uniformity and image display quality. Optionally, the distance between the shielding line 101 near the pixel electrode 120 and the data line 50 near the pixel electrode 120 is greater than or equal to 1.5μm. For example, the distance between the shielding line 101 near the pixel electrode 120 and the data line 50 near the pixel electrode 120 is greater than or equal to 2μm. The shielding line 101 can effectively reduce the coupling between the data line 50 and the pixel electrode 120 and reduce mutual interference between signals.

[0101] Please continue reading. Figure 15 , Figure 16 and Figure 17The array substrate 10 may further include a first storage line 71, which extends along a first direction X and along a second direction Y, with the first storage line 71 located at least partially on opposite sides of the pixel electrode 120. In this case, the shielding line 101 can be electrically connected to the first storage line 71 to form a mesh structure, which can improve the stability and uniformity of the common voltage signal, optimize the consistency of the capacitance value of the storage capacitor, and improve issues such as head-shaking patterns, image retention, and screen flicker. Furthermore, the via position H2 where the shielding line 101 is electrically connected to the first storage line 71 can be adjacent to the via position where the pixel electrode 120 connects to the connecting trace (first connecting trace 11 or second connecting trace 12), for example, adjacent to the via position H1 where the second pixel electrode 122 connects to the connecting trace (first connecting trace 11 or second connecting trace 12). This arrangement results in a compact structure, which is beneficial for improving the overall transmittance of the display panel 100.

[0102] For example, see Figure 15 , Figure 16 and Figure 17 The shielding line 101 includes a first shielding portion 011, a second shielding portion 012, and a connecting shielding portion 013. The first shielding portion 011 and the second shielding portion 012 extend along the second direction Y and are connected through the connecting shielding portion 013. In the same pixel P, the first electrodes of two first transistors 31 are electrically connected to the same data line 50. The data line 50 includes multiple trace segments 510, including a first trace segment 511 and a second trace segment 512.

[0103] like Figure 15 and Figure 16 As shown, the array substrate 10 includes a first active portion 91, which includes a first channel portion 31-1, a second channel portion 32-1, and a first ohmic contact portion 31-2. Along the first direction X, the first channel portion 31-1 and the second channel portion 32-1 are at least partially opposite to each other and connected by the first ohmic contact portion 31-2. In this case, in the orthographic projection onto the reference plane, the first shielding portion 011 overlaps with the first trace segment 511, and the second shielding portion 012 overlaps with the second trace segment 512. For example... Figure 15 As shown, when multiple trace segments 510 do not include connecting trace segment 513, a portion of the connecting shield 013 overlaps with the end of the first trace segment 511, and another portion overlaps with the end of the second trace segment 512. For example... Figure 16 As shown, when multiple trace segments 510 include connecting trace segments 513, the connecting shield 013 overlaps with the connecting trace segment 513.

[0104] like Figure 17As shown, the array substrate 10 further includes a second active portion 92 and a third active portion 93. The second active portion 92 includes a second ohmic contact portion 31-3 and two first channel portions 31-1. Along the first direction X, the two first channel portions 31-1 are at least partially opposite to each other and connected by the second ohmic contact portion 31-3. The third active portion 93 includes a second channel portion 32-1. Along the second direction Y, the second channel portion 32-1 is at least partially opposite to the first channel portion 31-1. At this time, in the orthographic projection onto the reference plane, the first shielding portion 011 overlaps with the first trace segment 511, the second shielding portion 012 overlaps with the second trace segment 512, and the connecting trace segment 513 is located between the second active portion 92 and the third active portion 93. Figure 17 The second shielding part 012 is located in the second sub-pixel P2 (see Figure 7 Taking the second active portion 92 and the third active portion 93 as an example, the second sub-pixel P2 with higher brightness (see...) Figure 7 The brightness is more stable and the display effect is better. Of course, the second shielding part 012 can also be located between the second active part 92 and the third active part 93 of the first sub-pixel P1, and this embodiment does not specifically limit this.

[0105] In addition, see Figure 9 and Figure 12 The array substrate 10 may further include a second storage line 72, which can be used to transmit a common voltage signal. The second storage line 72 is made of the same material as the first storage line 71 and is disposed in the same layer. In a projection onto the reference plane, the second storage line 72 may be at least partially located between the data line 50 and the pixel electrode 120 to reduce coupling between the data line and the pixel electrode 120, reduce signal interference, and improve brightness uniformity and image display quality. It should be understood that if a discharge signal line 60 or a shielding line 101 is provided in the area between the data line 50 and the pixel electrode 120, the array substrate 10 may not provide the second storage line 72 in that area to simplify the circuit structure. If no discharge signal line 60 or shielding line 101 is provided in the area between the data line 50 and the pixel electrode 120, the second storage line 72 may be added in that area to reduce coupling between the data line and the pixel electrode 120, reduce signal interference, and improve brightness uniformity and image display quality.

[0106] In some embodiments, see Figure 18 and Figure 19One of the two discharge signal lines 60 corresponding to the two pixel electrodes 120 is electrically connected to the shielding line 101. This allows the discharge signal line 60 to not only discharge the corresponding sub-pixel P0, but also improve the stability and uniformity of the common voltage signal, optimize the consistency of the storage capacitor's capacitance value, and improve issues such as head-shaking patterns, image retention, and screen flicker. Simultaneously, the discharge current of the discharge signal line 60 is relatively small, which can optimize the discharge potential deviation caused by differences in data voltage at different gray levels, thus improving horizontal crosstalk.

[0107] For example, such as Figure 18 and Figure 19 As shown, the second discharge signal line 62 is electrically connected to the shielding line 101. The via position H3 where the second discharge signal line 62 is electrically connected to the shielding line 101 can be arranged adjacent to the via position H1 of the second pixel electrode 122. This arrangement is compact and helps improve the overall transmittance of the display panel 100.

[0108] In the description of this specification, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples.

[0109] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. An array substrate, characterized in that, include: A pixel includes two sub-pixels, each sub-pixel including a pixel electrode, a first transistor and a second transistor, the second terminal of the first transistor being electrically connected to the first terminal of the second transistor, and the pixel electrode being electrically connected to the second terminal of the first transistor; In the same pixel, the control electrodes of the two first transistors and the two second transistors are electrically connected to the same gate line; In the same pixel, the first terminals of the two first transistors are electrically connected to at least one data line; In the same pixel, the second terminals of the two second transistors are respectively electrically connected to one of the discharge signal lines.

2. The array substrate according to claim 1, characterized in that, Two sub-pixels in the pixel are arranged along a first direction. The pixel electrode includes a main body and two first protrusions. Along a second direction, the two first protrusions are located on opposite sides of the main body and on opposite sides of the centerline of the main body extending along the second direction. The first direction and the second direction intersect.

3. The array substrate according to claim 2, characterized in that, Also includes: A first storage line, along the second direction, is at least partially located on opposite sides of the pixel electrode, and in a direction perpendicular to the array substrate, the first protrusion and the first storage line at least partially overlap.

4. The array substrate according to claim 1, characterized in that, In the orthographic projection onto the reference plane, the data line is located between the two pixel electrodes, and the reference plane is the plane containing the non-light-emitting side of the array substrate; In the orthographic projection onto the reference plane, the discharge signal line is at least partially located between the corresponding pixel electrode and the corresponding data line.

5. The array substrate according to claim 1, characterized in that, Two sub-pixels in the pixel are arranged along a first direction; in the orthographic projection onto the reference plane, the discharge signal line overlaps with the centerline of the corresponding sub-pixel extending along a second direction; the first direction and the second direction intersect, and the reference plane is the plane containing the surface of the non-light-emitting side of the array substrate.

6. The array substrate according to claim 5, characterized in that, Also includes: The first discharge connection line includes a first overlap portion and a first connection segment connected to each other. At least a portion of the first overlap portion forms the second electrode of the second transistor. The first connection segment is electrically connected to the discharge signal line. The first connection segment overlaps with the centerline of the corresponding sub-pixel extending along the first direction.

7. The array substrate according to claim 5, characterized in that, Also includes: The second discharge connection line includes a second overlapping portion, a second connecting segment, and a third connecting segment connected in sequence. At least a portion of the second overlapping portion forms the second electrode of the second transistor, and the third connecting segment is electrically connected to the discharge signal line. Along the first direction, at least a portion of the second connecting segment is located between the corresponding pixel electrode and the data line; along the second direction, the third connecting segment is located on one side of the pixel electrode.

8. The array substrate according to claim 7, characterized in that, Along the second direction, the second connecting segment is at least partially opposite to the data line in the second direction.

9. The array substrate according to claim 7, characterized in that, Two sub-pixels in the pixel are arranged along a first direction. The pixel electrode includes a main body and two first protrusions. Along a second direction, the two first protrusions are located on opposite sides of the main body and on opposite sides of the centerline of the main body extending along the second direction. The third connecting segment is located between the first protrusions and the corresponding data line.

10. The array substrate according to claim 1, characterized in that, In the same pixel, the first electrodes of the two first transistors are electrically connected to the same data line; in the orthographic projection onto the reference plane, the data line is located between the corresponding two pixel electrodes, and the reference plane is the plane containing the surface of the non-light-emitting side of the array substrate; Two sub-pixels in the pixel are arranged along a first direction. The data line includes multiple trace segments, which include multiple first trace segments and multiple second trace segments. Along a second direction, the first trace segments and the second trace segments are at least partially staggered, and one first trace segment and one second trace segment are alternately connected. The second direction intersects the first direction. Along the first direction, the side of the first trace segment closest to the second trace segment is the first side, and the pixel electrode located on the first side of the first trace segment is the first pixel electrode. The first trace segment is electrically connected to the first pixel electrode through a first transistor. Along the first direction, the side of the second trace segment closest to the first trace segment is the second side, and the pixel electrode located on the second side of the second trace segment is the second pixel electrode. The second trace segment is electrically connected to the second pixel electrode through a first transistor.

11. The array substrate according to claim 10, characterized in that, The channel portion of the first transistor is a first channel portion, and the channel portion of the second transistor is a second channel portion; the array substrate further includes: The first active portion includes a first channel portion, a second channel portion, and a first ohmic contact portion. Along the first direction, the first channel portion and the second channel portion are at least partially opposite to each other and connected through the first ohmic contact portion.

12. The array substrate according to claim 10, characterized in that, The channel portion of the first transistor is a first channel portion, and the channel portion of the second transistor is a second channel portion; the array substrate further includes: The second active portion includes a second ohmic contact portion and two first channel portions. Along the first direction, the two first channel portions are at least partially opposite to each other and connected by the second ohmic contact portion. The third active portion includes the second channel portion; along the second direction, the second channel portion is at least partially opposite to the first channel portion.

13. The array substrate according to claim 12, characterized in that, The data line further includes an extension section located between the trace segment and the pixel electrode, and connected to the end of the trace segment; along the first direction, a second ohmic contact portion and two first channel portions are located between the extension section and one of the trace segments.

14. The array substrate according to claim 1, characterized in that, One of the two sub-pixels of the pixel is a first sub-pixel, and the other is a second sub-pixel; the pixel electrode of the first sub-pixel is a first pixel electrode, and the pixel electrode of the second sub-pixel is a second pixel electrode; the two sub-pixels are electrically connected to two data lines that are electrically connected to each other, the data line electrically connected to the first sub-pixel is a first data line, and the data line electrically connected to the second sub-pixel is a second data line; The first sub-pixel and the second sub-pixel are arranged along a first direction; along the first direction, the first data line is located on the side of the first pixel electrode away from the second pixel electrode, and the second data line is located between the first pixel electrode and the second pixel electrode.

15. The array substrate according to claim 14, characterized in that, It includes a display area, a binding area, and a first border area, wherein the binding area and the first border area are located on opposite sides of the display area, and the pixel is located in the display area; The array substrate further includes: A data connection cable is disposed in the first border area; the first data line and the second data line are electrically connected through the data connection cable.

16. The array substrate according to any one of claims 1-15, characterized in that, Two of the sub-pixels in the pixel are arranged along a first direction, and the array substrate further includes: The shielding line, in its orthographic projection onto the reference plane, at least partially overlaps with the data line and is located at least partially between the data line and the pixel electrode; the reference plane is the plane containing the surface of the non-light-emitting side of the array substrate; the distance between the shielding line near the pixel electrode and the data line near the pixel electrode is greater than or equal to 1.5 μm.

17. The array substrate according to claim 16, characterized in that, Also includes: A first storage line, along the second direction, is at least partially located on opposite sides of the pixel electrode, and the shielding line is electrically connected to the first storage line.

18. The array substrate according to claim 16, characterized in that, One of the two discharge signal lines corresponding to the two pixel electrodes is electrically connected to the shielding line.

19. The array substrate according to any one of claims 1-15, characterized in that, It includes a display area, a binding area, and a first border area, wherein the binding area and the first border area are located on opposite sides of the display area, and the pixel is located in the display area; The array substrate further includes: A discharge signal bus is at least partially disposed in the first frame area; the discharge signal line is electrically connected to the discharge signal bus in the first frame area.

20. The array substrate according to any one of claims 1-15, characterized in that, The gate line extends along a first direction, and in a direction perpendicular to the array substrate, the gate line overlaps with the centerline of the pixel electrode extending along the first direction; at least one of the two pixel electrodes has a larger dimension along the first direction than its dimension along the second direction; the first direction and the second direction intersect.

21. The array substrate according to any one of claims 1-15, characterized in that, Two of the sub-pixels in the pixel are arranged along a first direction; The plurality of pixels include a first pixel, a second pixel, and a third pixel with different corresponding colors. Along the first direction, the plurality of first pixels are arranged in a row, the plurality of second pixels are arranged in a row, and the plurality of third pixels are arranged in a row; along the second direction, a row of first pixels, a row of second pixels, and a row of third pixels are arranged sequentially.

22. The array substrate according to any one of claims 1 to 15, characterized in that, One of the two sub-pixels of the pixel is a first sub-pixel, and the other is a second sub-pixel; the ratio of the area of ​​the first sub-pixel to the area of ​​the second sub-pixel is 1 to 2.5, and the display brightness corresponding to the electrode of the first sub-pixel is less than the display brightness corresponding to the second sub-pixel.

23. A display panel, characterized in that, include: The array substrate as described in any one of claims 1 to 22; The opposing substrate is disposed opposite to the array substrate; A liquid crystal layer is disposed between the array substrate and the opposing substrate.

24. A display device, characterized in that, include: The display panel as described in claim 23; A backlight module is disposed on the backlight side of the display panel.

Images