Array substrate, manufacturing method thereof, display panel and display device

Abstract

The application discloses an array substrate, a manufacturing method thereof, a display panel and a display device. The array substrate comprises a substrate, a first metal layer, a second metal layer and a first electrode layer arranged on the substrate in sequence. The substrate comprises a display area and a non-display area located on at least one side of the display area. The first metal layer comprises a first metal pattern located in the non-display area, the second metal layer comprises a second metal pattern located in the non-display area, and the first electrode layer comprises a first electrode located in the non-display area. The first electrode layer comprises a transparent conductive layer and a third metal layer arranged in a stack. The first electrode is directly connected with the first metal pattern and the second metal pattern, respectively, so that the electrical connection of the via hole does not need to be performed through ultra-deep hole etching, thereby avoiding problems such as etching residues or over-etching caused by one-time etching of multiple film layers, solving the problem of poor lap joint of the ultra-deep hole etching, and improving the contact performance of the via hole and the product yield.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to an array substrate and its manufacturing method, a display panel, and a display device. Background Technology

[0002] In display panels, the resistance uniformity of the common electrode is one of the key factors affecting display quality. Uneven resistance distribution can lead to problems such as flickering and display inconsistencies. As display panel sizes increase, the trace length of the common electrode increases, further amplifying the impact of resistance non-uniformity. For high-contrast or HDR display panels, to achieve ultimate black and bright field performance, even minute fluctuations in the common voltage can translate into noticeable flickering or display inconsistencies in low grayscale images.

[0003] Currently, to improve the resistance uniformity of the common electrode, a low-resistivity metal layer is typically introduced in parallel with the common electrode to reduce the overall resistance. However, adding a separate metal layer would require an additional photomask process, complicating the array substrate manufacturing process and increasing production capacity pressure. Therefore, a composite process is proposed that patterns a transparent conductive layer and a low-resistivity metal layer together in the same photomask. This process can simultaneously form the low-resistivity common electrode traces and the transparent conductive layer required for the pixel area in a single photomask.

[0004] However, when using this composite process to fabricate display substrates, only one hole etching is performed. The etching process requires etching through multiple layers of films, including the gate insulating layer, buffer layer, and low-temperature insulating layer, to form an ultra-deep hole. This ultra-deep hole etching process has a narrow window, making it prone to etching residue or over-etching, which can lead to poor subsequent metal bonding. Summary of the Invention

[0005] This application provides an array substrate and its fabrication method, a display panel, and a display device to solve the problem of poor etching of ultra-deep holes in existing composite layer processes.

[0006] The first aspect of this application provides an array substrate, comprising: a substrate, and a first metal layer, a second metal layer, and a first electrode layer sequentially disposed on the substrate; the substrate includes a display area and a non-display area located on at least one side of the display area; the first metal layer includes a first metal pattern located in the non-display area, the second metal layer includes a second metal pattern located in the non-display area, the first electrode layer includes a first electrode located in the non-display area, and the first electrode layer includes a transparent conductive layer and a third metal layer stacked together; The first electrode is in direct contact with and electrically connected to the first metal pattern and the second metal pattern, respectively.

[0007] In some embodiments, the orthogonal projection of the first electrode onto the substrate continuously covers the first metal pattern and the second metal pattern.

[0008] In some embodiments, the second metal layer further includes a third metal pattern located in the display area, and the first electrode layer further includes a second electrode located in the display area; wherein the second electrode is in direct contact with and electrically connected to the third metal pattern.

[0009] In some embodiments, a second electrode layer is further included on the side of the first electrode away from the substrate, the second electrode layer including a third electrode located within the display area; The orthographic projection of the third electrode on the substrate overlaps the orthographic projection of the second electrode on the substrate, and the third electrode is electrically connected to the second electrode.

[0010] In some embodiments, the system further includes a first insulating layer located between the first metal layer and the second metal layer, a second insulating layer located between the second metal layer and the first electrode layer, a planarization layer located between the second insulating layer and the first electrode layer, and a third insulating layer located between the first electrode layer and the second electrode layer; wherein... The first insulating layer includes a first via that overlaps with the first metal pattern in a direction perpendicular to the substrate; the second insulating layer includes a second via that overlaps with the first metal pattern and the second metal pattern in a direction perpendicular to the substrate; the planarization layer and the second insulating layer include a third via that overlaps with the third metal pattern in a direction perpendicular to the substrate; and the third insulating layer includes a fourth via that overlaps with the second electrode in a direction perpendicular to the substrate. The first electrode is electrically connected to the first metal pattern at the first via, and the first electrode is electrically connected to the second metal pattern at the second via. The second electrode is electrically connected to the third metal pattern at the third via, and the third electrode is electrically connected to the second electrode at the fourth via; wherein the first electrode is in complete contact with the side of the second metal pattern.

[0011] In some embodiments, the planarization layer is located only within the display area; or, the planarization layer extends from the display area into the non-display area, and the orthographic projection of the planarization layer on the substrate does not overlap with the orthographic projections of the first via and the second via on the substrate.

[0012] In some embodiments, the non-display area includes a first non-display area with pad terminals, a second non-display area opposite to the first non-display area, and two third non-display areas connecting the first non-display area and the second non-display area; The first non-display area is provided with a test signal line, the second non-display area is provided with an electrostatic unit, and at least one of the third non-display areas includes a gate signal output line and a shift register; At least one of the test signal line, the electrostatic unit, the gate signal output line, and the shift register includes the first metal pattern and the second metal pattern.

[0013] In some embodiments, a second electrode layer is further included on the side of the first electrode layer away from the substrate. The second electrode layer includes a fourth electrode located in the non-display area. The orthographic projection of the fourth electrode on the substrate overlaps with the orthographic projection of the first electrode on the substrate. The fourth electrode is insulated from or electrically connected to the first electrode.

[0014] In some embodiments, the orthographic projections of the first metal pattern on the substrate and the orthographic projections of the second metal pattern on the substrate overlap; or, the orthographic projections of the first metal pattern on the substrate and the orthographic projections of the second metal pattern on the substrate do not overlap.

[0015] The second aspect provided in this application embodiment provides a method for fabricating an array substrate, comprising: A substrate is provided, the substrate including a display area and a non-display area located on at least one side of the display area; A first metal layer is formed on the substrate, the first metal layer including a first metal pattern located in the non-display area; A second metal layer is formed on the first metal layer, the second metal layer including a second metal pattern located in the non-display area; A first electrode layer is formed on the second metal layer. The first electrode layer includes a transparent conductive layer and a third metal layer stacked together. The transparent conductive layer and the third metal layer are made using a common mask. The first electrode layer includes a first electrode located in the non-display area. The first electrode is in direct contact and electrically connected to the first metal pattern and the second metal pattern, respectively.

[0016] In some embodiments, after forming the first metal layer and before forming the second metal layer, the method further includes: forming a first insulating layer over the entire surface; After forming the second metal layer and before forming the first electrode layer, the process further includes: forming a second insulating layer over the entire surface; A dry etching process is used to etch the first insulating layer and the second insulating layer above the first metal pattern and the second metal pattern, exposing at least a portion of the first metal pattern and at least a portion of the second metal pattern.

[0017] In some embodiments, the second metal layer includes a third metal pattern located in the display area, and while etching the first and second insulating layers above the first and second metal patterns using a dry etching process to expose at least a portion of the first metal pattern and at least a portion of the second metal pattern, it also includes: The second insulating layer above the third metal pattern is etched using a dry etching process, exposing at least a portion of the third metal pattern.

[0018] A third aspect provided in this application embodiment is a display panel including the array substrate described above.

[0019] A fourth aspect provided in this application is a display device including the display panel described above.

[0020] The beneficial effects of this application are as follows: This application provides an array substrate and its fabrication method, a display panel, and a display device. The array substrate includes a substrate, and a first metal layer, a second metal layer, and a first electrode layer sequentially disposed on the substrate. The substrate includes a display area and a non-display area located on at least one side of the display area. The first metal layer includes a first metal pattern located in the non-display area, the second metal layer includes a second metal pattern located in the non-display area, and the first electrode layer includes a first electrode located in the non-display area. The first electrode layer includes a transparent conductive layer and a third metal layer stacked together. The first electrode directly contacts and electrically connects to the first metal pattern and the second metal pattern, respectively, eliminating the need for deep hole etching at the junction hole. This avoids problems such as etching residue or over-etching caused by etching multiple layers at once, solves the problem of poor overlap during deep hole etching, and improves the contact performance and product yield of the junction hole. Attached Figure Description

[0021] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the embodiments of this application will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0022] Figure 1a A flowchart illustrating a composite process for fabricating an array substrate is provided in this application embodiment; Figure 1bA flowchart illustrating another composite process for fabricating an array substrate, as provided in this application embodiment; Figure 2 A schematic diagram illustrating the fabrication process of an array substrate provided in an embodiment of this application; Figure 3 A schematic diagram illustrating the fabrication process of another array substrate provided in this application embodiment; Figure 4 A schematic diagram illustrating the fabrication process of another array substrate provided in this application embodiment; Figure 5 A schematic diagram illustrating the fabrication process of another array substrate provided in this application embodiment; Figure 6 A schematic diagram illustrating the fabrication process of another array substrate provided in this application embodiment; Figure 7 A schematic diagram illustrating the fabrication process of another array substrate provided in this application embodiment; Figure 8 This is a schematic diagram of another array substrate provided in the embodiments of this application; Figure 9 This is a schematic diagram of the structure of an array substrate provided in an embodiment of this application; Figure 10 This is a schematic diagram of another array substrate provided in the embodiments of this application; Figure 11 This is a schematic diagram of another array substrate provided in the embodiments of this application; Figure 12 This is a schematic diagram of another array substrate provided in the embodiments of this application; Figure 13 A top view of an array substrate within a first non-display area, provided in an embodiment of this application; Figure 14 for Figure 13 The diagram shows the layer-by-layer layout of the array substrate in the non-display area. Figure 15 A top view of the array substrate provided in an embodiment of this application; Figure 16 A flowchart illustrating the fabrication method of the array substrate provided in this application embodiment; Figure 17 A schematic diagram illustrating the fabrication process of another array substrate provided in this application embodiment; Figure 18 A schematic diagram illustrating the fabrication process of another array substrate provided in this application embodiment; Figure 19 A schematic diagram illustrating the fabrication process of another array substrate provided in this application embodiment; Figure 20A schematic diagram illustrating the fabrication process of another array substrate provided in this application embodiment; Figure 21 A schematic diagram illustrating the fabrication process of another array substrate provided in this application embodiment; Figure 22 A layer-by-layer diagram of an array substrate in the non-display area provided in an embodiment of this application; Figure 23 This is another layer-by-layer diagram of an array substrate in the non-display area provided in an embodiment of this application. Detailed Implementation

[0023] To make the above-mentioned objectives, features, and advantages of this application more apparent and understandable, the application will be further described below in conjunction with the accompanying drawings and embodiments. However, the exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided to make the application more comprehensive and complete, and to fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the figures denote the same or similar structures, and therefore repeated descriptions of them will be omitted. Terms describing position and direction described in this application are illustrative based on the accompanying drawings, but changes can be made as needed, and all such changes are included within the scope of protection of this application. The accompanying drawings of this application are for illustrating relative positional relationships only and do not represent actual scale.

[0024] In display panels, the resistance uniformity of the common electrode is one of the key factors affecting display quality. Uneven resistance distribution can lead to problems such as flickering and display inconsistencies. As display panel sizes increase, the trace length of the common electrode increases, further amplifying the impact of resistance non-uniformity. For high-contrast or HDR display panels, to achieve ultimate black and bright field performance, even minute fluctuations in the common voltage can translate into noticeable flickering or display inconsistencies in low grayscale images.

[0025] Currently, to improve the resistance uniformity of the common electrode, a low-resistivity metal layer (e.g., Cu, Al) is typically introduced in parallel with the common electrode to reduce the overall resistance. However, adding a separate metal layer requires an additional photomask process, complicating the array substrate manufacturing process and increasing production capacity pressure. Therefore, a composite process (HME Mask) has been developed, which patterns a transparent conductive layer and a low-resistivity metal layer together in the same photomask. This process can simultaneously form the low-resistivity common electrode traces and the transparent conductive layer required for the pixel areas in a single photomask. The process for manufacturing display products using this process is as follows: Figure 1a and Figure 1b As shown.

[0026] However, when using this composite process to fabricate a display substrate, only one hole etching is performed. During the etching process, multiple layers of film, including the gate insulating layer, buffer layer, and low-temperature insulating layer, need to be etched through in one go to form an ultra-deep hole. This ultra-deep hole etching process has a narrow window, making it highly susceptible to etching residue or over-etching, leading to poor subsequent metal bonding. The embodiments of this application use... Figure 1a Taking the illustrated process as an example, the process of fabricating array substrates using composite technology will be explained in detail: like Figure 2 (a) and Figure 2 As shown in (b), a gate metal thin film is deposited on substrate 10. The pattern on the gate mask is transferred onto photoresist through exposure. After development, etching, and photoresist stripping, a gate metal layer 20 is formed. After the gate metal layer 20 is fabricated, a SiNx thin film is deposited on top of the gate metal layer 20 to form a gate insulating layer 30, which isolates the gate from the active layer. After thin film deposition, photoresist coating, exposure, development, etching, and photoresist stripping, an active layer is formed. Subsequently, a source / drain metal thin film is deposited. The pattern on the mask is transferred onto photoresist through exposure. After development, etching, and photoresist stripping, a source / drain metal layer 40 is formed on the thin film. The active layer and the source / drain metal layer 40 can be formed by two masking processes, such as... Figure 1b As shown in the flowchart; the active layer and source / drain metal layer 40 can also be formed using a single-exposure technique, such as Figure 1a The flowchart is shown.

[0027] Currently, at locations where electrical connection is required between the gate metal layer 20 and the source / drain metal layer 40, the positional relationship between the patterns of the gate metal layer 20 and the source / drain metal layer 40 typically employs two designs. For example... Figures 2 to 8 As shown in (a), the pattern of the gate metal layer 20 is staggered from the pattern of the source / drain metal layers 40; as Figures 2 to 8 As shown in (b), the pattern of the gate metal layer 20 is widened to serve as a base, and the pattern of the source / drain metal layer 40 is above the pattern of the gate metal layer 20.

[0028] After the source / drain metal layer 40 is fabricated, a SiNx thin film is deposited on top of the source / drain metal layer 40 to form a buffer layer 50, which is used to isolate the subsequent organic film layer 60 from contamination of the transistor channel. When depositing the organic film layer 60, the organic film layer at locations requiring openings and perimeters is exposed, hollowed out entirely, or has large-diameter holes created. For example... Figure 3 (a) and Figure 3 As shown in (b), an ITO conductive layer 71 and a metal layer 72 are deposited sequentially. Figure 4 (a) and Figure 4 As shown in (b), within the non-display area BA, the photoresist PR is exposed to reveal the overlying metal layer 72, and the metal layer 72 within the non-display area BA is then etched. Figure 5(a) and Figure 5 As shown in (b), cleaning is performed after etching. Figure 6 (a) and Figure 6 As shown in (b), the ITO conductive layer 71 is then etched. Figure 7 (a) and Figure 7 As shown in (b), the metal layer 72 is then etched a second time. Figure 8 (a) and Figure 8 As shown in (b), after etching, a low-temperature PVX film 80 is deposited, and a dry etching process is performed using a mask to form multiple vias L. At this point, the vias overlapping the gate metal layer 20 in the direction perpendicular to the substrate 10 require etching of the gate insulating layer 30, the buffer layer 50, and the low-temperature PVX film 80. This multi-layer ultra-deep hole etching requires a longer time, involves more difficult processes, and is prone to causing morphological abnormalities, affecting the bonding of subsequent metal films. A pixel conductive film is then deposited, and the pattern on the pixel mask is transferred to the photoresist through exposure. After development, etching, and photoresist stripping, the pixel electrode layer 90 is formed.

[0029] In view of this, embodiments of this application provide an array substrate to solve the problem of poor etching of ultra-deep holes in existing composite layer processes.

[0030] Figures 9 to 12 This is a schematic diagram of the structure of an array substrate provided in an embodiment of this application, such as... Figures 9 to 12 As shown, the array substrate includes a substrate 10, and a first metal layer 200, a second metal layer 300, and a first electrode layer 400 sequentially disposed on the substrate 10. The substrate 10 includes a display area AA and a non-display area BA located on at least one side of the display area AA. The first metal layer 200 includes a first metal pattern 201 located in the non-display area BA, the second metal layer 300 includes a second metal pattern 301 located in the non-display area BA, and the first electrode layer 400 includes a first electrode 401 located in the non-display area BA. The first electrode layer 400 includes a transparent conductive layer 410 and a third metal layer 420 stacked together.

[0031] In this embodiment, the first electrode 401 is directly in contact with the first metal pattern 201 and the second metal pattern 301, respectively. By directly contacting the first electrode 401 with the first metal pattern 201 and the second metal pattern 301, the junction hole no longer requires electrical connection via ultra-deep hole etching. This avoids problems such as etching residue or over-etching caused by etching multiple layers at once, solves the problem of poor overlap during ultra-deep hole etching, and improves the contact performance of the junction hole and product yield.

[0032] In some embodiments, such as Figures 9 to 12As shown, the orthographic projection of the first electrode 401 onto the substrate 10 continuously covers the first metal pattern 201 and the second metal pattern 301. The first electrode 401 forms a continuous and uninterrupted covering contact with the first metal pattern 201 and the second metal pattern 301, increasing the contact area, reducing contact resistance, and improving the stability and reliability of signal transmission. Furthermore, the direct contact and continuous coverage between the first electrode 401 and the first metal pattern 201 and the second metal pattern 301 effectively prevents the etching solution from seeping along the edges of the metal patterns during subsequent etching processes, avoiding corrosion or over-etching of the second metal pattern 301, and improving the contact performance, process redundancy, and product yield of the connector.

[0033] In some embodiments, such as Figures 9 to 12 As shown, the second metal layer 300 further includes a third metal pattern 302 located in the display area AA, and the first electrode layer 400 further includes a second electrode 402 located in the display area AA. The second electrode 402 and the third metal pattern 302 are in direct contact and electrical connection. Figures 4 to 8 As shown, to achieve electrical connection between the pixel electrode layer 90 and the source / drain metal layer 40, vias need to be etched above the source / drain metal layer 40 in the display area AA, and metal layer 72 and ITO conductive layer 71 need to be etched sequentially within the vias. However, etching the metal within the vias is difficult, and when etching to form the vias, the buffer layer 50 and low-temperature PVX film layer 80 need to be etched to form deep holes. In this embodiment, the second electrode 402 and the third metal pattern 302 are directly contacted and electrically connected in the display area AA, requiring only the etching of the second insulating layer 700, without the need for ultra-deep hole etching of subsequent film layers. This avoids problems such as difficulty in etching the metal within the vias and etching residue or over-etching caused by etching multiple film layers at once, significantly improving product yield.

[0034] In some embodiments, such as Figures 9 to 12 As shown, the array substrate also includes a second electrode layer 500 located on the side of the first electrode 400 away from the substrate 10. The second electrode layer 500 includes a third electrode 501 located within the display area AA. Optionally, the third electrode 501 is a pixel electrode with a slit structure. Figures 9 to 12 As shown, the orthographic projection of the third electrode 501 on the substrate 10 partially overlaps with the orthographic projection of the first electrode layer 400 on the substrate 10. The overlapping area within the pixel aperture region P only includes the transparent conductive layer 410. By retaining only the transparent conductive layer 410 in the overlapping area within the pixel aperture region P and removing the third metal layer 420, the light blocking effect of the third metal layer 420 is avoided, thus ensuring the aperture ratio and light transmittance of the pixel region.

[0035] The orthographic projection of the third electrode 501 on the substrate 10 overlaps the orthographic projection of the second electrode 402 on the substrate 10, and the third electrode 501 is electrically connected to the second electrode 402. The third metal pattern 302 of the display area AA is in direct contact with and electrically connected to the second electrode 402, and the third metal pattern 302 also needs to be electrically connected to the third electrode 501, such as... Figures 9 to 12 As shown, a third insulating layer 900 exists between the second electrode 402 and the third electrode 501. The second electrode 402 and the third electrode 501 are directly electrically connected at the via positions of the third insulating layer 900, thereby ensuring the transmission of data voltage and ultimately realizing image display. Optionally, the third insulating layer 900 may not exist between the second electrode 402 and the third electrode 501, that is, the second electrode 402 and the third electrode 501 are in complete contact, thereby effectively reducing contact resistance and improving display uniformity.

[0036] In some embodiments, the array substrate further includes a first insulating layer 600 located between the first metal layer 200 and the second metal layer 300, a second insulating layer 700 located between the second metal layer 300 and the first electrode layer 400, a planarization layer 800 located between the second insulating layer 700 and the first electrode layer 400, and a third insulating layer 900 located between the first electrode layer 400 and the second electrode layer 500. The first insulating layer 600 includes a first via L1 overlapping the first metal pattern 201 in a direction perpendicular to the substrate 10; the second insulating layer 700 includes a second via L2 overlapping the first metal pattern 201 and the second metal pattern 301 in a direction perpendicular to the substrate 10; the planarization layer 800 and the second insulating layer 700 include a third via L3 overlapping the third metal pattern 302 in a direction perpendicular to the substrate 10; and the third insulating layer 900 includes a fourth via L4 overlapping the second electrode 402 in a direction perpendicular to the substrate 10.

[0037] The first electrode 401 is electrically connected to the first metal pattern 201 at the first via L1, and is electrically connected to the second metal pattern 301 at the second via L2. The second electrode 402 is electrically connected to the third metal pattern 302 at the third via L3, and the third electrode 501 is electrically connected to the second electrode 402 at the fourth via L4. The first electrode 401 is in complete contact with the side of the second metal pattern 301. The first electrode 401 directly contacts the first metal pattern 201 and the second metal pattern 301 through the first via L1 and the second via L2, and the second electrode 402 directly contacts the third metal pattern 302 through the third via L3. This eliminates the need for deep hole etching for electrical connection on the array substrate, avoiding etching residue or over-etching problems caused by etching multiple layers in a single process. It also solves the problem of poor overlap in deep hole etching, improving the contact performance of the adapter holes and increasing product yield. The second electrode 402 is directly electrically connected to the third electrode 501 through the fourth via L4, thereby ensuring the transmission of data voltage and ultimately realizing image display. Optionally, the fourth via L4 can be a transition hole between the pixel electrode and the transistor drain. Correspondingly, the third metal pattern 302 is the drain of the transistor, the third electrode 501 is the pixel electrode, and the second electrode 402 is the transition electrode connecting the transistor drain and the pixel electrode. The first electrode 401 is in complete contact with the side of the second metal pattern 302. The second metal pattern 302 can be covered by the transparent conductive layer 410 and the third metal layer 420, so it will not be damaged during subsequent cleaning, and there is no risk of exposure of the second metal pattern 302.

[0038] In some embodiments, such as Figure 15 As shown, the non-display area BA includes a first non-display area BA1 with pad terminals, a second non-display area BA2 opposite to the first non-display area BA1, and two third non-display areas BA3 connecting the first non-display area BA1 and the second non-display area BA2. The first non-display area BA1 has a test signal line (2D Line), the second non-display area BA2 has an electrostatic discharge (ESD) unit, and at least one third non-display area BA3 includes a gate signal output line (G-Out) and a shift register (GOA). At least one of the test signal line (2D Line), the ESD unit, the gate signal output line (G-Out), and the shift register (GOA) includes a first metal pattern 201 and a second metal pattern 301.

[0039] Specifically, Figure 13This is a top view of the array substrate within the first non-display area. When the test signal line (2D Line) includes a first metal pattern 201 and a second metal pattern 301, since the first metal pattern 201 and the second pattern 301 correspond to the first via L1 and the second via L2 respectively, the first via L1 and the second via L2 are located within the first non-display area BA1 where the test signal line (2D Line) is located. Similarly, when the electrostatic discharge (ESD) unit includes a first metal pattern 201 and a second metal pattern 301, since the first metal pattern 201 and the second metal pattern 301 correspond to the first via L1 and the second via L2 respectively, the first via L1 and the second via L2 are located within the second non-display area BA2 where the electrostatic discharge (ESD) unit is located. When the gate signal output line (G-Out) or shift register (GOA) includes a first metal pattern 201 and a second metal pattern 301, since the first metal pattern 201 and the second metal pattern 301 correspond to the first via L1 and the second via L2 respectively, that is, the first via L1 and the second via L2 are located in the third non-display area BA2 where the gate signal output line (G-Out) or shift register (GOA) is located. At the first via L1 and the second via L2 in the first non-display area BA1, the second non-display area BA2 and the third non-display area BA3, the first electrode 401 directly contacts the first metal pattern 201 and the second metal pattern 301 respectively and covers the second metal pattern 301. There is no need to make electrical connections through ultra-deep hole etching, thereby avoiding problems such as etching residue or over-etching caused by etching multiple film layers at one time, solving the problem of poor overlap caused by ultra-deep hole etching, and improving the contact performance of the adapter hole and the product yield. In addition, the first electrode 401 effectively blocks the etching solution from eroding the second metal pattern 301 in the subsequent etching process, avoiding problems such as corrosion, thinning of line width or poor contact of the second metal pattern 301, and ensuring the electrical connection reliability of each functional module in the non-display area and the overall manufacturing yield.

[0040] In practical applications, the first metal layer 200 can be the gate metal layer 20, and the second metal layer 300 can be the source / drain metal layer 40. For example... Figure 14As shown, a gate metal layer 20 and a source / drain metal layer 40 are formed sequentially, and a via L is formed at the junction hole location using a single dry etching process. The first metal layer 200 and the second metal layer 300 can be made of metal materials such as Cu, Al, Mo, Ti, Cr, W, or their alloys; each metal layer can be a single-layer structure or a multi-layer structure, such as Mo / Al / Mo, Ti / Cu / Ti, MoTi / Cu, etc., without specific limitations. The first insulating layer 500, the second insulating layer 600, and the third insulating layer 900 can be made of silicon nitride or silicon oxide, and can be a single-layer structure or a multi-layer structure (such as silicon oxide / silicon nitride). The above material selection ensures conductivity and insulation performance while being compatible with the structural design of this application, without increasing additional process complexity.

[0041] In some embodiments, the planarization layer 800 may be located only within the display area AA. Or, as... Figures 9 to 12 As shown, the planarization layer 800 extends from the display area into the non-display area BA. The orthographic projection of the planarization layer 800 on the substrate 10 does not overlap with the orthographic projections of the first via L1 and the second via L2 on the substrate 10. Optionally, the orthographic projection of the planarization layer 800 on the substrate 10 does not overlap with the orthographic projections of the first metal pattern 201 or the second metal pattern 301 on the substrate 10. When the planarization layer 800 is located in the display area AA, its thicker film and lower dielectric constant can significantly reduce the parasitic capacitance of the pixel storage capacitor, avoiding insufficient charging or increased power consumption due to excessive capacitance. At the same time, it planarizes the surface morphology of the display area AA, providing a flat substrate for the subsequent electrode layer and improving display uniformity. The planarization layer 800 has a certain degree of water absorption. If it is completely retained in the non-display area BA, moisture can easily seep in along the planarization layer 800, causing electrochemical corrosion of the metal layer. When the planarization layer 800 extends into the non-display area BA, its orthographic projection is designed to not overlap with the orthographic projections of the first via L1 and the second via L2. This means that the planarization layer 800 is either enlarged or completely hollowed out at the via locations. This prevents the planarization layer 800 from absorbing water at the via locations, thus avoiding subsequent metal corrosion and ensuring reliable electrical connections between metal layers at the via locations. Furthermore, during panel manufacturing, the non-display BA area includes dicing lines and sealant coating areas. At the dicing lines, the planarization layer 800 can cause burrs or cracks during cutting, affecting cutting quality. In the sealant area, the planarization layer 800's water absorption can reduce sealant adhesion, leading to encapsulation failure. By completely hollowing out the planarization layer 800 in the corresponding areas of the dicing lines and sealant, or by ensuring its projection avoids these critical areas, these problems are effectively avoided, improving cutting yield and encapsulation reliability.

[0042] In some embodiments, such as Figures 9 to 12As shown, the first electrode layer 400 includes a transparent conductive layer 410 and a third metal layer 420 stacked together, and the first electrode 401 and the second electrode 402 include the transparent conductive layer 410 and the third metal layer 420. Optionally, the orthogonal projection of the first electrode 401 onto the substrate 10 covers the second metal pattern 301. During the fabrication of the array substrate, as... Figure 2 As shown at point M in (a), there are step differences in the topography, such as slope, which will cause bottom etching; or as shown in the image. Figure 2 As shown at point N in (b), a steeper cross-sectional shape will appear. Figure 3 (a) and Figure 3 As shown in (b), an ITO conductive layer 71 and a metal layer 72 are deposited sequentially. When the ITO conductive layer 71 covers the source / drain metal layer 40, the poor morphology at M and N results in a thinner ITO conductive layer 71 at M and N. This can cause the ITO conductive layer 71 to break during magnetron sputtering. Figure 5 (a) and Figure 5 As shown in (b), after etching and cleaning, the ITO conductive layer 71 at M and N has poor morphology and contains breaks. Figure 7 (a) and Figure 7 As shown in (b), a second etching is performed on the metal layer 72. At this point, the etching solution penetrates and corrodes or etches the source / drain metal layer 40, causing corrosion or over-etching. Figure 8 (a) and Figure 8As shown in (b), abnormalities in the cross-sectional shape of the source / drain metal layer 40 are easily caused in the non-display area BA. Subsequent deposition of the buffer layer 50 and ITO conductive layer 71 cannot completely cover it. During cleaning, the buffer layer 50 above the source / drain metal layer 40 is easily etched, exposing the source / drain metal layer 40. During the etching of the metal layer 72, the exposed source / drain metal layer 40 is corroded and etched, resulting in poor transition vias between the gate and the source / drain metal layer. Severe surface damage to the source / drain metal layer 40 can lead to high contact resistance, via burnout, and consequently, defects such as GOA stripes and AD. In this embodiment, the first electrode 401 includes a transparent conductive layer 410 and a third metal layer 420. The transparent conductive layer 410 directly contacts and covers the first metal pattern 201 and the second metal pattern 301, forming a good interface contact with the underlying metal layer. Furthermore, the composite film layer used in the first electrode 401 effectively reduces contact resistance. This composite film layer has lower requirements for the side shape of the metal pattern and can cover defective sides of the metal pattern. The third metal layer 402 covers the transparent conductive layer 410, providing a low-resistance path and further enhancing the physical protection of the second metal pattern 301. In subsequent etching processes, the first electrode 401 effectively prevents the etching solution from penetrating, avoiding corrosion of the second metal pattern 301. Moreover, the first electrode 401 can be formed simultaneously in a single photomask process, eliminating the need for additional photomask passes, thus balancing product performance, manufacturing yield, and production cost.

[0043] In some embodiments, such as Figures 9 to 12 As shown, the array substrate also includes a second electrode layer 500 located on the side of the first electrode layer 400 away from the substrate 10, such as... Figure 11 and Figure 12 As shown, the second electrode layer 500 includes a fourth electrode 502 located in the non-display area BA. The orthographic projection of the fourth electrode 502 onto the substrate 10 overlaps with the orthographic projection of the first electrode 401 onto the substrate 10. The fourth electrode 502 and the first electrode 401 are either insulated from or electrically connected to each other. Optionally, as... Figure 9 and Figure 10 As shown, the non-display area BA may not retain the second electrode layer 500.

[0044] In some embodiments, such as Figure 10 and Figure 12 As shown, the orthographic projection of the first metal pattern 201 on the substrate 10 overlaps with the orthographic projection of the second metal pattern 301 on the substrate 10. Alternatively, as... Figure 9 and Figure 11As shown, the orthographic projection of the first metal pattern 201 on the substrate 10 and the orthographic projection of the second metal pattern 301 on the substrate 10 do not overlap. In this embodiment, regardless of whether the orthographic projections of the first metal pattern 201 and the second metal pattern 301 on the substrate 10 overlap or not, the first electrode 401 can directly contact and electrically connect with the first metal pattern 201 and the second metal pattern 301, and effectively cover the second metal pattern 301. Therefore, in subsequent etching processes, there is no need to perform electrical connections through ultra-deep hole etching, thereby avoiding problems such as etching residue or over-etching caused by etching multiple film layers at once, solving the problem of poor overlap during ultra-deep hole etching, and improving the contact performance of the adapter hole and the product yield. Furthermore, in subsequent etching processes, the first electrode 401 can prevent the etching solution from penetrating and corroding the second metal pattern 301, avoiding pattern defects or poor contact of the adapter hole caused by the exposure of the second metal pattern 301. The first electrode 401 can be used in two common layout designs, and can significantly improve the manufacturing yield and contact reliability of the array substrate without changing the existing process flow or increasing the number of photomasks.

[0045] Based on the same inventive concept, embodiments of this application also provide a method for fabricating an array substrate, such as... Figure 16 As shown, it includes: S161. A substrate is provided, the substrate including a display area and a non-display area located on at least one side of the display area.

[0046] S162. A first metal layer is formed on the substrate, the first metal layer including a first metal pattern located in the non-display area.

[0047] S163. A second metal layer is formed on the first metal layer, the second metal layer including a second metal pattern located in the non-display area.

[0048] S164. A first electrode layer is formed on the second metal layer. The first electrode layer includes a transparent conductive layer and a third metal layer stacked together. The transparent conductive layer and the third metal layer are made using a common mask. The first electrode layer includes a first electrode located in the non-display area. The first electrode is in direct contact and electrically connected to the first metal pattern and the second metal pattern, respectively.

[0049] In this embodiment, the first electrode 401 is directly in contact with the first metal pattern 201 and the second metal pattern 301, so that the adapter hole does not need to be electrically connected by ultra-deep hole etching. This avoids problems such as etching residue or over-etching caused by etching multiple film layers at one time, solves the problem of poor overlap caused by ultra-deep hole etching, and improves the contact performance of the adapter hole and the product yield.

[0050] In some embodiments, after forming the first metal layer 200 and before forming the second metal layer 300, the method further includes: forming a first insulating layer 600 over the entire surface. After forming the second metal layer 300 and before forming the first electrode layer 400, the method further includes: forming a second insulating layer 700 over the entire surface, followed by etching the first insulating layer 600 and the second insulating layer 700 over the first metal pattern 201 and the second metal pattern 301 using a dry etching process, exposing at least a portion of the first metal pattern 201 and at least a portion of the second metal pattern 301. Figure 18 As shown, this application adds a dry etching process to etch the first insulating layer 600 and the second insulating layer 700 above the first metal pattern 201, and simultaneously etches the second insulating layer 700 above the second metal pattern 301. This allows the subsequently fabricated first electrode 401 to directly contact the first metal pattern 201 and the second metal pattern 301, eliminating the need for deep hole etching for electrical connection at the junction. This avoids etching residue or over-etching issues caused by etching multiple layers in a single process, solves the problem of poor overlap during deep hole etching, and improves the contact performance and product yield of the junction.

[0051] In some embodiments, such as Figure 18 As shown, the second metal layer 300 includes a third metal pattern 302 located in the display area AA. While using a dry etching process to etch the first insulating layer 600 and the second insulating layer 700 above the first metal pattern 201 and the second metal pattern 301, exposing at least a portion of the first metal pattern 201 and at least a portion of the second metal pattern 301, it also includes: A dry etching process is used to etch the second insulating layer 700 above the third metal pattern 302, exposing at least a portion of the third metal pattern 302. Furthermore, within the display area AA, the second electrode 402 is directly electrically connected to the third metal pattern 302, eliminating the need for subsequent deep hole etching of the film layers. This avoids problems such as difficulty in etching metal within vias, etching residues caused by etching multiple film layers in a single operation, or over-etching, significantly improving product yield.

[0052] To better understand the fabrication method of the array substrate in this application, it is described in detail. Figures 17 to 21 In diagram (a), the orthographic projections of the first metal pattern 201 on the substrate 10 and the second metal pattern 301 on the substrate 10 do not overlap. Figure 22 This is a top-down view of the structure within the non-display area, layer by layer. Figures 17 to 21 (b) shows a structure where the orthographic projections of the first metal pattern 201 on the substrate 10 and the second metal pattern 301 on the substrate 10 overlap. Figure 23This is a top-down view of the structure within the non-display area, layer by layer.

[0053] like Figure 17 As shown, a first metal layer 200 is deposited on substrate 10. The pattern on the photomask is transferred to photoresist through exposure. After development, etching, and photoresist stripping processes, a first metal pattern 201 is formed. A first insulating layer 600 is deposited above the first metal layer 200. Subsequently, a second metal layer 300 is deposited, and the pattern on the photomask is transferred to photoresist. After development, etching, and photoresist stripping processes, a second metal pattern 301 and a third metal pattern 302 are formed on the thin film. A second insulating layer 700 is then deposited. Finally, a planarization layer 800 is deposited, and large holes are drilled in the planarization layer 800.

[0054] like Figure 18 As shown, a dry etching process is used to etch the first insulating layer 600 and the second insulating layer 700 above the first metal pattern 201 and the second metal pattern 301, exposing at least a portion of the first metal pattern 201 and the second metal pattern 301. Simultaneously, a dry etching process is used to etch the second insulating layer 700 above the third metal pattern 302, exposing at least a portion of the third metal pattern 302. The dry etching process is anisotropic, resulting in less corrosion of the first metal pattern 201 and the second metal pattern 301 during etching. Furthermore, the subsequent production of the thicker first electrode 401 can effectively cover the locations of corrosion-induced defects in the metal patterns.

[0055] like Figure 19 , Figure 22 (c) and Figure 23 As shown in (c), a transparent conductive layer 410 and a third metal layer 420 are sequentially deposited to form a first electrode layer 400. Figure 20 As shown, a portion of photoresist PR is retained within the non-display area BA and the display area AA, wherein the orthogonal projection of the photoresist PR in the non-display area BA onto the substrate 10 covers the orthogonal projections of the first metal pattern 201 and the second metal pattern 301 onto the substrate 10. Figure 21As shown, firstly, the third metal layer 420 without photoresist PR protection is etched, and then part of the photoresist PR is cleaned. Since the second metal pattern 301 is covered by the transparent conductive layer 410 and the third metal layer 420, the etching and cleaning will not damage the edge position of the second metal pattern 301, and the second metal pattern 301 will not be corroded. The exposed transparent conductive layer 410 is etched, and the part of the third metal layer 420 exposed in the display area AA is etched to remove the photoresist PR. The third insulating layer 900 is deposited, and the third insulating layer 900 in the display area AA and the non-display area BA is etched through a mask. At this time, only one layer of the third insulating layer 900 needs to be etched. Compared with simultaneously etching the first insulating layer 600, the second insulating layer 700 and the third insulating layer 900, the dry etching process of only etching the third insulating layer 900 is simple and has a low error risk. A second electrode layer 500 is then deposited. The pattern on the photomask is transferred to the photoresist through exposure. After development, etching, and photoresist stripping processes, as shown... Figure 11 and Figure 12 As shown, a fourth electrode 502 is formed in the non-display area BA and a third electrode 501 is formed in the display area AA, or, as... Figure 9 and Figure 10 As shown, the third electrode 501 is formed only in the display area AA. This application adds a dry etching process after forming the second insulating layer 700 to etch the first insulating layer 600 and the second insulating layer 700 above the first metal pattern 201, and to etch the second insulating layer 700 above the second metal pattern 301. Furthermore, the first electrode 401 is directly in contact with the first metal pattern 201 and the second metal pattern 301, eliminating the need for deep hole etching for electrical connection at the junction. This avoids problems such as etching residue or over-etching caused by etching multiple layers in a single operation, solves the problem of poor overlap during deep hole etching, and improves the contact performance and product yield of the junction.

[0056] Based on the same inventive concept, embodiments of this application also provide a display panel, which includes a counter substrate and an array substrate disposed opposite to each other, and a liquid crystal layer encapsulated between the counter substrate and the array substrate. The array substrate is any of the array substrates provided in the embodiments of this application. The principle by which this display panel solves the problem is similar to that of the aforementioned array substrate, therefore, the implementation of this display panel can refer to the implementation of the aforementioned array substrate, and the repeated parts will not be described again here.

[0057] Based on the same inventive concept, this application also provides a display device, including the display panel described above in this application embodiment. The principle by which this display device solves the problem is similar to that of the aforementioned display panel; therefore, the implementation of this display device can refer to the implementation of the aforementioned display panel, and the repeated parts will not be described again here.

[0058] In specific implementations, in the embodiments of this application, the display device can be any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator. Other essential components of the display device are those that should be understood by those skilled in the art, and will not be described in detail here, nor should they be construed as limitations on this application.

[0059] In summary, embodiments of this application provide an array substrate and its fabrication method, a display panel, and a display device. The array substrate includes a substrate 10, and a first metal layer 200, a second metal layer 300, and a first electrode layer 400 sequentially disposed on the substrate 10. The substrate 10 includes a display area AA and a non-display area BA located on at least one side of the display area AA. The first metal layer 200 includes a first metal pattern 201 located in the non-display area BA, the second metal layer 300 includes a second metal pattern 301 located in the non-display area BA, and the first electrode layer 400 includes a first electrode 401 located in the non-display area BA. The first electrode 401 is directly contacted and electrically connected to the first metal pattern 201 and the second metal pattern 301, respectively. In this embodiment, the first electrode 401 is directly in contact with the first metal pattern 201 and the second metal pattern 301, so that the adapter hole does not need to be electrically connected by ultra-deep hole etching. This avoids problems such as etching residue or over-etching caused by etching multiple film layers at one time, solves the problem of poor overlap caused by ultra-deep hole etching, and improves the contact performance of the adapter hole and the product yield.

[0060] Although preferred embodiments of this application have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this application.

[0061] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the spirit and scope of this application. Therefore, if such modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include such modifications and variations.

Claims

1. An array substrate, characterized in that, The substrate includes a substrate, and a first metal layer, a second metal layer, and a first electrode layer sequentially disposed on the substrate; the substrate includes a display area and a non-display area located on at least one side of the display area; the first metal layer includes a first metal pattern located in the non-display area, the second metal layer includes a second metal pattern located in the non-display area, the first electrode layer includes a first electrode located in the non-display area, and the first electrode layer includes a transparent conductive layer and a third metal layer stacked together. The first electrode is in direct contact with and electrically connected to the first metal pattern and the second metal pattern, respectively.

2. The array substrate as described in claim 1, characterized in that, The orthogonal projection of the first electrode onto the substrate continuously covers the first metal pattern and the second metal pattern.

3. The array substrate as described in claim 1, characterized in that, The second metal layer further includes a third metal pattern located in the display area, and the first electrode layer further includes a second electrode located in the display area; wherein the second electrode is in direct contact with and electrically connected to the third metal pattern.

4. The array substrate as described in claim 3, characterized in that, It also includes a second electrode layer located on the side of the first electrode away from the substrate, the second electrode layer including a third electrode located within the display area; The orthographic projection of the third electrode on the substrate overlaps the orthographic projection of the second electrode on the substrate, and the third electrode is electrically connected to the second electrode.

5. The array substrate as described in claim 4, characterized in that, It also includes a first insulating layer located between the first metal layer and the second metal layer, a second insulating layer located between the second metal layer and the first electrode layer, a planarization layer located between the second insulating layer and the first electrode layer, and a third insulating layer located between the first electrode layer and the second electrode layer; wherein, The first insulating layer includes a first via that overlaps with the first metal pattern in a direction perpendicular to the substrate; the second insulating layer includes a second via that overlaps with the first metal pattern and the second metal pattern in a direction perpendicular to the substrate; the planarization layer and the second insulating layer include a third via that overlaps with the third metal pattern in a direction perpendicular to the substrate; and the third insulating layer includes a fourth via that overlaps with the second electrode in a direction perpendicular to the substrate. The first electrode is electrically connected to the first metal pattern at the first via, and the first electrode is electrically connected to the second metal pattern at the second via. The second electrode is electrically connected to the third metal pattern at the third via, and the third electrode is electrically connected to the second electrode at the fourth via; wherein the first electrode is in complete contact with the side of the second metal pattern.

6. The array substrate as described in claim 5, characterized in that, in, The planarization layer is located only within the display area; or, the planarization layer extends from the display area into the non-display area, and the orthographic projection of the planarization layer on the substrate does not overlap with the orthographic projections of the first via and the second via on the substrate.

7. The array substrate as described in claim 5 or 6, characterized in that, The non-display area includes a first non-display area with pad terminals, a second non-display area opposite to the first non-display area, and two third non-display areas connecting the first non-display area and the second non-display area; The first non-display area is provided with a test signal line, the second non-display area is provided with an electrostatic unit, and at least one of the third non-display areas includes a gate signal output line and a shift register; At least one of the test signal line, the electrostatic unit, the gate signal output line, and the shift register includes the first metal pattern and the second metal pattern.

8. The array substrate as claimed in claim 1, characterized in that, It also includes a second electrode layer located on the side of the first electrode layer away from the substrate. The second electrode layer includes a fourth electrode located in the non-display area. The orthographic projection of the fourth electrode on the substrate overlaps with the orthographic projection of the first electrode on the substrate. The fourth electrode is insulated from or electrically connected to the first electrode.

9. The array substrate as described in any one of claims 1-6 and 8, characterized in that, The orthographic projections of the first metal pattern on the substrate and the second metal pattern on the substrate overlap in an area; or, the orthographic projections of the first metal pattern on the substrate and the second metal pattern on the substrate do not overlap.

10. A method for manufacturing an array substrate as described in any one of claims 1-9, characterized in that, include: A substrate is provided, the substrate including a display area and a non-display area located on at least one side of the display area; A first metal layer is formed on the substrate, the first metal layer including a first metal pattern located in the non-display area; A second metal layer is formed on the first metal layer, the second metal layer including a second metal pattern located in the non-display area; A first electrode layer is formed on the second metal layer. The first electrode layer includes a transparent conductive layer and a third metal layer stacked together. The transparent conductive layer and the third metal layer are fabricated using a single photomask. The first electrode layer includes a first electrode located in the non-display area. The first electrode is in direct contact with and electrically connected to the first metal pattern and the second metal pattern, respectively.

11. The manufacturing method as described in claim 10, characterized in that, After forming the first metal layer and before forming the second metal layer, the method further includes: forming a first insulating layer over the entire surface; After forming the second metal layer and before forming the first electrode layer, the process further includes: forming a second insulating layer over the entire surface; A dry etching process is used to etch the first insulating layer and the second insulating layer above the first metal pattern and the second metal pattern, exposing at least a portion of the first metal pattern and at least a portion of the second metal pattern.

12. The manufacturing method as described in claim 11, characterized in that, The second metal layer includes a third metal pattern located in the display area. While employing a dry etching process to etch the first and second insulating layers above the first and second metal patterns, exposing at least a portion of the first and second metal patterns, it also includes: The second insulating layer above the third metal pattern is etched using a dry etching process, exposing at least a portion of the third metal pattern.

13. A display panel, characterized in that, Includes the array substrate as described in any one of claims 1-9.

14. A display device, characterized in that, Includes the display panel as described in claim 13.

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