Display panel and display terminal

Abstract

The application discloses a display panel and a display terminal. The display terminal comprises a display area and a non-display area arranged at the periphery of the display area. The display panel comprises a substrate, at least one metal layer and a frame electrode. The at least one metal layer is arranged on one side of the substrate. The frame electrode is arranged on the side of the metal layer away from the substrate, and the frame electrode is located in the non-display area and surrounds the display area. The metal layer comprises a first connecting part located in the non-display area, and the first connecting part is connected in parallel with the frame electrode. The resistivity of the first connecting part is smaller than that of the frame electrode. In the display panel, the first connecting part is connected in parallel with the frame electrode, and the resistivity of the first connecting part is smaller than that of the frame electrode, so that the resistance of the frame electrode can be reduced, the signal attenuation degree on the frame electrode can be reduced, and the color difference can be improved.

Description

Technical Field

[0001] This application relates to the field of display technology, and more particularly to a display panel and a display terminal. Background Technology

[0002] Electronic paper is a reflective display technology that uses electrical signals to control the arrangement of charged particles to display images. Its display effect is close to that of traditional paper, it requires no backlighting, relies on ambient light for imaging, and has the significant advantage of zero power consumption when the image is still. It has been widely used in electronic tags, electronic signage, and e-readers, becoming an increasingly important type of flat panel display.

[0003] Electronic paper typically features a border signal area between the display area and the peripheral circuitry. This border signal area shields the display area from the influence of signals from the peripheral circuitry. The border signal area is displayed in white or black; however, inconsistencies in color can occur, resulting in color differences and affecting the display quality of the border signal area. Summary of the Invention

[0004] This application provides a display panel and a display terminal to improve the technical problem that color inconsistency and color difference easily occur when displaying the border signal area, thus affecting the display effect of the border signal area.

[0005] To achieve the above objectives, according to a first aspect of this application, a display panel is provided, including a display area and a non-display area disposed around the periphery of the display area, the display panel comprising: substrate; A first connecting portion is disposed on one side of the substrate, and the first connecting portion is located in the non-display area; A bezel electrode is disposed on the side of the first connection portion away from the substrate, and the bezel electrode is located in the non-display area, and the bezel electrode is disposed around the display area; The first connecting portion is connected in parallel with the frame electrode, and the resistivity of the first connecting portion is less than the resistivity of the frame electrode.

[0006] Optionally, the display panel includes at least one metal layer, the first connection portion is located on the same metal layer or a different metal layer, and the frame electrode passes through a via and is electrically connected to the first connection portion.

[0007] Optionally, the non-display area includes a first border area disposed on opposite sides of the display area, and the first connecting portion includes a first sub-line and a second sub-line disposed on different layers; the display panel also includes a plurality of gate driving signal lines, and the gate driving signal lines are located in the first border area; At least one of the gate drive signal lines is disposed on the same layer as the first sub-line. The first sub-line includes a plurality of spaced connecting blocks. The gate drive signal line extends through the gap between two adjacent connecting blocks to the display area, and the two adjacent connecting blocks are electrically connected through the second sub-line.

[0008] Optionally, the gate drive signal lines are all disposed on the same layer as the first sub-line, the second sub-line is located on the side of the first sub-line away from the substrate, the second sub-line passes through a via and is electrically connected to the connecting block, each of the connecting blocks corresponds to at least two vias, and the frame electrode passes through the via and is electrically connected to the second sub-line.

[0009] Optionally, the second sub-line includes a plurality of connection segments extending along the extension direction of the gate drive signal line, the plurality of connection segments being arranged along the extension direction of the first frame region, and one connection segment connecting two adjacent connection blocks.

[0010] Optionally, the second sub-line is continuously arranged in the extending direction of the first frame area, and the second sub-line has a plurality of openings, the openings exposing a portion of the gate drive signal line.

[0011] Optionally, the non-display area further includes a second border area connecting the two first border areas, the display panel includes a driver chip disposed in the second border area, and the display panel further includes a second connecting portion, the driver chip being connected to the first connecting portion through the second connecting portion.

[0012] Optionally, the non-display area further includes a third border area opposite to the second border area, wherein at least one of the first sub-line and the second sub-line is continuously disposed in the extending direction of the third border area.

[0013] Optionally, the non-display area includes a corner area, and the first connecting portion is provided with a plurality of hollow patterns. The hollow patterns extend along the extension direction of the outline of the display area and are located outside the corner area.

[0014] According to a second aspect of this application, a display terminal is provided, including the display panel described above.

[0015] In the display panel of this application embodiment, by connecting the first connecting part in parallel with the frame electrode, and the resistivity of the first connecting part is less than the resistivity of the frame electrode, the resistance of the frame electrode can be reduced, the signal attenuation on the frame electrode can be reduced, and the color difference can be improved.

[0016] Other features and advantages of this application will be described in detail in the following detailed description section. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] To gain a more complete understanding of this application and its beneficial effects, the following description will be provided in conjunction with the accompanying drawings, wherein the same reference numerals in the following description denote the same parts.

[0019] Figure 1 This is a top view of the display panel provided in an exemplary embodiment of this disclosure; Figure 2 yes Figure 1 A magnified structural diagram at point A in the diagram; Figure 3 yes Figure 1 A magnified structural diagram at point B in the diagram; Figure 4 yes Figure 2 Schematic diagram of the cross-sectional structure at point CC; Figure 5 yes Figure 2 Another cross-sectional structural diagram at the CC section; Figure 6 yes Figure 1 Another enlarged structural diagram at point A in the diagram; Figure 7 yes Figure 1 Another enlarged structural diagram at point B in the diagram; Figure 8 yes Figure 6 Schematic diagram of the cross-sectional structure at point CC; Figure 9 yes Figure 6 A schematic diagram of the structure of a portion of the membrane layer in the first border region; Figure 10 yes Figure 6 A schematic diagram of the structure of the first border area in the image; Figure 11 yes Figure 6 Another structural diagram of the first border area in the image; Figure 12 This is a schematic diagram of the structure of a display terminal provided in an exemplary embodiment of this disclosure.

[0020] Explanation of reference numerals in the attached figures: 1-Display panel; AA-Display area; NA-Non-display area; NA1-First border area; NA2-Second border area; NA3-Third border area; NA4-Corner area; 10-Substrate; 20-Metal layer; 21-First metal layer; 22-Second metal layer; 201-First connecting part; 2111-Connecting block; 211-First sub-wire; 221-Second sub-wire; 2211-Connecting segment; 221b-Opening; 201a-Hollow pattern; 202-Second connecting part; 30-Border electrode; 40 - Gate drive signal line; 50-Driver chip; 61 - Gate insulation layer; 62 - Interlayer insulation layer; HL - Via; 2-Display terminal; 3-Terminal body. Detailed Implementation

[0021] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the protection scope of this application.

[0022] According to the first aspect of this application, Figures 1 to 10 As shown, a display panel 1 is provided, including a display area AA and a non-display area NA disposed around the display area AA. The display panel 1 includes a substrate 10, a first connecting portion 201 and a frame electrode 30. The frame electrode 30 is disposed on the side of the first connecting portion 201 away from the substrate 10, and the frame electrode 30 is located in the non-display area NA. The frame electrode 30 surrounds the display area AA. The first connecting portion 201 is located in the non-display area NA, and the first connecting portion 201 is connected in parallel with the frame electrode 30. The resistivity of the first connecting portion 201 is less than the resistivity of the frame electrode 30.

[0023] like Figure 1 As shown, the display panel 1 includes a display area AA and a non-display area NA disposed around the display area AA. The display area AA can be provided with multiple sub-pixels, which can include red sub-pixels, green sub-pixels, and blue sub-pixels, thereby realizing color display. The non-display area NA can be provided with a driving circuit, such as a gate driving circuit, which can provide driving signals to the sub-pixels.

[0024] The substrate 10 can be a rigid material or a flexible material. The rigid material can be glass, quartz, or silicon wafer. The flexible material can be one of polyimide (PI), polycarbonate (PC), polynorbornene (PNB), and polyethylene terephthalate (PET).

[0025] In some embodiments, the material of the first connecting portion 201 is formed of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and copper (Cu) or an alloy thereof.

[0026] In some embodiments, the material of the frame electrode 30 is a transparent conductive metal, such as ITO (indium tin oxide), IZO (indium zinc oxide), etc.

[0027] like Figures 1 to 3 As shown, the bezel electrode 30 is located in the non-display area NA and surrounds the display area AA. Bezel signals can be input to the bezel electrode 30. The bezel electrode 30 can shield the influence of external circuit signals on the signals in the display area AA.

[0028] In some embodiments, the display panel 1 can be used in electronic paper display products, etc. The bezel electrode 30 can be used to implement the display. By controlling the bezel signal, the area corresponding to the bezel electrode 30 can be displayed in white or black.

[0029] Since the bezel electrode 30 surrounds the display area AA, the bezel signal will attenuate when it is transmitted on the bezel electrode 30. This will cause a color difference in the white or black display of the bezel electrode 30 area, affecting the display effect of the bezel electrode 30 area.

[0030] To address this, in the non-display area NA, the first connection portion 201 is connected in parallel with the frame electrode 30, and the resistivity of the first connection portion 201 is less than the resistivity of the frame electrode 30, thereby reducing the resistance of the frame electrode 30, reducing the signal attenuation on the frame electrode 30, and thus improving color difference.

[0031] Optionally, such as Figures 1 to 8 As shown, the display panel 1 includes at least one metal layer 20, the first connection portion 201 is located on the same metal layer 20 or a different metal layer 20, and the frame electrode 30 passes through the via HL and is electrically connected to the first connection portion 201.

[0032] In some embodiments, such as Figures 2 to 5 As shown, the first connecting part 201 can be located in the same metal layer 20.

[0033] In other embodiments, such as Figures 6 to 8 As shown, the first connection portion 201 can be disposed on two metal layers 20. In this case, the first connection portion 201 in two adjacent metal layers 20 can be electrically connected through via HL.

[0034] In some embodiments, such as Figure 4 , Figure 5 and Figure 8As shown, the metal layer 20 may include a first metal layer 21 and a second metal layer 22. The display panel 1 also includes a gate insulating layer 61 located between the first metal layer 21 and the second metal layer 22, and an interlayer insulating layer 62 located between the second metal layer 22 and the frame electrode 30.

[0035] The gate insulating layer 61 can be an inorganic insulating layer, which can be one or more layers of silicon oxide, silicon nitride, silicon oxynitride, etc.

[0036] The interlayer insulation layer 62 can be an inorganic insulation layer and / or an organic insulation layer. The inorganic insulation layer can be one or more layers of silicon oxide, silicon nitride, or silicon oxynitride. The organic insulation layer can be polyimide, acrylic resin, epoxy resin, etc.

[0037] In some embodiments, such as Figures 2 to 4 As shown, the first connection portion 201 is located on the first metal layer 21. The frame electrode 30 is electrically connected to the first connection portion 201 through the via HL. The via HL between the first metal layer 21 and the frame electrode 30 passes through the gate insulating layer 61 and the interlayer insulating layer 62, and the via HL is a deep hole.

[0038] In some embodiments, such as Figure 2 , Figure 3 and Figure 5 As shown, the first connection portion 201 is located on the second metal layer 22, and the frame electrode 30 is electrically connected to the first connection portion 201 through the via HL. The via HL between the second metal layer 22 and the frame electrode 30 passes through the interlayer insulating layer 62 and... Figure 4 Compared to the embodiments in, Figure 5 The via HL in the diagram does not penetrate the gate insulation layer 61, and the via HL is a shallow hole.

[0039] In some embodiments, such as Figures 6 to 8 As shown, the first connection portion 201 is located on the first metal layer 21 and the second metal layer 22. The frame electrode 30 can be electrically connected to the first connection portion 201 on the second metal layer 22 through the via HL. The via HL between the frame electrode 30 and the second metal layer 22 passes through the interlayer insulating layer 62. The first connection portion 201 on the second metal layer 22 can be electrically connected to the first connection portion 201 on the first metal layer 21 through the via HL. The via HL between the second metal layer 22 and the first metal layer 21 passes through the gate insulating layer 61.

[0040] Optionally, such as Figure 1 , Figures 6 to 11As shown, the non-display area NA includes a first frame area NA1 disposed on opposite sides of the display area AA. The first connection portion 201 includes a first sub-line 211 and a second sub-line 221 disposed on different layers. The display panel 1 also includes a plurality of gate drive signal lines 40, which are located in the first frame area NA1. At least one gate drive signal line 40 is disposed on the same layer as the first sub-line 211. The first sub-line 211 includes a plurality of spaced connecting blocks 2111. The gate drive signal line 40 extends through the gap between two adjacent connecting blocks 2111 to the display area AA, and the two adjacent connecting blocks 2111 are electrically connected through the second sub-line 221. And / or, at least one gate drive signal line 40 is disposed on the same layer as the second sub-line 221. The second sub-line 221 includes a plurality of spaced connecting blocks 2111. The gate drive signal line 40 extends through the gap between two adjacent connecting blocks 2111 to the display area AA, and the two adjacent connecting blocks 2111 are electrically connected through the first sub-line 211.

[0041] The first connection portion 201 includes a first sub-line 211 and a second sub-line 221 disposed in different layers, meaning that the first sub-line 211 and the second sub-line 221 can be located in different metal layers 20. For example, the first sub-line 211 is located in the first metal layer 21 and the second sub-line 221 is located in the second metal layer 22, or the first sub-line 211 is located in the second metal layer 22 and the second sub-line 221 is located in the first metal layer 21.

[0042] In some embodiments, such as Figure 1 As shown, the first border area NA1 can be the left border area and the right border area of ​​the display panel 1, and the left border area and the right border area are located on both sides of the display area AA.

[0043] like Figure 1 and Figure 9 As shown, the first frame area NA1 is provided with a gate drive signal line 40. The gate drive signal line 40 is used to input gate drive signals, such as scan signals and common electrode signals, to the sub-pixels of the display area AA. The left and right frame areas of the display panel 1 can both be provided with gate drive signal lines 40.

[0044] In some embodiments, the left and right border areas of the display panel 1 can be symmetrically arranged. The border electrode 30, gate drive signal line 40, first connection portion 201, etc. in the left border area can be symmetrically arranged with the border electrode 30, gate drive signal line 40, first connection portion 201, etc. in the right border area, thereby reducing the resistance difference between the left and right border areas, and thus reducing the display color difference between the left and right border areas.

[0045] In some embodiments, the first border area NA1 is further provided with a gate driving unit (not shown in the figure), one end of the gate driving signal line 40 near the gate driving unit is connected to the gate driving unit, and the other end of the gate driving signal line 40 near the display area AA extends toward the display area AA.

[0046] In some embodiments, such as Figures 6 to 9 As shown, the first connection portion 201 includes a first sub-line 211 and a second sub-line 221. The first sub-line 211 is connected in parallel with the frame electrode 30, and the second sub-line 221 is connected in parallel with the frame electrode 30. By configuring the first connection portion 201 to include the first sub-line 211 and the second sub-line 221, the resistance of the frame electrode 30 can be further reduced without increasing the footprint of the first connection portion 201.

[0047] In some embodiments, such as Figure 9 As shown, the gate drive signal line 40 can be arranged on the same layer as the first sub-line 211. In order to avoid short circuit between the gate drive signal line 40 and the first sub-line 211, the first sub-line 211 can be configured to include multiple spaced connection blocks 2111. A first break is formed between two adjacent connection blocks 2111. The gate drive signal line 40 extends through the first break toward the display area AA. The connection blocks 2111 on both sides of the first break can be electrically connected through the second sub-line 221.

[0048] It should be noted that the second sub-line 221 can be located on the side of the first sub-line 211 away from the substrate, or the second sub-line 221 can be located on the side of the first sub-line 211 close to the substrate.

[0049] In some embodiments, a portion of the gate drive signal lines 40 can be disposed on the same layer as the first sub-line 211, and another portion of the gate drive signal lines 40 can be disposed on the same layer as the second sub-line 221. To prevent the gate drive signal lines 40 from short-circuiting with the first sub-line 211 and the second sub-line 221, multiple first breaks can be provided on the first sub-line 211, through which the gate drive signal lines 40 extend toward the display area AA; multiple spaced connecting blocks 2111 are provided on the second sub-line 221, with a second break formed between two adjacent connecting blocks 2111, through which the gate drive signal lines 40 extend toward the display area AA. By distributing the gate drive signal lines 40 on the first metal layer 21 and the second metal layer 22, the wiring area of ​​the gate drive signal lines 40 can be increased, thereby reducing the width of the first border area NA1.

[0050] like Figure 10 and Figure 11 As shown, Figure 10 yes Figure 6 A schematic diagram of the structure of the first border region NA1 in the image. Figure 11 yes Figure 6Another structural diagram of the first border region NA1 in the diagram. Because the first sub-line 211 has a first break to avoid the gate drive signal line 40, this causes the first sub-line 211 to be disconnected. For example... Figure 10 and Figure 11 As shown, the first sub-line 211 located on both sides of the first break can be connected through the second sub-line 221, thereby making the first sub-line 211 on both sides of the first break electrically connected.

[0051] In other embodiments, the second sub-line 221 is disconnected because it has a second break to avoid the gate drive signal line 40. The second sub-line 221 located on both sides of the second break can be connected by the first sub-line 211, thereby making the second sub-lines 221 on both sides of the second break electrically connected.

[0052] Optionally, such as Figures 6 to 11 As shown, the gate drive signal lines 40 are all disposed on the same layer as the first sub-line 211. The second sub-line 221 is located on the side of the first sub-line 211 away from the substrate 10. The second sub-line 221 passes through the via HL and is electrically connected to the connecting block 2111. Each connecting block 2111 corresponds to at least two vias HL. The frame electrode 30 passes through the via HL and is electrically connected to the second sub-line 221.

[0053] In some embodiments, such as Figure 9 As shown, all gate drive signal lines 40 are located in the first metal layer 21, that is, all gate drive signal lines 40 are disposed in the same layer as the first sub-line 211. The first sub-line 211 includes multiple spaced connecting blocks 2111, and a first break is formed between two adjacent connecting blocks 2111. The gate drive signal line 40 extends towards the display area AA through the first break.

[0054] The second sub-line 221 passes through via HL and is electrically connected to the connecting block 2111, and each connecting block 2111 corresponds to at least two vias HL. That is to say, each connecting block 2111 is electrically connected to the second sub-line 221 through at least two vias HL, thereby improving the reliability of the conduction between the connecting block 2111 and the second sub-line 221.

[0055] The frame electrode 30 is connected to the second sub-line 221 through the via HL, and the second sub-line 221 is connected to the first sub-line 211 through the via HL, thereby connecting the frame electrode 30, the second sub-line 221, and the first sub-line 211 in parallel.

[0056] Optionally, such as Figure 10 As shown, the second sub-line 221 includes multiple connection segments 2211. The connection segments 2211 extend along the extension direction of the gate drive signal line 40. The multiple connection segments 2211 are arranged along the extension direction of the first border region NA1. The connection segments 2211 connect two adjacent connection blocks 2111.

[0057] In some embodiments, such as Figure 10 As shown, the connection segment 2211 extends along the extension direction of the gate drive signal line 40, and multiple connection segments 2211 are arranged along the extension direction of the first frame region NA1. The long side of the connection segment 2211 extends in the same direction as the gate drive signal line 40, and the short side of the connection segment 2211 is perpendicular to the long side.

[0058] It should be noted that the extension direction of the first border area NA1 is the same as the extension direction of the outline of the display area AA. When the display area AA is rectangular, the extension direction of the first border area NA1 is... Figure 10 The vertical direction in the middle.

[0059] In some embodiments, such as Figure 10 As shown, the connecting segment 2211 connects two connecting blocks 2111 located on both sides of the first break. This means that one connecting segment 2211 can correspond to one first break, i.e., one connecting segment 2211 corresponds to one gate drive signal line 40. Through this arrangement, the area of ​​the connecting segment 2211 can be reduced, thereby reducing the coupling capacitance between the connecting segment 2211 and the gate drive signal line 40, and reducing the signal influence of the connecting segment 2211 on the gate drive signal line 40.

[0060] Optionally, Figure 11 The embodiments and Figure 10 The difference in the embodiment lies in the second sub-line 221. For example... Figure 11 As shown, the second sub-line 221 is continuously arranged in the extension direction of the first frame area NA1, and the second sub-line 221 is provided with a plurality of openings 221b, the openings 221b exposing part of the gate drive signal line 40.

[0061] In some embodiments, such as Figure 11 As shown, the second sub-line 221 is continuously arranged in the extension direction of the first frame area NA1, thereby increasing the footprint of the second sub-line 221 and further reducing the resistance of the frame electrode 30 and the second sub-line 221 after being connected in parallel.

[0062] In some embodiments, such as Figure 11 As shown, the second sub-line 221 has multiple openings 221b, with each opening exposing a portion of the gate drive signal line 40. This arrangement reduces the overlap area between the second sub-line 221 and the gate drive signal line 40, thereby reducing the coupling capacitance between them and minimizing the signal impact of the second sub-line 221 on the gate drive signal line 40.

[0063] Optionally, such as Figure 1As shown, the non-display area NA also includes a second border area NA2 that connects the two first border areas NA1. The display panel 1 includes a driver chip 50 disposed in the second border area NA2. The metal layer 20 also includes a second connection portion 202. The driver chip 50 is connected to the first connection portion 201 through the second connection portion 202.

[0064] The second bezel area NA2 can be the lower bezel area of ​​the display panel 1, and the driver chip 50 is disposed within the second bezel area NA2. The second connection part 202 is connected to the first connection part 201. The driver chip 50 outputs a bezel signal, which is transmitted to the first connection part 201 via the second connection part 202, and then to the bezel electrode 30 via the first connection part 201, thereby inputting a bezel signal to the bezel electrode 30.

[0065] In some embodiments, such as Figure 1 As shown, there can be two second connecting parts 202. One second connecting part 202 can be connected to the first connecting part 201 at the left frame, and the other second connecting part 202 can be connected to the first connecting part 201 at the right frame. The first connecting part 201 can surround the left, top, and right sides of the display area AA, that is, the first connecting part 201 can be continuously arranged in other frame areas except for the second frame area NA2.

[0066] Optionally, such as Figure 1 and Figure 2 , Figure 6 As shown, the non-display area NA also includes a third border area NA3 opposite to the second border area NA2. In the third border area NA3, at least one of the first sub-line 211 and the second sub-line 221 is continuously arranged in the extending direction of the third border area NA3.

[0067] The third frame area NA3 can be the upper frame area of ​​the display panel 1. In the third frame area NA3, at least one of the first sub-line 211 and the second sub-line 221 can be continuously arranged. Through the above arrangement, the resistance of the first sub-line 211 and / or the second sub-line 221 can be reduced, thereby further reducing the resistance of the frame electrode 30 after being connected in parallel with the first connection part 201.

[0068] In some embodiments, the first sub-line 211 is continuously disposed in the extension direction of the third border area NA3.

[0069] In some embodiments, the second sub-line 221 is continuously disposed in the extension direction of the third border area NA3.

[0070] In some embodiments, the first sub-line 211 and the second sub-line 221 are continuously arranged in the extension direction of the third border area NA3.

[0071] Optionally, such as Figures 1 to 3 , Figure 6 and Figure 7 As shown, the non-display area NA includes a corner area NA4. The first connecting part 201 is provided with a plurality of hollow patterns 201a. The hollow patterns 201a extend along the extension direction of the outline of the display area AA and are located outside the corner area NA4.

[0072] In some embodiments, the non-display area NA includes a corner area NA4, which is located at the corner of the display panel 1. The display panel 1 includes four corner areas NA4, which are located between adjacent first border area NA1 and second border area NA2, and between first border area NA1 and third border area NA3, respectively.

[0073] like Figures 2 to 3 , Figure 6 and Figure 7 As shown, the first connecting portion 201 is provided with multiple hollow patterns 201a. The hollow patterns 201a can be elongated, with the long side of the elongated pattern extending along the outline of the display area AA. This arrangement reduces the overlap area between the first connecting portion 201 and the gate drive signal line 40, thereby reducing the coupling capacitance between the first connecting portion 201 and the gate drive signal line 40, and decreasing the influence of the first connecting portion 201 on the signal of the gate drive signal line 40.

[0074] In some embodiments, such as Figures 2 to 3 , Figure 6 and Figure 7 As shown, the number of cutout patterns 201a can be set as needed. For example, in the width direction of the first border area NA1, the number of cutout patterns 201a can be one or more. In the width direction of the third border area NA3, the number of cutout patterns 201a can be one or more.

[0075] In some embodiments, such as Figures 2 to 3 , Figure 6 and Figure 7 As shown, the hollow pattern 201a is located outside the corner area NA4. This means that the first connecting part 201 of the corner area NA4 may not have the hollow pattern 201a. By setting it as described above, the area of ​​the first connecting part 201 of the corner area NA4 can be increased, thereby allowing more vias HL to be set in the corner area NA4, which improves the reliability of the electrical connection between the first connecting part 201 and the frame electrode 30.

[0076] According to the second aspect of this application, such as Figure 12 As shown, a display terminal 2 is provided, including the display panel 1 described above.

[0077] In some embodiments, such as Figure 12As shown, the display terminal 2 includes a display panel 1 and a terminal body 3, which are combined into one unit.

[0078] In some embodiments, such as Figure 12 As shown, the display terminal 2 can be any product or component with display function, such as electronic paper, mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator.

[0079] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0080] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0081] The embodiments, implementation methods, and related technical features of this application can be combined and substituted for each other without conflict.

[0082] The above are merely preferred embodiments of this application and are not intended to limit this application in any way. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of this application without departing from the scope of the technical solution of this application shall still fall within the scope of the technical solution of this application.

Claims

1. A display panel, characterized in that, The display panel includes a display area and a non-display area disposed around the periphery of the display area. substrate; A first connecting portion is disposed on one side of the substrate, and the first connecting portion is located in the non-display area; A bezel electrode is disposed on the side of the first connection portion away from the substrate, and the bezel electrode is located in the non-display area, and the bezel electrode is disposed around the display area; The first connecting portion is connected in parallel with the frame electrode, and the resistivity of the first connecting portion is less than the resistivity of the frame electrode.

2. The display panel according to claim 1, characterized in that, The display panel includes at least one metal layer, the first connection portion is located on the same metal layer or a different metal layer, and the frame electrode passes through a via and is electrically connected to the first connection portion.

3. The display panel according to claim 2, characterized in that, The non-display area includes a first frame area disposed on opposite sides of the display area; the first connecting portion includes a first sub-line and a second sub-line disposed in different layers; the display panel also includes a plurality of gate driving signal lines, the gate driving signal lines being located in the first frame area. At least one of the gate drive signal lines is disposed on the same layer as the first sub-line. The first sub-line includes a plurality of spaced connecting blocks. The gate drive signal line extends through the gap between two adjacent connecting blocks to the display area, and the two adjacent connecting blocks are electrically connected through the second sub-line.

4. The display panel according to claim 3, characterized in that, The gate drive signal lines are all disposed on the same layer as the first sub-line. The second sub-line is located on the side of the first sub-line away from the substrate. The second sub-line passes through a via and is electrically connected to the connecting block. Each of the connecting blocks corresponds to at least two vias. The frame electrode passes through the via and is electrically connected to the second sub-line.

5. The display panel according to claim 4, characterized in that, The second sub-line includes multiple connection segments that extend along the extension direction of the gate drive signal line. The multiple connection segments are arranged along the extension direction of the first frame region, and one connection segment connects two adjacent connection blocks.

6. The display panel according to claim 4, characterized in that, The second sub-line is continuously arranged in the extending direction of the first frame area, and the second sub-line has a plurality of openings, the openings exposing a portion of the gate drive signal line.

7. The display panel according to claim 3, characterized in that, The non-display area further includes a second border area connecting the two first border areas. The display panel includes a driver chip disposed in the second border area. The display panel also includes a second connecting portion, and the driver chip is connected to the first connecting portion through the second connecting portion.

8. The display panel according to claim 7, characterized in that, The non-display area also includes a third border area opposite to the second border area, wherein at least one of the first sub-line and the second sub-line is continuously arranged in the extending direction of the third border area.

9. The display panel according to any one of claims 2 to 8, characterized in that, The non-display area includes a corner area, and the first connecting part is provided with multiple hollow patterns. The hollow patterns extend along the extension direction of the outline of the display area and are located outside the corner area.

10. A display terminal, characterized in that, Includes the display panel as described in any one of claims 1 to 9.

Images