A clock correction method for a chip

Abstract

The application discloses a clock correction method of a chip, and relates to the technical field of signal processing, and comprises the following steps: acquiring a real-time CFC value of a CAN clock in a target chip; the CAN clock is obtained by frequency division of a system clock; calculating a standard CFC value of the CAN clock according to a CAN baud rate, a CAN clock frequency and a CFSEL mode of a CAN controller in the target chip; determining whether a frequency error exists in the system clock according to the real-time CFC value and a preset standard CFC value; if the frequency error exists in the system clock, then adjusting a frequency division coefficient of a phase-locked loop of the system clock according to a frequency error type, and returning to acquire the real-time CFC value of the CAN clock until the frequency error does not exist in the system clock. The application improves the precision of the system clock in the chip.

Description

Technical Field

[0001] This invention relates to the field of signal processing technology, and more particularly to a clock correction method for a chip. Background Technology

[0002] With the continuous development of automotive electrification and intelligentization technologies, many chip manufacturers have successively launched dedicated SOC (System on Chip) chips for small automotive motors. The main feature of these chips is that they integrate power supply, microcontroller unit, power drive, CAN transceiver, and various peripheral functional units.

[0003] Some chips incorporate a high-precision internal clock source, which can be multiplied by two sets of phase-locked loops and configured as a system clock or further configured as a CAN clock. However, some internal clock sources have lower precision and may still exhibit slight frequency deviations, leading to deviations in the system clock obtained by dividing these internal clock sources, making them unsuitable for scenarios requiring high-precision clocking. Summary of the Invention

[0004] This invention provides a clock calibration method for chips to improve the accuracy of clocks in chips.

[0005] In a first aspect, embodiments of the present invention provide a clock calibration method for a chip, comprising:

[0006] Obtain the real-time CFC (CAN Frame Counter) value of the CAN (Controller Area Network) clock in the target chip; the CAN clock is obtained by dividing the system clock.

[0007] Based on the CAN baud rate, CAN clock frequency, and CFSEL (CAN FrameCounter Selection) mode of the CAN controller in the target chip, calculate the standard CFC value of the CAN clock;

[0008] Based on the real-time CFC value and the preset standard CFC value, determine whether the system clock has a frequency error;

[0009] If the system clock has a frequency error, the frequency division coefficient of the phase-locked loop of the system clock is adjusted according to the type of frequency error, and the process returns to obtain the real-time CFC value of the CAN clock in the target chip until the system clock has no frequency error; the phase-locked loop is used to divide the clock source of the target chip to obtain the system clock.

[0010] Secondly, embodiments of the present invention also provide a clock correction device for a chip, comprising:

[0011] The acquisition module is used to acquire the real-time CFC (CAN Frame Counter) value of the CAN (Controller Area Network) clock in the target chip; the CAN clock is obtained by dividing the system clock.

[0012] The calculation module is used to calculate the standard CFC value of the CAN clock based on the CAN baud rate, CAN clock frequency and CFSEL (CANFrame Counter Selection) mode of the target chip;

[0013] The determination module is used to determine whether there is a frequency error in the system clock based on the real-time CFC value and the preset standard CFC value;

[0014] The adjustment module is used to adjust the frequency division coefficient of the phase-locked loop of the system clock according to the type of frequency error if the system clock has a frequency error, and return to obtain the real-time CFC value of the CAN clock in the target chip until the system clock has no frequency error; the phase-locked loop is used to divide the clock source of the target chip to obtain the system clock.

[0015] Thirdly, embodiments of the present invention also provide an electronic device, comprising:

[0016] At least one processor; and

[0017] A memory that is communicatively connected to at least one processor; wherein

[0018] The memory stores instructions that can be executed by at least one processor, which enables the at least one processor to perform the clock correction method for the chip provided in any embodiment of the present invention.

[0019] Fourthly, embodiments of the present invention also provide a computer-readable storage medium storing computer instructions for causing a processor to execute a clock correction method for a chip according to any embodiment of the present invention.

[0020] Fifthly, embodiments of the present invention also provide a computer program product, characterized in that the computer program product includes a computer program, which, when executed by a processor, implements the clock correction method for a chip according to any embodiment of the present invention.

[0021] The embodiments of the present invention can count the real-time CFC value of the CAN clock in the chip and calculate the standard CFC value of the CAN clock. By comparing the real-time CFC value and the standard CFC value of the CAN clock, the system clock can be indirectly detected to detect whether there is a frequency deviation. If there is a frequency deviation, the frequency of the system clock can be corrected by adjusting the frequency division coefficient of the phase-locked loop, thereby obtaining an accurate system clock and improving the accuracy of the system clock.

[0022] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0023] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0024] Figure 1A This is a flowchart of a chip clock calibration method according to Embodiment 1 of the present invention;

[0025] Figure 1B This is a system clock control block diagram provided according to Embodiment 1 of the present invention;

[0026] Figure 2 This is a flowchart of a chip clock correction method according to Embodiment 2 of the present invention;

[0027] Figure 3 This is a schematic diagram of the structure of a chip clock correction device according to Embodiment 3 of the present invention;

[0028] Figure 4 This is a structural diagram of an electronic device that implements a chip clock correction method according to an embodiment of the present invention. Detailed Implementation

[0029] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0030] It should be noted that the terms "first" and "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0031] The acquisition, storage, and application of CAN baud rate, CAN clock frequency, and CFSEL mode involved in the technical solutions of this invention comply with the provisions of relevant laws and regulations and do not violate public order and good morals.

[0032] Example 1

[0033] Figure 1A This is a flowchart of a chip clock calibration method provided in Embodiment 1 of the present invention. This embodiment is applicable to the case of calibrating the system clock of a chip. The method can be executed by a chip clock calibration device, which can be implemented in hardware and / or software and specifically configured in an electronic device.

[0034] See Figure 1A The clock calibration method for the chip shown includes:

[0035] S101. Obtain the real-time CFC (CAN Frame Counter) value of the CAN (Controller Area Network) clock in the target chip; the CAN clock is obtained by dividing the system clock.

[0036] S102. Calculate the standard CFC value of the CAN clock based on the CAN baud rate, CAN clock frequency, and CFSEL (CANFrame Counter Selection) mode of the CAN controller in the target chip.

[0037] S103. Determine whether the system clock has a frequency error based on the real-time CFC value and the preset standard CFC value.

[0038] S104. If the system clock has a frequency error, adjust the division coefficient of the phase-locked loop of the system clock according to the type of frequency error, and return to obtain the real-time CFC value of the CAN clock in the target chip until the system clock has no frequency error; the phase-locked loop is used to divide the clock source of the target chip to obtain the system clock.

[0039] In this embodiment, the target chip can be the chip to be calibrated using the system clock. The real-time CFC value can be the CFC value acquired in real time. The standard CFC value can be the CFC value used as a frequency error detection standard. The CFC value can refer to the number of CAN clock cycles within a set CAN bus timing interval; wherein, the set CAN bus timing interval can be determined by the CFSEL mode. The CFSEL mode can refer to the mode of the CAN bus timing interval used to determine the CFC value, which may include, but is not limited to, the first mode and the second mode; wherein, the first mode can be the interval between two received dominant levels as the CAN bus timing interval required to determine the CFC value, which can be achieved by setting the CFESL value to 000B, that is, when the CFSEL mode is the first mode, the CFC value is the number of CAN clock cycles between two dominant levels; the second mode can be the interval between two bit time start points as the CAN bus timing interval required to determine the CFC value, which can be achieved by setting the CFESL value to 101B, that is, when the CFSEL mode is the second mode, the CFC value is the number of CAN clock cycles between two bit time start points. In an alternative embodiment, the real-time CFC value can be obtained by reading fixed-width frames such as the 0x55 frame of the CAN bus.

[0040] In one optional embodiment, obtaining the real-time CFC value of the CAN clock in the target chip includes: configuring the CFMOD (CAN Frame Counter Mode) mode of the CAN controller in the target chip to bit timing analysis mode, and configuring the CFSEL mode to a similar timing interval mode; controlling the CAN controller to count the real-time CFC value of the CAN clock.

[0041] CFMOD mode refers to the operating mode of the CFC (CAN Frame Counter) built into the CAN controller. CFMOD mode can include, but is not limited to, bit timing analysis mode, frame counting mode, timestamp mode, and error counting mode. Bit timing analysis mode is a dedicated operating mode used to monitor, analyze, and verify bit timing-related parameters of the CAN bus. In this mode, the CAN controller can obtain bit timing characteristic information such as CAN bit duration, bit timing deviation, and bus transmission delay by counting CAN clock cycles. Similar timing interval mode can use the interval between similar timing sequences as the CAN bus timing interval for determining the CFC value. Similar timing interval mode can specifically include a first mode and a second mode.

[0042] Specifically, after each power-on or reset of the target chip, the CFMOD mode of the CAN controller in the target chip is configured to bit timing analysis mode, which can be achieved by setting the CFMOD value to 10B; and the CFSEL mode is configured to either the first mode or the second mode; the CAN controller is controlled to count the real-time CFC value of the CAN clock; the CAN controller stores the real-time CFC value in the CFC register and reads the real-time CFC value from the CFC register.

[0043] It is understandable that by adopting the above technical solution, after each power-on or reset of the target chip, the CAN controller is configured with CFMOD mode and CFSEL mode to automatically count the real-time CFC value and store it in the CFC register. This allows the real-time CFC value to be quickly obtained from the CFC register when the real-time CFC value of the CAN clock in the target chip is obtained, thus improving the efficiency of obtaining the real-time CFC value.

[0044] In this embodiment, the frequency error type may include, but is not limited to, a high error type and a low error type. A high error type indicates that the system clock frequency is too high; a low error type indicates that the system clock frequency is too low.

[0045] Specifically, by comparing the real-time CFC value with the preset standard CFC value, if the real-time CFC value is greater than the standard CFC value, or if the real-time CFC value is less than the standard CFC value, it is determined whether the system clock has a frequency error; if the real-time CFC value is greater than the standard CFC value, the frequency error type is large; if the real-time CFC value is less than the standard CFC value, the frequency error type is small.

[0046] If a frequency error exists in the system clock, and the frequency error type is high, the frequency division coefficient of the phase-locked loop of the system clock is reduced by a set step size; if the frequency error type is low, the frequency division coefficient of the phase-locked loop of the system clock is increased by a set step size; then return to obtain the real-time CFC value of the CAN clock in the target chip until the system clock has no frequency error.

[0047] In one optional embodiment, the frequency division coefficient ranges from 39 to 200, and the step size can be 1; that is, if the frequency error type is high, the frequency division coefficient of the phase-locked loop of the system clock is reduced by 1; if the frequency error type is low, the frequency division coefficient of the phase-locked loop of the system clock is increased by 1.

[0048] Optional, Figure 1B This is a block diagram of the system clock control for a chip. For example... Figure 1B As shown, the SYS1_CLK clock selector can select a clock source from HP30_CLK, PLL0_CLK, and PLL1_CLK to generate SYS1_CLK, the system clock. CAN_CLK, the CAN clock, can be obtained by dividing the SYS1_CLK clock. HP30_CLK is the chip's built-in original clock source; PLL0_CLK is the clock source obtained by dividing HP30_CLK using a phase-locked loop (PLL0); and PLL1_CLK is the clock source obtained by dividing HP30_CLK using a PLL1. In this embodiment, the SYS1_CLK clock selector uses either PLL0_CLK or PLL1_CLK as the clock source to generate SYS1_CLK; and by adjusting the division coefficient of PLL0_CLK or PLL1_CLK, a system clock with no frequency deviation is obtained.

[0049] Optionally, determining whether the system clock has a frequency error based on the real-time CFC value and a preset standard CFC value includes: filtering the real-time CFC value to obtain a filtered CFC value; and determining whether the system clock has a frequency error based on the filtered CFC value and the standard CFC value.

[0050] Specifically, historical CFC values ​​that are close to the real-time time corresponding to the real-time CFC value can be obtained; for example, five historical CFC values ​​prior to the real-time CFC value can be selected, and the average value between each historical CFC value and the real-time CFC value can be determined as the filtered CFC value; or the maximum and minimum values ​​can be removed from each historical CFC value and the real-time CFC value, and the average value between the remaining CFC values ​​can be calculated as the filtered CFC value; using a certain algorithm, it can be determined whether the system clock has a frequency error based on the filtered CFC value and the standard CFC value.

[0051] It is understandable that by adopting the above technical solution, the real-time CFC value can be filtered to avoid the misjudgment of the system clock frequency error caused by instantaneous glitches. Thus, by using the more accurate filtered CFC value and the standard CFC value, the existence of frequency error in the system clock can be accurately determined, thereby improving the accuracy of frequency error judgment.

[0052] Optionally, determining whether the system clock has a frequency error based on the filtered CFC value and the standard CFC value includes: comparing the filtered CFC value and the standard CFC value to obtain a comparison result; if the comparison result is different, then determining that the system clock has a frequency error; otherwise, determining that the system clock does not have a frequency error.

[0053] The embodiments of the present invention can count the real-time CFC value of the CAN clock in the chip and calculate the standard CFC value of the CAN clock. By comparing the real-time CFC value and the standard CFC value of the CAN clock, the system clock can be indirectly detected to detect whether there is a frequency deviation. If there is a frequency deviation, the frequency of the system clock can be corrected by adjusting the frequency division coefficient of the phase-locked loop, thereby obtaining an accurate system clock and improving the accuracy of the system clock.

[0054] Example 2

[0055] Figure 2 This is a flowchart of a chip clock correction method provided in Embodiment 2 of the present invention. Based on the technical solution of the above embodiments, the present invention optimizes and improves the determination operation of the standard CFC value.

[0056] Furthermore, the step of "calculating the standard CFC value of the CAN clock based on the CAN baud rate, CAN clock frequency, and CFSEL mode of the CAN controller in the target chip" is refined into "querying the number of CAN bit measurements corresponding to the CFSEL mode; calculating the standard CFC value based on the number of CAN bit measurements, the CAN clock frequency, and the CAN baud rate" to improve the operation of determining the standard CFC value.

[0057] It should be noted that for any parts not described in detail in the embodiments of the present invention, please refer to the description in the foregoing embodiments.

[0058] See Figure 2 The clock calibration method for the chip shown includes:

[0059] S201. Obtain the real-time CFC value of the CAN clock in the target chip; the CAN clock is obtained by dividing the system clock.

[0060] S202. Calculate the standard CFC value of the CAN clock based on the CAN baud rate, CAN clock frequency, and CFSEL mode of the CAN controller in the target chip.

[0061] S203. Query the number of CAN bit measurements corresponding to the CFSEL mode.

[0062] S204. Calculate the standard CFC value based on the number of CAN bit measurements, the CAN clock frequency, and the CAN baud rate.

[0063] S205. If the system clock has a frequency error, adjust the division coefficient of the phase-locked loop of the system clock according to the type of frequency error, and return to obtain the real-time CFC value of the CAN clock in the target chip until the system clock has no frequency error; the phase-locked loop is used to divide the clock source of the target chip to obtain the system clock.

[0064] In this embodiment, the number of CAN bits measured can be the number of CAN bits contained within a set CAN bus timing interval; a CAN bit is the smallest unit of CAN bus data transmission.

[0065] Specifically, the CFSEL mode includes a first mode and a second mode; the number of CAN bit measurements corresponding to the first mode is 2; the number of CAN bit measurements corresponding to the second mode is 1; the number of CAN bit measurements corresponding to the CFSEL mode is queried; a certain algorithm is used to determine the unit CAN clock cycle length based on the CAN clock frequency; the standard CFC value is calculated based on the unit measurement duration and the CAN clock cycle length.

[0066] Optionally, calculating the standard CFC value based on the number of CAN bit measurements, the CAN clock frequency, and the CAN baud rate includes: determining the unit measurement duration based on the CAN baud rate and the number of CAN bit measurements; determining the unit CAN clock cycle length based on the CAN clock frequency; and calculating the standard CFC value based on the unit measurement duration and the CAN clock cycle length.

[0067] The unit measurement duration can be the duration of a set CAN bus timing interval; the unit CAN clock cycle length is the length of one CAN clock cycle. Specifically, the ratio between the number of CAN bit measurements and the CAN baud rate is determined as the unit measurement duration; the unit CAN clock cycle length is determined according to the CAN clock frequency; and the ratio between the unit measurement duration and the CAN clock cycle length is determined as the standard CFC value.

[0068] For example, the standard CFC value can be determined using the following formula:

[0069] ;

[0070] ;

[0071] ;

[0072] in, Indicates the standard CFC value; Indicates the unit of measurement duration; Indicates the CAN clock cycle length; Indicates the number of CAN bit measurements; Indicates the CAN baud rate; Indicates the CAN clock frequency.

[0073] In an optional embodiment, if the system clock of the target chip does not have a frequency error, the user subroutine is entered, and the real-time CFC value is continuously acquired to detect whether the system clock has a frequency error. If a frequency error occurs, the frequency division coefficient of the phase-locked loop of the system clock is adjusted until the system clock does not have a frequency error, and the user subroutine is continued to be executed.

[0074] In one optional embodiment, before adjusting the frequency division factor of the phase-locked loop (PLL), the global interrupt is disabled and the PLL is unlocked; after adjusting the frequency division factor and before obtaining a new real-time CFC value, the PLL is locked and the global interrupt is enabled; the microcontroller unit in the target chip monitors whether the PLL can be stably locked after the frequency division factor is adjusted.

[0075] If the phase-locked loop (PLL) can stably lock after the frequency division factor is adjusted, the process returns to obtaining the real-time CFC value of the CAN clock in the target chip until the system clock has no frequency error. The PLL is used to divide the clock source of the target chip to obtain the system clock. If the PLL cannot stably lock after the frequency division factor is adjusted, the frequency division factor is restored to its value before the adjustment, and the PLL is relocked. The process returns to obtaining the real-time CFC value of the CAN clock in the target chip, and the system clock is re-determined for a frequency error based on the newly obtained real-time CFC value and the standard CFC value.

[0076] This invention can calculate the standard CFC value by querying the number of CAN bit measurements corresponding to the CFSEL mode and combining it with the CAN clock frequency and CAN baud rate. This ensures that the standard CFC value calculated by the number of CAN bit measurements corresponding to the CFSEL mode has the same physical meaning as the real-time CFC value obtained by configuring the CAN controller in the CFSEL mode, avoiding misjudgments caused by the mismatch between the measurement scenarios of the standard CFC value and the real-time CFC value. At the same time, by querying the number of CAN bit measurements corresponding to the CFSEL mode, it can adapt to multiple CFSEL modes without having to predetermine a fixed standard CFC value for a specific CFSEL mode. Moreover, it can also determine the matching standard CFC value when the CAN baud rate or CAN clock frequency changes, thus broadening the applicable scenarios and improving universality.

[0077] Example 3

[0078] Figure 3 This is a schematic diagram of a chip clock correction device according to Embodiment 3 of the present invention. This embodiment of the present invention is applicable to situations where the system clock of a chip needs to be corrected. The device can execute a chip clock correction method and can be implemented in hardware and / or software. The device can be configured in an electronic device.

[0079] like Figure 3 The clock correction device for the chip shown includes: an acquisition module 301, a calculation module 302, a determination module 303, and an adjustment module 304. Among them,

[0080] The acquisition module 301 is used to acquire the real-time CFC (CAN Frame Counter) value of the CAN (Controller Area Network) clock in the target chip; the CAN clock is obtained by dividing the system clock.

[0081] The calculation module 302 is used to calculate the standard CFC value of the CAN clock based on the CAN baud rate, CAN clock frequency and CFSEL (CANFrame Counter Selection) mode of the target chip;

[0082] The determination module 303 is used to determine whether there is a frequency error in the system clock based on the real-time CFC value and the preset standard CFC value;

[0083] The adjustment module 304 is used to adjust the frequency division coefficient of the phase-locked loop of the system clock according to the type of frequency error if the system clock has a frequency error, and return to obtain the real-time CFC value of the CAN clock in the target chip until the system clock has no frequency error; the phase-locked loop is used to divide the clock source of the target chip to obtain the system clock.

[0084] The embodiments of the present invention can count the real-time CFC value of the CAN clock in the chip and calculate the standard CFC value of the CAN clock. By comparing the real-time CFC value and the standard CFC value of the CAN clock, the system clock can be indirectly detected to detect whether there is a frequency deviation. If there is a frequency deviation, the frequency of the system clock can be corrected by adjusting the frequency division coefficient of the phase-locked loop, thereby obtaining an accurate system clock and improving the accuracy of the system clock.

[0085] Optionally, module 303 includes:

[0086] A filtering unit is used to filter the real-time CFC value to obtain a filtered CFC value;

[0087] The determining unit is used to determine whether there is a frequency error in the system clock based on the filtered CFC value and the standard CFC value.

[0088] Optional, define the unit, specifically for:

[0089] The filtered CFC value and the standard CFC value are compared to obtain the comparison result;

[0090] If the comparison results are different, it is determined that the system clock has a frequency error;

[0091] Otherwise, it is determined that the system clock has no frequency error.

[0092] Optionally, the calculation module 302 includes:

[0093] The query unit is used to query the number of CAN bit measurements corresponding to the CFSEL mode;

[0094] The calculation unit is used to calculate the standard CFC value based on the number of CAN bit measurements, the CAN clock frequency, and the CAN baud rate.

[0095] Optional, computational unit, specifically used for:

[0096] The unit measurement duration is determined based on the CAN baud rate and the number of CAN bits measured.

[0097] The length of a unit CAN clock cycle is determined based on the CAN clock frequency;

[0098] The standard CFC value is calculated based on the unit measurement duration and the CAN clock cycle length.

[0099] Optionally, module 301 is used specifically for:

[0100] Configure the CFMOD (CAN Frame Counter Mode) mode of the CAN controller in the target chip to bit timing analysis mode, and configure the CFSEL mode to the same timing interval mode.

[0101] The CAN controller is controlled to count the real-time CFC value of the CAN clock.

[0102] The chip clock correction device provided in the embodiments of the present invention can execute the chip clock correction method provided in any embodiment of the present invention, and has the corresponding functional modules and beneficial effects for executing the chip clock correction method.

[0103] Example 4

[0104] Figure 4 A schematic diagram of a chip clock correction device 410 that can be used to implement embodiments of the present invention is shown. The chip clock correction device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The chip clock correction device can also represent various forms of mobile devices, such as personal digital processors, cellular phones, smartphones, wearable devices (such as helmets, glasses, watches, etc.), and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the invention described and / or claimed herein.

[0105] like Figure 4 As shown, the chip's clock correction device 410 includes at least one processor 411 and a memory, such as a read-only memory (ROM) 412 or a random access memory (RAM) 413, communicatively connected to the at least one processor 411. The memory stores computer programs executable by the at least one processor. The processor 411 can perform various appropriate actions and processes based on the computer program stored in the ROM 412 or loaded from storage unit 418 into the RAM 413. The RAM 413 can also store various programs and data required for the operation of the chip's clock correction device 410. The processor 411, ROM 412, and RAM 413 are interconnected via a bus 414. An input / output (I / O) interface 415 is also connected to the bus 414.

[0106] Multiple components in the chip's clock correction device 410 are connected to the I / O interface 415, including: an input unit 416, such as a keyboard or mouse; an output unit 417, such as various types of displays or speakers; a storage unit 418, such as a disk or optical disk; and a communication unit 419, such as a network card, modem, or wireless transceiver. The communication unit 419 allows the chip's clock correction device 410 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks.

[0107] Processor 411 can be a variety of general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of processor 411 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special-purpose artificial intelligence (AI) computing chips, various processors running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. Processor 411 performs the various methods and processes described above, such as chip clock correction methods.

[0108] In some embodiments, the chip clock calibration method may be implemented as a computer program tangibly contained in a computer-readable storage medium, such as storage unit 418. In some embodiments, part or all of the computer program may be loaded and / or mounted onto the chip clock calibration device 410 via ROM 412 and / or communication unit 419. When the computer program is loaded into RAM 413 and executed by processor 411, one or more steps of the chip clock calibration method described above may be performed. Alternatively, in other embodiments, processor 411 may be configured to execute the chip clock calibration method by any other suitable means (e.g., by means of firmware).

[0109] Various implementations of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), systems-on-a-chip (SoCs), complex programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various implementations may include: implementations in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a dedicated or general-purpose programmable processor, capable of receiving data and instructions from a storage system, at least one input device, and at least one output device, and transmitting data and instructions to the storage system, the at least one input device, and the at least one output device.

[0110] Computer programs used to implement the methods of the present invention can be written in any combination of one or more programming languages. These computer programs can be provided to the processor of a general-purpose computer, a special-purpose computer, or other clock correction device of a programmable chip, such that when executed by the processor, the computer programs cause the functions / operations specified in the flowcharts and / or block diagrams to be implemented. The computer programs can be executed entirely on the machine, partially on the machine, as a standalone software package partially on the machine and partially on a remote machine, or entirely on a remote machine or server.

[0111] In the context of this invention, a computer-readable storage medium can be a tangible medium that may contain or store a computer program for use by or in conjunction with an instruction execution system, apparatus, or device. A computer-readable storage medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination thereof. Alternatively, a computer-readable storage medium may be a machine-readable signal medium. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof.

[0112] To provide user interaction, the systems and techniques described herein can be implemented on a chip clock calibration device, which includes: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and pointing device (e.g., a mouse or trackball) through which the user provides input to the chip clock calibration device. Other types of devices can also be used to provide user interaction; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including sound input, voice input, or tactile input).

[0113] The systems and technologies described herein can be implemented in computing systems that include backend components (e.g., as data servers), or middleware components (e.g., application servers), or frontend components (e.g., user computers with graphical user interfaces or web browsers through which users can interact with implementations of the systems and technologies described herein), or any combination of such backend, middleware, or frontend components. The components of the system can be interconnected via digital data communication of any form or medium (e.g., communication networks). Examples of communication networks include local area networks (LANs), wide area networks (WANs), blockchain networks, and the Internet.

[0114] A computing system can include clients and servers. Clients and servers are generally geographically separated and typically interact via communication networks. The client-server relationship is created by computer programs running on the respective computers and having a client-server relationship with each other. The server can be a cloud server, also known as a cloud computing server or cloud host, which is a hosting product within the cloud computing service system. It addresses the shortcomings of traditional physical hosts and VPS (Virtual Private Server) services, such as high management difficulty and weak business scalability.

[0115] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0116] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A clock calibration method for a chip, characterized in that, The method includes: Obtain the real-time CFC (CANFrame Counter) value of the CAN (Controller Area Network) clock in the target chip; the CAN clock is obtained by dividing the system clock. Based on the CAN baud rate, CAN clock frequency, and CFSEL (CAN FrameCounter Selection) mode of the CAN controller in the target chip, calculate the standard CFC value of the CAN clock; Based on the real-time CFC value and the preset standard CFC value, determine whether the system clock has a frequency error; If the system clock has a frequency error, the frequency division coefficient of the phase-locked loop of the system clock is adjusted according to the type of frequency error, and the process returns to obtain the real-time CFC value of the CAN clock in the target chip until the system clock has no frequency error; the phase-locked loop is used to divide the clock source of the target chip to obtain the system clock.

2. The method according to claim 1, characterized in that, The step of determining whether the system clock has a frequency error based on the real-time CFC value and the preset standard CFC value includes: The real-time CFC value is filtered to obtain the filtered CFC value; Based on the filtered CFC value and the standard CFC value, determine whether the system clock has a frequency error.

3. The method according to claim 2, characterized in that, The step of determining whether the system clock has a frequency error based on the filtered CFC value and the standard CFC value includes: The filtered CFC value and the standard CFC value are compared to obtain the comparison result; If the comparison results are different, it is determined that the system clock has a frequency error; Otherwise, it is determined that the system clock has no frequency error.

4. The method according to claim 1, characterized in that, The step of calculating the standard CFC value of the CAN clock based on the CAN baud rate, CAN clock frequency, and CFSEL mode of the CAN controller in the target chip includes: Query the number of CAN bit measurements corresponding to the CFSEL mode; The standard CFC value is calculated based on the number of CAN bit measurements, the CAN clock frequency, and the CAN baud rate.

5. The method according to claim 4, characterized in that, The step of calculating the standard CFC value based on the number of CAN bit measurements, the CAN clock frequency, and the CAN baud rate includes: The unit measurement duration is determined based on the CAN baud rate and the number of CAN bits measured. The length of a unit CAN clock cycle is determined based on the CAN clock frequency; The standard CFC value is calculated based on the unit measurement duration and the CAN clock cycle length.

6. The method according to claim 1, characterized in that, The process of obtaining the real-time CFC value of the CAN clock in the target chip includes: Configure the CFMOD (CAN Frame Counter Mode) mode of the CAN controller in the target chip to bit timing analysis mode, and configure the CFSEL mode to the same timing interval mode. The CAN controller is controlled to count the real-time CFC value of the CAN clock.

7. A clock correction device for a chip, characterized in that, The device includes: The acquisition module is used to acquire the real-time CFC (CAN Frame Counter) value of the CAN (Controller Area Network) clock in the target chip; the CAN clock is obtained by dividing the system clock. The calculation module is used to calculate the standard CFC value of the CAN clock based on the CAN baud rate, CAN clock frequency and CFSEL (CAN FrameCounter Selection) mode of the target chip; The determination module is used to determine whether there is a frequency error in the system clock based on the real-time CFC value and the preset standard CFC value; The adjustment module is used to adjust the frequency division coefficient of the phase-locked loop of the system clock according to the type of frequency error if the system clock has a frequency error, and return to obtain the real-time CFC value of the CAN clock in the target chip until the system clock has no frequency error; the phase-locked loop is used to divide the clock source of the target chip to obtain the system clock.

8. An electronic device, characterized in that, The electronic device includes: At least one processor; and A memory communicatively connected to the at least one processor; wherein, The memory stores a computer program that can be executed by the at least one processor, the computer program being executed by the at least one processor to enable the at least one processor to perform a clock correction method for a chip according to any one of claims 1-6.

9. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions that, when executed by a processor, implement the clock correction method of the chip according to any one of claims 1-6.

10. A computer program product, characterized in that, The computer program product includes a computer program that, when executed by a processor, implements the clock correction method for the chip according to any one of claims 1-6.

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