A multi-solver heterogeneous platform adaptive compilation optimization adaptation method and system

Abstract

The application belongs to the technical field of compiler optimization, and particularly relates to a multi-solver heterogeneous platform adaptive compilation optimization adaptation method and system, wherein the method comprises the following steps: achieving low-cost adaptation by constructing a scoring model, wherein the scoring model comprises a program graph encoder, a hardware portrait encoder, a sequence encoder and a fusion output network; obtaining a program graph, a hardware portrait, an optimization sequence and a corresponding speedup ratio label of a training solver program, inputting the program graph, the hardware portrait and the optimization sequence into corresponding encoders respectively, and training the scoring model under the supervision of the speedup ratio label; during deployment, inputting a target program graph, a target hardware portrait and a candidate optimization sequence into the trained scoring model to obtain sequence scores, and generating a deployment configuration according to the scores and selecting a sequence to compile and verify. The application replaces real compilation running with model inference, and significantly reduces the optimization cost of multi-solver cross-platform adaptation.

Description

Technical Field

[0001] This invention relates to the field of compiler optimization technology, and in particular to an adaptive compilation optimization method and system for heterogeneous platforms with multiple solvers. Background Technology

[0002] The selection of compiler optimization options or optimization paths has a significant impact on program performance. Modern compilers such as LLVM and GCC provide a large number of optimization paths, and the combinations of different optimization paths constitute a huge search space, making it difficult to exhaustively find the optimal configuration through manual tuning. Existing technologies have proposed various tuning schemes for combinations of compiler optimization options, such as recommendation methods based on Bayesian optimization, methods using surrogate models to predict performance, methods based on evolutionary algorithms, and research on performance prediction using program graph representations.

[0003] However, existing technologies still have the following shortcomings: high optimization costs, with many methods still requiring repeated compilation and execution on the target program; insufficient expression of program structure, making it difficult to characterize the impact of compilation optimization on control flow and data flow; insufficient joint hardware and software modeling, with hardware features not being fully incorporated into the unified prediction model; lack of representative optimization sequence libraries that can be built offline and reused across programs; and lack of an engineering closed loop for multi-solver deployment. Summary of the Invention

[0004] This invention proposes an adaptive compilation optimization method and system for heterogeneous platforms with multiple solvers, aiming to solve the technical problem of how to quickly generate high-performance compilation optimization configurations that can be used across platforms without exhaustively running a large number of compilation optimization sequences.

[0005] In a first aspect, the present invention provides an adaptive compilation optimization and adaptation method for heterogeneous platforms with multiple solvers, comprising: A scoring model is constructed, which includes a program graph encoder, a hardware profile encoder, a sequence encoder, and a fusion output network. The fusion output network merges the outputs of the three encoders and outputs a score. Obtain training samples, which include the program graph, hardware profile, optimization sequence, and corresponding speedup labels of the training solver program; The scoring model is trained using the training samples. During deployment, the target program graph of the target solver program, the target hardware profile of the target hardware platform, and the candidate optimization sequences are input into the trained scoring model to obtain the scores of each candidate optimization sequence. Based on the scoring results, candidate optimization sequences are selected to generate the final deployment optimization path sequence; The target solver program is compiled using the final deployment optimization path sequence, verified, and the deployment configuration is output.

[0006] Furthermore, the program graph encoder is a graph neural network, used to perform graph convolution operations on the input program graph to obtain a graph-level representation vector; The hardware profile encoder is a multi-layer fully connected network used to map the input hardware profile vector to a platform representation vector; The sequence encoder is a sequence network used to embed and aggregate the various pathways in the optimized sequence into a sequence encoding vector; The fusion output network is a multi-layer fully connected network, which concatenates the graph-level representation vector, the platform representation vector, and the sequence encoding vector, and then passes them sequentially through a fully connected layer and an activation function to output a score.

[0007] Furthermore, the method for constructing the program graph includes: Extract basic blocks, instructions, operands, control transfer relationships, data dependencies, and calling relationships from the intermediate representation of the solver program; Using basic blocks, instructions, or operands as nodes, and control flow edges, data dependency edges, and call relationship edges as edges, construct a program graph that integrates control flow graph and data flow graph; Node features include at least instruction type histogram, opcode encoding, constant marking, memory access type, loop depth, and branch type; edge features include at least control flow edge type and data dependency edge type.

[0008] Furthermore, the hardware profile includes at least the following structured features: processor architecture, number of physical cores, number of logical cores, clock speed, cache hierarchy and capacity, instruction set support type, memory capacity, memory bandwidth, non-uniform memory access architecture node information, graphics processor model, graphics processor memory capacity, graphics processor memory bandwidth, interconnect topology information, operating system kernel version, compiler version, and runtime library version.

[0009] Furthermore, the speedup label is generated using a dual-graph performance prediction model: The dual-graph performance prediction model includes a first graph encoder, a second graph encoder, a hardware encoder, and a fusion regression network; The first graph encoder encodes the first procedural graph at the baseline optimization level to obtain a first graph-level representation. The second graph encoder encodes the second procedural graph at the candidate optimization sequence to obtain a second graph-level representation. The hardware encoder encodes the hardware profile to obtain a platform representation. The fusion regression network fuses the first graph-level representation, the second graph-level representation, and the platform representation to output the prediction speedup.

[0010] Furthermore, the method also includes the step of screening a representative optimized sequence library: Based on the profit coverage objective, representative optimization sequences are selected from the candidate optimization sequence pool so that the selected sequence set maximizes the overall profit coverage of the training program set within a preset size. During deployment, the candidate optimization sequence is a sequence from the representative optimization sequence library.

[0011] Furthermore, the selection of the representative optimized sequence library adopts a greedy approximation algorithm. In each iteration, the candidate sequence that can give the currently uncovered program the greatest new benefit is selected and added to the representative optimized sequence library until a preset size is reached.

[0012] Further, the step of selecting candidate optimization sequences based on the scoring results and generating the final deployment optimization path sequence includes: Sort the candidate optimized sequences according to their scores from high to low, and select the M sequences with the highest scores; The optimized paths in the M sequences are sequentially spliced ​​to form candidate splicing sequences; the candidate splicing sequences are then conflict-resolved to remove duplicate and conflicting optimized paths. The candidate splicing sequence is truncated at the end according to the preset maximum sequence length to obtain the final deployment optimized path sequence.

[0013] Furthermore, the method also includes: writing back the compilation and verification results of the target platform to the sample library for incremental training and model calibration.

[0014] Secondly, the present invention provides an adaptive compilation optimization and adaptation system for heterogeneous platforms with multiple solvers, the system being used to execute the method, comprising: The model building module is used to build a scoring model, which includes a program graph encoder, a hardware profile encoder, a sequence encoder, and a fusion output network. The fusion output network merges the outputs of the three encoders and outputs a score. The model training module is used to acquire training samples and train the scoring model using the training samples. The training samples include the program graph of the training solver program, hardware profile, optimization sequence, and corresponding speedup label. The scoring inference module is used to input the target program graph of the target solver program, the hardware profile of the target hardware platform, and the candidate optimization sequences into the trained scoring model during deployment to obtain the scores of each candidate optimization sequence. The sequence generation module is used to select candidate optimization sequences based on the scoring results and generate the final deployment optimization path sequence; The compilation and verification module is used to compile the target solver program using the final deployment optimization path sequence, perform verification, and output the deployment configuration.

[0015] The technical effects of this invention are: First, by extracting the first program graph at the baseline optimization level and the second program graph at the candidate optimization sequence, and inputting both program graphs and hardware profiles into a dual-graph performance prediction model, the speedup of the candidate optimization sequence relative to the baseline optimization level is predicted. This approach enables the model to learn the relationship between program structure changes caused by the optimization sequence and performance gains, replacing extensive real-world evaluations with model predictions, significantly reducing online tuning costs.

[0016] Second, the program graph integrates control flow and data flow information. Node features include at least instruction type histograms, opcode encoding, constant markers, memory access types, loop depths, and branch types. Edge features include at least control flow edge types and data dependency edge types. This approach allows for a more complete expression of program structure and effectively characterizes the impact of compiler optimizations on the semantics of the underlying program.

[0017] Third, the hardware profile includes at least the processor architecture, number of cores, cache levels, instruction set, memory capacity and bandwidth, non-uniform memory access architecture information, graphics processor information, operating system and compiler toolchain version, and is encoded as a numerical vector as the model input modality. This approach enables the model to dynamically adjust its revenue predictions based on hardware differences, improving cross-platform generalization capabilities.

[0018] Fourth, based on the benefit coverage objective, a representative optimization sequence library is selected from a large-scale candidate optimization sequence pool, enabling the representative optimization sequence library to cover the main optimization benefits in the training program set at a relatively small scale. This approach allows different solvers and platforms to share existing tuning experience, reducing the search space in the deployment phase from exponential to a representative sequence space of manageable size.

[0019] Fifth, during the deployment phase, the representative optimized sequence library undergoes yield scoring, high-yield sequence selection, combined sampling, conflict resolution, and tail truncation to generate the final compiler-executable optimized path sequence. This approach enables the system to output not only prediction scores but also configurations that can be directly used for compilation and deployment, facilitating project integration.

[0020] Sixth, through a multi-platform model fusion and feedback update mechanism, the compilation and verification results are written back to the sample library for incremental training and updating of the representative optimization sequence library. This approach enables the system to continuously evolve as the number of platforms and solvers increases. Attached Figure Description

[0021] Figure 1 This is a flowchart illustrating an adaptive compilation optimization method for heterogeneous platforms with multiple solvers, as proposed in an embodiment of the present invention. Detailed Implementation

[0022] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0023] To address the technical problem mentioned in the background art—how to quickly generate high-performance, cross-platform-usable compiler optimization configurations without exhaustively running a large number of compiler optimization sequences—this invention provides an adaptive compiler optimization adaptation method for heterogeneous platforms with multiple solvers.

[0024] This invention is applicable to the adaptive compilation and optimization deployment of programs such as basic mathematical libraries, scientific computing solvers, and engineering simulation solvers on different heterogeneous high-performance computing platforms. Heterogeneous platforms include CPU-only platforms, CPU-and-GPU hybrid platforms, multi-node non-uniform memory access architectures, and platforms with different instruction sets and cache levels. Compilers include LLVM and Clang, GCC, or other compilation toolchains with optimized path configuration capabilities.

[0025] This invention uses LLVM intermediate representations as the object of program structure extraction. The system collects platform hardware profiles and encodes them into numerical vectors. A scoring model is trained by jointly modeling the program graph and hardware profiles to predict the returns of each optimization sequence. To avoid excessive search costs during the inference phase, the system offline filters a representative optimization sequence library; during deployment, only this small library needs to be scored.

[0026] refer to Figure 1 As shown, the specific steps include: Step S101: Collect training samples.

[0027] Multiple training solver programs were acquired, and structured hardware profiles were collected from multiple heterogeneous hardware platforms. For each platform, the following information was recorded: CPU architecture, number of physical cores, number of logical cores, clock speed, L1 cache capacity, L2 cache capacity, L3 cache capacity, instruction set support types, memory capacity, memory bandwidth, number of nodes with non-uniform memory access architecture, graphics processor model, graphics processor memory capacity, graphics processor memory bandwidth, interconnect topology information, operating system kernel version, compiler version, and runtime library version. The collected hardware profiles were then encoded into numerical vectors.

[0028] For each trained solver program, a first intermediate representation at the baseline optimization level and a second intermediate representation at the candidate optimization sequence are generated. A first program graph and a second program graph are extracted from the first and second intermediate representations, respectively. The program graph is constructed as follows: basic blocks, instructions, operands, control transfer relationships, data dependencies, and call relationships are extracted from the intermediate representations; using basic blocks, instructions, or operands as nodes, and control flow edges, data dependency edges, and call relationship edges as edges, a program graph fusing control flow graph and data flow graph is constructed. Node features include instruction type histogram, opcode encoding, constant label, memory access type, loop depth, and branch type. Edge features include control flow edge type and data dependency edge type.

[0029] The program graph encoder performs graph convolution operations on the input program graph to obtain a graph-level representation vector. Specifically, the graph convolutional layer aggregates the feature information of its neighboring nodes for each node, captures structural information within a multi-hop range through multi-layer stacking, and then aggregates the node-level representations into a graph-level representation vector through a graph pooling layer.

[0030] The hardware profile encoder is a multi-layer fully connected network that maps the input hardware profile vector to the platform representation vector.

[0031] The sequence encoder encodes the optimized sequence into a sequence encoding vector. Specifically, each pathway name in the optimized sequence is mapped to a pathway embedding vector, which is then aggregated into a fixed-length sequence encoding vector through a long short-term memory network.

[0032] For each training program, platform, and candidate sequence combination, the actual speedup ratio is calculated by measuring the runtime of the candidate version relative to the baseline version through actual compilation and execution. ; in, This represents the speedup of program i on platform j using the optimized sequence q relative to the baseline optimization level, and is dimensionless. This represents the runtime of program i on platform j using the baseline optimization level, in seconds. This represents the runtime of program i on platform j using the optimized sequence q, in seconds. The minimum time constant to prevent division by zero is in seconds.

[0033] Step S102: Construct a dual-graph performance prediction model and generate training labels.

[0034] The dual-graph performance prediction model comprises a first-graph encoder, a second-graph encoder, a hardware encoder, and a fusion regression network. The first-graph encoder encodes the first program graph to obtain a first-graph-level representation, the second-graph encoder encodes the second program graph to obtain a second-graph-level representation, and the hardware encoder... Hardware profile vector Mapped to platform representation Fusion regression network The prediction speedup is output after fusing the two graph-level representations and the platform representation mentioned above: ; in, This represents the prediction speedup ratio output by the dual-graph performance prediction model, and is dimensionless. This represents the program diagram of program i at the baseline optimization level; This represents the program graph of program i under the candidate optimization sequence q; Represents the hardware profile vector of platform j; Indicates a program graph encoder; This indicates a hardware image encoder; Indicates the fusion and regression network, These are its trainable parameters.

[0035] The actual acceleration ratio obtained in step S101 The bi-graph performance prediction model is trained using these labels until it converges. After training, the model predicts the speedup ratio of each candidate sequence in a large pool of candidate sequences and sorts them from highest to lowest speedup ratio. The sorting results are used to generate training labels for the sequence benefit scoring model—the higher the ranking of a sequence, the higher its training target value for the probability of being selected.

[0036] Step S103: Select a representative optimized sequence library.

[0037] Based on the benefit coverage on the training program set, the system selects a small set of representative optimization sequences from the candidate sequence pool, thus reducing the search space in the subsequent inference stage to a controllable size.

[0038] The selection objective is to choose a specified number of representative sequences that maximize the overall benefit coverage of the training program set: ; in, This represents the optimal and representative sequence library. Represents the set of representative optimized sequences from the candidates; This represents the preset size of the representative optimized sequence library, and is a positive integer. This indicates that program i is in the selected representative sequence set. The fusion benefits are dimensionless.

[0039] A greedy approximation algorithm is used for selection: the representative sequence library is initialized as an empty set; in each iteration, for each sequence in the candidate sequence pool that has not yet been selected, the additional benefit after adding it to the representative sequence library is calculated; the sequence that maximizes the additional benefit is selected and added; this process is repeated until the size of the representative sequence library reaches a preset value K.

[0040] Step S104: Construct and train the sequence benefit scoring model.

[0041] The sequence return scoring model includes a program graph encoder. Hardware image encoder Sequence encoder and fusion output network Programming encoder Input program diagram Encoded as a graph-level representation vector; hardware profile encoder Input hardware profile vector Mapped to platform representation vector; sequence encoder Encode the input optimized sequence q into a sequence encoding vector. ; Fusion output network The three representation vectors mentioned above are concatenated and then used to output the profit score through a multi-layer fully connected network.

[0042] The calculation method for the sequence return scoring model is as follows: ; in, This represents the dimensionless probability that program i will choose the optimal sequence q on platform j, satisfying the following condition: ; Its trainable parameters; This is a Softmax function with a temperature coefficient, where τ is the temperature coefficient and is a positive number.

[0043] The training labels are generated from the speedup ranking results obtained in step S102: the ranking results are normalized into a probability distribution as the training objective. The training objective is to minimize the cross-entropy loss between the model output probability and the training labels.

[0044] Step S105: Input the target solver and target platform.

[0045] During the deployment phase, the user inputs the target solver program to be adapted. The system collects data from the target hardware platform. Structured hardware profile and encoding into numerical vectors Simultaneously generate the target program benchmark diagram .

[0046] Step S106: Scoring and generating deployment sequences.

[0047] Baseline of the target program Target hardware profile vector The sequence benefit scoring model is trained with sequences from the representative optimized sequence library R as inputs. The selection probability of each sequence is calculated, and the M sequences with the highest probabilities are selected. These M selected sequences are then sorted and concatenated according to their scores from highest to lowest. After conflict resolution, they are truncated to the maximum length L to obtain the final deployment optimized pathway sequence. ; in, This indicates the final optimized deployment path sequence; This indicates that the M sequences with the highest probability should be selected; Indicates sequence concatenation; This indicates that the length is truncated to the maximum length L.

[0048] Step S107: Compile, verify, and output the deployment configuration.

[0049] The target solver program is compiled using the final deployment optimized path sequence, and correctness checks and performance verifications are performed. Once the verification is successful, the compilation configuration is output.

[0050] The present invention will be further illustrated by a specific embodiment below.

[0051] In this embodiment, the target program consists of a matrix factorization module, a sparse matrix multiplication module, and an iterative solution module from a basic mathematical library. The target platform is a multi-core CPU platform configured with an x86_64 architecture, 32 physical cores, a clock speed of 2.6GHz, 32KB of L1 data cache per core, 256KB of L2 cache per core, 32MB of shared L3 cache, supports the AVX-512 instruction set, has 128GB of memory, approximately 100GB / s of memory bandwidth, two nodes in a non-uniform memory access architecture, and runs on Linux kernel version 5.15 with LLVM 15.0 as the compiler.

[0052] Training phase: Collect hardware profiles on multiple training platforms, generate -O2 baseline version and candidate sequence version for each training program, extract program graphs, measure speedup through actual compilation and execution, and train a dual-graph performance prediction model; use this model to predict speedup of the candidate sequence pool and rank them to generate training labels; select a representative optimized sequence library (size K=50); train a sequence benefit scoring model with program baseline graph encoding, hardware profile encoding, and sequence encoding as input.

[0053] Inference phase: The target program baseline graph, target platform hardware profile, and 50 representative sequences are input into the trained scoring model to obtain 50 selection probabilities. The top 5 sequences are selected, concatenated, and truncated to obtain the final deployment sequence. The LLVM opt tool and Clang are used to complete compilation and linking. After running the test set and verifying successful compilation, the compilation configuration is output.

[0054] Based on the same inventive concept, embodiments of the present invention also provide an adaptive compilation optimization and adaptation system for heterogeneous platforms with multiple solvers, the system being used to execute the method, including: The model building module is used to build a scoring model, which includes a program graph encoder, a hardware profile encoder, a sequence encoder, and a fusion output network. The fusion output network merges the outputs of the three encoders and outputs a score. The model training module is used to acquire training samples and train the scoring model using the training samples. The training samples include the program graph of the training solver program, hardware profile, optimization sequence, and corresponding speedup label. The scoring inference module is used to input the target program graph of the target solver program, the hardware profile of the target hardware platform, and the candidate optimization sequences into the trained scoring model during deployment to obtain the scores of each candidate optimization sequence. The sequence generation module is used to select candidate optimization sequences based on the scoring results and generate the final deployment optimization path sequence; The compilation and verification module is used to compile the target solver program using the final deployment optimization path sequence, perform verification, and output the deployment configuration.

[0055] Example embodiments have been disclosed herein, and while specific terminology has been used, it is for illustrative purposes only and should be construed as such, and is not intended to be limiting. In some instances, it will be apparent to those skilled in the art that features, characteristics, and / or elements described in conjunction with particular embodiments may be used alone, or in combination with features, characteristics, and / or elements described in conjunction with other embodiments, unless otherwise expressly indicated. Therefore, those skilled in the art will understand that various changes in form and detail may be made without departing from the scope of the invention as set forth in the appended claims.

Claims

1. A method for adaptive compilation optimization and adaptation for heterogeneous platforms with multiple solvers, characterized in that, include: A scoring model is constructed, which includes a program graph encoder, a hardware profile encoder, a sequence encoder, and a fusion output network. The fusion output network merges the outputs of the three encoders and outputs a score. Obtain training samples, which include the program graph, hardware profile, optimization sequence, and corresponding speedup labels of the training solver program; the speedup labels are generated using a dual-graph performance prediction model. The dual-graph performance prediction model includes a first graph encoder, a second graph encoder, a hardware encoder, and a fusion regression network; The first graph encoder encodes the first procedural graph at the baseline optimization level to obtain a first graph-level representation; the second graph encoder encodes the second procedural graph at the candidate optimization sequence to obtain a second graph-level representation; the hardware encoder encodes the hardware profile to obtain a platform representation; and the fusion regression network fuses the first graph-level representation, the second graph-level representation, and the platform representation to output the prediction speedup. The scoring model is trained using the training samples. During deployment, the target program graph of the target solver program, the target hardware profile of the target hardware platform, and the candidate optimization sequences are input into the trained scoring model to obtain the scores of each candidate optimization sequence. Based on the scoring results, candidate optimization sequences are selected to generate the final deployment optimization path sequence; The target solver program is compiled using the final deployment optimization path sequence, verified, and the deployment configuration is output.

2. The method according to claim 1, characterized in that, The program graph encoder is a graph neural network, used to perform graph convolution operations on the input program graph to obtain a graph-level representation vector; The hardware profile encoder is a multi-layer fully connected network used to map the input hardware profile vector to a platform representation vector; The sequence encoder is a sequence network used to embed and aggregate the various pathways in the optimized sequence into a sequence encoding vector; The fusion output network is a multi-layer fully connected network, which concatenates the graph-level representation vector, the platform representation vector, and the sequence encoding vector, and then passes them sequentially through a fully connected layer and an activation function to output a score.

3. The method according to claim 1, characterized in that, The method for constructing the program graph includes: Extract basic blocks, instructions, operands, control transfer relationships, data dependencies, and calling relationships from the intermediate representation of the solver program; Using basic blocks, instructions, or operands as nodes, and control flow edges, data dependency edges, and call relationship edges as edges, construct a program graph that integrates control flow graph and data flow graph; Node features include at least instruction type histogram, opcode encoding, constant marking, memory access type, loop depth, and branch type; edge features include at least control flow edge type and data dependency edge type.

4. The method according to claim 1, characterized in that, The hardware profile includes at least the following structured features: Processor architecture, number of physical cores, number of logical cores, clock speed, cache hierarchy and capacity, instruction set support type, memory capacity, memory bandwidth, non-uniform memory access architecture node information, graphics processor model, graphics processor memory capacity, graphics processor memory bandwidth, interconnect topology information, operating system kernel version, compiler version, and runtime library version.

5. The method according to claim 1, characterized in that, The method also includes the step of screening a representative optimized sequence library: Based on the profit coverage objective, representative optimization sequences are selected from the candidate optimization sequence pool so that the selected sequence set maximizes the overall profit coverage of the training program set within a preset size. During deployment, the candidate optimization sequence is a sequence from the representative optimization sequence library.

6. The method according to claim 5, characterized in that, The selection of the representative optimized sequence library adopts a greedy approximation algorithm. In each iteration, the candidate sequence that can give the currently uncovered program the greatest new benefit is selected and added to the representative optimized sequence library until a preset size is reached.

7. The method according to claim 1, characterized in that, The step of selecting candidate optimization sequences based on the scoring results and generating the final deployment optimization path sequence includes: Sort the candidate optimized sequences according to their scores from high to low, and select the M sequences with the highest scores; The optimized paths in the M sequences are sequentially spliced ​​to form candidate splicing sequences; the candidate splicing sequences are then conflict-resolved to remove duplicate and conflicting optimized paths. The candidate splicing sequence is truncated at the end according to the preset maximum sequence length to obtain the final deployment optimized path sequence.

8. The method according to claim 1, characterized in that, The method further includes: writing back the compilation and verification results of the target platform to the sample library for incremental training and model calibration.

9. A multi-solver heterogeneous platform adaptive compilation optimization adaptation system, characterized in that, The system is used to perform the method according to any one of claims 1-8, comprising: The model building module is used to build a scoring model, which includes a program graph encoder, a hardware profile encoder, a sequence encoder, and a fusion output network. The fusion output network merges the outputs of the three encoders and outputs a score. The model training module is used to acquire training samples and train the scoring model using the training samples. The training samples include the program graph of the training solver program, hardware profile, optimization sequence, and corresponding speedup label. The scoring inference module is used to input the target program graph of the target solver program, the hardware profile of the target hardware platform, and the candidate optimization sequences into the trained scoring model during deployment to obtain the scores of each candidate optimization sequence. The sequence generation module is used to select candidate optimization sequences based on the scoring results and generate the final deployment optimization path sequence; The compilation and verification module is used to compile the target solver program using the final deployment optimization path sequence, perform verification, and output the deployment configuration.

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