Cache system for processor verification acceleration process

Abstract

The application provides a cache system for a processor verification acceleration process, comprising: a cache block storage unit containing a plurality of cache blocks; a request processing unit containing a request input port, a request output port, and a read-write port of the cache block storage unit, and an access port of a first RAM. The cache system can realize high-concurrency memory access.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit design and verification technology, and in particular to a cache system for accelerating processor verification. Background Technology

[0002] To improve memory access efficiency, traditional processor designs typically incorporate multi-level cache systems to reduce the number of memory accesses and provide greater memory bandwidth and lower latency. However, complex cache management strategies and cache coherence protocols significantly increase the complexity of cache system design.

[0003] In traditional software reference models, there is typically an independent RAM memory space, which has the same initial value as the RAM of the device under test (DUT). When executing instructions, the reference model sends all memory access read / write operations to its locally maintained RAM, ensuring strict correctness. In other words, in a software co-simulation environment, the reference processor and the DUT each maintain their own independent RAM, not only physically independent but also logically without sharing data. Furthermore, the reference model's RAM needs to have the same capacity as the DUT's RAM, which incurs additional resource overhead, halving the actual usable RAM capacity during processor co-simulation verification. In addition, the core computing unit RCore architecture of the reference model requires a high-concurrency memory access system, and independent off-chip RAM is insufficient to support multiple accesses within a single clock cycle. Summary of the Invention

[0004] To address the shortcomings of existing technologies, this invention proposes a caching system for accelerating the processor verification process. This caching system only records write data that differs between the reference model and the RAM corresponding to the processor under test, reusing memory access information between the processor under test and the RAM, thus providing efficient memory access support for processor verification.

[0005] This invention provides a caching system for accelerating processor verification processes, comprising:

[0006] A cache block storage unit contains several cache blocks;

[0007] The request processing unit includes a request input port and a request output port, wherein the request output port is connected to the read / write port of the cache block storage unit and the access port of the first RAM.

[0008] In one embodiment of the present invention, the cache system is used for co-simulation verification of a reference processor and a processor under test, and the cache system is connected to the reference processor, the processor under test, and a first RAM;

[0009] The cache block storage unit is used to store write data generated by the reference model of the reference processor executing write instructions, which differs from the corresponding address data in the first RAM; wherein the first RAM is the RAM corresponding to the processor under test.

[0010] In one embodiment of the present invention, the cache block storage unit adopts a storage unit replication structure, which simulates a logical storage unit with multiple physical cache blocks and multiple ports for reading and writing, and each cache block has an independent read and write port.

[0011] In one embodiment of the present invention, the cache block storage unit internally comprises at least one of a read port cache module, a read port arbitration module, a write port cache module, and a storage block module; wherein:

[0012] The read port cache module is connected to the read port of the cache block storage unit and stores the most recently read data;

[0013] The read port arbitration module is connected to the read port of the cache block storage unit to filter valid read requests;

[0014] The write port caching module is connected to the write port of the cache block storage unit to cache the requests to be written;

[0015] The storage block module divides the cache block storage unit into several independent cache blocks, each with an independent read / write port.

[0016] In one embodiment of the present invention, it further includes: a listening unit, wherein the input interface of the listening unit is connected to the communication interface between the processor under test and the first RAM, so as to obtain a read request initiated by the processor under test to the first RAM, a read response returned by the first RAM to the processor under test, and a write request initiated by the processor under test to the first RAM.

[0017] In one embodiment of the present invention, the input interface of the listening unit includes a first sub-interface and a second sub-interface;

[0018] The first sub-interface is connected to the output interface of the processor under test initiating a read request to the first RAM, and the output interface of the first RAM returning a read response to the processor under test;

[0019] The second sub-interface is connected to the output interface of the processor under test that initiates a write request to the first RAM.

[0020] In one embodiment of the present invention, the request input port includes:

[0021] The core computing unit read request port is connected to the read request output interface of the core computing unit of the reference model;

[0022] The core computing unit write request port is connected to the write request output interface of the core computing unit of the reference model.

[0023] In one embodiment of the present invention, when the core computing unit read request port receives the core computing unit read request,

[0024] If a cache block with the corresponding address exists in the cache block storage unit, the request output port returns the cache block data to the core computing unit.

[0025] If it does not exist, the request output port initiates a read request to the access port of the first RAM. After the first RAM returns data, the request processing unit controls the cache block storage unit to allocate a new cache block and write the data.

[0026] In one embodiment of the present invention, when the core computing unit write request port receives the core computing unit write request,

[0027] If a cache block with the corresponding address exists in the cache block storage unit, the request output port writes data to that cache block.

[0028] If it does not exist, the request processing unit controls the cache block storage unit to allocate a new cache block. If the written data does not constitute a complete cache block, the request output port initiates a read request to the access port of the first RAM. After the first RAM returns data, the missing part of the new cache block is filled, and then the written data is written.

[0029] In one embodiment of the present invention, the request input port includes:

[0030] The processor under test fills back the request port, which is connected to the output of the first sub-interface of the listening unit;

[0031] The processor under test eviction request port is connected to the output of the second sub-interface of the listening unit.

[0032] In one embodiment of the present invention, when the backfill request port of the processor under test receives a backfill request,

[0033] If a cache block with the corresponding address exists in the cache block storage unit, the data verification module inside the request processing unit performs a consistency check on the bytes in the cache block that have not been written by the core computing unit and the backfilled data.

[0034] If it does not exist, the request processing unit controls the cache block storage unit to allocate a new cache block and write backfill data.

[0035] In one embodiment of the present invention, when the processor under test receives an eviction request port,

[0036] If a cache block with the corresponding address exists in the cache block storage unit, the data verification module inside the request processing unit performs a consistency check between the cache block data and the data in the eviction request.

[0037] If it does not exist, the request output interface sends an expulsion missing event signal.

[0038] In one embodiment of the present invention, the request processing unit is provided with a first optional configuration module. When the core computing unit's read request fails, the first optional configuration module controls the request processing unit to output a missing signal to the core computing unit and not to initiate a read request to the access port of the first RAM.

[0039] In one embodiment of the present invention, the request processing unit is provided with a second optional configuration module. When the core computing unit write request fails, the second optional configuration module controls the request processing unit to output a missing signal to the core computing unit and not to initiate a read request to the access port of the processor RAM under test.

[0040] In one embodiment of the present invention, the request processing unit is provided with a third optional configuration module. When the eviction request of the processor under test is not hit, the third optional configuration module controls the request processing unit to send an eviction missing event signal.

[0041] In one embodiment of the present invention, when the data verification module detects that the bytes in the cache block that have not been written by the core computing unit are inconsistent with the backfill data, or when the cache block data is consistent with the data in the eviction request, the request output interface sends a verification error signal.

[0042] As can be seen from the above solutions, the advantages of the present invention are:

[0043] This invention provides a caching system comprising: a cache block storage unit containing a plurality of cache blocks; and a request processing unit including a request input port and a request output port, wherein the request output port is connected to a read / write port of the cache block storage unit and an access port of a first RAM. This caching system only records write data that differs between the reference model and the first RAM corresponding to the processor under test, reusing memory access information between the processor under test and the first RAM, thus providing efficient memory access support for processor verification. Attached Figure Description

[0044] Figure 1 The schematic diagram of the caching system of the present invention is shown;

[0045] Figure 2 A schematic diagram of the overall structure of a caching system provided in an embodiment of the present invention is shown;

[0046] Figure 3 A schematic diagram of the specific structure of a caching system provided in an embodiment of the present invention is shown;

[0047] Figure 4 A schematic diagram of the specific structure of a caching system provided in an embodiment of the present invention is shown.

[0048] The attached figures are labeled as follows:

[0049] 10: Caching system;

[0050] 11: Cache block storage unit;

[0051] 12: Request processing unit;

[0052] 13: Listening unit;

[0053] 20: Reference processor;

[0054] 30: Processor under test;

[0055] 40: First RAM;

[0056] 111: Read port cache module;

[0057] 112: Read port arbitration module;

[0058] 113: Write port cache module;

[0059] 114: Storage block module;

[0060] 121: Requesting port number;

[0061] 122: Requesting output port;

[0062] 1211: Core computing unit read request port;

[0063] 1212: Core computing unit write request port;

[0064] 1213: The port for requesting backfilling from the processor under test;

[0065] 1214: Port for requesting eviction of the processor under test;

[0066] 131: First sub-interface;

[0067] 132: Second sub-interface. Detailed Implementation

[0068] It should be noted that, in this invention, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus.

[0069] In the absence of further restrictions, an element defined by the phrase "comprising a..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0070] As previously mentioned, in the prior art, during the simulation verification process between the reference processor as a reference model and the processor under test (DUT), the off-chip RAM of the reference processor needs to have the same capacity as the RAM of the DUT. This incurs additional resource overhead, halving the actual usable RAM capacity during processor co-simulation verification. Furthermore, the core computing unit RCore of the reference model also requires a high-concurrency memory access system, and independent off-chip RAM is insufficient to support multiple accesses within a single clock cycle.

[0071] To address this, to achieve the functionality of the reference model RAM, it is not necessary to store the complete RAM data. Instead, only the write data that differs from the RAM of the processor under test can be maintained. This allows for a simplified implementation of the reference model RAM by combining the reuse of the RAM resources of the processor under test.

[0072] Given initial RAM values ​​in co-simulation When the store command After execution, the second RAM corresponding to the reference model The ideal data state is:

[0073]

[0074] Meanwhile, due to the presence of microarchitectural components such as caches, the processor under test may not have yet written all the write data to the corresponding first RAM. Therefore, the first RAM of the processor under test... The data status is:

[0075]

[0076] Based on this, the present invention considers designing a caching system Rcache. It is related to the first RAM The second RAM was implemented in conjunction with this. :

[0077]

[0078] Figure 1 The design principles of the caching system Rcache are illustrated with specific examples.

[0079] In traditional instruction set simulator design, the reference model's second RAM has the same initialization values ​​as the processor under test's first RAM, and it stores the write data of all instructions executed by the reference model during program execution. During co-simulation, when the processor under test (DUT) is in the first moment... After executing a store instruction, the reference model executes the same store instruction and simultaneously writes data into the reference model's second RAM. The processor under test (DUT) then executes the same store instruction at the second time step. After the data is written into the first RAM, the first RAM and the second RAM will again have the same data state. Therefore, the cache system RCache provided in this embodiment needs to maintain the write data of the store instruction between the first time and the second time. After confirming that the write data of the processor under test and the write data of the reference model are the same in the second time, the data in the first RAM can be used directly to jointly realize simplified support for the second RAM of the reference model.

[0080] Similarly, in the third moment Before the load instruction is submitted at time step four, the processor under test will definitely be at time step four. At the fourth time step, the reference model accesses the first RAM in advance and obtains the read data. In traditional instruction set simulator designs, the reference model executes the same load instruction after the processor under test completes the load instruction, sends a read request to the same address in its second RAM, and obtains exactly the same read data. In contrast, the cache system Rcache utilizes the read data from the processor under test to avoid duplicate memory access operations. Rcache will backfill and merge the read data of the processor under test into its own cache, and in the third moment... This data is used to support read requests for the core computing unit RCore of the reference model.

[0081] Based on the above ideas, this invention considers designing a cache system Rcache that only records write data that differs between the reference model and the first RAM of the processor under test, reusing memory access information between the processor under test and the first RAM, and providing efficient memory access support for the core computing unit RCore of the reference model without occupying a large amount of memory bandwidth or introducing a complex cache system and management strategy.

[0082] For details, please refer to the following: Figure 2 As shown, Figure 2 A schematic diagram of a cache system for accelerating processor verification processes, provided by an embodiment of the present invention, is shown.

[0083] A caching system 10 includes:

[0084] Cache block storage unit 11 contains several cache blocks;

[0085] The request processing unit 12 includes a request input port 121 and a request output port 122. The request output port 122 is connected to the read / write port of the cache block storage unit 11 and the access port of the first RAM 40.

[0086] In one embodiment, the cache system is used for co-simulation verification of a reference processor and a processor under test (DUT). The cache system 10 is connected to the reference processor 20, the DUT 30, and a first RAM 40. The cache block storage unit stores write data generated by the reference model of the reference processor executing write instructions, which differs from the corresponding address data in the first RAM. The first RAM is the RAM corresponding to the DUT.

[0087] In this embodiment, the caching system implements the function of the reference model RAM. It does not need to store the complete RAM data, but only needs to maintain the write data that is different from the first RAM of the processor under test. This allows for a simplified implementation of the reference model RAM by combining the reuse of RAM resources of the processor under test.

[0088] In the implementation of a caching system, due to resource limitations of the hardware simulation platform, not all synthesizable circuit logic can be implemented, which imposes certain constraints on the design of the caching system. Specifically, the caching system needs to handle multiple concurrent access requests within the same clock cycle. These requests all need to access the storage units responsible for storing specific data within the caching system, thus requiring concurrent read and write operations on the storage units. However, on the FPGA platform, storage units are implemented using Block RAM (BRAM) or UltraRAM (URAM), which can only support a maximum of one read request and one write request per clock cycle. Therefore, in one embodiment, the cache block storage unit adopts a storage unit replication structure, simulating a multi-port read, single-port write logic storage unit through multiple physical cache blocks, with each cache block having an independent read / write port. This enables the caching system to support multiple concurrent read requests.

[0089] refer to Figure 3 As shown, in one embodiment, the cache block storage unit 11 internally includes at least one of a read port cache module 111, a read port arbitration module 112, a write port cache module 113, and a storage banking module 114, supporting optimized and concurrent access to the storage unit through read port caching, read port arbitration, write port caching, and storage banking.

[0090] The read port cache module is connected to the read port of the cache block storage unit and stores the most recently read data;

[0091] The read port arbitration module is connected to the read port of the cache block storage unit to filter valid read requests;

[0092] The write port caching module is connected to the write port of the cache block storage unit to cache the requests to be written;

[0093] The storage block module divides the cache block storage unit into several independent cache blocks, each with an independent read / write port.

[0094] Furthermore, in practice, when the processor under test (DUT) initiates a read request to the first RAM, regardless of whether the read address sent by the DUT matches the design expectations of the DUT, the read data returned by the first RAM must be the corresponding data stored in the first RAM at that address. If it can be ensured that all data written to the first RAM is correct, then this cache system Rcache can directly use the data returned by the first RAM to backfill itself when the DUT initiates a read request. In addition, to ensure that all data written by the DUT to the RAM is correct, this cache system Rcache verifies the write request address and data between the DUT and the RAM. Therefore, this cache system Rcache listens for write requests from the DUT. When the DUT initiates a write request, it uses the request address to query the cache block in this cache system Rcache and performs a correctness check on its data. If there is a backup of the data block in RCache, then this data block should be consistent with the data written by the DUT. Furthermore, write requests from the processor under test (DUT) also provide RCache with hints about cache block replacement. This indicates that a data block has been evicted from the DUT's cache and may no longer be used. Even if it needs to be used again, the DUT will re-initiate a read request to retrieve it from the first RAM. Therefore, RCache can work with the DUT to discard the corresponding cache block or mark it as the highest priority in the replacement strategy, thereby refining RCache's own management strategy using information from the DUT.

[0095] In one embodiment, further reference is made to Figure 4 As shown, the cache system 10 is also provided with a listening unit 13 to listen for read requests and read responses from the processor under test. While the first RAM returns read data to the processor under test, the read data is used to update the cache block of the cache system 10.

[0096] Specifically, the input interface of the listening unit 13 is connected to the communication interface between the processor under test 30 and the first RAM 40 to obtain the read request initiated by the processor under test to the first RAM, the read response returned by the first RAM to the processor under test, and the write request initiated by the processor under test to the first RAM.

[0097] In one embodiment, reference Figure 4 As shown, the input interface of the listening unit 13 includes a first sub-interface 131 and a second sub-interface 132;

[0098] The first sub-interface is connected to the output interface of the processor under test initiating a read request to the first RAM, and the output interface of the first RAM returning a read response to the processor under test;

[0099] The second sub-interface is connected to the output interface of the processor under test that initiates a write request to the first RAM.

[0100] In one embodiment, further reference is made to Figure 4 As shown, the request input port 121 of the request processing unit 12 includes:

[0101] The core computing unit read request port 1211 is connected to the read request output interface of the core computing unit of the reference model;

[0102] The core computing unit write request port 1212 is connected to the write request output interface of the core computing unit of the reference model;

[0103] The processor under test fills back request port 1213, which is connected to the output of the first sub-interface 131 of the listening unit 13;

[0104] The processor under test eviction request port 1214 is connected to the output of the second sub-interface 132 of the listening unit 13.

[0105] In this embodiment, RCache needs to handle four types of requests: read requests, write requests, fill requests, and eviction requests.

[0106] Specifically, when the core computing unit read request port receives a read request from the core computing unit, if a cache block with the corresponding address exists in the cache block storage unit, the request output port returns the cache block data to the core computing unit; if it does not exist, the request output port initiates a read request to the access port of the first RAM. After the first RAM returns the data, the request processing unit controls the cache block storage unit to allocate a new cache block and write the data.

[0107] When the core computing unit write request port receives a write request from the core computing unit, if a cache block with the corresponding address exists in the cache block storage unit, the request output port writes data to the cache block; if it does not exist, the request processing unit controls the cache block storage unit to allocate a new cache block. If the written data does not constitute a complete cache block, the request output port initiates a read request to the access port of the first RAM. After the first RAM returns data, the missing part of the new cache block is filled, and then the written data is written.

[0108] When the backfill request port of the processor under test receives a backfill request, if a cache block with the corresponding address exists in the cache block storage unit, the data verification module inside the request processing unit performs a consistency check on the bytes in the cache block that have not been written by the core computing unit and the backfill data; if they do not exist, the request processing unit controls the cache block storage unit to allocate a new cache block and write the backfill data.

[0109] When the processor under test receives an eviction request at its eviction request port, if a cache block with the corresponding address exists in the cache block storage unit, the data verification module inside the request processing unit performs a consistency check between the cache block data and the data in the eviction request; if it does not exist, the request output interface sends an eviction missing event signal.

[0110] Furthermore, in one embodiment, the request processing unit 12 is provided with a first optional configuration module. When the core computing unit's read request misses, the first optional configuration module controls the request processing unit to output a missing signal to the core computing unit and not to initiate a read request to the access port of the first RAM. Specifically, when processing an RCore read request, if an RCache misses, the RCache will initiate a read request to the first RAM and fill in a new cache block after the data is returned. However, this behavior may interfere with the access of the processor under test to the first RAM at locations such as the memory bus and controller, affecting the deterministic co-simulation of the processor under test. Note that, to support the efficient execution of RCore, the instruction execution carries the memory access result information of the processor under test. Therefore, RCache can choose to avoid refilling when a read miss occurs, thereby avoiding the access requirement to the first RAM. In this case, RCache returns a miss for the read request, allowing RCore to execute using the calculation result of the processor under test, that is, skipping the strict check of the read request and the corresponding instruction.

[0111] The request processing unit 12 is equipped with a second optional configuration module. When the core computing unit's write request misses, the second optional configuration module controls the request processing unit to output a missing signal to the core computing unit and not to initiate a read request to the access port of the processor under test's RAM. Similar to read requests, RCache can avoid refilling when a write request misses, thereby avoiding access requirements to the first RAM.

[0112] The request processing unit 12 is equipped with a third optional configuration module. When a processor under test (DUT) eviction request fails, the third optional configuration module controls the request processing unit to send an eviction miss event signal. Specifically, when processing a DUT eviction request, RCache requires a hit, meaning the corresponding cache block must exist in RCache. However, due to inconsistencies in cache size and replacement policies between RCache and the DUT, RCache may have already replaced the corresponding cache block when the DUT initiates an eviction request. In this case, to ensure the continued progress of co-simulation, RCache can choose to relax the correctness check on the request, report an eviction miss event, and not terminate the co-simulation.

[0113] In this embodiment, by providing a first, second, and third optional configuration module in the request processing unit 13, the inspection of the behavior of the processor under test can be relaxed under certain conditions. The resource overhead of the cache system will be greatly reduced, and it can be better mapped to the hardware simulation platform to support efficient collaborative simulation.

[0114] In addition, in one embodiment, the request processing unit 13 is provided with a data verification module. When the data verification module detects that the bytes in the cache block that have not been written by the core computing unit are inconsistent with the backfill data, or that the cache block data is consistent with the data in the eviction request, the request output interface sends a verification error signal.

[0115] In summary, the caching system disclosed in this invention includes: a cache block storage unit comprising a plurality of cache blocks; and a request processing unit comprising a request input port and a request output port, wherein the request output port is connected to the read / write port of the cache block storage unit and the access port of the first RAM. This caching system only records write data that differs between the reference model and the first RAM corresponding to the processor under test, reusing memory access information between the processor under test and the first RAM, thus providing efficient memory access support for processor verification.

[0116] The embodiments of the present invention have been described above with reference to the accompanying drawings. However, the present invention is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of the present invention without departing from the spirit and scope of the claims, and all of these forms are within the protection scope of the present invention.

Claims

1. A cache system for accelerating processor verification processes, characterized in that, include: A cache block storage unit contains several cache blocks; The request processing unit includes a request input port and a request output port, wherein the request output port is connected to the read / write port of the cache block storage unit and the access port of the first RAM.

2. The caching system according to claim 1, characterized in that, The cache system is connected to the reference processor, the processor under test, and the first RAM; The cache block storage unit is used to store write data generated by the reference model of the reference processor executing write instructions, which differs from the corresponding address data in the first RAM; wherein the first RAM is the RAM corresponding to the processor under test.

3. The caching system according to claim 2, characterized in that, The cache block storage unit adopts a storage unit replication structure, which simulates a logical storage unit with multiple physical cache blocks and multiple ports for reading and writing. Each cache block has an independent read and write port.

4. The caching system according to claim 3, characterized in that, The cache block storage unit internally includes at least one of the following: a read port cache module, a read port arbitration module, a write port cache module, and a storage block module; wherein: The read port cache module is connected to the read port of the cache block storage unit and stores the most recently read data; The read port arbitration module is connected to the read port of the cache block storage unit to filter valid read requests; The write port caching module is connected to the write port of the cache block storage unit to cache the requests to be written; The storage block module divides the cache block storage unit into several independent cache blocks, each with an independent read / write port.

5. The caching system according to claim 2, characterized in that, It also includes: a listening unit, the input interface of which is connected to the communication interface between the processor under test and the first RAM, to obtain read requests initiated by the processor under test to the first RAM, read responses returned by the first RAM to the processor under test, and write requests initiated by the processor under test to the first RAM.

6. The caching system according to claim 5, characterized in that, The input interface of the listening unit includes a first sub-interface and a second sub-interface; The first sub-interface is connected to the output interface of the processor under test initiating a read request to the first RAM, and the output interface of the first RAM returning a read response to the processor under test; The second sub-interface is connected to the output interface of the processor under test that initiates a write request to the first RAM.

7. The caching system according to claim 2, characterized in that, The request input port includes: The core computing unit read request port is connected to the read request output interface of the core computing unit of the reference model; The core computing unit write request port is connected to the write request output interface of the core computing unit of the reference model.

8. The caching system according to claim 7, characterized in that, When the core computing unit receives a read request at its read request port, If a cache block with the corresponding address exists in the cache block storage unit, the request output port returns the cache block data to the core computing unit. If it does not exist, the request output port initiates a read request to the access port of the first RAM. After the first RAM returns data, the request processing unit controls the cache block storage unit to allocate a new cache block and write the data.

9. The caching system according to claim 7, characterized in that, When the write request port of the core computing unit receives a write request from the core computing unit, If a cache block with the corresponding address exists in the cache block storage unit, the request output port writes data to that cache block. If it does not exist, the request processing unit controls the cache block storage unit to allocate a new cache block. If the written data does not constitute a complete cache block, the request output port initiates a read request to the access port of the first RAM. After the first RAM returns data, the missing part of the new cache block is filled, and then the written data is written.

10. The caching system according to claim 7, characterized in that, The request input port includes: The processor under test fills back the request port, which is connected to the output of the first sub-interface of the listening unit; The processor under test eviction request port is connected to the output of the second sub-interface of the listening unit.

11. The caching system according to claim 10, characterized in that, The request processing unit includes a data verification module; When the backfill request port of the processor under test receives a backfill request, If a cache block with a corresponding address exists in the cache block storage unit, the data verification module performs a consistency check on the bytes in the cache block that have not been written by the core computing unit and the backfilled data. If it does not exist, the request processing unit controls the cache block storage unit to allocate a new cache block and write backfill data.

12. The caching system according to claim 11, characterized in that, When the eviction request port of the processor under test receives an eviction request. If a cache block with the corresponding address exists in the cache block storage unit, the data verification module performs a consistency check on the cache block data and the data in the eviction request. If it does not exist, the request output interface sends an expulsion missing event signal.

13. The caching system according to claim 8, characterized in that, The request processing unit includes a first optional configuration module. When the core computing unit's read request fails, the first optional configuration module controls the request processing unit to output a missing signal to the core computing unit and not to initiate a read request to the access port of the first RAM.

14. The caching system according to claim 9, characterized in that, The request processing unit includes a second optional configuration module. When the core computing unit write request fails, the second optional configuration module controls the request processing unit to output a missing signal to the core computing unit and not to initiate a read request to the access port of the processor under test RAM.

15. The caching system according to claim 12, characterized in that, The request processing unit includes a third optional configuration module. When the eviction request of the processor under test is not hit, the third optional configuration module controls the request processing unit to send an eviction missing event signal.

16. The caching system according to claim 11 or 12, characterized in that, The request output interface sends a verification error signal when the data verification module detects that the bytes in the cache block that were not written by the core computing unit are inconsistent with the backfill data, or when the cache block data is consistent with the data in the eviction request.

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