A fault high-speed configuration injection serial communication verification method and device
Patent Information
- Application Number
- CN202610744178.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-05-27
- Publication Date
- 2026-08-21
AI Technical Summary
[0002]随着电子设备集成度与功能复杂度的持续提升，设备间的串行通信在传输速率、通信协议种类、实时性与可靠性方面均提出更高要求，与之对应的串行通信验证工作难度显著增加
[0016]本发明相对于现有技术而言，通过采用基于PXI总线的故障高速配置注入架构，将串行通信帧抽象为物理层、链路层、应用层的三层结构化模型，并配合双缓冲解析机制与DMA高速数据传输方式，从根本上解决了串行通信验证维度不足、验证不充分的问题，实现了从电气接口特性、链路传输规则到应用层数据处理的全链路覆盖验证；以上位机统一完成参数配置与下发，使验证装置无需针对不同被测设备更改硬件，有效降低了专用验证设备带来的高成本与长周期问题，显著提升通用性与适配能力，能够满足多品种、小批量、快速迭代的研发需求；通过双缓冲模式实现配置信息的实时解析与加载，避免通信过程中断与时序紊乱，配合DMA直接存储器访问方式大幅提升配置注入速度与数据回传效率，实现故障参数的高速、实时、动态注入；同时，通过可配置的匹配电阻与开关矩阵结构，实现通信驱动能力与带载性能的量化验证，弥补传统验证方式无法覆盖硬件驱动能力的缺陷，使验证结果更贴近真实工况，提升验证结果的可信度与复现性；在提升验证充分性与全面性的同时，简化验证流程、降低硬件投入、缩短验证周期，使串行通信验证从依赖专用设备、局限于接口层检测的传统模式，转变为通用化、全链路、高速可配置的自动化验证模式。
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Abstract
Description
Technical Field
[0001] This invention relates to the field of serial communication verification technology for electronic devices. Background Technology
[0002] With the continuous increase in the integration and functional complexity of electronic devices, serial communication between devices faces higher requirements in terms of transmission rate, communication protocol types, real-time performance, and reliability. Consequently, the difficulty of serial communication verification has increased significantly. In existing technologies, conventional verification methods for serial communication mainly rely on devices such as oscilloscopes and dedicated communication boards to perform basic functional verification of communication waveforms and transmission rates at the communication interface level. This type of verification method can only cover the signal integrity detection of the physical interface. It is lacking in the verification of hardware-level indicators such as communication driving capability and load adaptability, as well as application-level indicators such as communication data processing logic, frame structure parsing, and fault response. This results in insufficient verification of communication methods and incomplete verification dimensions, making it difficult to fully reflect the communication performance of the device under test under real-world operating conditions.
[0003] Meanwhile, dedicated verification equipment for complex communication scenarios suffers from high hardware costs, long development cycles, and poor versatility. It cannot be flexibly configured and quickly switched according to different communication protocols and interface parameters, making it difficult to adapt to the current R&D model of multi-variety, small-batch, and rapidly iterating electronic devices.
[0004] In addition, existing verification devices mostly use conventional data transmission and processing methods, which are prone to problems such as timing interruption, data delay, and untimely configuration loading when performing high-speed fault injection and batch data back transmission. This makes it impossible to achieve high-speed configuration injection and real-time verification of fault parameters, further limiting the efficiency and reliability of serial communication verification. Summary of the Invention
[0005] The purpose of this invention is to provide a high-speed fault configuration injection serial communication verification method and apparatus, which can realize full-link communication verification, covering hardware driver and application data processing, and improve the sufficiency of verification; adopting a general bus architecture to reduce costs and shorten the cycle, and using double buffering and DMA to ensure high-speed fault injection and real-time communication, it has strong versatility and high efficiency, and is suitable for the rapid iterative development needs of multiple varieties and small batches.
[0006] To address the aforementioned technical problems, this invention provides a high-speed fault configuration injection serial communication verification method, comprising the following steps: S1. Build a verification hardware channel based on the PXI bus and abstract the serial communication frame into a three-layer model of physical layer, link layer and application layer. S2. The host computer sends configuration information to the verification device via the PXI bus, and the configuration information is stored in the internal memory of the verification device. S3. The verification device performs double-buffered parsing of the configuration information through the data scheduling module; S4. The verification device communicates serially with the device under test based on the parsed three-layer model parameters. S5. The verification device transmits the communication process data back to the host computer through the DMA communication mode of the PXI bus, and the host computer completes the data processing and verification judgment.
[0007] Step S2 includes: S21. The configuration information is defined in XML file format and is divided into physical layer parameters, link layer parameters, and application layer parameters. S22. The host computer loads the configuration information into the internal memory of the verification device via the PXI bus. S23. The configuration information is uniformly edited and distributed by the host computer to realize the universal configuration of the verification device.
[0008] Step S3 includes: S31. The verification device stores the configuration information in its internal memory according to the physical layer, link layer, and application layer partitions. S32. The data scheduling module performs double-buffered scheduling. During the data reading of the first buffer, the next configuration data is loaded into the second buffer. S33. The communication configuration module parses the configuration information according to the three-layer model structure and generates executable communication parameters; S34. The double-buffered parsing process is executed in real time during communication without interrupting the communication sequence.
[0009] The physical layer parameters include data bit length, parity bit length, parity method, stop bit length, and communication baud rate; the physical layer parameters are used to configure the serial communication electrical interface and basic transmission parameters.
[0010] The link layer parameters include communication mode, frame byte count, frame period, frame format, transmitter matching resistor, and receiver matching resistor; the communication mode includes three types: full-duplex, half-duplex, and simplex.
[0011] The application layer parameters include the dataset to be sent, frame header content, frame sequence number step, and frame verification parameters; the application layer data is sent in the order of communication frame format and period, and the dataset to be sent is stored in the storage space of the verification device and called cyclically.
[0012] This invention also provides a fault high-speed configuration injection serial communication verification device, comprising a PXI bus module, a communication configuration module, a data access module, a bus communication module, a DMA communication module, and a data scheduling module, wherein: The PXI bus module is used to realize the PXI bus communication connection between the host computer and the verification device. The DMA communication module is used to perform direct data transmission between the host computer and the internal memory of the verification device, and to complete the acquisition of configuration information and the return of communication data. The communication configuration module is used to receive and parse the configuration information output by the data access module, and organize it into communication execution data according to the physical layer, link layer, and application layer structure. The bus communication module is used to establish a serial communication connection with the device under test and complete data transmission and reception based on the communication execution data output by the communication configuration module; The data access module is used to write, store, read, and output configuration information and communication data; The data scheduling module is used to perform double-buffered scheduling on the underlying data in the data access module, and to control the timing of data reading and loading.
[0013] The bus communication module integrates a switch matrix. The switch matrix configures the resistance values of the transmitting end matching resistor and the receiving end matching resistor according to the matching resistor parameters output by the communication configuration module. The minimum resistance level is 10Ω and the maximum resistance value is 2550Ω, which is used to complete the communication drive capability verification.
[0014] The data access module uses RAM as the data storage medium to store all communication data under heterogeneous communication mode; the bus communication module sends the communication data stored in RAM sequentially according to a unified time start point, which is provided by an external synchronous clock, supporting one-to-many communication scenarios.
[0015] The data scheduling module is connected to an external synchronization clock, which provides a unified timing reference for the data transmission of the double-buffered data scheduling and bus communication modules. The DMA communication module supports bidirectional high-speed data interaction and uploads communication data to the host computer in real time during the communication process, realizing high-speed fault configuration injection and real-time data feedback.
[0016] Compared to existing technologies, this invention employs a high-speed fault configuration injection architecture based on the PXI bus, abstracting serial communication frames into a three-layer structured model of physical layer, link layer, and application layer. Combined with a double-buffered parsing mechanism and DMA high-speed data transmission, it fundamentally solves the problems of insufficient verification dimensions and inadequate verification in serial communication, achieving full-link coverage verification from electrical interface characteristics and link transmission rules to application layer data processing. Parameter configuration and distribution are uniformly completed by the host computer, eliminating the need for hardware modifications to the verification device for different devices under test. This effectively reduces the high cost and long cycle time associated with dedicated verification equipment, significantly improving versatility and adaptability, and meeting the R&D needs of multi-variety, small-batch, and rapid iteration. Configuration is achieved through a double-buffered mode. Real-time information parsing and loading avoid communication interruptions and timing disruptions. Combined with DMA direct memory access, it significantly improves configuration injection speed and data return efficiency, enabling high-speed, real-time, and dynamic injection of fault parameters. Simultaneously, through configurable matching resistors and switch matrix structures, it achieves quantitative verification of communication driving capability and load-bearing performance, compensating for the shortcomings of traditional verification methods that cannot cover hardware driving capabilities. This makes the verification results closer to real-world operating conditions, improving the reliability and reproducibility of the verification results. While improving the sufficiency and comprehensiveness of verification, it simplifies the verification process, reduces hardware investment, and shortens the verification cycle. This transforms serial communication verification from a traditional mode that relies on dedicated equipment and is limited to interface layer testing into a universal, end-to-end, high-speed, configurable, and automated verification mode.
[0017] The above description is merely an overview of the technical solution of the present invention. In order to better understand the technical means of the present invention and to implement it in accordance with the contents of the specification, and in order to make the above and other objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention are described below. Attached Figure Description
[0018] One or more embodiments are illustrated by way of example with reference numerals in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are denoted as similar elements. Unless otherwise stated, the figures in the drawings are not to be limited by scale.
[0019] Figure 1 This is a flowchart illustrating at least one embodiment of the present invention; Figure 2 This is a schematic diagram of the functional module connections of at least one embodiment of the present invention. Detailed Implementation
[0020] To make the objectives, technical solutions, and advantages of this invention clearer, the embodiments of this invention will be described in detail below with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details are presented in the embodiments of this invention to facilitate a better understanding of this application. However, the technical solutions claimed in this application can be implemented even without these technical details and various variations and modifications based on the following embodiments. The division of the following embodiments is for ease of description and should not constitute any limitation on the specific implementation of this invention. The embodiments can be combined with and referenced by each other without contradiction.
[0021] Example 1 like Figure 1 The method for high-speed configuration injection and serial communication verification of faults, as shown, includes the following steps: S1. Based on the PXI bus, a verification hardware channel is built, and the serial communication frame is abstracted into a three-layer model of physical layer, link layer and application layer. Through layered abstraction, the communication behavior is divided into three independently configurable elements: electrical characteristics, transmission rules and service data, providing structured support for full-link, configurable verification.
[0022] S2. The host computer sends the configuration information to the verification device and stores it in the internal memory via the PXI bus. By utilizing the standardized, high-bandwidth, and high-stability characteristics of the PXI bus, the reliable transmission of configuration information is ensured. At the same time, the verification device has universal bus compatibility and does not require the design of a dedicated interface.
[0023] S3. The verification device performs dual-buffered parsing of configuration information through the data scheduling module, enabling configuration parsing and data reading to be processed in parallel, avoiding data overwriting, read-write conflicts and communication interruptions, and ensuring the timing continuity in high-speed fault injection scenarios.
[0024] S4. The verification device communicates serially with the device under test based on the parsed three-layer model parameters, and performs sending and receiving actions according to unified parameters to ensure that the communication process is consistent with the actual working conditions, thereby improving the reproducibility and reliability of the verification results.
[0025] S5. The verification device transmits communication process data back to the host computer through the DMA communication mode of the PXI bus. The host computer completes data processing and verification judgment. DMA directly realizes data transfer between memory, without occupying controller resources, significantly improving the data transmission rate and meeting the real-time acquisition and judgment requirements under high-speed communication.
[0026] Therefore, a complete serial communication verification process was constructed based on the PXI bus as the hardware foundation, a three-layer model abstraction as the software core, double-buffered parsing as the operating mechanism, and DMA as the high-speed data interaction method. This solution expands the traditional verification that only targets interface waveforms to a full-dimensional verification covering physical electrical components, link transmission, and application data, fundamentally solving the problems of insufficient verification of communication methods and missing verification dimensions in existing technologies. At the same time, by adopting a general-purpose bus architecture to replace high-cost dedicated verification equipment, there is no need to customize hardware for a single device, which significantly reduces verification investment and shortens the verification cycle. It can be well adapted to the development mode of multi-variety, small-batch, and rapidly iterating electronic devices, significantly improving engineering efficiency while ensuring the adequacy of verification.
[0027] Example 2 Based on Example 1, steps S2 and S3 are as follows: S21. The configuration information is defined in XML file format and divided into physical layer, link layer and application layer parameters. XML is highly structured, easy to edit and store, and can clearly carry layer parameters, realizing the universality, reusability and traceability of configuration files.
[0028] S22. The host computer loads the configuration information into the internal memory of the verification device via the PXI bus, realizing centralized configuration distribution, avoiding errors and operational complexity caused by local parameter settings, and improving configuration consistency.
[0029] S23. The configuration information is uniformly edited and distributed by the host computer. The verification device can adapt to different communication scenarios without changing the hardware, achieving highly universal configuration and reducing hardware modification costs.
[0030] S31. The verification device stores the configuration information in the internal memory according to the physical layer, link layer and application layer. The hierarchical storage facilitates hierarchical parsing and hierarchical calling, reduces parameter interference, and improves parsing speed and accuracy.
[0031] S32. The data scheduling module performs double buffering scheduling. During the data reading of the first buffer, the next configuration data is loaded into the second buffer. By alternating read and write, the data loading waiting time is eliminated, ensuring continuous and uninterrupted communication.
[0032] S33. The communication configuration module parses the configuration information according to the three-layer model structure, generates communication parameters that can be directly executed by the hardware, and completes the standardized conversion from configuration file to execution instructions.
[0033] S34. The double-buffered parsing process is executed in real time during communication without interrupting the communication sequence. It supports dynamic fault parameter injection and can load fault configurations during communication to realize online simulation of fault scenarios.
[0034] The physical layer parameters include data bit length, parity bit length, parity method, stop bit length, and communication baud rate. They are used to fully configure the electrical interface and basic transmission attributes, covering all the core adjustable elements of the serial communication physical layer.
[0035] The link layer parameters include communication mode, frame byte count, frame period, frame format, transmitter matching resistor, and receiver matching resistor. The communication modes include full-duplex, half-duplex, and simplex, which can be flexibly adapted to different bus topologies and transmission control logic.
[0036] The application layer parameters include the dataset to be sent, frame header content, frame sequence number step, and frame verification parameters. The application layer data is sent in order according to the format and period. The dataset is cyclically accessed in the device's storage space to meet the requirements of long-term stable verification and business logic traversal.
[0037] This solution achieves controllable parameters, configurable scenarios, and automated processes throughout the entire serial communication verification process through XML structured configuration, fine-grained three-layer parameter definition, and double-buffered real-time parsing. The layered parameter design ensures verification coverage of the entire chain, from electrical drive capability and transmission timing control to application data processing, overcoming the shortcomings of traditional verification methods that only focus on signal waveforms and neglect drive capability and data processing logic. The double-buffering mechanism guarantees uninterrupted communication during high-speed fault injection, meeting stringent real-time requirements. Unified configuration on the host computer gives the device strong versatility, allowing for rapid switching between different tested objects and verification scenarios without the need for redeveloping hardware or dedicated tools. The overall solution significantly reduces manual intervention, equipment investment, and cycle time while improving verification coverage, enabling efficient, stable, and batch verification of complex serial communication.
[0038] Example 3 like Figure 2 The fault high-speed configuration injection serial communication verification device shown includes: a PXI bus module, a communication configuration module, a data access module, a bus communication module, a DMA communication module, and a data scheduling module.
[0039] The PXI bus module enables PXI bus communication between the host computer and the verification device. It adopts a standardized industrial bus interface, is compatible with general PXI chassis and controllers, and reduces hardware development and integration costs.
[0040] The DMA communication module performs direct data transmission between the host computer and the internal memory of the verification device, completes configuration information acquisition and communication data return, bypasses the CPU to directly read and write to the memory, improves data throughput efficiency and reduces system resource consumption.
[0041] The communication configuration module receives and parses the configuration information output by the data access module, organizes it according to the physical layer, link layer, and application layer structure to generate communication execution data, and completes the standardized conversion from upper-layer configuration to lower-layer hardware instructions.
[0042] The bus communication module establishes a serial communication connection with the device under test and completes data transmission and reception based on the communication execution data output by the communication configuration module. It serves as the external communication interface and undertakes driving and interaction functions.
[0043] The data access module completes the writing, storage, reading, and output of configuration information and communication data, providing a stable cache space to ensure that configuration and communication data are not lost or dropped.
[0044] The data scheduling module performs double-buffered scheduling on the underlying data in the data access module, controls the timing of data reading and loading, coordinates the read and write processes to avoid conflicts, and ensures continuous and stable communication.
[0045] Therefore, a highly modular architecture design is adopted, with clear division of labor and reliable collaboration among modules, forming a complete hardware verification system. Modular design reduces development and maintenance difficulty, and improves device reliability and scalability; the PXI standard bus enables the device to have good compatibility and versatility, eliminating dependence on dedicated verification equipment. The DMA communication module significantly improves configuration injection and data return speed, meeting the requirements of high-speed fault injection; the double-buffered scheduling mechanism ensures real-time and continuous communication; the communication configuration module implements standardized parameter parsing, enabling the device to adapt to various protocols and parameter combinations. The overall device achieves universal, high-speed, and full-link coverage serial communication verification, effectively solving the problems of high cost, long cycle, insufficient verification, and poor versatility of existing technologies, and has significant engineering application value.
[0046] Example 4 Based on Example 3, the bus communication module integrates a switch matrix. The switch matrix configures the matching resistor values of the transmitting and receiving ends according to the matching resistor parameters output by the communication configuration module. The minimum resistance level is 10Ω and the maximum resistance is 2550Ω, which can accurately simulate different load conditions and realize the quantitative verification of communication driving capability.
[0047] The data access module uses RAM as the data storage medium to store all communication data under heterogeneous communication mode; the bus communication module sends data sequentially according to the unified time starting point provided by the external synchronization clock, supports complex topology scenarios such as one sender and multiple receivers, and ensures accurate timing synchronization of multiple channels.
[0048] The data scheduling module connects to an external synchronous clock, providing a unified timing reference for double-buffered scheduling and bus communication; the DMA communication module supports bidirectional high-speed data interaction, uploading data in real time during communication, enabling high-speed fault configuration injection and real-time feedback of verification data.
[0049] This further enhances the verification of driving capabilities, adaptability to complex scenarios, and high-speed real-time performance. The switch matrix and graded resistors enable quantifiable and simulated verification of electrical load-carrying capabilities, filling the gap in traditional verification that cannot cover hardware driving capabilities. High-speed RAM storage and an external unified clock enable the device to stably support complex scenarios such as heterogeneous communication, one-to-many transmission and multiple-to-receive, and multi-cycle delay, ensuring accurate and reliable verification results under multiple devices, multiple frames, and multiple timing sequences. The unified timing reference improves the system synchronization accuracy, and bidirectional DMA transmission further improves configuration and return efficiency. This allows the verification device to fully cover all dimensions of verification requirements, including electrical characteristics, driving capabilities, timing synchronization, business logic, and fault injection. It has the advantages of high precision, high reliability, high efficiency, and high versatility, and can fully meet the stringent requirements of serial communication verification for modern electronic equipment.
[0050] Example 5 Based on the above embodiments, the method steps are as follows: The serial communication frame is abstracted into a model, including an application layer, a link layer, and a physical layer. The physical layer configures the data bit length, checksum bit length, checksum method, etc. The link layer includes information such as frame byte count, frame period, frame format, and processing mode. The application layer includes the data information to be sent. The verification device hardware is implemented based on the PXI bus. The host computer software loads the configuration information to the verification device via the PXI bus. The verification device stores the configuration information in its internal memory, parses the configuration information according to a double-buffered mode, and processes it in real time during communication. During communication, data is returned to the host computer software via the DMA communication mode of the PXI bus, and the configuration information is obtained through DMA mode. All communication parameters and states are configured by the host computer, and the verification device performs reliable verification of the device under test according to the actual working conditions, parsing and executing according to a unified time starting point. Because the configuration information is controlled by the host computer, the universality of the verification device is also achieved, significantly improving quality and efficiency.
[0051] The device is configured as follows: a PXI bus module, a communication configuration module, a data access module, a bus communication module, a DMA communication module, and a data scheduling module. The PXI bus module enables PXI bus communication between the host computer and the verification device. The DMA communication module handles direct data access between the host computer and the verification device's memory. The communication adaptation module parses the configuration information in memory and organizes it into physical layer, data link layer, and application layer data. The bus communication module communicates with the device under test according to the configuration data. The data access module stores and retrieves configuration data and communication data. The data scheduling module performs double-buffered scheduling of the underlying data. For heterogeneous communication modes, all communication data can be stored in RAM and sent uniformly by the bus communication module according to a time start point, which can be controlled by an external clock.
[0052] This allows for the configuration of various communication formats and data on the host computer, which is then parsed and communicated by the verification device based on the PXI bus architecture, enabling reliable verification of the device under test according to actual operating conditions. Because the configuration information is controlled by the host computer, the verification device also achieves versatility, significantly improving quality and efficiency.
[0053] Those skilled in the art will understand that the above embodiments can be modified in form and detail in practical applications without departing from the spirit and scope of the invention.
Claims
1. A fault high-speed configuration injection serial communication verification method, characterized in that, Includes the following steps: S1. Build a verification hardware channel based on the PXI bus and abstract the serial communication frame into a three-layer model of physical layer, link layer and application layer. S2. The host computer sends configuration information to the verification device via the PXI bus, and the configuration information is stored in the internal memory of the verification device. S3. The verification device performs double-buffered parsing of the configuration information through the data scheduling module; S4. The verification device communicates serially with the device under test based on the parsed three-layer model parameters. S5. The verification device transmits the communication process data back to the host computer through the DMA communication mode of the PXI bus, and the host computer completes the data processing and verification judgment.
2. The fault high-speed configuration injection serial communication verification method according to claim 1, characterized in that, Step S2 includes: S21. The configuration information is defined in XML file format and is divided into physical layer parameters, link layer parameters, and application layer parameters. S22. The host computer loads the configuration information into the internal memory of the verification device via the PXI bus. S23. The configuration information is uniformly edited and distributed by the host computer to realize the universal configuration of the verification device.
3. The fault high-speed configuration injection serial communication verification method according to claim 2, characterized in that, Step S3 includes: S31. The verification device stores the configuration information in its internal memory according to the physical layer, link layer, and application layer partitions. S32. The data scheduling module performs double-buffered scheduling. During the data reading of the first buffer, the next configuration data is loaded into the second buffer. S33. The communication configuration module parses the configuration information according to the three-layer model structure and generates executable communication parameters; S34. The double-buffered parsing process is executed in real time during communication without interrupting the communication sequence.
4. The fault high-speed configuration injection serial communication verification method according to claim 3, characterized in that, The physical layer parameters include data bit length, parity bit length, parity method, stop bit length, and communication baud rate; the physical layer parameters are used to configure the serial communication electrical interface and basic transmission parameters.
5. The fault high-speed configuration injection serial communication verification method according to claim 3, characterized in that, The link layer parameters include communication mode, frame byte count, frame period, frame format, transmitter matching resistor, and receiver matching resistor; the communication mode includes three types: full-duplex, half-duplex, and simplex.
6. The fault high-speed configuration injection serial communication verification method according to claim 3, characterized in that, The application layer parameters include the dataset to be sent, frame header content, frame sequence number step, and frame verification parameters; the application layer data is sent in the order of communication frame format and period, and the dataset to be sent is stored in the storage space of the verification device and called cyclically.
7. A fault high-speed configuration injection serial communication verification device, characterized in that, It includes a PXI bus module, a communication configuration module, a data access module, a bus communication module, a DMA communication module, and a data scheduling module, among which: The PXI bus module is used to realize the PXI bus communication connection between the host computer and the verification device. The DMA communication module is used to perform direct data transmission between the host computer and the internal memory of the verification device, and to complete the acquisition of configuration information and the return of communication data. The communication configuration module is used to receive and parse the configuration information output by the data access module, and organize it into communication execution data according to the physical layer, link layer, and application layer structure. The bus communication module is used to establish a serial communication connection with the device under test and complete data transmission and reception based on the communication execution data output by the communication configuration module; The data access module is used to write, store, read, and output configuration information and communication data; The data scheduling module is used to perform double-buffered scheduling on the underlying data in the data access module, and to control the timing of data reading and loading.
8. The fault high-speed configuration injection serial communication verification device according to claim 7, characterized in that, The bus communication module integrates a switch matrix. The switch matrix configures the resistance values of the transmitting end matching resistor and the receiving end matching resistor according to the matching resistor parameters output by the communication configuration module. The minimum resistance level is 10Ω and the maximum resistance value is 2550Ω, which is used to complete the communication drive capability verification.
9. The fault high-speed configuration injection serial communication verification device according to claim 7, characterized in that, The data access module uses RAM as the data storage medium to store all communication data under heterogeneous communication mode; The bus communication module sequentially sends communication data stored in RAM based on a unified time start point, which is provided by an external synchronous clock, supporting one-to-many communication scenarios.
10. The fault high-speed configuration injection serial communication verification device according to claim 7, characterized in that, The data scheduling module is connected to an external synchronization clock, which provides a unified timing reference for the data transmission of the double-buffered data scheduling and bus communication modules. The DMA communication module supports bidirectional high-speed data interaction and uploads communication data to the host computer in real time during the communication process, realizing high-speed fault configuration injection and real-time data feedback.