Memory semantic access device, system and method

Abstract

This disclosure proposes a memory semantic access device, system, and method. The device includes a first processing module located in a computing chip, used to receive read / write instructions for accessing remote memory initiated by computing units in the computing chip, and to encapsulate the read / write instructions into remote memory access requests conforming to the on-chip bus protocol. A second processing module located in an input / output chip, communicatively connected to the first processing module, is used to encapsulate the remote memory access request into an Ethernet packet and send it to the target computing chip via Ethernet. This disclosure, by adding a first processing module to the device, directly interfaces with read / write instructions for accessing remote memory initiated by computing units, encapsulating the read / write instructions into remote memory access requests. This allows native read / write instructions initiated by computing units to be directly converted into remote memory access requests, significantly reducing hardware and software interaction steps, significantly reducing end-to-end latency in small packet communication, and adapting to high-frequency small packet communication scenarios in GPU clusters.

Description

Technical Field

[0001] This disclosure relates to the field of chip interconnect technology, and in particular to a memory semantic access device, system and method. Background Technology

[0002] Against the backdrop of the continued explosive growth in demand for artificial intelligence (AI) computing power, AI accelerators have become the core hardware supporting large-scale model training and high-performance inference. Inter-chip interconnect technology for Graphics Processing Unit (GPU) clusters is a key factor determining the overall performance of AI accelerators. Existing mainstream AI accelerators primarily rely on Remote Direct Memory Access (RDMA) technology for inter-chip interconnect, which essentially uses message passing semantics to achieve data transmission. Its core requires multiple interactions between hardware and software to complete a single transmission operation, mainly meeting the bandwidth requirements for transmitting large data blocks.

[0003] However, in practical applications of GPU clusters, besides the need to transmit large data blocks such as model parameters and training datasets, there are also numerous scenarios involving frequent communication of small messages between GPUs, such as control flow synchronization, training progress updates, and status instruction exchanges. The amount of data transmitted in these scenarios is typically only tens to hundreds of bytes, and their sensitivity to transmission latency is far greater than their sensitivity to bandwidth. The hardware and software interaction overhead brought about by the message passing semantics of RDMA technology will generate extremely high end-to-end latency in small packet communication, making it difficult to match the performance requirements of such scenarios. Moreover, existing RDMA technology cannot directly respond to native read / write (Load / Store) instructions issued by the processor. It requires complex software stacks for instruction conversion and protocol adaptation before remote data transmission can be triggered, further increasing transmission latency and raising the complexity of hardware usage. Summary of the Invention

[0004] This disclosure provides a memory semantic access device, system, and method that can significantly reduce the hardware and software interaction steps in remote memory access, significantly reduce end-to-end latency in small packet communication, and adapt to high-frequency small packet communication scenarios in GPU clusters.

[0005] According to one aspect of this disclosure, a memory semantic access device is provided, applied in a computing chip, comprising:

[0006] The first processing module, located in the computing chip, is used to receive read and write instructions for accessing remote memory initiated by the computing unit in the computing chip, and to encapsulate the read and write instructions into a remote memory access request that conforms to the on-chip bus protocol.

[0007] The second processing module, located in the input / output chip and communicatively connected to the first processing module, is used to encapsulate the remote memory access request into an Ethernet message and send it to the target computing chip via Ethernet.

[0008] Optionally, it also includes a connectivity network for communicating between the computing chip and the input / output chip, the connectivity network including an inter-chip interconnect protocol interface or an on-chip network.

[0009] Optionally, the computing chip also includes:

[0010] At least one computing unit

[0011] A control processor, communicatively connected to the first processing module, is used to send configuration parameter information to the first processing module; wherein the configuration parameter information includes at least one of target computing chip identifier, data packet length, and read / write type information.

[0012] Optionally, the first processing module is further configured to generate user field information based on the configuration parameter information sent by the control processor. The user field information is in a user field format that conforms to the on-chip bus protocol, and the user field information includes at least one of the target computing chip identifier, data packet length, and read / write type information.

[0013] Optionally, the first processing module is disposed inside the computing unit, and the first processing module includes:

[0014] The bus extension register, which is communicatively connected to the control processor, is used to set the user field information according to the configuration operation of the control processor.

[0015] Optionally, the computing unit includes:

[0016] The memory management unit is used to determine that the read / write instruction is a remote access request;

[0017] A bus controller is used to acquire the remote access request and the user field information, and encapsulate the remote access request and the user field information into the remote memory access request;

[0018] An on-chip bus is used to send the remote memory access request to the second processing module.

[0019] Optionally, the first processing module is independently located outside the computing unit.

[0020] Optionally, the first processing module includes:

[0021] Configuration registers are used to map to the address space of the control processor via memory-mapped input / output.

[0022] The control processor is used to write the configuration parameter information into the mapped local address and generate the user field information;

[0023] The first processing module is used to read the user field information in the mapped configuration register.

[0024] Optionally, the computing chip also includes a data scheduling unit, with the first processing module located inside or outside the data scheduling unit.

[0025] Optionally, the computing unit includes:

[0026] The memory management unit is used to determine that the read / write instruction is a remote access request;

[0027] When the first processing module is located inside the data scheduling unit, the memory management unit sends the remote access request to the first processing module inside the data scheduling unit.

[0028] When the first processing module is located outside the data scheduling unit, the memory management unit sends the remote access request to the data scheduling unit, and the data scheduling unit forwards the remote memory access request to the first processing module.

[0029] The first processing module is used to encapsulate the remote access request and the user field information into a remote memory access request and send it to the second processing module.

[0030] Optionally, the first processing module integrates a multi-channel direct memory access engine, which is used to split the remote memory access request into multiple sub-requests and issue the multiple sub-requests in parallel through multiple channels;

[0031] The multi-channel direct memory access engine is equipped with a dedicated register interface for real-time feedback and notification of parameter configuration and transmission status of the multiple channels.

[0032] Optionally, the second processing module is further configured to extract user field information from the remote memory access request, perform queue scheduling processing on the remote memory access request based on the user field information, and then encapsulate it into the Ethernet packet;

[0033] The queue scheduling process includes enqueueing, dequeueing, or merging processes; the merging process is used to merge multiple remote memory access requests with the same target computing chip and the same read / write type into a single Ethernet packet.

[0034] Optionally, it also includes a network interface card (NIC) unit, wherein the second processing module is disposed in the NIC unit.

[0035] The network interface card (NIC) unit further includes a remote direct memory access module, which is integrated with the second processing module in the same NIC unit, and the two work independently and transmit in parallel.

[0036] The remote direct memory access module is used to process remote direct memory access transmission of the first type of data, and the second processing module is used to process memory semantic access transmission of the second type of data.

[0037] The data length of the first type of data is greater than the data length of the second type of data.

[0038] Optionally, the first processing module further includes:

[0039] A tag allocation unit is used to assign a unique identifier to each remote memory access request and encapsulate the unique identifier into the remote memory access request;

[0040] The response matching unit is used to route the response data to the computing unit that initiated the read / write command based on the unique identifier carried in the response message.

[0041] Optionally, the first processing module is also configured to perform remote memory access asynchronously, receive and process the next read / write instruction without waiting for a response after issuing the remote memory access request, and receive response data through interrupt or polling.

[0042] Optionally, the first processing module is further configured to map the remote address in the read / write instruction to the network address of the target computing chip;

[0043] The second processing module is also used to write the network address into the frame header of the Ethernet packet when encapsulating the Ethernet packet.

[0044] Optionally, the remote address is an address in a unified global address space, which is defined by node identifier, chip identifier, chip identifier and address offset.

[0045] The first processing module is further configured to determine the identifier of the target computing chip based on the node identifier and chip identifier in the unified global address space, and map the identifier of the target computing chip to the network address.

[0046] Optionally, the second processing module is also used to receive Ethernet packets sent by other computing chips, strip the frame headers to restore them to remote memory access requests, and send them to the first processing module;

[0047] The first processing module is communicatively connected to the storage controller of the computing chip, and is used to access the storage controller to read and write data according to the remote memory access request, and return response data to the other computing chips.

[0048] Optionally, the second processing module is further configured to receive the Ethernet response sent by the target computing chip, strip the frame header to restore it as bus response data, and send it to the first processing module;

[0049] The first processing module is also used to send the bus response data to the computing unit that initiated the read / write command.

[0050] According to one aspect of this disclosure, a memory semantic access system is provided, comprising:

[0051] The first computing chip includes a memory semantic access device as described in any of the preceding claims;

[0052] The second computing chip is connected to the first computing chip via Ethernet.

[0053] The first computing chip is used to send encapsulated Ethernet packets to the second computing chip to access the memory of the second computing chip.

[0054] According to one aspect of this disclosure, a memory semantic access method is proposed for application in a computing chip, comprising:

[0055] The first processing module located in the computing chip receives read and write instructions for accessing remote memory initiated by the computing unit in the computing chip;

[0056] The first processing module encapsulates the read / write instructions into a remote memory access request conforming to the on-chip bus protocol;

[0057] The second processing module located in the input / output chip encapsulates the remote memory access request into an Ethernet message and sends it to the target computing chip via Ethernet.

[0058] According to one aspect of this disclosure, an electronic device is proposed, the electronic device including a memory, a processor, a program stored in the memory and executable on the processor, and a data bus for implementing connection communication between the processor and the memory, wherein the program is executed by the processor to implement memory semantic access means as described above.

[0059] According to one aspect of this disclosure, a computer-readable storage medium is provided that stores one or more programs, which can be executed by one or more processors to implement the memory semantic access means as described above.

[0060] This disclosure proposes a memory semantic access device, system, and method. The device includes a first processing module located in a computing chip, used to receive read / write instructions for accessing remote memory initiated by computing units in the computing chip, and to encapsulate the read / write instructions into a remote memory access request conforming to the on-chip bus protocol; and a second processing module located in an input / output chip, communicatively connected to the first processing module, used to encapsulate the remote memory access request into an Ethernet message, and send it to the target computing chip via Ethernet. This disclosure solves the technical problem that traditional RDMA cannot directly respond to the processor's native read and write instructions initiated by the computing unit by adding a first processing module to the device. The first processing module encapsulates the read and write instructions into remote memory access requests, allowing the native read and write instructions initiated by the computing unit to be directly converted into remote memory access requests. This simplifies the instruction triggering logic of remote memory access. The second processing module completes Ethernet packet encapsulation based on the request and sends it to the target computing chip. This realizes direct hardware encapsulation of read and write instructions without the need for instruction conversion, queue scheduling, and other operations in the software stack of traditional RDMA. This significantly reduces the number of software and hardware interaction links, significantly reduces the end-to-end latency of small packet communication, and is suitable for high-frequency small packet communication scenarios of GPU clusters.

[0061] Furthermore, by setting up a connection network to realize the communication connection between the computing core and the input / output core, a dedicated and stable transmission link is provided for the remote memory access request after the read and write instructions are encapsulated. This ensures the efficient and interference-free transmission of the request data between modules, ensures the continuity of the memory semantic access link, and lays a reliable transmission foundation for subsequent Ethernet packet encapsulation and transmission.

[0062] Furthermore, by adding a control processor to the computing chip and connecting it to the first processing module, flexible configuration and precise control of remote memory access are achieved. The control processor can send configuration parameters, including the target computing chip identifier, data packet length, and read / write type, to the first processing module, enabling the device to adapt to the needs of different target chips, different data lengths, and different read / write scenarios, thus improving the versatility and scenario adaptability of the memory semantic access device.

[0063] Furthermore, the first processing module generates user field information conforming to the on-chip bus protocol format based on the configuration parameters, achieving seamless integration between the configuration information and the on-chip transmission protocol. The user fields directly carry core information such as the target computing chip identifier, data packet length, and read / write type, ensuring the integrity and standardization of the configuration information during on-chip transmission and guaranteeing the efficiency and reliability of remote memory access requests during on-chip transmission.

[0064] Furthermore, by placing the first processing module inside the computing unit and implementing user field configuration through the bus extension register, deep coupling between the configuration logic and the computing unit is achieved. The bus extension register communicates directly with the control processor, enabling rapid response to user field configuration operations and reducing the transmission path and latency of configuration information. At the same time, integrating the first processing module inside the computing unit facilitates the direct acquisition of configured user field information after the computing unit initiates read / write commands, improving the response speed of remote access request encapsulation and optimizing the link efficiency from command initiation to request encapsulation.

[0065] Furthermore, the memory management unit accurately determines that the read / write command is a remote access request, avoiding confusion between local and remote access; the bus controller encapsulates the remote access request and user field information into a remote memory access request conforming to the on-chip bus specification, ensuring the standardization of the request format; the on-chip bus, as an efficient transmission carrier, directs the encapsulated request to the second processing module. The three work together to realize the hardware-based processing of the entire process of remote memory access request from identification to on-chip transmission, improving access efficiency and stability.

[0066] Furthermore, an independent deployment scheme is provided for the first processing module, located outside the computing unit, enhancing the hardware architecture flexibility of the device. This avoids strong coupling between the first processing module and the computing unit, facilitating adjustments to the module layout based on different hardware resources and performance requirements, adapting to scenarios with limited computing unit resources, and improving the scalability and hardware adaptability of the memory semantic access device.

[0067] Furthermore, by mapping the configuration registers to the control processor's address space using memory-mapped input / output, the control processor can conveniently read and write user field information and manage it efficiently. The control processor can write configuration parameters through its local address, while the first processing module can directly read the mapped configuration registers to obtain user fields, eliminating the need for complex communication protocols and simplifying the configuration process.

[0068] Furthermore, combining the first processing module with the data scheduling unit provides two flexible deployment modes, one internal and one external, further enhancing the adaptability of the hardware architecture. When the first processing module is located inside the data scheduling unit, the request forwarding path can be reduced, improving encapsulation efficiency; when located externally, the hardware complexity of the data scheduling unit can be reduced, facilitating independent module optimization. Both modes can adapt to different performance and resource constraint scenarios, enabling the device to ensure functional integrity while balancing hardware implementation flexibility and efficiency.

[0069] Furthermore, regardless of whether the first processing module is located inside or outside the data scheduling unit, the memory management unit can accurately direct the transmission of remote access requests. The first processing module then encapsulates the request and user fields and sends them to the second processing module. This ensures the uniformity of functions and optimizes the transmission path according to the deployment mode, avoiding redundant overhead of request forwarding and improving the processing efficiency of remote memory access requests.

[0070] Furthermore, by integrating a multi-channel direct memory access engine into the first processing module, high-bandwidth parallel transmission of large blocks of data for remote access is achieved. A single large block of remote memory access request can be split into multiple sub-requests. Through multi-channel parallel transmission, the bandwidth bottleneck of single-channel transmission is broken through, and the efficiency of large data transmission is greatly improved. At the same time, the dedicated register interface supports channel parameter configuration and real-time feedback of transmission status, enabling the control processor to accurately manage the multi-channel transmission process and ensuring the stability and controllability of large blocks of data for remote access.

[0071] Furthermore, through queue scheduling in the second processing module, efficient routing and packet optimization of remote memory access requests are achieved. Enqueueing and dequeueing based on user field information enables hardware isolation of requests from different target computing chips, avoiding cross-device request chaos. Merging processing aggregates small requests of the same target and type into a single Ethernet packet, reducing frame header overhead and network forwarding pressure, improving the transmission efficiency of small data remote access, while simultaneously considering request isolation and bandwidth optimization.

[0072] Furthermore, the second processing module and the remote direct memory access module are integrated into the same network interface card (NIC) unit, constructing a dual-function NIC architecture that enables fine-grained adaptation to the transmission requirements of different data types. The remote direct memory access module is responsible for high-bandwidth transmission of large data blocks, while the second processing module is responsible for low-latency memory semantic access of small data. The two work independently and transmit in parallel, which not only fully utilizes NIC hardware resources but also solves the latency bottleneck problem of traditional single RDMA mode in small packet transmission scenarios, improving the overall data transmission efficiency and scenario adaptability of the device.

[0073] Furthermore, through the tag allocation unit and response matching unit, accurate routing and response matching of multiple concurrent remote memory access requests are achieved. The tag allocation unit assigns a unique identifier to each request, ensuring a one-to-one correspondence between requests and responses; the response matching unit routes the response data to the computation unit that initiated the request based on the identifier, avoiding response confusion and data corruption in multi-request concurrent scenarios, and ensuring the concurrent reliability and data integrity of memory semantic access.

[0074] Furthermore, the next instruction can be processed without waiting for a response after a request is issued, which greatly improves the instruction throughput and resource utilization of the computing unit. At the same time, by receiving response data through interrupt or polling, the real-time response is guaranteed and the blocking waiting of the computing unit is avoided, thus optimizing the parallelism of instruction execution and memory access operations.

[0075] Furthermore, a hardware-based mapping from remote addresses to network addresses is implemented. The first processing module directly converts the remote address in the read / write instruction into the network address of the target computing chip, while the second processing module writes the address into the Ethernet frame header. This avoids the overhead of software address translation and achieves seamless connection from instruction-level remote addresses to network-level routing addresses. It improves the encapsulation and routing efficiency of remote memory access requests and ensures accurate transmission of packets in the Ethernet.

[0076] Furthermore, by defining remote addresses based on a unified global address space, and using node identifiers, chip identifiers, chip identifiers, and address offsets for joint location, a globally unique identifier for memory addresses in large-scale computing clusters is achieved. The first processing module can accurately map network addresses based on node and chip identifiers in the unified global address space, ensuring both the scalability of the address space and providing a unified addressing basis for cross-node and cross-chip memory semantic access.

[0077] Furthermore, when acting as the accessed end, the second processing module can receive and parse Ethernet packets from other computing chips, restore them to remote access requests, and then the first processing module directly accesses the storage controller to complete read and write operations and return a response. This realizes bidirectional data interaction for memory semantic access, builds a complete end-to-end remote memory access ecosystem, and enables the device to act as both a request initiator and a target server.

[0078] Furthermore, after the second processing module receives the Ethernet response from the target computing chip, it strips the frame header and restores it to the bus response data. The first processing module then accurately routes it to the computing unit that initiated the request, completing a complete closed loop from request to response reception. This ensures the continuity and reliability of end-to-end memory semantic access, enabling the computing unit to obtain remote access results in a timely manner and reducing memory access waiting time.

[0079] Furthermore, by connecting the first and second computing chips via Ethernet, remote memory access across chips is achieved without relying on the traditional RDMA software stack, significantly reducing the latency and overhead of cross-chip memory access. At the same time, the system is compatible with general Ethernet infrastructure, facilitating deployment and expansion, and providing an efficient and flexible cross-chip memory access solution for large-scale AI computing clusters.

[0080] Other features and advantages of this disclosure will be set forth in the following description and will be apparent in part from the description or may be learned by practicing the disclosure. The objectives and other advantages of this disclosure may be realized and obtained by means of the structures particularly pointed out in the description, claims and drawings. Attached Figure Description

[0081] The accompanying drawings are provided to further understand the technical solutions of this disclosure and form part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of this disclosure and do not constitute a limitation on the technical solutions of this disclosure.

[0082] Figure 1 This is a system architecture diagram of a computing chip and a target computing chip according to an embodiment of the present disclosure;

[0083] Figure 2 This is a system architecture of a computing chip according to an embodiment of the present disclosure. Figure 1 ;

[0084] Figure 3 This is a system architecture of a computing chip according to an embodiment of the present disclosure. Figure 2 ;

[0085] Figure 4 This is a system architecture of a computing chip according to an embodiment of the present disclosure. Figure 3 ;

[0086] Figure 5 This is a system architecture of a computing chip according to an embodiment of the present disclosure. Figure 4 ;

[0087] Figure 6 This is a system architecture of a computing chip according to an embodiment of the present disclosure. Figure 5 ;

[0088] Figure 7 This is an architecture diagram of a memory semantic access system according to an embodiment of this disclosure;

[0089] Figure 8 This is a schematic diagram of a memory semantic access method according to an embodiment of this disclosure. Figure 1 ;

[0090] Figure 9 This is a schematic diagram of a memory semantic access method according to an embodiment of this disclosure. Figure 2 ;

[0091] Figure 10 This is a schematic diagram of the structure of an electronic device proposed in one embodiment of the present disclosure.

[0092] Figure label:

[0093] 100. Memory semantic access device; 101. Computing unit; 102. First processing module; 103. Second processing module; 104. Network connection; 105. Memory management unit; 106. Bus controller; 107. On-chip bus; 108. Network interface card unit; 109. Remote direct memory access module;

[0094] 200. Target computing chip;

[0095] 300. Second computing chip. Detailed Implementation

[0096] To make the objectives, technical solutions, and advantages of this disclosure clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and are not intended to limit the scope of this disclosure.

[0097] Before providing a further detailed description of the embodiments of this disclosure, the terms and concepts used in these embodiments are explained, and they are subject to the following interpretations:

[0098] Graphics Processing Unit (GPU): As the core computing power carrier of AI accelerators, GPU is the core computing device of scale-up supernode clusters, supporting remote memory access and data interaction between chips.

[0099] Vertical scaling: Scale-up is a computing power and interconnection expansion method for GPU supernode clusters. It refers to the aggregation of computing power and the construction of supernode clusters by improving the hardware performance of a single node and optimizing the interconnection efficiency between GPUs within the node. It is the core application scenario of the memory semantic access scheme in this application. In this scenario, there are a large number of high-frequency communication requirements for small packets such as control flow synchronization and flag updates between GPUs, and the sensitivity to transmission latency is much higher than that to bandwidth.

[0100] Computing In Memory Die (CIM Die) is the core computing die of a GPU, integrating computing units, data scheduling units, etc., and is the core hardware carrier for initiating remote memory read and write commands.

[0101] Input and Output Die (IO Die) is the GPU's interconnect and data transmission die, integrating the engine, network interface card, etc., and is responsible for protocol conversion and Ethernet transmission of data within and between chips.

[0102] Compute Unit (CU): The core computing submodule within the CIM Die, used to initiate Load / Store read / write commands to access remote memory, and is the instruction initiator for memory semantic access.

[0103] Data scheduling unit: Data Unit / Data Unit-Task Scheduler, DU / DU_TS, a hardware module within the CIM Die, responsible for forwarding remote access requests and connecting the computing unit and the interconnect module.

[0104] Control processor: Central Processing Unit, CPU, specifically referring to RISC-V CPU in this application, is used to configure the core parameters of remote memory access and to issue configuration parameter information.

[0105] Advanced eXtensible Interface (AXI): A high-performance on-chip bus protocol introduced by ARM, it is the main channel for data transmission between modules within the GPU and is used to carry out transaction transmission for remote memory access.

[0106] Remote Direct Memory Access (RDMA) enables high-speed data transfer between hosts by bypassing the operating system kernel. In this invention, it is implemented using the RoCEv2 engine and is dedicated to high-bandwidth transmission of large data blocks.

[0107] Remote Direct Memory Access over Converged Ethernet Version 2 (RoCEv2) is a technical standard for implementing RDMA over Ethernet, supporting routing across Layer 3.

[0108] Scale-Up Ethernet (SUE) is an Ethernet technology for interconnecting GPU supernode clusters. Its core provides high-speed communication capabilities with memory access semantics and is the core technology for achieving low-latency small packet communication.

[0109] In related technologies, inter-chip interconnection in AI accelerators mainly relies on Remote Direct Memory Access (RDMA) technology. Essentially, it uses message passing semantics to achieve data transmission. Its core requires multiple hardware and software interactions to complete a single transmission operation, primarily meeting the bandwidth requirements for large data block transmissions. However, in practical applications of GPU clusters, besides the need to transmit large data blocks such as model parameters and training datasets, there are numerous scenarios involving frequent, small-message communication between GPUs, such as control flow synchronization, training progress updates, and status command interactions. The data volume in these scenarios is typically only tens to hundreds of bytes, making them far more sensitive to transmission latency than bandwidth. The hardware and software interaction overhead caused by the message passing semantics of RDMA technology results in extremely high end-to-end latency in small-packet communication, making it difficult to meet the performance requirements of such scenarios. Furthermore, existing RDMA technology cannot directly respond to native load / store commands issued by the processor; it requires complex software stacks for instruction conversion and protocol adaptation before remote data transmission can be triggered, further increasing transmission latency and the complexity of hardware usage.

[0110] Based on this, this disclosure proposes a memory semantic access device, system, and method. By adding a first processing module to the device, it directly interfaces with read and write instructions initiated by the computing unit to access remote memory, encapsulating the read and write instructions into remote memory access requests. This allows the native read and write instructions initiated by the computing unit to be directly converted into remote memory access requests, solving the technical problem that traditional RDMA cannot directly respond to the processor's native read and write instructions and simplifying the instruction triggering logic for remote memory access. The second processing module completes Ethernet packet encapsulation based on the request and sends it to the target computing chip, realizing direct hardware encapsulation of read and write instructions. This eliminates the need for instruction conversion, queue scheduling, and other operations in the traditional RDMA software stack, significantly reducing the number of software and hardware interaction links, significantly reducing the end-to-end latency of small packet communication, and adapting to high-frequency small packet communication scenarios in GPU clusters.

[0111] System architecture description applied in the embodiments of this disclosure

[0112] Figure 1 This is a system architecture diagram of a computing chip and a target computing chip according to an embodiment of this disclosure. The computing chip includes a computing core and an input / output core. The memory semantic access device 100 of this application is applied to the computing chip, specifically including a first processing module 102 located in the computing core and a second processing module 103 located in the input / output core.

[0113] The first processing module 102 is used to receive read and write instructions for accessing remote memory initiated by the computing unit 101 in the computing chip, and encapsulate the read and write instructions into a remote memory access request that conforms to the on-chip bus protocol.

[0114] The second processing module 103 is communicatively connected to the first processing module 102 and is used to encapsulate the remote memory access request into an Ethernet message and send it to the target computing chip 200 via Ethernet.

[0115] In this embodiment, the memory semantic access device 100 is specifically hardware that implements end-to-end load / store memory semantic access based on Ethernet. It completes remote memory access and data interaction between GPU clusters via Ethernet, and can specifically be GPU0. The target computing chip 200 is the memory semantic access device 100, that is, the device that GPU0 needs to access memory for data interaction, and can specifically be GPU1.

[0116] In this embodiment, the computing chip is mainly used to execute computing tasks, initiate remote memory access instructions, and complete instruction parsing and encapsulation of remote memory access requests. It is the computing core and instruction initiation end of the entire memory semantic access device 100.

[0117] The input / output chip is mainly used to receive remote memory access requests from the computing chip, complete message encapsulation, queue scheduling and network transmission, and receive Ethernet response messages from the target computing chip 200 to realize message parsing, frame header stripping and response data return. It is the core of external communication and data interaction interface of the entire memory semantic access device 100.

[0118] In this embodiment of the application, the read / write instructions for accessing the memory of the target computing chip 200 are specifically load / store instructions natively issued by the GPU. These instructions are the basic native instructions for GPU memory access, which do not need to be converted by the software stack and are directly initiated by the computing unit 101 to perform read and write operations on the physical memory of the target computing chip 200, that is, the remote GPU 1.

[0119] In this embodiment of the application, the computing chip further includes at least one computing unit 101, which is a memory semantic access device 100, that is, the core computing power module of GPU0, specifically a CU (Compute Unit).

[0120] The first processing module 102 is specifically the SUE_Manager (Scale-Up Ethernet Manager) module, which directly interfaces with the read and write instructions for accessing remote memory initiated by the computing unit 101. It encapsulates the read and write instructions into remote memory access requests, so that the native read and write instructions initiated by the computing unit 101 can be directly converted into remote memory access requests. This solves the technical problem that traditional RDMA cannot directly respond to the processor's native read and write instructions and simplifies the instruction triggering logic for remote memory access.

[0121] The second processing module 103 is specifically the SUE (Scale-Up Ethernet) module. Based on the request, it completes Ethernet packet encapsulation and sends it to the target computing chip 200. It realizes direct hardware encapsulation of read and write instructions, without the need for instruction conversion, queue scheduling and other operations through the traditional RDMA software stack. This greatly reduces the software and hardware interaction links, significantly reduces the end-to-end latency of small packet communication, and adapts to the high-frequency small packet communication scenario of GPU clusters.

[0122] In one possible embodiment, since there may be multiple computing units 101 that issue read and write instructions, the first processing module 102 further includes a tag allocation unit, which is used to assign a unique identifier to each remote memory access request and encapsulate the unique identifier into the remote memory access request.

[0123] The first processing module 102 also includes a response matching unit, which routes the response data to the computing unit 101 that initiated the read / write command based on the unique identifier carried in the response message. Through the tag allocation unit and the response matching unit, accurate routing and response matching of multiple concurrent remote memory access requests are achieved, avoiding response confusion and data corruption in multi-request concurrent scenarios, and ensuring the concurrent reliability and data integrity of memory semantic access.

[0124] Furthermore, the first processing module 102 is also used to perform remote memory access asynchronously. After issuing the remote memory access request, it can receive and process the next read / write instruction without waiting for a response, and receives response data through interrupt or polling. Since the next instruction can be processed without waiting for a response after issuing the request, the instruction throughput and resource utilization of the computing unit 101 are greatly improved. Receiving response data through interrupt or polling ensures the real-time nature of the response and avoids blocking and waiting of the computing unit 101, thus optimizing the parallelism of instruction execution and memory access operations.

[0125] Figure 2 This is a system architecture of a computing chip according to an embodiment of the present disclosure. Figure 1 ,like Figure 2 As shown, the computing chip includes an input / output die (IO Die) and a computing die (CIM Die). The input / output die is... Figure 2 The IO Die in the chip is responsible for protocol conversion between on-chip and inter-chip data, Ethernet packet encapsulation and parsing, and remote data interaction with other devices via Ethernet. The computing chip is... Figure 2 The CIM Die in the GPU is responsible for executing various computing tasks and is also the initiator of read and write commands.

[0126] In this embodiment, the computing unit 101 is located on the CIM Die and is responsible for executing various GPU computing tasks. The first processing module 102 is also located on the CIM Die and is responsible for encapsulating instructions. The second processing module 103 is located on the IO Die and is responsible for further encapsulating the encapsulated requests into an Ethernet format for inter-GPU transmission.

[0127] Optionally, the memory semantic access device in the computing chip of this application further includes a connection network 104 for connecting the input / output chip and the computing chip, thereby realizing communication connection between the first processing module 102 and the second processing module 103.

[0128] In this embodiment, the connection network 104 can specifically be a NOC on-chip network or a chip interconnect protocol (UCIe) module. Both are built based on the Advanced Extensible Interface (AXI) protocol and are fully compatible with the AXI transmission specification. As a dedicated data transmission link between the computing die and the input / output die, it undertakes the high-speed data interaction task between the CIM Die and the IO Die. It can efficiently and with low latency transmit the remote memory access request that conforms to the AXI protocol, which is encapsulated by the first processing module 102 in the CIM Die, to the second processing module 103 in the IO Die. This achieves a stable communication connection between the first processing module 102 and the second processing module 103, ensuring the continuity of data transmission and hardware transmission efficiency of the entire link from instruction encapsulation to Ethernet message conversion during memory semantic access, and adapting to the small data low-latency transmission requirements of scale-up supernode clusters.

[0129] In one possible embodiment, the computing chip further includes a control processor, which is communicatively connected to the first processing module 102 and is used to send configuration parameter information to the first processing module 102.

[0130] In this embodiment, the control processor is a Reduced Instruction Set Computing (RISC-V) CPU, which can provide AXI bus control capabilities and perform register configuration.

[0131] The configuration parameters in this embodiment include at least one of the following: target computing chip identifier, data packet length, and read / write type information. Specifically, the target computing chip identifier is the target GPU ID (XPU ID), which is the ID of GPU1, used to identify the target computing chip for remote memory access. The data packet length defines the number of data bytes transmitted in this remote memory access, adapting to the bandwidth requirements of small data, low-latency transmission. The read / write type information identifies whether this remote memory access is a read operation (Load) or a write operation (Store), allowing the first processing module 102 to complete the corresponding AXI transaction encapsulation configuration according to the operation type.

[0132] The format of the above configuration parameters can be customized and configured by the control processor according to the actual remote memory access requirements.

[0133] In this embodiment, the first processing module 102 is further configured to generate user field information, namely AXI.User field information, based on the configuration parameter information sent by the control processor. The user field information conforms to the user field format of the on-chip bus protocol, and the user field information includes at least one of the following: target computing chip identifier, data packet length, and read / write type information.

[0134] In one possible embodiment, such as Figure 2 As shown, the first processing module 102 is located inside the computing unit 101. This is the first deployment method of the first processing module 102 provided in this embodiment of the application, which realizes the nearby deployment of memory semantic access related modules, shortens the transmission path of instructions and requests, and reduces the internal data interaction latency. The first processing module 102 inside the computing unit 101 receives configuration parameter information sent by the control processor, generates user field information based on the configuration parameter information, and sends it to the bus controller 106.

[0135] In this embodiment, the first processing module 102 includes a bus extension register, which is communicatively connected to the control processor and is used to set the user field information according to the configuration operation of the control processor.

[0136] like Figure 2 As shown, the computing unit 101 also includes a memory management unit (MMU) 105, a bus controller 106, and an on-chip bus 107.

[0137] Among them, the memory management unit 105, which is Figure 2 The Memory Management Unit (MMU) in the MMU is used to determine whether the read / write instruction is a remote access request. It is responsible for address identification and request classification. Specifically, the MMU 105 parses and identifies the access address of the Load / Store read / write instruction issued by the Computing Unit 101. Based on the Unified Physical Address (UPA) space defined in this application, it accurately determines whether the access address corresponding to the read / write instruction is a local memory address or a memory address of a remote target device, and then classifies the read / write instruction into a local access request or a remote access request. If the MMU 105 determines that the read / write instruction is a remote access request, it forwards the request to the Bus Controller 106 or the First Processing Module 102, where the Bus Controller 106 or the First Processing Module 102 performs subsequent encapsulation and forwarding.

[0138] In this embodiment, the bus controller 106 is the Advanced eXtensible Interface Control Register (AXI Ctrl Reg), which is responsible for receiving remote access requests determined by the memory management unit 105. At the same time, it receives user field information, namely AXI.User field information, generated by the bus extension register based on the control processor configuration parameters. In accordance with the Advanced eXtensible Interface (AXI) protocol specification, the two are integrated and encapsulated into a complete AXI access transaction that conforms to the on-chip transmission standard, generating a remote memory access request. After encapsulation, the remote memory access request is forwarded to the on-chip bus 107, realizing AXI transaction assembly and forwarding.

[0139] Finally, the on-chip bus 107, also known as AXI in the figure, is used to send the packaged remote memory access request to the second processing module 103 to realize inter-chip information transmission.

[0140] Figure 3 This is a system architecture of a computing chip according to an embodiment of the present disclosure. Figure 2 ,like Figure 3 As shown, the first processing module 102 is independently located outside the computing unit 101.

[0141] In this embodiment, the first processing module 102 includes a configuration register, which is used to map to the address space of the control processor via memory-mapped input / output. Correspondingly, the control processor is used to write the configuration parameter information to the mapped local address to generate the user field information, namely the AXI.User field information. The first processing module 102 is used to read the user field information from the mapped configuration register.

[0142] In one possible embodiment, the computing chip further includes a data scheduling unit. For example... Figure 3 As shown, the data scheduling unit is set on the CIM Die in the figure. It is responsible for receiving various data processing requests issued by the computing unit 101, completing data caching, forwarding and scheduling, and connecting the computing unit 101 with other hardware modules and cross-die interconnect modules in the CIM Die.

[0143] In one possible embodiment, such as Figure 3 As shown, the first processing module 102 is located inside the data scheduling unit and is independent of the computing unit 101. This is the second deployment method of the first processing module 102 provided in this application embodiment, which can make full use of the hardware resources of the data scheduling unit and optimize the hardware layout of the device.

[0144] Figure 4 This is a system architecture of a computing chip according to an embodiment of the present disclosure. Figure 3 In this embodiment, the first processing module 102 is located outside the computing unit 101 and outside the data scheduling unit. The first processing module 102 works independently from both the computing unit 101 and the data scheduling unit. This is the third deployment method of the first processing module 102 provided by this application embodiment. It can reserve an independent hardware working space for the first processing module 102, avoid resource competition with other components inside the data scheduling unit, and improve the stability and independence of the module's operation.

[0145] like Figure 3-4 As shown, the computing unit 101 includes a memory management unit 105. In this embodiment, the memory management unit 105 is also used to determine that the read / write instruction is a remote access request and forward the remote access request to the first processing module 102.

[0146] Specifically, the first processing module 102 is used to generate user field information based on configuration parameter information through memory-mapped input / output.

[0147] like Figure 3 As shown, in the second deployment mode of the first processing module 102, when the first processing module 102 is located inside the data scheduling unit, the memory management unit 105 sends the remote access request to the first processing module 102 inside the data scheduling unit. The first processing module 102 is responsible for AXI transaction assembly and forwarding, encapsulating the remote access request and user field information forwarded by the memory management unit 105 into a remote memory access request, and sending it to the on-chip network, and then to the second processing module 103.

[0148] like Figure 4 As shown, in the third deployment mode of the first processing module 102, when the first processing module 102 is located outside the data scheduling unit, the memory management unit 105 sends the remote access request to the data scheduling unit, and the data scheduling unit forwards the remote memory access request to the first processing module 102. The first processing module 102 is responsible for AXI transaction assembly and forwarding, encapsulating the remote access request and the user field information into the remote memory access request, and sending it to the on-chip network, and then to the second processing module 103.

[0149] In one possible embodiment, the first processing module 102 integrates a multi-channel direct memory access engine, which is used to split the remote memory access request into multiple sub-requests and issue the multiple sub-requests in parallel through multiple channels.

[0150] Specifically, when the first processing module 102 receives a remote memory access request for a large block of data, the multi-channel direct memory access engine can split the single large block of remote memory access request into several small data sub-requests conforming to the AXI protocol specification according to a preset data granularity. This can overcome the bandwidth limitation of single-channel transmission and send the multiple sub-requests to the second processing module 103 in parallel through multiple independent transmission channels. This achieves high-bandwidth and high-efficiency transmission for remote access to large blocks of data, making up for the bandwidth shortcomings of pure memory semantic access in large data transmission scenarios. This allows the memory semantic access device of this application to simultaneously adapt to the remote access requirements of small data with low latency and large data with high bandwidth.

[0151] The multi-channel direct memory access engine in this embodiment is configured with a dedicated register interface for configuring parameters and providing real-time feedback and notification of transmission status for the multiple channels. The transmission parameters of each transmission channel can be flexibly configured through this dedicated register interface, including channel activation and deactivation, sub-request data length for single-channel transmission, and channel transmission priority. This dedicated register interface can also collect real-time transmission status information for each channel, including sub-request transmission progress, transmission completion status, and error messages, and feed this status information back to the CPU. This enables precise control and real-time notification of the multi-channel parallel transmission process, ensuring the controllability and stability of the remote transmission of large blocks of data.

[0152] In this embodiment of the application, after receiving a remote memory access request, the second processing module 103 is further configured to extract user field information from the remote memory access request, perform queue scheduling processing on the remote memory access request based on the user field information, and encapsulate it into the Ethernet packet.

[0153] Optionally, the queue scheduling process includes enqueue, dequeue, or merging processes. The merging process is used to combine multiple remote memory access requests targeting the same computing chip and of the same read / write type into a single Ethernet packet.

[0154] Specifically, after the second processing module 103 extracts the user field information in the AXI.User field of the remote memory access request, it performs the corresponding queue scheduling processing operation on the remote memory access request based on the target computing chip identifier in the user field information.

[0155] The enqueueing process involves the second processing module 103 allocating independent hardware FIFO queues for different target computing chip identifiers. Corresponding remote memory access requests are written into dedicated queues in the order they are received, achieving hardware isolation of access requests from different target devices and avoiding cross-device request transmission chaos. The dequeueing process involves the second processing module 103 monitoring the buffer status of each hardware FIFO queue and the transmission idle status of the Ethernet MAC layer in real time. When the line-rate forwarding condition is met, the remote memory access request is retrieved from the corresponding queue according to the first-in-first-out principle and pushed to the packet encapsulation logic, matching the transmission rate characteristics of Ethernet. The merging process involves hardware aggregating multiple small-data remote memory access requests with the same target computing chip identifier, the same read / write type, and arriving consecutively into a single access request, reducing the number of subsequent Ethernet packets sent and lowering Ethernet frame header overhead and switch forwarding pressure.

[0156] After completing the queue scheduling process, the second processing module 103 encapsulates the processed remote memory access request as a payload into a message conforming to the Ethernet transmission standard, ensuring the accuracy and efficiency of the request transmission in the Ethernet, which meets the design requirements of small data and low latency transmission.

[0157] In one possible embodiment, the first processing module 102 is further configured to map the remote address in the read / write instruction to the network address of the target computing chip. The second processing module 103 is further configured to write the network address into the frame header of the Ethernet packet when encapsulating the Ethernet packet, thereby avoiding the overhead of software address translation, realizing the conversion of the instruction-level remote address to the network-level routing address, improving the encapsulation and routing efficiency of remote memory access requests, and ensuring the accurate transmission of packets in the Ethernet.

[0158] The remote address is an address in a unified global address space. This unified global address space is defined by node identifier, chip identifier, chip identifier, and address offset, which realizes a globally unique identifier for memory addresses in a large-scale computing cluster.

[0159] The first processing module 102 is also used to determine the identifier of the target computing chip based on the node identifier and chip identifier in the unified global address space, and map the identifier of the target computing chip to a network address, which not only ensures the scalability of the address space, but also provides a unified addressing basis for cross-node and cross-chip memory semantic access.

[0160] In this embodiment of the application, the second processing module 103 is further configured to receive Ethernet packets sent by other computing chips, strip the frame headers and restore them to remote memory access requests, and send them to the first processing module 102.

[0161] In this embodiment, the other computing chip is a device that needs to remotely access the memory of the memory semantic access device of this application, namely GPU2. It is also equipped with computing unit 101, first processing module 102 and second processing module 103. Therefore, it sends encapsulated Ethernet packets to the memory semantic access device for reading and writing the memory of the memory semantic access device.

[0162] The first processing module 102 is communicatively connected to the storage controller of the computing unit 101, and is used to access the storage controller to read and write data based on the second remote memory access request, and return response data to other computing chips.

[0163] Specifically, when this memory semantic access device is the accessed end, the second processing module 103 can receive Ethernet packets from other computing chips. The second processing module 103 performs a frame header stripping operation on the Ethernet packets, removes the frame header information required for Ethernet transmission, and restores the packet payload to a remote memory access request that conforms to the AXI protocol specification. This request fully carries the remote memory access instructions and related configuration information of other computing chips.

[0164] After the second processing module 103 transmits the restored remote memory access request to the first processing module 102, the first processing module 102, based on its direct communication connection with the storage controller of the computing unit 101, forwards the remote memory access request to the storage controller. The storage controller then performs the corresponding local memory read / write operation, generates the corresponding response data after completing the data reading or writing, and then sends the response data back to the first processing module 102 along the original path, thus completing the bidirectional data interaction process of memory semantic access.

[0165] After sending an Ethernet message to the target computing chip and receiving a corresponding response from the target computing chip, the second processing module 103 is further configured to receive the Ethernet response sent by the target computing chip, strip the frame header to restore it to bus response data, and send it to the first processing module 102. The first processing module 102 is further configured to send the bus response data to the computing unit 101.

[0166] Specifically, after the target computing chip 200 completes the processing of the remote memory access request and generates response data, it encapsulates the response data into an Ethernet response message conforming to the Ethernet transmission specification and transmits it back to the memory semantic access device via Ethernet. Upon receiving the Ethernet response, the second processing module 103 first performs an Ethernet frame header stripping operation to remove the frame header information added for Ethernet transmission adaptation, restoring the payload within the message to bus response data conforming to the AXI bus protocol specification. This data fully carries the memory access response result of the target computing chip.

[0167] After the second processing module 103 transmits the restored bus response data to the first processing module 102, the first processing module 102 transmits the bus response data back to the computing unit 101 that initiated this remote access step by step along the original instruction transmission path of the remote memory access, completing the end-to-end data interaction process of the entire memory semantic access, allowing the computing unit 101 to obtain the results of the remote memory access in a timely manner, realizing the efficient connection between computing instructions and communication operations, and reducing the memory access waiting time of the computing unit 101.

[0168] Figure 5 This is a system architecture of a computing chip according to an embodiment of the present disclosure. Figure 4 In one possible embodiment, the memory semantic access device in the computing chip further includes a network interface card (NIC) unit 108, a second processing module 103 is disposed in the NIC unit 108, and the NIC unit 108 further includes a remote direct memory access module 109. The second processing module 103 and the remote direct memory access module 109 are integrated in the same NIC unit 108, and the two work independently and transmit in parallel, so that the NIC unit 108 becomes a dual-function NIC that simultaneously supports RDMA message passing semantics and SUE memory semantics.

[0169] The remote direct memory access module 109 is used to process remote direct memory access transmission of the first type of data, and the second processing module 103 is used to process memory semantic access transmission of the second type of data.

[0170] The data length of the first type of data is greater than the data length of the second type of data.

[0171] In this embodiment, the network interface card unit 108 is specifically a Remote Direct Memory Access over Converged Ethernet Version 2 (RoCEv2) engine. The Remote Direct Memory Access module 109 relies on the traditional RDMA capabilities of the RoCEv2 engine to handle the remote transmission of the first type of data, which is a large block of data, such as model parameters and training datasets. By bypassing the transmission characteristics of the operating system kernel through RDMA, high-bandwidth and high-efficiency large data transmission is achieved. The second processing module 103 relies on SUE technology to handle the memory semantic access transmission of the second type of data, which is a small data, such as small messages of tens or hundreds of bytes, such as control flow synchronization and flag updates. Through the Load / Store instruction-level direct access mechanism, the RDMA software stack is bypassed to achieve ultra-low latency small data transmission.

[0172] Figure 6 This is a system architecture of a computing chip according to an embodiment of the present disclosure. Figure 5 In one possible implementation, the two types of data can be transmitted simultaneously, such as... Figure 6 As shown, the solid line represents SUE small data transmission, and the dashed line represents RDMA large data transmission. The two types of modules work independently and do not interfere with each other, and can transmit data simultaneously. The device can automatically match the corresponding transmission module and transmission mode according to the actual length of the data to be transmitted, enabling large data blocks to achieve high-bandwidth transmission through RDMA and small data to achieve low-latency access through SUE. This achieves refined utilization of network and computing resources, takes into account the transmission needs of different types of data in the Scale-up supernode cluster, effectively solves the latency bottleneck problem of the traditional single RDMA transmission mode in small packet communication scenarios, and improves the overall data transmission adaptability and efficiency of the memory semantic access device.

[0173] Specifically, the dashed section represents RDMA data transmission driven by the Cluster Communication Library (CCL) packet, which, after being issued by the Control Processor (CP), involves the following steps:

[0174] Step 1: Send the Cluster Communication Library (CCL) request to the internal Remote Direct Memory Access Interface (RDMA_IF) for processing, encapsulate it as a Work Queue Element (WQE) request, and after waiting for the data to be prepared, send the request to the RoCEv2 or C910 module for further processing.

[0175] Step 2: Synchronously send an in-memory computation packet (CIM packet) to notify the data scheduling unit (DU / DU_TS) on the CIM to prepare the data. After pushing the data to be transmitted to the transmission buffer (TX_buffer), send a notification to the synchronization engine (SyncEngine) to inform it that the data is ready.

[0176] Step 3: The Remote Direct Memory Access Interface (RDMA_IF) sends a processing notification to the RoCEv2 or C910 module, and the RDMA module in RoCEv2 in the figure is responsible for completing the final data transmission.

[0177] The solid line represents small data read / write operations driven by the CIM CU, with the data transmission ultimately handled by the SUE module in RoCEV2 shown in the diagram.

[0178] Overall Implementation of the Memory Semantic Access System of the Embodiments of this Disclosure

[0179] This disclosure proposes a memory semantic access system. Figure 7This is an architectural diagram of a memory semantic access system according to an embodiment of this disclosure. The memory semantic access system includes a first computing chip and a second computing chip 300. The first computing chip includes the memory semantic access device 100 described in any of the above-mentioned embodiments. The second computing chip 300 is communicatively connected to the first computing chip via Ethernet. The first computing chip is used to send encapsulated Ethernet packets to the second computing chip 300 to access the memory of the second computing chip 300.

[0180] The first computing chip and the second computing chip 300 are both equipped with a first processing module and a second processing module to realize low-latency transmission of small data and remote memory access.

[0181] Overall Implementation of the Memory Semantic Access Method of the Embodiments of this Disclosure

[0182] This disclosure proposes a memory semantic access method. Figure 8 This is a schematic diagram of a memory semantic access method according to an embodiment of this disclosure. Figure 1 Memory semantic access methods include:

[0183] In step S410, the first processing module located in the computing chip receives a read / write instruction for accessing remote memory initiated by the computing unit in the computing chip.

[0184] Step S420: The first processing module encapsulates the read / write instruction into a remote memory access request conforming to the on-chip bus protocol.

[0185] In step S430, the second processing module located in the input / output chip encapsulates the remote memory access request into an Ethernet message and sends it to the target computing chip via Ethernet.

[0186] In step S410, the computing unit (CU) on the computing chip (CIM) initiates a Load / Store native read / write instruction to access the target computing chip's memory. First, by controlling the processor to pre-configure the AXI.User user field information, the memory management unit parses the access address of the read / write instruction, and determines that the address is the remote memory address of the target computing chip based on the unified global address space, thus confirming that the read / write instruction is a remote memory access request.

[0187] In step S410, the user field information configuration method can be selected according to the different deployment locations of the first processing module.

[0188] In step S420, the first processing module receives the remote access request, combines it with the pre-configured AXI.User user field information, and encapsulates the two into a remote memory access request conforming to the on-chip bus protocol according to the Advanced Extensible Interface Protocol Specification, which is the complete AXI access transaction.

[0189] If the first processing module integrates a multi-channel direct memory access engine, it will also split remote memory access requests for large blocks of data into multiple sub-requests and issue them in parallel through multiple channels.

[0190] In step S420, the second processing module receives a remote memory access request transmitted via the on-chip network. First, it extracts the AXI.User user field information from the request. Based on this information, it performs queue scheduling processing such as enqueueing, dequeueing, or merging on the request. Then, it encapsulates the remote memory access request that has completed the scheduling processing into an Ethernet packet that conforms to the Ethernet transmission standard. Finally, it sends the packet to the target computing chip via Ethernet.

[0191] Figure 9 This is a schematic diagram of a memory semantic access method according to an embodiment of this disclosure. Figure 2 This paper uses an end-to-end (GPU0 to GPU1) read operation as an example to illustrate the entire process of data request and response. The first processing module is deployed in the second manner, as shown below. Figure 8 As shown, the solid line represents the data request process, and the dashed line represents the data response process. The specific steps are as follows:

[0192] The first step is to pre-configure the AXI.User field. Before initiating a Load / Store remote memory access, the CIM Kernel completes the configuration of the AXI.User field. The address space of this field is mapped by the first processing module (SUE_Manager) to the address space of the compute unit (CU) / control processor (Risc-V CPU) through memory-mapped input / output (MMIO). The configuration information includes core content such as the target compute chip identifier, read / write type, and data transfer length.

[0193] In the second step, the computing unit (CU) on the CIM Die of GPU0 executes the Load / Store instruction to access the pre-configured address segment. The memory management unit (MMU) parses the access address and determines it to be the memory address of the remote destination GPU1 based on the Unified Global Address Space (UPA). Then, the remote memory access request is sent to the data scheduling unit (DU / DU_TS) of the CIM Die, and DU / DU_TS forwards it to the SUE_Manager module.

[0194] Third, SUE_Manager directly manages the flow of data reception and transmission through the ready / valid handshake signals of the AXI protocol. It can also temporarily cache AXI transactions using a first-in-first-out (FIFO) queue according to hardware deployment requirements to adapt to scenarios with multiple concurrent transmission requests.

[0195] The fourth step is for SUE_Manager to encapsulate the memory access request initiated by CIM CU, extract the read / write request sent from Risc-VCPU / CIM Kernel, add AXI USER bit fields (AWUSER, BUSER, ARUSER, RUSER) to it, combine the request information with the configuration information into a new AXI transaction that conforms to the AXI protocol specification, and then send it from the corresponding AXI transport channel.

[0196] In the fifth step, SUE_Manager will transmit the encapsulated AXI transaction from the CIM Die to the second processing module (SUE module) within the RoCEv2 engine in the IO Die via the on-chip network (NOC).

[0197] In the sixth step, after the SUE module in the RoCEv2 engine of IO Die receives the AXI transaction, it extracts and parses various information from the AXI.User field. Then, based on the destination GPU ID in the field, it performs scheduling operations such as enqueuing, dequeuing, or merging on the AXI access transaction.

[0198] In the seventh step, the SUE module takes the AXI access request that has completed the scheduling and processing as the payload and sends it to the Ethernet Media Access Control (MAC) layer for data sorting. The MAC layer adds an Ethernet frame header to the payload according to the Ethernet transmission standard and actual application requirements to complete the message encapsulation. During the encapsulation process, the XPU_ID is mapped to the MAC address to provide a basis for routing.

[0199] Step 8: The encapsulated Ethernet packet is sent to the Ethernet via the network card port of local GPU0. The Ethernet switch accurately forwards the packet according to the address information in the packet and finally transmits it to the destination GPU1.

[0200] In the ninth step, after the network interface card of the target GPU1 receives the Ethernet packet, it strips the Ethernet frame header and sends the packet payload to the SUE module in the RoCEv2 engine of its own IO Die. The SUE module continues to parse the payload, restores the AXI access transaction that conforms to the AXI protocol specification, that is, the read request, and submits the transaction to the SUE_Manager of the target GPU1 through the NOC of the IO Die.

[0201] Step 10: The SUE_Manage of the target GPU1 processes the received AXI read request. Based on the direct communication connection with the storage controller (DDR / HBM Controller), it accesses the storage controller and performs a read operation on the local physical memory. After reading the specified data, it generates response data, which will be sent back to the request source GPU0 along the original access path.

[0202] In the eleventh step, the response data generated by the target GPU1 is transmitted to the SUE module in the RoCEv2 engine of its IO Die. The module encapsulates the response data into an Ethernet message and sends it to the local GPU0 at the request source via Ethernet.

[0203] Step 12: After the local GPU0 at the request source receives the Ethernet packet carrying the response data, the SUE module in the RoCEv2 engine of the IO Die strips the Ethernet frame header, restores the packet payload to AXI response data conforming to the AXI protocol specification, and returns the data to the SUE_Manager of the local GPU0.

[0204] In step thirteen, the SUE_Manager of local GPU0 will send the received AXI response data back to the DU / DU_TS of CIM Die in sequence, and then the DU / DU_TS will push the response data to the CIM CU that initiated this remote access.

[0205] Finally, the Load / Store remote memory access request initiated by the CIM CU of local GPU0 was completed, achieving end-to-end memory semantic access.

[0206] The memory semantic access device proposed in this disclosure adds a first processing module to the device, which directly interfaces with read and write instructions initiated by the computing unit to access remote memory. It encapsulates the read and write instructions into remote memory access requests, allowing the native read and write instructions initiated by the computing unit to be directly converted into remote memory access requests. This solves the technical problem that traditional RDMA cannot directly respond to the processor's native read and write instructions and simplifies the instruction triggering logic for remote memory access. The second processing module completes Ethernet packet encapsulation based on the request and sends it to the target computing chip, realizing direct hardware encapsulation of read and write instructions. It eliminates the need for instruction conversion, queue scheduling, and other operations in the software stack of traditional RDMA, significantly reducing the number of software and hardware interaction links, significantly reducing the end-to-end latency of small packet communication, and adapting to the high-frequency small packet communication scenarios of GPU clusters.

[0207] Furthermore, by setting up a connection network to realize the communication connection between the computing core and the input / output core, a dedicated and stable transmission link is provided for the remote memory access request after the read and write instructions are encapsulated. This ensures the efficient and interference-free transmission of the request data between modules, ensures the continuity of the memory semantic access link, and lays a reliable transmission foundation for subsequent Ethernet packet encapsulation and transmission.

[0208] Furthermore, by adding a control processor to the computing chip and connecting it to the first processing module, flexible configuration and precise control of remote memory access are achieved. The control processor can send configuration parameters, including the target computing chip identifier, data packet length, and read / write type, to the first processing module, enabling the device to adapt to the needs of different target chips, different data lengths, and different read / write scenarios, thus improving the versatility and scenario adaptability of the memory semantic access device.

[0209] Furthermore, the first processing module generates user field information conforming to the on-chip bus protocol format based on the configuration parameters, achieving seamless integration between the configuration information and the on-chip transmission protocol. The user fields directly carry core information such as the target computing chip identifier, data packet length, and read / write type, ensuring the integrity and standardization of the configuration information during on-chip transmission and guaranteeing the efficiency and reliability of remote memory access requests during on-chip transmission.

[0210] Furthermore, by placing the first processing module inside the computing unit and implementing user field configuration through the bus extension register, deep coupling between the configuration logic and the computing unit is achieved. The bus extension register communicates directly with the control processor, enabling rapid response to user field configuration operations and reducing the transmission path and latency of configuration information. At the same time, integrating the first processing module inside the computing unit facilitates the direct acquisition of configured user field information after the computing unit initiates read / write commands, improving the response speed of remote access request encapsulation and optimizing the link efficiency from command initiation to request encapsulation.

[0211] Furthermore, the memory management unit accurately determines that the read / write command is a remote access request, avoiding confusion between local and remote access; the bus controller encapsulates the remote access request and user field information into a remote memory access request conforming to the on-chip bus specification, ensuring the standardization of the request format; the on-chip bus, as an efficient transmission carrier, directs the encapsulated request to the second processing module. The three work together to realize the hardware-based processing of the entire process of remote memory access request from identification to on-chip transmission, improving access efficiency and stability.

[0212] Furthermore, an independent deployment scheme is provided for the first processing module, located outside the computing unit, enhancing the hardware architecture flexibility of the device. This avoids strong coupling between the first processing module and the computing unit, facilitating adjustments to the module layout based on different hardware resources and performance requirements, adapting to scenarios with limited computing unit resources, and improving the scalability and hardware adaptability of the memory semantic access device.

[0213] Furthermore, by mapping the configuration registers to the control processor's address space using memory-mapped input / output, the control processor can conveniently read and write user field information and manage it efficiently. The control processor can write configuration parameters through its local address, while the first processing module can directly read the mapped configuration registers to obtain user fields, eliminating the need for complex communication protocols and simplifying the configuration process.

[0214] Furthermore, combining the first processing module with the data scheduling unit provides two flexible deployment modes, one internal and one external, further enhancing the adaptability of the hardware architecture. When the first processing module is located inside the data scheduling unit, the request forwarding path can be reduced, improving encapsulation efficiency; when located externally, the hardware complexity of the data scheduling unit can be reduced, facilitating independent module optimization. Both modes can adapt to different performance and resource constraint scenarios, enabling the device to ensure functional integrity while balancing hardware implementation flexibility and efficiency.

[0215] Furthermore, regardless of whether the first processing module is located inside or outside the data scheduling unit, the memory management unit can accurately direct the transmission of remote access requests. The first processing module then encapsulates the request and user fields and sends them to the second processing module. This ensures the uniformity of functions and optimizes the transmission path according to the deployment mode, avoiding redundant overhead of request forwarding and improving the processing efficiency of remote memory access requests.

[0216] Furthermore, by integrating a multi-channel direct memory access engine into the first processing module, high-bandwidth parallel transmission of large blocks of data for remote access is achieved. A single large block of remote memory access request can be split into multiple sub-requests. Through multi-channel parallel transmission, the bandwidth bottleneck of single-channel transmission is broken through, and the efficiency of large data transmission is greatly improved. At the same time, the dedicated register interface supports channel parameter configuration and real-time feedback of transmission status, enabling the control processor to accurately manage the multi-channel transmission process and ensuring the stability and controllability of large blocks of data for remote access.

[0217] Furthermore, through queue scheduling in the second processing module, efficient routing and packet optimization of remote memory access requests are achieved. Enqueueing and dequeueing based on user field information enables hardware isolation of requests from different target computing chips, avoiding cross-device request chaos. Merging processing aggregates small requests of the same target and type into a single Ethernet packet, reducing frame header overhead and network forwarding pressure, improving the transmission efficiency of small data remote access, while simultaneously considering request isolation and bandwidth optimization.

[0218] Furthermore, the second processing module and the remote direct memory access module are integrated into the same network interface card (NIC) unit, constructing a dual-function NIC architecture that enables fine-grained adaptation to the transmission requirements of different data types. The remote direct memory access module is responsible for high-bandwidth transmission of large data blocks, while the second processing module is responsible for low-latency memory semantic access of small data. The two work independently and transmit in parallel, which not only fully utilizes NIC hardware resources but also solves the latency bottleneck problem of traditional single RDMA mode in small packet transmission scenarios, improving the overall data transmission efficiency and scenario adaptability of the device.

[0219] Furthermore, through the tag allocation unit and response matching unit, accurate routing and response matching of multiple concurrent remote memory access requests are achieved. The tag allocation unit assigns a unique identifier to each request, ensuring a one-to-one correspondence between requests and responses; the response matching unit routes the response data to the computation unit that initiated the request based on the identifier, avoiding response confusion and data corruption in multi-request concurrent scenarios, and ensuring the concurrent reliability and data integrity of memory semantic access.

[0220] Furthermore, the next instruction can be processed without waiting for a response after a request is issued, which greatly improves the instruction throughput and resource utilization of the computing unit. At the same time, by receiving response data through interrupt or polling, the real-time response is guaranteed and the blocking waiting of the computing unit is avoided, thus optimizing the parallelism of instruction execution and memory access operations.

[0221] Furthermore, a hardware-based mapping from remote addresses to network addresses is implemented. The first processing module directly converts the remote address in the read / write instruction into the network address of the target computing chip, while the second processing module writes the address into the Ethernet frame header. This avoids the overhead of software address translation and achieves seamless connection from instruction-level remote addresses to network-level routing addresses. It improves the encapsulation and routing efficiency of remote memory access requests and ensures accurate transmission of packets in the Ethernet.

[0222] Furthermore, by defining remote addresses based on a unified global address space, and using node identifiers, chip identifiers, chip identifiers, and address offsets for joint location, a globally unique identifier for memory addresses in large-scale computing clusters is achieved. The first processing module can accurately map network addresses based on node and chip identifiers in the unified global address space, ensuring both the scalability of the address space and providing a unified addressing basis for cross-node and cross-chip memory semantic access.

[0223] Furthermore, when acting as the accessed end, the second processing module can receive and parse Ethernet packets from other computing chips, restore them to remote access requests, and then the first processing module directly accesses the storage controller to complete read and write operations and return a response. This realizes bidirectional data interaction for memory semantic access, builds a complete end-to-end remote memory access ecosystem, and enables the device to act as both a request initiator and a target server.

[0224] Furthermore, after the second processing module receives the Ethernet response from the target computing chip, it strips the frame header and restores it to the bus response data. The first processing module then accurately routes it to the computing unit that initiated the request, completing a complete closed loop from request to response reception. This ensures the continuity and reliability of end-to-end memory semantic access, enabling the computing unit to obtain remote access results in a timely manner and reducing memory access waiting time.

[0225] Furthermore, by connecting the first and second computing chips via Ethernet, remote memory access across chips is achieved without relying on the traditional RDMA software stack, significantly reducing the latency and overhead of cross-chip memory access. At the same time, the system is compatible with general Ethernet infrastructure, facilitating deployment and expansion, and providing an efficient and flexible cross-chip memory access solution for large-scale AI computing clusters.

[0226] This disclosure also provides an electronic device 500, including:

[0227] At least one processor, and,

[0228] A memory that is communicatively connected to at least one processor; wherein,

[0229] The memory stores instructions that are executed by at least one processor to cause the at least one processor to perform the method as described in any of the above embodiments of this application when executing the instructions.

[0230] The following is combined with Figure 5 The hardware structure of the electronic device is described in detail. The electronic device includes: a processor 510, a memory 520, an input / output interface 530, a communication interface 540, and a bus 550.

[0231] The processor 510 can be implemented using a general-purpose central processing unit (CPU), microprocessor, application specific integrated circuit (ASIC), or one or more integrated circuits, and is used to execute relevant programs to implement the technical solutions provided in the embodiments of this disclosure.

[0232] The memory 520 can be implemented as a read-only memory (ROM), a static storage device, a dynamic storage device, or a random access memory (RAM). The memory 520 can store the operating system and other applications. When the technical solutions provided in the embodiments of this specification are implemented through software or firmware, the relevant program code is stored in the memory 520 and is called and executed by the processor 510 using the memory semantic access method of the embodiments of this disclosure.

[0233] The input / output interface 530 is used to implement information input and output;

[0234] The communication interface 540 is used to enable communication and interaction between this device and other devices. Communication can be achieved via wired means (e.g., USB, Ethernet cable) or wireless means (e.g., mobile network, Wi-Fi, Bluetooth).

[0235] Bus 550 transmits information between various components of the device (e.g., processor 510, memory 520, input / output interface 530, and communication interface 540);

[0236] The processor 510, memory 520, input / output interface 530 and communication interface 540 are connected to each other within the device via bus 550.

[0237] This application also provides a computer-readable storage medium that stores one or more programs, which can be executed by one or more processors to implement the memory semantic access method of the above embodiments, which will not be described again here.

[0238] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in this disclosure and the foregoing drawings are used to distinguish similar objects and are not necessarily used to describe a particular order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this disclosure described herein can be implemented, for example, in orders other than those illustrated or described herein. Furthermore, the terms “comprising” and “including,” and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that includes a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatuses.

[0239] It should be understood that in this disclosure, "at least one item" means one or more, and "more than one" means two or more. "And / or" is used to describe the relationship between related objects, indicating that three relationships can exist. For example, "A and / or B" can represent three cases: only A exists, only B exists, and both A and B exist simultaneously, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c can represent: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, and c can be single or multiple.

[0240] It should be understood that in the description of the embodiments of this disclosure, "multiple" means two or more, "greater than", "less than", "exceeding" etc. are understood to exclude the number itself, and "above", "below", "within" etc. are understood to include the number itself.

[0241] In the several embodiments provided in this disclosure, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces, indirect coupling or communication connection between apparatuses or units, and may be electrical, mechanical, or other forms.

[0242] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0243] Furthermore, the functional units in the various embodiments of this disclosure can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0244] It should also be understood that the various implementation methods provided in this disclosure can be combined arbitrarily to achieve different technical effects.

[0245] The above is a detailed description of the embodiments of this disclosure. However, this disclosure is not limited to the above embodiments. Those skilled in the art can make various equivalent modifications or substitutions without departing from the spirit of this disclosure. All such equivalent modifications or substitutions are included within the scope defined by the claims of this disclosure.

Claims

1. A memory semantic access device, characterized in that, Used in computing chips, including: The first processing module, located in the computing chip, is used to receive read and write instructions for accessing remote memory initiated by the computing unit in the computing chip, and to encapsulate the read and write instructions into a remote memory access request that conforms to the on-chip bus protocol. The second processing module, located in the input / output chip and communicatively connected to the first processing module, is used to encapsulate the remote memory access request into an Ethernet message and send it to the target computing chip via Ethernet.

2. The memory semantic access device according to claim 1, characterized in that, It also includes a connectivity network for communicating between the computing chip and the input / output chip, the connectivity network including chip-to-chip interconnect protocol interfaces or on-chip networks.

3. The memory semantic access device according to claim 1, characterized in that, The computing core also includes: At least one computing unit A control processor, communicatively connected to the first processing module, is used to send configuration parameter information to the first processing module; wherein the configuration parameter information includes at least one of the target computing chip identifier, data packet length, and read / write type information.

4. The memory semantic access device according to claim 3, characterized in that, The first processing module is further configured to generate user field information based on the configuration parameter information sent by the control processor. The user field information is in a user field format that conforms to the on-chip bus protocol, and the user field information includes at least one of the target computing chip identifier, data packet length, and read / write type information.

5. The memory semantic access device according to claim 4, characterized in that, The first processing module is disposed inside the computing unit, and the first processing module includes: The bus extension register, which is communicatively connected to the control processor, is used to set the user field information according to the configuration operation of the control processor.

6. The memory semantic access device according to claim 5, characterized in that, The computing unit includes: The memory management unit is used to determine that the read / write instruction is a remote access request; A bus controller is used to acquire the remote access request and the user field information, and encapsulate the remote access request and the user field information into the remote memory access request; An on-chip bus is used to send the remote memory access request to the second processing module.

7. The memory semantic access device according to claim 3, characterized in that, The first processing module is set up independently outside the computing unit.

8. The memory semantic access device according to claim 7, characterized in that, The first processing module includes: Configuration registers are used to map to the address space of the control processor via memory-mapped input / output. The control processor is used to write the configuration parameter information into the mapped local address and generate the user field information; The first processing module is used to read the user field information in the mapped configuration register.

9. The memory semantic access device according to claim 8, characterized in that, The computing chip also includes a data scheduling unit, and the first processing module is located inside or outside the data scheduling unit.

10. The memory semantic access device according to claim 9, characterized in that, The computing unit includes: The memory management unit is used to determine that the read / write instruction is a remote access request; When the first processing module is located inside the data scheduling unit, the memory management unit sends the remote access request to the first processing module inside the data scheduling unit. When the first processing module is located outside the data scheduling unit, the memory management unit sends the remote access request to the data scheduling unit, and the data scheduling unit forwards the remote access request to the first processing module. The first processing module is used to encapsulate the remote access request and the user field information into a remote memory access request and send it to the second processing module.

11. The memory semantic access device according to claim 1, characterized in that, The first processing module integrates a multi-channel direct memory access engine, which is used to split the remote memory access request into multiple sub-requests and issue the multiple sub-requests in parallel through multiple channels; The multi-channel direct memory access engine is equipped with a dedicated register interface for real-time feedback and notification of parameter configuration and transmission status of the multiple channels.

12. The memory semantic access device according to claim 1, characterized in that, The second processing module is also used to extract user field information from the remote memory access request, perform queue scheduling processing on the remote memory access request based on the user field information, and encapsulate it into the Ethernet packet; The queue scheduling process includes enqueueing, dequeueing, or merging processes; the merging process is used to merge multiple remote memory access requests with the same target computing chip and the same read / write type into a single Ethernet packet.

13. The memory semantic access device according to claim 1, characterized in that, It also includes a network interface card (NIC) unit, in which the second processing module is disposed. The network interface card (NIC) unit further includes a remote direct memory access module, which is integrated with the second processing module in the same NIC unit, and the two work independently and transmit in parallel. The remote direct memory access module is used to process remote direct memory access transmission of the first type of data, and the second processing module is used to process memory semantic access transmission of the second type of data. The data length of the first type of data is greater than the data length of the second type of data.

14. The memory semantic access device according to claim 1, characterized in that, The first processing module further includes: A tag allocation unit is used to assign a unique identifier to each remote memory access request and encapsulate the unique identifier into the remote memory access request; The response matching unit is used to route the response data to the computing unit that initiated the read / write command based on the unique identifier carried in the response message.

15. The memory semantic access device according to claim 1, characterized in that, The first processing module is also used to perform remote memory access asynchronously. After issuing the remote memory access request, it can receive and process the next read / write instruction without waiting for a response, and receive response data through interrupt or polling.

16. The memory semantic access device according to claim 1, characterized in that, The first processing module is also used to map the remote address in the read / write instruction to the network address of the target computing chip; The second processing module is also used to write the network address into the frame header of the Ethernet packet when encapsulating the Ethernet packet.

17. The memory semantic access device according to claim 16, characterized in that, The remote address is an address in a unified global address space, which is defined by node identifier, chip identifier, chip identifier, and address offset. The first processing module is further configured to determine the identifier of the target computing chip based on the node identifier and chip identifier in the unified global address space, and map the identifier of the target computing chip to the network address.

18. The memory semantic access device according to claim 1, characterized in that, The second processing module is also used to receive Ethernet packets sent by other computing chips, strip the frame headers to restore them to remote memory access requests, and send them to the first processing module. The first processing module is communicatively connected to the storage controller of the computing chip, and is used to access the storage controller to read and write data according to the remote memory access request, and return response data to the other computing chips.

19. The memory semantic access device according to claim 1, characterized in that, The second processing module is also used to receive the Ethernet response sent by the target computing chip, strip the frame header and restore it to bus response data, and send it to the first processing module; The first processing module is also used to send the bus response data to the computing unit that initiated the read / write command.

20. A memory semantic access system, characterized in that, include: The first computing chip includes a memory semantic access device as described in any one of claims 1 to 19; The second computing chip is connected to the first computing chip via Ethernet. The first computing chip is used to send encapsulated Ethernet packets to the second computing chip to access the memory of the second computing chip.

21. A memory semantic access method, characterized in that, Used in computing chips, including: The first processing module located in the computing chip receives read and write instructions for accessing remote memory initiated by the computing unit in the computing chip; The first processing module encapsulates the read / write instructions into a remote memory access request conforming to the on-chip bus protocol; The second processing module located in the input / output chip encapsulates the remote memory access request into an Ethernet message and sends it to the target computing chip via Ethernet.

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