Cross-architecture big data service integration method and system based on xinchuang heterogeneous cooperation

Abstract

The application relates to the technical field of cross-architecture big data integration, and proposes a cross-architecture big data service integration method and system based on Xinhua heterogeneous cooperation, which comprises the following steps: taking a numerical field value as an operation number, performing a floating point operation in a source environment and a reference environment respectively, capturing an exception flag bit set and then analyzing the exception flag bit set into a semantic label group to identify a difference semantic dimension; selecting a compensation operation from a compensation strategy library to construct a mapping rule, converting sample data records which are not involved in the construction into candidate target records, performing a floating point operation after injecting a verification environment, capturing a new exception flag bit set and then analyzing the new exception flag bit set into a verification semantic label group; if there is a residual difference between the verification semantic label group and the semantic label group, determining a parameter correction amount according to a deterministic mapping relationship, single-time correcting the mapping rule to obtain a final mapping rule, converting residual data records in the source environment into target data records, and writing the target data records into a target data sink. The application can improve the efficiency of cross-architecture big data service integration.

Description

Technical Field

[0001] This invention relates to the field of cross-architecture big data integration technology, and in particular to a cross-architecture big data service integration method and system based on domestically developed heterogeneous collaboration. Background Technology

[0002] Driven by the information technology innovation industry, data centers and big data platforms generally face heterogeneous environments with mixed deployments of multiple instruction set architectures. Cross-architecture big data integration requires the complete and accurate migration of numerical data fields from the source architecture to the target architecture for unified computation and analysis by upper-layer applications. However, floating-point execution units of different instruction set architectures have deep differences in hardware state machine design, exception triggering conditions, and flag encoding methods. Even when executing logically equivalent floating-point instructions, the same numerical operand may produce different exception flag outputs under different architectures. This underlying semantic inconsistency causes the floating-point operation behavior of the data record at the target end to deviate from the expected semantics of the source end after migration, resulting in accuracy deviations or computational anomalies in big data services that rely on numerical computation, such as report generation and statistical analysis. Existing integration solutions typically rely on manual comparison of manuals or repeated trial and error to adjust conversion parameters, making it difficult to systematically capture and eliminate cross-architecture semantic deviations. The automation and reliability of the integration process are significantly insufficient.

[0003] Existing cross-architecture data migration tools mostly use fixed mapping tables or rule bases to convert field types and numerical formats. These mapping rules lack dynamic awareness of the state machine transition conditions within floating-point execution units, failing to cover subtle differences in anomaly handling paths across different architectures. When migrating data involves a large number of high-precision floating-point fields, fixed conversion rules struggle to adaptively compensate for the state machine behavior offsets specific to the target architecture. This results in the converted data records repeatedly triggering unexpected anomaly flags during verification at the target end, requiring multiple rounds of manual intervention and rule correction. This serial process of repeated verification and correction significantly increases the time consumption of large-scale data integration tasks. Therefore, improving the automation and reliability of cross-architecture big data service integration has become an urgent problem to be solved. Summary of the Invention

[0004] This invention provides a method and system for cross-architecture big data service integration based on domestically developed heterogeneous collaboration, in order to solve the problems mentioned in the background art.

[0005] To achieve the above objectives, the present invention provides a cross-architecture big data service integration method based on heterogeneous collaboration in domestic IT innovation, comprising: Using the numeric field values ​​of the first instruction set architecture as operands, floating-point operations are performed in the source environment and the reference environment of the second instruction set architecture, respectively. The set of exception flags is captured and then parsed into an architecture-independent semantic tag group to identify the difference semantic dimensions. Based on the difference semantic dimension, compensation operations are selected from the compensation strategy library to construct mapping rules. Then, sample data records that did not participate in the construction are converted into candidate target records. After being injected into the verification environment of the second instruction set architecture, floating-point operations are performed to capture a new set of abnormal flag bits and then parse them into a verification semantic tag group. If there are residual differences between the verification semantic tag group and the semantic tag group, the parameter correction amount is determined according to the deterministic mapping relationship, the mapping rule is corrected once to obtain the final mapping rule, the remaining data records in the source environment are converted into target data records and written into the target data sink; The compensation strategy library and the deterministic mapping relationship are both established based on the reverse analysis of the state machine jump conditions inside the floating-point execution unit of the first instruction set architecture and the second instruction set architecture.

[0006] In a preferred embodiment, the step of performing floating-point operations in the source environment and the reference environment of the second instruction set architecture, using numeric field values ​​of the first instruction set architecture as operands, includes: Send a first probe instruction to the source environment of the first instruction set architecture. The first probe instruction carries a numeric field value and a first floating-point arithmetic instruction selected from the floating-point instruction set of the first instruction set architecture, instructing the floating-point execution unit of the source environment to execute the first floating-point arithmetic instruction with the numeric field value as an operand. Read the exception flag bits in the hardware status register of the source environment, and combine the exception flag bits into an exception flag bit set according to the bit order of the exception flag bits in the hardware status register; Send a second probe instruction to a reference environment of the second instruction set architecture, the second probe instruction carrying the numeric field value and a second floating-point arithmetic instruction selected from the floating-point instruction set of the second instruction set architecture; The second floating-point arithmetic instruction is logically equivalent to the first floating-point arithmetic instruction, instructing the floating-point execution unit of the reference environment to execute the second floating-point arithmetic instruction with the numeric field value as an operand.

[0007] In a preferred embodiment, the set of captured anomaly flags is further parsed into architecture-independent semantic tag groups to identify differential semantic dimensions, including: The reference environment receives a second set of exception flags returned by the reference environment. The second set of exception flags is formed by the reference environment reading the exception flags in the hardware status register of the reference environment and combining them in bit order after the second floating-point operation instruction is executed. According to the correspondence between exception flags and exception types in the exception flag definition specification of the first instruction set architecture, each flag in the exception flag set is converted into a corresponding exception type label to obtain the first semantic label group; According to the correspondence between exception flags and exception types in the exception flag definition specification of the second instruction set architecture, each flag in the second exception flag set is converted into the corresponding exception type label to obtain the second semantic label group; The abnormal type labels under the same semantic dimension in the first semantic label group and the second semantic label group are compared dimension by dimension, and the semantic dimensions with different values ​​are determined as the differential semantic dimensions.

[0008] In a preferred embodiment, the step of selecting compensation operations from the compensation strategy library to construct mapping rules based on the differential semantic dimension, and then converting sample data records not involved in the construction into candidate target records, includes: Search the compensation strategy library for compensation operation entries that match the difference semantic dimension, and extract the operation type identifier and operation parameters recorded in the compensation operation entries; The mapping rule is generated by associating the operation type identifier and the operation parameters with the original semantic labels of the numeric field values. From the source data records of the source environment, select data records that were not used to identify the difference semantic dimension as sample data records; The numerical field values ​​in the sample data record are compensated according to the operation type identifier and operation parameters recorded in the mapping rule to obtain field values. The numerical field values ​​in the sample data record are replaced with the field values ​​to form candidate target records.

[0009] In a preferred embodiment, performing floating-point operations after injecting the verification environment of the second instruction set architecture includes: The candidate target record is sent to the verification environment of the second instruction set architecture, and a verification probe instruction is sent to the verification environment. The verification probe instruction carries the field value and a verification floating-point operation instruction selected from the floating-point instruction set of the second instruction set architecture. The verification probe instruction instructs the floating-point execution unit of the verification environment to execute the verification floating-point operation instruction with the field value as an operand. The verification floating-point operation instruction is logically equivalent to the second floating-point operation instruction.

[0010] In a preferred embodiment, the step of capturing a new set of anomaly flags and then parsing it into a set of verification semantic tags includes: Read the exception flag bits in the hardware status register of the verification environment, and combine the exception flag bits into a new set of exception flag bits according to their bit order in the hardware status register. Based on the correspondence between exception flags and exception types recorded in the exception flag definition specification of the second instruction set architecture, each flag in the exception flag set is mapped to the corresponding exception type label to obtain a verification semantic label group.

[0011] In a preferred embodiment, if there is a residual difference between the verification semantic tag group and the semantic tag group, then determining the parameter correction amount based on the deterministic mapping relationship, and obtaining the final mapping rule by correcting the mapping rule once, includes: The verification semantic label group is compared dimension by dimension with the anomaly type label in the same semantic dimension. If there are at least one semantic dimension with different values ​​for the anomaly type label, it is determined that there is a residual difference, and the semantic dimension with different values ​​for the anomaly type label is determined as the residual difference dimension. In the deterministic mapping relationship, find the correction entry that matches the residual difference dimension, extract the parameter correction type and correction step size recorded in the correction entry, and form the parameter correction amount; The parameter correction amount is applied to the operation parameters of the mapping rule, and the operation parameters are adjusted according to the parameter correction type and the correction step size to obtain the corrected operation parameters. The operation parameters of the mapping rule are then replaced with the corrected operation parameters to form the final mapping rule.

[0012] In a preferred embodiment, the step of converting the remaining data records in the source environment into target data records and writing them into the target data sink includes: Obtain the remaining data records in the source environment other than the sample data records, and extract the value of each numeric field and the corresponding original semantic label from the remaining data records; Based on the original semantic label, the corresponding operation type identifier and the corrected operation parameter are retrieved in the final mapping rule, and a compensation operation is performed on the numeric field value corresponding to the original semantic label in the remaining data record to generate the target field value. The target field values ​​are combined according to the original arrangement order of the fields in the remaining data records to form the target data record. A data write request is sent to the target data assembly of the second instruction set architecture to write the target data record into the storage area of ​​the target data assembly.

[0013] In a preferred embodiment, both the compensation strategy library and the deterministic mapping relationship are established based on the reverse analysis of the state machine transition conditions within the floating-point execution unit of the first instruction set architecture and the second instruction set architecture, including: Logically compare the internal state machine transition conditions of the first instruction set architecture and the internal state machine transition conditions of the second instruction set architecture to establish a correspondence between the exception flag bits of the first instruction set architecture and the second instruction set architecture under the same semantic dimension. Based on the correspondence, compensation operation entries for the difference semantic dimension and compensation operation in the compensation strategy library, as well as correction entries for the residual difference dimension and parameter correction amount in the deterministic mapping relationship, are constructed.

[0014] To address the aforementioned problems, this invention also provides a cross-architecture big data service integration system based on heterogeneous collaboration in the field of information technology innovation, the system comprising: The differential semantic dimension identification module is used to perform floating-point operations in the source environment and the reference environment of the second instruction set architecture with the numerical field value of the first instruction set architecture as the operand, capture the set of exception flags and then parse them into an architecture-independent semantic tag group to identify the differential semantic dimension. The mapping rule construction and verification module is used to select compensation operations from the compensation strategy library to construct mapping rules based on the difference semantic dimension, then convert the sample data records that did not participate in the construction into candidate target records, inject them into the verification environment of the second instruction set architecture, perform floating-point operations, capture a new set of abnormal flag bits, and then parse them into a verification semantic tag group. The residual correction and conversion module is used to determine the parameter correction amount based on the deterministic mapping relationship if there is a residual difference between the verification semantic label group and the semantic label group, correct the mapping rule in one step to obtain the final mapping rule, convert the remaining data records in the source environment into target data records, and write them into the target data sink. The compensation strategy reverse analysis module, used for the compensation strategy library and the deterministic mapping relationship, is established based on the reverse analysis of the state machine jump conditions inside the floating-point execution unit of the first instruction set architecture and the second instruction set architecture.

[0015] Compared with the prior art, the present invention has the following beneficial effects: 1. This invention achieves automated and accurate identification of differences by transforming the underlying semantic differences of cross-architecture floating-point operations into architecture-independent semantic tag sets for comparison. The method executes floating-point operations in both the source and reference environments and captures anomaly flags. These are then parsed into unified semantic tag sets for dimension-by-dimensional comparison, accurately locating semantic deviations in the floating-point execution unit state machine behavior across different instruction set architectures. Based on this, a compensation strategy library established through reverse analysis automatically selects matching compensation operations to construct mapping rules. The effectiveness of these mapping rules is verified through a closed-loop feedback mechanism in the verification environment, creating an automated closed loop for the entire difference discovery and compensation rule generation process. This mechanism fundamentally reduces reliance on manual manual comparisons and repeated trial and error, significantly improving the automation and intelligence of cross-architecture big data integration processes, enabling integration operations to adaptively address deep semantic differences between different instruction set architectures.

[0016] 2. This invention further introduces a single-step correction mechanism for residual differences. When residual differences still exist between the verification semantic tag group and the source semantic tag group, the parameter correction amount is directly determined based on the deterministic mapping relationship, and the mapping rule is corrected in one step, avoiding the process repetition and delay caused by multiple iterations of verification. By solidifying the reverse analysis results of the state machine jump conditions inside the floating-point execution unit into the deterministic mapping relationship, the correction operation has a clear theoretical basis and directionality, and can achieve the semantic consistency state of the target architecture after a single round of adjustment. At the same time, this correction mechanism only acts on the operation parameter level of the mapping rule, without affecting the original arrangement order and overall structure of the fields in the data record, ensuring the integrity and consistency of the data during the conversion process. Finally, this method converts the remaining data records in the source environment into target data records that meet the semantic requirements of the target architecture in one go and writes them into the target data sink, effectively improving the processing efficiency of cross-architecture big data integration tasks and reliably improving the timeliness of downstream service acquisition. Attached Figure Description

[0017] Figure 1 This is a flowchart illustrating a cross-architecture big data service integration method based on heterogeneous collaboration in information technology innovation, as provided in an embodiment of the present invention. Figure 2 This is a functional module diagram of a cross-architecture big data service integration system based on heterogeneous collaboration in information technology innovation, provided in an embodiment of the present invention.

[0018] The realization of the objective, functional features and advantages of the present invention will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0019] It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0020] This application provides a method for integrating cross-architecture big data services based on heterogeneous collaboration in the context of domestic IT innovation. The execution entity of this method includes, but is not limited to, at least one of the following electronic devices that can be configured to execute the method provided in this application: a server, a terminal, etc. In other words, the method for integrating cross-architecture big data services based on heterogeneous collaboration in the context of domestic IT innovation can be executed by software or hardware installed on a terminal device or a server device. The server includes, but is not limited to, a single server, a server cluster, a cloud server, or a cluster of cloud servers. The server can be an independent server or a cloud server that provides basic cloud computing services such as cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communication, middleware services, domain name services, security services, content delivery networks (CDN), and big data and artificial intelligence platforms.

[0021] Reference Figure 1 The diagram shown is a flowchart illustrating a cross-architecture big data service integration method based on heterogeneous collaboration in domestic IT innovation, according to an embodiment of the present invention. In this embodiment, the cross-architecture big data service integration method based on heterogeneous collaboration in domestic IT innovation includes: Using the numeric field values ​​of the first instruction set architecture as operands, floating-point operations are performed in the source environment and the reference environment of the second instruction set architecture, respectively. The set of exception flags is captured and then parsed into an architecture-independent semantic tag group to identify the difference semantic dimensions. In this embodiment of the invention, the step of performing floating-point operations in the source environment and the reference environment of the second instruction set architecture, using the numeric field value of the first instruction set architecture as an operand, includes: Send a first probe instruction to the source environment of the first instruction set architecture. The first probe instruction carries a numeric field value and a first floating-point arithmetic instruction selected from the floating-point instruction set of the first instruction set architecture, instructing the floating-point execution unit of the source environment to execute the first floating-point arithmetic instruction with the numeric field value as an operand. Read the exception flag bits in the hardware status register of the source environment, and combine the exception flag bits into an exception flag bit set according to the bit order of the exception flag bits in the hardware status register; Send a second probe instruction to a reference environment of the second instruction set architecture, the second probe instruction carrying the numeric field value and a second floating-point arithmetic instruction selected from the floating-point instruction set of the second instruction set architecture; The second floating-point arithmetic instruction is logically equivalent to the first floating-point arithmetic instruction, instructing the floating-point execution unit of the reference environment to execute the second floating-point arithmetic instruction with the numeric field value as an operand.

[0022] The set of captured anomaly flags is then parsed into architecture-independent semantic tag groups to identify differential semantic dimensions, including: The reference environment receives a second set of exception flags returned by the reference environment. The second set of exception flags is formed by the reference environment reading the exception flags in the hardware status register of the reference environment and combining them in bit order after the second floating-point operation instruction is executed. According to the correspondence between exception flags and exception types in the exception flag definition specification of the first instruction set architecture, each flag in the exception flag set is converted into a corresponding exception type label to obtain the first semantic label group; According to the correspondence between exception flags and exception types in the exception flag definition specification of the second instruction set architecture, each flag in the second exception flag set is converted into the corresponding exception type label to obtain the second semantic label group; The abnormal type labels under the same semantic dimension in the first semantic label group and the second semantic label group are compared dimension by dimension, and the semantic dimensions with different values ​​are determined as the differential semantic dimensions.

[0023] In the source environment, a single-precision floating-point addition instruction corresponding to the field type of the numeric field value in the floating-point instruction set of the first instruction set architecture is selected as the first floating-point arithmetic instruction. The numeric field value is used as the first operand, and a preset base constant is used as the second operand. Together with the opcode of the first floating-point arithmetic instruction, they are encapsulated into a first probe instruction. The first probe instruction is then sent to the floating-point execution unit of the source environment.

[0024] After receiving the first probe instruction, the floating-point execution unit of the source environment loads the numerical field value and the reference constant into the floating-point register, executes the single-precision floating-point addition instruction, and writes the generated rounding mode flag, precision loss flag, overflow flag and underflow flag into the hardware status register of the source environment after the operation is completed. Starting from the bit offset zero in the hardware status register, the binary values ​​of each exception flag bit are read sequentially, and the read binary values ​​are arranged and combined according to the bit order in the hardware status register to form an exception flag set.

[0025] In the reference environment, a floating-point addition instruction that is logically equivalent to the single-precision floating-point addition instruction in the floating-point instruction set of the second instruction set architecture is selected as the second floating-point arithmetic instruction. The same numerical field value is used as the first operand, and the same reference constant is used as the second operand. Together with the opcode of the second floating-point arithmetic instruction, they are encapsulated into a second probe instruction. The second probe instruction is sent to the floating-point execution unit of the reference environment.

[0026] After receiving the second probe instruction, the floating-point execution unit of the reference environment loads the numerical field value and the reference constant into the floating-point register, executes the floating-point addition instruction, writes the generated exception flag bit into the hardware status register of the reference environment after the operation is completed, reads the binary value of each exception flag bit sequentially from the hardware status register starting from bit offset zero, arranges and combines them according to the bit order in the hardware status register to form a second exception flag bit set, and returns the second exception flag bit set.

[0027] The exception flag definition specification of the first instruction set architecture is obtained from the source environment. The exception flag definition specification stores the correspondence between the offset of each flag bit in the hardware status register and the exception type in the form of a mapping table. Each flag bit in the exception flag set is traversed, and its corresponding flag bit offset is determined according to its position in the exception flag set. The exception type corresponding to the flag bit offset is retrieved in the exception flag definition specification, and the exception type is used as the exception type label of the flag bit. When the binary value of the flag bit is valid, the corresponding exception type label is marked as triggered. When the binary value of the flag bit is invalid, the corresponding exception type label is marked as not triggered. After all flag bits are converted, each exception type label and its trigger state are combined into a first semantic label group.

[0028] The exception flag definition specification of the second instruction set architecture is obtained from the reference environment. The exception flag definition specification of the second instruction set architecture stores the correspondence between the offset of each flag bit in the hardware status register and the exception type in the form of a mapping table. Each flag bit in the second exception flag set is traversed, and its corresponding flag bit offset is determined according to its bit order in the second exception flag set. The exception type corresponding to the flag bit offset is retrieved in the exception flag definition specification of the second instruction set architecture, and the exception type is used as the exception type label of the flag bit. When the binary value of the flag bit is valid, the corresponding exception type label is marked as triggered; when the binary value of the flag bit is invalid, the corresponding exception type label is marked as not triggered. After all flag bits are converted, each exception type label and its trigger state are combined into a second semantic label group.

[0029] The first semantic tag group and the second semantic tag group are aligned semantically according to the name of the exception type tag. A comparison relationship between the two semantic tag groups under each semantic dimension is established. The triggering state of the exception type tag in the first semantic tag group and the triggering state of the exception type tag in the second semantic tag group are compared dimension by dimension. When the triggering states of the two are inconsistent under the same semantic dimension, the semantic dimension is determined as the difference semantic dimension. All difference semantic dimensions are summarized into the difference semantic dimension set.

[0030] The beneficial effect is that logically equivalent floating-point operations are performed using the same numeric field value as an operand in both the source and reference environments. The binary values ​​of exception flags are directly captured from the hardware status register and combined bit-wise into an exception flag set. This allows the detection of cross-architecture semantic differences to reach the actual behavioral state at the hardware execution level, rather than relying on superficial comparisons of upper-level numerical results. Based on the correspondence between flag offsets and exception types in the exception flag definition specifications of each instruction set architecture, the exception flag sets with different bit orders under different architectures are uniformly converted into architecture-independent semantic label groups represented by exception type labels and their trigger states. This eliminates bit-level difference noise caused by different instruction set architecture encoding formats, making the first and second semantic label groups directly comparable in the same semantic dimension coordinate system. By comparing the trigger state differences of the same exception type label in the two semantic label groups dimension by dimension, the semantic deviation dimension caused by instruction set architecture differences can be accurately located, providing precise semantic-level guidance for the selection of subsequent compensation operations.

[0031] Based on the difference semantic dimension, compensation operations are selected from the compensation strategy library to construct mapping rules. Then, sample data records that did not participate in the construction are converted into candidate target records. After being injected into the verification environment of the second instruction set architecture, floating-point operations are performed to capture a new set of abnormal flag bits and then parse them into a verification semantic tag group. In this embodiment of the invention, the step of selecting compensation operations from the compensation strategy library to construct mapping rules based on the difference semantic dimension, and then converting sample data records that did not participate in the construction into candidate target records, includes: Search the compensation strategy library for compensation operation entries that match the difference semantic dimension, and extract the operation type identifier and operation parameters recorded in the compensation operation entries; The mapping rule is generated by associating the operation type identifier and the operation parameters with the original semantic labels of the numeric field values. From the source data records of the source environment, select data records that were not used to identify the difference semantic dimension as sample data records; The numerical field values ​​in the sample data record are compensated according to the operation type identifier and operation parameters recorded in the mapping rule to obtain field values. The numerical field values ​​in the sample data record are replaced with the field values ​​to form candidate target records.

[0032] The execution of floating-point operations after injecting the verification environment of the second instruction set architecture includes: The candidate target record is sent to the verification environment of the second instruction set architecture, and a verification probe instruction is sent to the verification environment. The verification probe instruction carries the field value and a verification floating-point operation instruction selected from the floating-point instruction set of the second instruction set architecture. The verification probe instruction instructs the floating-point execution unit of the verification environment to execute the verification floating-point operation instruction with the field value as an operand. The verification floating-point operation instruction is logically equivalent to the second floating-point operation instruction.

[0033] The process of capturing a new set of anomaly flags and then parsing it into a set of verification semantic tags includes: Read the exception flag bits in the hardware status register of the verification environment, and combine the exception flag bits into a new set of exception flag bits according to their bit order in the hardware status register. Based on the correspondence between exception flags and exception types recorded in the exception flag definition specification of the second instruction set architecture, each flag in the exception flag set is mapped to the corresponding exception type label to obtain a verification semantic label group.

[0034] In the compensation strategy library, each difference semantic dimension in the difference semantic dimension set is used as a search key and matched one by one with the index dimension of each compensation operation entry in the compensation strategy library. The compensation strategy library is organized and stored in the form of a mapping table from difference semantic dimensions to compensation operation entries. Each compensation operation entry contains an operation type identifier field and an operation parameter field. The operation type identifier and operation parameter recorded in the compensation operation entry that completely matches the difference semantic dimension are extracted.

[0035] The field name corresponding to the numerical field value in the source data record is used as the original semantic tag. A mapping rule structure is established with the original semantic tag as the index. The operation type identifier is written into the operation type field of the mapping rule structure, and the operation parameter is written into the operation parameter field of the mapping rule structure. The correspondence between the operation type identifier, the operation parameter and the original semantic tag constitutes the mapping rule.

[0036] From the source data record set of the source environment, exclude the data records that have been used as operands in the stage of identifying the difference semantic dimension, and select the first data record in the remaining data records in the storage order as the sample data record. The sample data record contains a field with the same name as the original semantic label and its corresponding other numeric field value.

[0037] The specific execution method of the compensation operation is determined according to the operation type identifier recorded in the mapping rule. When the operation type identifier indicates rounding compensation, the operation parameters recorded in the mapping rule are read as the target rounding mode, and the numeric field values ​​in the sample data record are re-rounded according to the target rounding mode to obtain the field value. When the operation type identifier indicates precision adjustment compensation, the operation parameters recorded in the mapping rule are read as the precision correction amount, and the numeric field values ​​in the sample data record are added to the precision correction amount to obtain the field value. The field value is used to overwrite the original numeric field values ​​in the sample data record, and the replaced sample data record is used as the candidate target record.

[0038] The candidate target record is serialized into a data packet, and the data packet is sent to the verification environment through the communication interface provided by the verification environment of the second instruction set architecture. A floating-point operation instruction with the same opcode and operand format as the second floating-point operation instruction is selected from the floating-point instruction set of the second instruction set architecture as the verification floating-point operation instruction. The field value is used as the first operand, and the same reference constant is used as the second operand. Together with the opcode of the verification floating-point operation instruction, they are encapsulated into a verification probe instruction.

[0039] After receiving the verification probe instruction, the floating-point execution unit of the verification environment loads the field value and the base constant into the floating-point register, executes the verification floating-point operation instruction, and writes the generated exception flag bit into the hardware status register of the verification environment after the operation is completed.

[0040] Starting from a bit offset of zero, read the binary values ​​of each exception flag bit sequentially from the hardware status register of the verification environment, and arrange the read binary values ​​according to the bit order in the hardware status register to form a new set of exception flag bits.

[0041] Obtain the exception flag definition specification of the second instruction set architecture from the reference environment, traverse each flag in the new exception flag set, determine the corresponding flag offset according to the position of the flag in the new exception flag set, retrieve the exception type corresponding to the flag offset in the exception flag definition specification of the second instruction set architecture, and use the exception type as the exception type label of the flag. When the binary value of the flag is valid, mark the corresponding exception type label as triggered; when the binary value of the flag is invalid, mark the corresponding exception type label as not triggered. After all flags are converted, combine each exception type label and its trigger state into a verification semantic label group.

[0042] The beneficial effects are as follows: by using the difference semantic dimension as the search key to match the corresponding compensation operation entries in the compensation strategy library, the operation type identifier and operation parameters are directly extracted, and a deterministic mapping is established between the semantic difference dimension and the specific compensation operation parameters. This avoids the inefficiency and error-proneness of manually analyzing the instruction set architecture manual and customizing conversion rules one by one. Mapping rules are constructed by associating operation parameters with the original semantic tags, ensuring that each mapping rule is precisely bound to the semantics of the fields in the source data record. This guarantees that the compensation operation can automatically locate the correct field during batch data migration. Sample data records that did not participate in the difference semantic dimension identification are selected for compensation conversion to form candidate target records. This ensures that the data used in the verification process is independent of the data used to construct the mapping rules, truly reflecting the adaptability of the mapping rules on unknown data. The candidate target records are injected into the verification environment of the second instruction set architecture and perform floating-point operations that are logically equivalent to the reference environment. The abnormal flag bits are recaptured from the hardware status register and parsed into a verification semantic tag group. This enables direct verification of the semantic correctness of the compensated field values ​​at the target architecture hardware level, thereby discovering residual semantic deviations before a single correction and providing accurate feedback for deterministic single correction.

[0043] If there are residual differences between the verification semantic tag group and the semantic tag group, the parameter correction amount is determined according to the deterministic mapping relationship, the mapping rule is corrected once to obtain the final mapping rule, the remaining data records in the source environment are converted into target data records and written into the target data sink; In this embodiment of the invention, if there is a residual difference between the verification semantic tag group and the semantic tag group, the parameter correction amount is determined based on the deterministic mapping relationship, and the mapping rule is corrected once to obtain the final mapping rule, including: The verification semantic label group is compared dimension by dimension with the anomaly type label in the same semantic dimension. If there are at least one semantic dimension with different values ​​for the anomaly type label, it is determined that there is a residual difference, and the semantic dimension with different values ​​for the anomaly type label is determined as the residual difference dimension. In the deterministic mapping relationship, find the correction entry that matches the residual difference dimension, extract the parameter correction type and correction step size recorded in the correction entry, and form the parameter correction amount; The parameter correction amount is applied to the operation parameters of the mapping rule, and the operation parameters are adjusted according to the parameter correction type and the correction step size to obtain the corrected operation parameters. The operation parameters of the mapping rule are then replaced with the corrected operation parameters to form the final mapping rule.

[0044] The step of converting the remaining data records in the source environment into target data records and writing them into the target data sink includes: Obtain the remaining data records in the source environment other than the sample data records, and extract the value of each numeric field and the corresponding original semantic label from the remaining data records; Based on the original semantic label, the corresponding operation type identifier and the corrected operation parameter are retrieved in the final mapping rule, and a compensation operation is performed on the numeric field value corresponding to the original semantic label in the remaining data record to generate the target field value. The target field values ​​are combined according to the original arrangement order of the fields in the remaining data records to form the target data record. A data write request is sent to the target data assembly of the second instruction set architecture to write the target data record into the storage area of ​​the target data assembly.

[0045] The verification semantic tag group and the semantic tag group are aligned semantically according to the name of the anomaly type tag. The trigger state of each anomaly type tag in the verification semantic tag group is extracted and compared with the trigger state of the corresponding anomaly type tag in the semantic tag group in each dimension. When the trigger state of the anomaly type tag in the verification semantic tag group is triggered and the trigger state of the corresponding anomaly type tag in the semantic tag group is not triggered in a certain semantic dimension, the semantic dimension is determined as the residual difference dimension. When the trigger state of the anomaly type tag in the verification semantic tag group is not triggered and the trigger state of the corresponding anomaly type tag in the semantic tag group is triggered in a certain semantic dimension, the semantic dimension is also determined as the residual difference dimension. All semantic dimensions with inconsistent trigger states constitute the residual difference dimension set.

[0046] In the deterministic mapping relationship, each residual difference dimension in the residual difference dimension set is used as a retrieval key and matched one by one with the index dimension of each correction entry in the deterministic mapping relationship. The deterministic mapping relationship is organized and stored in the form of a mapping table from residual difference dimensions to correction entries. Each correction entry contains a parameter correction type field and a correction step size field. The parameter correction type field indicates whether the adjustment method performed on the operation parameter is to increase, decrease, or replace. The correction step size field indicates the magnitude of the adjustment. The parameter correction type and correction step size recorded in the correction entry that completely matches the residual difference dimension are extracted, and the parameter correction type and correction step size are combined into a parameter correction amount.

[0047] The operation parameters are read from the mapping rules as the original operation parameters. When the parameter correction type indicator in the parameter correction amount increases, the value of the original operation parameter is added to the correction step size to obtain the corrected operation parameters. When the parameter correction type indicator in the parameter correction amount decreases, the value of the original operation parameter is subtracted from the correction step size to obtain the corrected operation parameters. When the parameter correction type indicator in the parameter correction amount is replaced, the correction step size is directly used as the corrected operation parameters. The corrected operation parameters are used to overwrite the original operation parameters in the mapping rules. The mapping rules after the operation parameters are replaced are used as the final mapping rules.

[0048] Exclude the data record that has been used as a sample data record from the source data record set of the source environment, take all the remaining data records in the source data record set as the remaining data records, traverse each data record in the remaining data records, extract the field name of each field from each data record as the original semantic label, and read the numeric field value from the field position corresponding to the original semantic label.

[0049] Based on the original semantic tag extracted from each remaining data record, a mapping rule structure indexed by the original semantic tag is retrieved from the final mapping rule. The operation type identifier and the corrected operation parameters are read from the mapping rule structure. When the operation type identifier indicates rounding compensation, the numeric field value of the corresponding field in the remaining data record is re-rounded using the corrected operation parameters as the target rounding mode to generate the target field value. When the operation type identifier indicates precision adjustment compensation, the corrected operation parameters are added to the numeric field value of the corresponding field in the remaining data record as the precision correction amount to generate the target field value. The above compensation operation is performed on each field in the remaining data record covered by the final mapping rule.

[0050] Keeping the original order of each field in the remaining data records unchanged, the target field values ​​corresponding to each field are sequentially filled into the newly created data record structure in this order. The order of each field in the newly created data record structure is completely consistent with the original order of each field in the remaining data records. The completed data record structure is used as the target data record.

[0051] A data write connection is established to the target data sink of the second instruction set architecture. The target data record is serialized into a data block that is compatible with the storage format of the target data sink. The data block is sent to the target data sink through the data write connection. The target data sink parses the data block and stores it in its storage area at the target storage location corresponding to the source environment data record.

[0052] The beneficial effect is that by comparing the verified semantic label group with the semantic label group obtained from the reference environment dimension by dimension according to the anomaly type label name, the residual difference dimension that has not been eliminated after the compensation operation can be directly located, making the correction target precise to the specific anomaly type level. In the deterministic mapping relationship, the parameter correction type and correction step size are retrieved according to the residual difference dimension, and the correction amount is directly applied to the operation parameters of the mapping rule to perform a single deterministic adjustment of addition, reduction or replacement, skipping the cycle of repeated trial and error and iterative verification, making the correction path clear and traceable. Using the corrected final mapping rule, the remaining data records are retrieved one by one according to the original semantic label and the compensation operation is performed. The numerical field values ​​in each data record are converted into target field values ​​that are semantically equivalent to the source architecture at the target architecture hardware level, maintaining the original arrangement order of the fields to form the target data record, ensuring the integrity of the data record structure during the batch migration process. Finally, the target data records are stored in the storage area of ​​the target data sink through the data write connection, completing the semantically faithful data migration from the source environment to the target data sink.

[0053] The compensation strategy library and the deterministic mapping relationship are both established based on the reverse analysis of the state machine jump conditions inside the floating-point execution unit of the first instruction set architecture and the second instruction set architecture.

[0054] In this embodiment of the invention, both the compensation strategy library and the deterministic mapping relationship are established based on the reverse analysis of the state machine transition conditions within the floating-point execution unit of the first instruction set architecture and the second instruction set architecture, including: Logically compare the internal state machine transition conditions of the first instruction set architecture and the internal state machine transition conditions of the second instruction set architecture to establish a correspondence between the exception flag bits of the first instruction set architecture and the second instruction set architecture under the same semantic dimension. Based on the correspondence, compensation operation entries for the difference semantic dimension and compensation operation in the compensation strategy library, as well as correction entries for the residual difference dimension and parameter correction amount in the deterministic mapping relationship, are constructed.

[0055] The system obtains the control signal transition records of each stage of the internal pipeline of the floating-point execution unit of the first instruction set architecture during the execution of a single-precision floating-point addition instruction. It extracts the triggering condition that causes the least significant bit of the operand mantissa to be truncated when the precision loss flag in the hardware status register changes from an invalid state to an valid state. It also extracts the correspondence between the rounding mode adopted by the rounding control logic inside the floating-point execution unit and the rounding direction of the operand mantissa when the rounding mode flag changes from an invalid state to a valid state. Finally, it extracts the threshold condition that causes the exponent field of the operation result to exceed the maximum representation range of a single-precision floating-point number when the overflow flag changes from an invalid state to a valid state. The system uses the above triggering conditions, correspondences, and threshold conditions as the internal state machine transition conditions of the first instruction set architecture.

[0056] The system obtains the control signal transition records of each stage of the internal pipeline of the floating-point execution unit of the second instruction set architecture during the execution of a single-precision floating-point addition instruction. It extracts the triggering condition that causes the least significant bit of the operand mantissa to be truncated when the precision loss flag in the hardware status register changes from an invalid state to an valid state. It also extracts the correspondence between the rounding mode adopted by the rounding control logic inside the floating-point execution unit and the rounding direction of the operand mantissa when the rounding mode flag changes from an invalid state to a valid state. Finally, it extracts the threshold condition that causes the exponent field of the operation result to exceed the maximum representation range of a single-precision floating-point number when the overflow flag changes from an invalid state to a valid state. The system uses the above triggering conditions, correspondences, and threshold conditions as the internal state machine transition conditions of the second instruction set architecture.

[0057] The trigger conditions for the precision loss flag in the internal state machine transition conditions of the first instruction set architecture are compared with those in the internal state machine transition conditions of the second instruction set architecture. When the first and second instruction set architectures set the precision loss flag at the least significant bit truncation position of the same operand mantissa while the other architecture does not, a trigger asymmetry correspondence is established between the precision loss flags of the first and second instruction set architectures under the precision loss semantic dimension. The correspondence between the rounding mode flags in the internal state machine transition conditions of the first and second instruction set architectures is compared. When the two architectures use different rounding modes under the same operand mantissa rounding direction, the correspondence between the rounding mode flags of the two architectures is marked as a trigger asymmetry correspondence under the rounding mode semantic dimension. The trigger asymmetry correspondences established under each semantic dimension are summarized as the correspondence between the exception flags of the first and second instruction set architectures under the same semantic dimension.

[0058] Based on the trigger asymmetry between the exception flag bits of the first and second instruction set architectures under the same semantic dimension recorded in the correspondence, each difference semantic dimension and its corresponding exception flag bit trigger difference between the two architectures are transformed into a compensation operation entry and stored in the compensation strategy library. The operation type identifier and operation parameters in the compensation operation entry are directly determined by the trigger difference features of the difference semantic dimension in the correspondence. Each residual difference dimension and its corresponding exception flag bit trigger difference that still exists after compensation are transformed into a correction entry and stored in the deterministic mapping relationship. The parameter correction type and correction step size in the correction entry are directly determined by the trigger difference features of the residual difference dimension in the correspondence.

[0059] The beneficial effect is that by extracting the triggering conditions, correspondences, and threshold conditions of precision loss flags, rounding mode flags, and overflow flags from the pipeline control signal transition records within the floating-point execution units of the first and second instruction set architectures, the foundation for establishing the compensation strategy library and deterministic mapping relationship is shifted from static comparison in the instruction set architecture manual to a reverse comparison of hardware state machine transition conditions. This allows the correspondence between the difference semantic dimension and the compensation operation to be directly derived from the asymmetric relationship triggered by the abnormal flags of the two architectures, rather than relying on statistical fitting or trial-and-error experiments. Using the asymmetric correspondence between the abnormal flags of the two architectures under the same semantic dimension as a unified basis, the compensation operation entries for the difference semantic dimension and compensation operation in the compensation strategy library, as well as the correction entries for the residual difference dimension and parameter correction amount in the deterministic mapping relationship, are constructed simultaneously. This ensures the consistency in technical origin between the initial compensation operation and the single correction amount, making the construction and correction of mapping rules based on the same analysis results of hardware behavior logic.

[0060] like Figure 2 The diagram shown is a functional block diagram of a cross-architecture big data service integration system based on heterogeneous collaboration in information technology innovation, provided by an embodiment of the present invention.

[0061] The cross-architecture big data service integration system 100 based on domestically developed heterogeneous collaboration described in this invention can be installed in electronic devices. Depending on the functions implemented, the cross-architecture big data service integration system 100 may include a difference semantic dimension identification module 101, a mapping rule construction and verification module 102, a residual correction and transformation module 103, and a compensation strategy reverse analysis module 104. The modules described in this invention can also be referred to as units, which are a series of computer program segments that can be executed by the processor of an electronic device and can perform a fixed function, stored in the memory of the electronic device.

[0062] In this embodiment, the functions of each module / unit are as follows: The differential semantic dimension identification module 101 is used to perform floating-point operations in the source environment and the reference environment of the second instruction set architecture respectively, with the numerical field value of the first instruction set architecture as the operand, capture the abnormal flag set and then parse it into an architecture-independent semantic tag group to identify the differential semantic dimension. The mapping rule construction and verification module 102 is used to select compensation operations from the compensation strategy library to construct mapping rules based on the difference semantic dimension, then convert the sample data records that did not participate in the construction into candidate target records, inject them into the verification environment of the second instruction set architecture, perform floating-point operations, capture a new set of abnormal flag bits, and then parse them into a verification semantic tag group. The residual correction and conversion module 103 is used to determine the parameter correction amount based on the deterministic mapping relationship if there is a residual difference between the verification semantic label group and the semantic label group, correct the mapping rule once to obtain the final mapping rule, convert the remaining data records in the source environment into target data records, and write them into the target data sink. The compensation strategy reverse analysis module 104, used for the compensation strategy library and the deterministic mapping relationship, is established based on the reverse analysis of the state machine jump conditions inside the floating-point execution unit of the first instruction set architecture and the second instruction set architecture.

[0063] In the several embodiments provided by this invention, it should be understood that the disclosed methods and systems can be implemented in other ways. For example, the system embodiments described above are merely illustrative; for instance, the division of modules is only a logical functional division, and other division methods may be used in actual implementation.

[0064] The modules described as separate components may or may not be physically separate. The components shown as modules may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.

[0065] Furthermore, the functional modules in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or in the form of hardware plus software functional modules.

[0066] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the present invention can be implemented in other specific forms without departing from the spirit or essential characteristics of the present invention.

[0067] The embodiments of this application can acquire and process relevant data based on an artificial intelligence technology. Artificial intelligence is the theory, method, technology, and application system that uses digital computers or machines controlled by digital computers to simulate, extend, and expand human intelligence, perceive the environment, acquire knowledge, and use that knowledge to obtain optimal results.

[0068] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention.

Claims

1. A cross-architecture big data service integration method based on heterogeneous collaboration in information technology innovation, characterized in that: The method includes: Using the numeric field values ​​of the first instruction set architecture as operands, floating-point operations are performed in the source environment and the reference environment of the second instruction set architecture, respectively. The set of exception flags is captured and then parsed into an architecture-independent semantic tag group to identify the difference semantic dimensions. Based on the difference semantic dimension, compensation operations are selected from the compensation strategy library to construct mapping rules. Then, sample data records that did not participate in the construction are converted into candidate target records. After being injected into the verification environment of the second instruction set architecture, floating-point operations are performed to capture a new set of abnormal flag bits and then parse them into a verification semantic tag group. If there are residual differences between the verification semantic tag group and the semantic tag group, the parameter correction amount is determined according to the deterministic mapping relationship, the mapping rule is corrected once to obtain the final mapping rule, the remaining data records in the source environment are converted into target data records and written into the target data sink; The compensation strategy library and the deterministic mapping relationship are both established based on the reverse analysis of the state machine jump conditions inside the floating-point execution unit of the first instruction set architecture and the second instruction set architecture.

2. The cross-architecture big data service integration method based on heterogeneous collaboration in information technology innovation as described in claim 1, characterized in that, The step of performing floating-point operations with numeric field values ​​of the first instruction set architecture as operands in the source environment and the reference environment of the second instruction set architecture includes: Send a first probe instruction to the source environment of the first instruction set architecture. The first probe instruction carries a numeric field value and a first floating-point arithmetic instruction selected from the floating-point instruction set of the first instruction set architecture, instructing the floating-point execution unit of the source environment to execute the first floating-point arithmetic instruction with the numeric field value as an operand. Read the exception flag bits in the hardware status register of the source environment, and combine the exception flag bits into an exception flag bit set according to the bit order of the exception flag bits in the hardware status register; Send a second probe instruction to a reference environment of the second instruction set architecture, the second probe instruction carrying the numeric field value and a second floating-point arithmetic instruction selected from the floating-point instruction set of the second instruction set architecture; The second floating-point arithmetic instruction is logically equivalent to the first floating-point arithmetic instruction, instructing the floating-point execution unit of the reference environment to execute the second floating-point arithmetic instruction with the numeric field value as an operand.

3. The cross-architecture big data service integration method based on heterogeneous collaboration in information technology innovation as described in claim 2, characterized in that, The set of captured anomaly flags is then parsed into architecture-independent semantic tag groups to identify differential semantic dimensions, including: The reference environment receives a second set of exception flags returned by the reference environment. The second set of exception flags is formed by the reference environment reading the exception flags in the hardware status register of the reference environment and combining them in bit order after the second floating-point operation instruction is executed. According to the correspondence between exception flags and exception types in the exception flag definition specification of the first instruction set architecture, each flag in the exception flag set is converted into a corresponding exception type label to obtain the first semantic label group; According to the correspondence between exception flags and exception types in the exception flag definition specification of the second instruction set architecture, each flag in the second exception flag set is converted into the corresponding exception type label to obtain the second semantic label group; The abnormal type labels under the same semantic dimension in the first semantic label group and the second semantic label group are compared dimension by dimension, and the semantic dimensions with different values ​​are determined as the differential semantic dimensions.

4. The cross-architecture big data service integration method based on heterogeneous collaboration in information technology innovation as described in claim 3, characterized in that, The step of selecting compensation operations from the compensation strategy library to construct mapping rules based on the difference semantic dimension, and then converting sample data records that did not participate in the construction into candidate target records, includes: Search the compensation strategy library for compensation operation entries that match the difference semantic dimension, and extract the operation type identifier and operation parameters recorded in the compensation operation entries; The mapping rule is generated by associating the operation type identifier and the operation parameters with the original semantic labels of the numeric field values. From the source data records of the source environment, select data records that were not used to identify the difference semantic dimension as sample data records; The numerical field values ​​in the sample data record are compensated according to the operation type identifier and operation parameters recorded in the mapping rule to obtain field values. The numerical field values ​​in the sample data record are replaced with the field values ​​to form candidate target records.

5. The cross-architecture big data service integration method based on heterogeneous collaboration in information technology innovation as described in claim 4, characterized in that, The execution of floating-point operations after injecting the verification environment of the second instruction set architecture includes: The candidate target record is sent to the verification environment of the second instruction set architecture, and a verification probe instruction is sent to the verification environment. The verification probe instruction carries the field value and a verification floating-point operation instruction selected from the floating-point instruction set of the second instruction set architecture. The verification probe instruction instructs the floating-point execution unit of the verification environment to execute the verification floating-point operation instruction with the field value as an operand. The verification floating-point operation instruction is logically equivalent to the second floating-point operation instruction.

6. The cross-architecture big data service integration method based on heterogeneous collaboration in information technology innovation as described in claim 5, characterized in that, The process of capturing a new set of anomaly flags and then parsing it into a set of verification semantic tags includes: Read the exception flag bits in the hardware status register of the verification environment, and combine the exception flag bits into a new set of exception flag bits according to their bit order in the hardware status register. Based on the correspondence between exception flags and exception types recorded in the exception flag definition specification of the second instruction set architecture, each flag in the exception flag set is mapped to the corresponding exception type label to obtain a verification semantic label group.

7. The cross-architecture big data service integration method based on heterogeneous collaboration in information technology innovation as described in claim 1, characterized in that, If there are residual differences between the verified semantic label group and the semantic label group, then the parameter correction amount is determined according to the deterministic mapping relationship, and the mapping rule is corrected once to obtain the final mapping rule, including: The verification semantic label group is compared dimension by dimension with the anomaly type label in the same semantic dimension. If there are at least one semantic dimension with different values ​​for the anomaly type label, it is determined that there is a residual difference, and the semantic dimension with different values ​​for the anomaly type label is determined as the residual difference dimension. In the deterministic mapping relationship, find the correction entry that matches the residual difference dimension, extract the parameter correction type and correction step size recorded in the correction entry, and form the parameter correction amount; The parameter correction amount is applied to the operation parameters of the mapping rule, and the operation parameters are adjusted according to the parameter correction type and the correction step size to obtain the corrected operation parameters. The operation parameters of the mapping rule are then replaced with the corrected operation parameters to form the final mapping rule.

8. The cross-architecture big data service integration method based on heterogeneous collaboration in information technology innovation as described in claim 7, characterized in that, The step of converting the remaining data records in the source environment into target data records and writing them into the target data sink includes: Obtain the remaining data records in the source environment other than the sample data records, and extract the value of each numeric field and the corresponding original semantic label from the remaining data records; Based on the original semantic label, the corresponding operation type identifier and the corrected operation parameter are retrieved in the final mapping rule, and a compensation operation is performed on the numeric field value corresponding to the original semantic label in the remaining data record to generate the target field value. The target field values ​​are combined according to the original arrangement order of the fields in the remaining data records to form the target data record. A data write request is sent to the target data assembly of the second instruction set architecture to write the target data record into the storage area of ​​the target data assembly.

9. The cross-architecture big data service integration method based on domestically developed heterogeneous collaboration as described in claim 1, characterized in that, The compensation strategy library and the deterministic mapping relationship are both established based on the reverse analysis of the state machine transition conditions inside the floating-point execution unit of the first instruction set architecture and the second instruction set architecture, including: Logically compare the internal state machine transition conditions of the first instruction set architecture and the internal state machine transition conditions of the second instruction set architecture to establish a correspondence between the exception flag bits of the first instruction set architecture and the second instruction set architecture under the same semantic dimension. Based on the correspondence, compensation operation entries for the difference semantic dimension and compensation operation in the compensation strategy library, as well as correction entries for the residual difference dimension and parameter correction amount in the deterministic mapping relationship, are constructed.

10. A cross-architecture big data service integration system based on domestically developed heterogeneous collaboration, characterized in that: The system for implementing the cross-architecture big data service integration method based on heterogeneous collaboration according to claim 1 includes: The differential semantic dimension identification module is used to perform floating-point operations in the source environment and the reference environment of the second instruction set architecture with the numerical field value of the first instruction set architecture as the operand, capture the set of exception flags and then parse them into an architecture-independent semantic tag group to identify the differential semantic dimension. The mapping rule construction and verification module is used to select compensation operations from the compensation strategy library to construct mapping rules based on the difference semantic dimension, then convert the sample data records that did not participate in the construction into candidate target records, inject them into the verification environment of the second instruction set architecture, perform floating-point operations, capture a new set of abnormal flag bits, and then parse them into a verification semantic tag group. The residual correction and conversion module is used to determine the parameter correction amount based on the deterministic mapping relationship if there is a residual difference between the verification semantic label group and the semantic label group, correct the mapping rule in one step to obtain the final mapping rule, convert the remaining data records in the source environment into target data records, and write them into the target data sink. The compensation strategy reverse analysis module, used for the compensation strategy library and the deterministic mapping relationship, is established based on the reverse analysis of the state machine jump conditions inside the floating-point execution unit of the first instruction set architecture and the second instruction set architecture.

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