Transistor-level circuit dc analysis optimization method based on graph-enhanced large language model

Abstract

The application relates to a transistor-level circuit direct current analysis optimization method based on a graph-enhanced large language model, and belongs to the technical field of integrated circuits. The method comprises the following steps: (1) first, converting a circuit netlist into a graph representation, and extracting circuit topology features through a graph neural network (GNN)-based graph encoder; (2) then, adopting a text-graph alignment strategy to map circuit topology embedding into a text embedding space of an LLM, and realizing multi-modal information fusion; and (3) finally, designing a multi-perspective few-shot prompt, and guiding the LLM to complete optimal PTA method selection through in-context learning. The PTA method selection accuracy of the application reaches 97.14%, significantly improves the efficiency of transistor-level circuit direct current analysis, and can be widely applied to an integrated circuit design verification process.

Description

Technical Field

[0001] This invention relates to the fields of integrated circuit electronic design automation (EDA) and SPICE simulation, specifically to a method for DC analysis and optimization of transistor-level circuits based on graph-enhanced large language models. Background Technology

[0002] DC analysis is a core step in nonlinear circuit simulation. It serves not only as the initial verification of the circuit's operating state but also as a necessary prerequisite for subsequent processes such as transient analysis and AC analysis. Its efficiency directly impacts the cycle time of integrated circuit design verification. In DC analysis, pseudo-transient analysis (PTA) and its variants (such as DPTA, RPTA, and CEPTA) have become widely adopted and highly efficient algorithms in industry due to their strong continuity and ease of implementation. However, different PTA methods exhibit significant differences in simulation efficiency for the same circuit, and there is a lack of effective rules to guide the selection of the optimal method. Currently, the industry mainly relies on engineers to manually select the method based on circuit type, topology, and experience. This approach has low automation and high subjectivity, severely restricting the widespread application of PTA methods in commercial simulators.

[0003] In recent years, Large Language Models (LLMs) have begun to emerge in the EDA field due to their powerful text understanding and reasoning capabilities, and have been applied to scenarios such as code generation and circuit design. However, directly applying LLMs to PTA method selection faces two major challenges: First, the input token length of LLMs is limited, making it impossible to directly process industrial-grade circuit netlists containing tens of millions of nodes, and it is difficult to capture the complex topological information contained in the circuit; second, the insufficient quantity and diversity of circuit samples result in poor generalization ability of LLMs under low data conditions, making it difficult to achieve high-accuracy PTA method classification.

[0004] In existing technologies, Graph Neural Networks (GNNs) have a natural advantage in topological feature extraction. However, using GNNs alone makes it difficult to combine them with the functional semantic information of circuits, and their generalization ability to large-scale, diverse circuits is limited. Traditional LLM fine-tuning methods are prone to overfitting in low-data scenarios and cannot effectively integrate structured topological data with unstructured textual information. Therefore, there is an urgent need for a technical solution that can integrate the topological extraction capabilities of GNNs with the semantic understanding capabilities of LLMs to solve the problem of automatic selection in PTA methods and improve the efficiency and automation level of DC analysis of transistor-level circuits. Summary of the Invention

[0005] The purpose of this invention is to overcome the shortcomings of existing technologies. Addressing the problems of existing pseudo-transient analysis (PTA) methods relying on human experience, low automation, and high subjectivity; large language models (LLMs) struggling to handle large-scale circuit netlists and effectively capturing circuit topology information; and poor model generalization under low data conditions leading to insufficient accuracy in PTA method selection, this invention provides a transistor-level circuit DC analysis optimization method based on graph-enhanced large language models. This method achieves automatic and efficient selection of the optimal PTA method, significantly improving the efficiency and automation of transistor-level circuit DC analysis and effectively reducing reliance on human experience.

[0006] To achieve the above objectives, this invention provides a DC analysis optimization method for transistor-level circuits based on a graph-enhanced large language model. The core idea is to convert the circuit netlist into a graph structure and extract topological features using a Generative Neural Network (GNN); to fuse topological features with LLM text features through a text-graph alignment strategy; to design few-sample cue words to address the low data generalization problem; and finally, to select the optimal PTA method using LLM. The method includes the following steps:

[0007] S1: Circuit Topology Construction Steps: Achieving accurate mapping from netlist to structured graph. Addressing the unstructured nature of circuit netlists and the topological complexity caused by multi-port devices, a two-step netlist-to-graph conversion scheme is designed: First, multi-port nonlinear devices such as MOSFETs and BJTs undergo equivalent transformation. Following the small-signal circuit principle, a T-equivalent small-signal model is used to decompose them into multiple groups of two-port devices, eliminating hyperedges formed by multi-port devices in the graph representation and simplifying topological connectivity. Then, the processed netlist is mapped to an undirected graph. The electrical nodes correspond to the set of graph nodes. The connections between electrical nodes correspond to the set of graph edges. Furthermore, feature vectors are assigned to nodes and edges respectively. The node feature vector contains the type and quantity statistics of the connected devices, while the edge feature vector uniquely identifies the device type and records the number of parallel devices through a special code, ensuring that the graph structure retains the physical connection and device composition information of the circuit, and providing high-quality input for subsequent feature extraction.

[0008] Specifically as follows:

[0009] 1-1. Equivalent Transformation of Multiport Devices: Multiport nonlinear devices (MOSFETs, BJTs) are transformed into multiple sets of two-port devices using a T-equivalent small-signal model. This addresses the problem of hyperedges in graphs caused by multiport devices, which complicate topological connectivity.

[0010] 1-2. Graph Structure and Feature Generation: Converting the netlist file of transistor-level circuits into an undirected graph representation. The circuit nodes correspond to the graph node set. The connection relationships between circuit nodes correspond to the graph edge set. For each graph node Assigning feature vectors , For each node feature dimension, the node feature vector contains statistics on the number of various devices (including resistors, independent voltage sources, independent current sources, etc.) connected to that node; for each graph edge... Assigning feature vectors , For edge features, the edge feature vector uniquely identifies the type of connecting devices between corresponding nodes and the number of parallel devices between nodes;

[0011] S2: Topology Feature Extraction Steps: Achieving a complete and efficient representation of circuit topology information. To address the issues of traditional GNNs' inability to fully utilize edge information and the tendency of traditional Readout functions to lose topology details, an optimized GNN graph encoder is constructed: An innovative EdgeAware aggregation strategy is adopted. During GNN message passing, edge features are concatenated with neighboring node features, then subjected to MLP dimensionality reduction before aggregation. This deeply integrates edge information such as device type and parallel connection information into node feature updates, improving the discriminative power of topology features. Combined with a gated Readout mechanism, an adaptive weight is assigned to each node through a learnable gating function, dynamically aggregating node-level embeddings to generate graph-level topology embeddings. This effectively avoids the loss of topology information caused by traditional Readout methods such as summation and averaging, ensuring that graph-level embeddings accurately reflect the core topology of the circuit. Specifically:

[0012] 2-1: To fully utilize the rich edge information of the graph in the circuit topology graph construction step, EdgeAware incorporates edge information into the information transmission process of the GNN. The EdgeAware aggregation strategy achieves iterative updates of node features in the following ways:

[0013]

[0014] in, This represents the current layer number of the GNN. For nodes The set of neighboring nodes, For aggregate functions, This is a mapping function that performs dimensionality reduction using a multilayer perceptron (MLP) after concatenating node embeddings and edge features. For nodes The current GNN layer embedding, and They are nodes , The previous layer of embedding, For the edge eigenvectors.

[0015] 2-2: To address the issue of topological information loss that often occurs when traditional readout functions aggregate node-level embeddings to generate graph-level representations, this proposed gated readout mechanism introduces learnable parameters and dynamically integrates the embedding features of each node through an adaptive weighting strategy. Its expression is as follows:

[0016]

[0017] in, For graph-level topology embedding, For a set of graph nodes, It is a non-linear activation function. For learnable gating functions based on MLP, For nodes The final embedding.

[0018] S3: Multimodal Embedding Alignment Step: Achieving spatial alignment between topological features and textual features. Addressing the technical bottleneck of spatial incompatibility between the topological embeddings output by GNNs and the textual embeddings of LLMs, a text-graph alignment module is designed: the core of this module is a trainable linear projection layer, which learns the weight matrix... and bias vector Embed the graph-level topology generated by GNN Mapped to the text token embedding space of LLM, generating aligned topological embeddings. This ensures that topological features can be directly inserted into text prompts.

[0019] In the multimodal embedding alignment step, the mathematical expression for the linear projection layer is:

[0020]

[0021] in, For graph-level topological embeddings output by GNN, The projection weight matrix is... Represents the field of real numbers OK, The space of real matrices in columns, For bias vectors, The aligned topological embedding has the same dimensions as the text token embedding dimensions in the LLM.

[0022] S4: Multimodal Cue Word Construction Steps: Achieving Efficient Contextual Learning under Low Data Conditions. To address the insufficient generalization ability of models due to the scarcity of transistor-level circuit samples, a phased, multi-dimensional few-sample cue word design is implemented: During the training phase, a concise cue word structure of "task description + target instance" is adopted. The task description clearly defines the core objective and classification range for PTA method selection. The target instance includes circuit text description (name, device statistics) and topology embedding placeholders, ensuring the model acquires core information while avoiding redundant examples from interfering with parameter optimization efficiency. During the inference phase, a few-sample cue word structure of "task description + multiple class example instances + guiding text + target instance" is adopted. All example instances are selected from the training set, and each example instance fully represents a class of PTA methods, achieving full coverage of all candidate PTA methods. This ensures the integrity of contextual information while strictly distinguishing between training and test data, avoiding data leakage. Topology embedding is inserted into the cue words using dedicated tag strings, enabling the cue words to simultaneously contain textual semantic information and structured topological information, providing a comprehensive reasoning basis for LLM.

[0023] Specifically as follows:

[0024] 4-1: Training Phase Cue Word Generation: Generate cue words for model training. Each cue word is specific to a circuit instance and contains only a task description and a target instance portion, without any contextual examples. The target instance portion consists of a text description sub-part and the topology embedding sub-part generated in step 4.

[0025] 4-2: Inference Stage Cue Generation: Generate few-sample cue words for model inference. Each cue word includes a task description, multiple example instance blocks, and a target instance block. Each instance in the example instance block consists of a text description sub-part, a topological embedding sub-part generated in step 4, and its corresponding PTA method category label. The target instance block has the same format as the example instances but omits the category labels. Guiding text for the classification step is inserted between the example instance blocks and the target instance block.

[0026] 4-3: Components of the cue word information: The task description sub-part in the cue word generation step during the training and inference phases specifies the overall context and objective of the task selected by the PTA method, and also includes a human-readable summary of circuit names and device composition statistics; the topology embedding sub-part is represented by a pair of specially designed token strings ([Graph Token Start] and [Graph Token End]) as placeholders, and the topology embedding representation generated in step 4... It was inserted between the two marker characters.

[0027] 4-4: Example Instance Information Composition: Multiple example instances in the prompt word generation step of the inference stage are all selected from the model's training dataset to ensure strict separation from the test data. Furthermore, multiple example instances collectively cover all candidate PTA method categories, thereby enabling the large language model to access all possible prediction results.

[0028] S5: Optimizing Decision-Making and Model Training Steps: Achieving Efficient and Accurate PTA Method Selection. To reduce training costs while preserving the semantic understanding capabilities of the LLM, a training strategy of "freezing the LLM + optimizing key modules" is adopted: the LLM with its input parameters of cue words incorporating multimodal information is frozen. Leveraging its powerful contextual reasoning capabilities, combined with the "circuit feature-optimal PTA method" mapping learned from example instances, the PTA method classification result is output through a linear output layer. During training, only the parameters of the GNN graph encoder, multimodal alignment module, and output layer are updated. This avoids destroying the semantic capabilities of the LLM pre-training, significantly reduces computational resource consumption, and effectively alleviates overfitting problems in low-data scenarios.

[0029] A transistor-level circuit DC analysis and optimization system based on a graph-enhanced large language model, the system comprising:

[0030] Netlist-to-Graph Conversion Module: Used to convert netlist files of transistor-level circuits into undirected graph representations;

[0031] Topology feature extraction module: Based on graph neural network (GNN), it adopts edge-aware aggregation strategy and gated readout mechanism to extract graph-level topology embedding of circuit diagram;

[0032] Multimodal alignment module: contains a trainable linear projection layer for mapping topological embeddings to the text embedding space of a large language model (LLM);

[0033] The cue word building module is used to generate training and inference cue words.

[0034] PTA method selection module: contains an LLM with frozen parameters and an output layer, used to receive prompt words for fusing multimodal information and output the optimal PTA method.

[0035] An electronic device includes a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor, when executing the program, implements the aforementioned method for DC analysis and optimization of transistor-level circuits based on a graph-enhanced large language model.

[0036] A computer-readable storage medium storing computer instructions thereon, which, when executed by a processor, implement the described method for DC analysis optimization of transistor-level circuits based on a graph-enhanced large language model.

[0037] Compared with the prior art, the present invention has the following significant advantages:

[0038] 1. Achieve automatic PTA method selection, eliminating reliance on manual experience: Through multimodal fusion and few-sample learning, the optimal PTA method can be automatically matched to the target circuit without the need for engineer intervention, raising the level of automation of DC analysis to a new level;

[0039] 2. Precise and efficient topology feature extraction: The combination of EdgeAware aggregation strategy and gated Readout mechanism ensures full utilization of circuit edge information while avoiding loss of topology information, significantly improving the discriminative power of graph-level topology embedding;

[0040] 3. Deep fusion of multimodal information: The text-graph alignment module solves the spatial adaptation problem of topology embedding and text embedding, and the phased prompt word design realizes the effective integration of text semantics and topology structure, improving the model's comprehensive understanding of circuit features;

[0041] 4. Strong generalization ability with low data: The few sample prompts in the inference stage cover all PTA method categories. Combined with the context learning ability of LLM, it can still maintain a high selection accuracy under the condition of limited circuit samples (experimental verification shows 97.14%).

[0042] 5. Significantly improved DC analysis efficiency: Experiments show that the optimal PTA method selected in this invention, compared with the default method of commercial SPICE simulators, accelerates the PTA steps by an average of 2.89 times (up to 12.24 times) and the Newton-Raphson (NR) iterations by an average of 3.45 times (up to 30.39 times), significantly improving the DC analysis efficiency of the circuit.

[0043] 6. Low training cost: By freezing the LLM pre-training parameters and optimizing only a few key modules, the computational resource consumption during the training process is reduced, making it easy to deploy and implement in a conventional hardware environment. Attached Figure Description

[0044] Figure 1 This is a schematic diagram of the overall process of the DC analysis and optimization method for transistor-level circuits based on graph-enhanced large language models.

[0045] Figure 2 This diagram illustrates the equivalent transformation of multi-port devices and the mapping from netlist to structured graph in an embodiment of the present invention. The diagram depicts the T-equivalent transformation process of multi-port devices (MOSFET, BJT) in a transistor-level circuit and the process of converting the circuit netlist into an undirected graph.

[0046] Figure 3This is a detailed schematic diagram illustrating the multimodal prompts used in the training and inference phases of this invention. Detailed Implementation

[0047] The implementation process of the DC analysis optimization method for transistor-level circuits based on graph-enhanced large language models of the present invention will be described in detail below with reference to the accompanying drawings and specific embodiments.

[0048] Example:

[0049] like Figure 1 As shown, this invention proposes an optimization method for DC analysis of transistor-level circuits based on a graph-enhanced large language model. The core of this method is achieved through a technical chain of "circuit topology structured representation - accurate topology feature extraction - multimodal information fusion - low-data context learning," enabling the automatic and efficient selection of the optimal pseudo-transient analysis (PTA) method. The overall process of this method includes: first, converting the transistor-level circuit netlist into a structured undirected graph, and extracting graph-level topology embeddings through a GNN-based graph encoder; then, mapping the topology embeddings to the text embedding space of an LLM through a multimodal alignment module; subsequently, constructing staged few-sample cue words, fusing textual semantic information and topology information into a comprehensive input; finally, inputting the parameter-frozen LLM, outputting the optimal PTA method through the output layer, and using it for circuit DC analysis to improve efficiency. The specific implementation steps of this embodiment are as follows:

[0050] S1: Hardware and Software Environment: The hardware environment in this embodiment uses four NVIDIA GeForce RTX 3090 GPU servers equipped with Intel(R) Xeon(R) Gold 6128 CPU @ 3.40GHz and 24GB of video memory per card. 1TB SSDs are configured to store circuit datasets, netlist files, model parameters, and simulation results. The software environment is built on the Ubuntu 20.04.6 LTS 64-bit operating system and integrates the PyTorch 2.0.1 (with CUDA 11.7) deep learning framework and the commercial SPICE simulator (C-SPICE).

[0051] S2: Dataset Preparation: The dataset in this embodiment selects 164 transistor-level benchmark circuits, covering various typical circuit types such as operational amplifiers (UA741, MOSAMP1), digital-to-analog converters (DAC), multipliers (smult20), logic gate chains (BIPInvchain15), and reference voltage sources (HVRefRCL154), covering different topological complexities and application scenarios; it is divided into a training set (129 circuits) and a test set (35 circuits) in an 8:2 ratio, and the data distribution is ensured to be uniform; DC simulations of the four basic PTA, DPTA, RPTA, and CEPTA methods are performed on each circuit using C-SPICE, and the number of PTA steps and Newton-Raphson (NR) iterations for each method are recorded. The method with the fewest iterations is labeled as the optimal PTA method for that circuit.

[0052] S3: Data Preprocessing and Circuit Topology Construction: In this embodiment, the SPICE netlist file is first parsed to extract circuit node numbers, device types (resistors R, capacitors C, MOSFETs, BJTs, etc.), and device connection relationships. Then, multi-port devices such as MOSFETs and BJTs undergo T-model equivalent transformation according to the small-signal circuit principle to generate an equivalent list of two-port devices. Subsequently, an undirected graph is constructed. Mapping circuit electrical nodes to graph nodes The connections between nodes are mapped as graph edges. And assign a feature vector containing statistics on the number of connected devices to each node (e.g., node...). The feature vector contains information such as "R: 3, C: 5, voltage source: 2", and assigns a feature vector containing device type encoding and the number of parallel connections to each edge (e.g., edge). The feature vector contains information such as "device type code: C, number of parallel connections: 2"); finally, the graph structure is converted into a Data format supported by the DeepGraph Library (DGL) and saved for easy reading by the GNN model.

[0053] S4: Topological Feature Extraction: This module is implemented based on the DGL library. Its core is a 4-layer GNN. The design of this network follows the principles of EdgeAware and gated Readout. The specific implementation is as follows:

[0054] S4-1: Message Passing Layer: Each layer performs EdgeAware message aggregation once. For each node in the diagram... It not only aggregates its neighboring nodes The features will also connect the edges The features are introduced as key information. In specific operations, the node's own features are used... Features of neighboring nodes and edge features The features are concatenated along the feature dimension, then fused and transformed using a neural network (in this embodiment, a fully connected layer with an input dimension of 300*3=900 and an output dimension of 300, with a ReLU function inserted in between) to generate a "message". Finally, the "messages" from all neighbors are aggregated using the sum function and added to the features of the node's previous layer to update the node's features. This process is repeated four times to ensure that information can be fully propagated within a four-hop neighborhood.

[0055] S4-2: Graph-level Readout Layer: After obtaining the final features of all nodes, a graph-level embedding representing the entire circuit needs to be generated. To avoid ambiguity of structural information caused by simple summation or averaging, this embodiment employs a learnable gating weighting strategy. Specifically, for each node's feature vector... It is equipped with a "gated network" consisting of two fully connected layers, which outputs a scalar weight. Then, sort all the node features by Weighted summation yields the final graph-level topological embedding vector. Its dimension is 300.

[0056] S5: Multimodal Embedding Alignment: To enable the topological vectors generated by the GNN to be understood by the LLM, this embodiment uses a trainable linear transformation layer as an adapter. This layer embeds the 300-dimensional graph. Direct linear projection onto the LLM text embedding space yields the output. Its dimensions are consistent with the text embedding dimensions of the selected LLM (LLaMa-2-7B and Vicuna-7B-v1.5 are 4096 dimensions, DeepSeek-R1-Distill-Qwen-7B is 3584 dimensions, and GPT2-Large is 1280 dimensions). The projected vector That is, it is regarded as an embedded representation of a special graph topology token.

[0057] S6: Cue Word Construction: This embodiment employs a phased cue strategy to adapt to different task stages. Training Stage Cue Words: Concise format, directly combining task instructions, target circuit text descriptions, and embedded representations of graph topology tokens. Inference Stage Cue Words (Few Samples): Eight training set circuits are selected as examples. Each example includes a complete text description, an embedded representation of the graph topology token, and its corresponding label. A guiding statement is inserted after each example, followed by the target circuit information to be analyzed. This construction method aims to activate the contextual learning capability of LLM, enabling it to inductively derive the mapping rule of "circuit features - optimal PTA method" from a few examples.

[0058] S7: PTA Method Selection: This module is based on the LLM with frozen parameters (in this embodiment, four models were tested: LLaMa-2-7B, Vicuna-7B-v1.5, DeepSeek-R1-Distill-Qwen-7B, and GPT2-Large). The constructed prompt words are input into the LLM, the output vector of the last hidden layer is taken, and it is mapped to a 4-dimensional class space through a linear classification output layer. Then, the prediction probability distribution of the four PTA methods is obtained through the Softmax function.

[0059] S8: Model Training and Optimization: The cross-entropy loss function was used, the optimizer was AdamW, the initial learning rate was set to 1e-4, and the batch size was 4. During training, only the parameters of the graph encoder (GNN), the multimodal alignment module (linear projection layer), and the output classification layer were updated. The pre-training parameters of the LLM were kept frozen, and the model was trained on the training set for 300 epochs.

[0060] S9: Model Inference and Performance Validation: After training, inference evaluation was performed on 35 independent circuit test sets. The proposed method achieved a 97.14% classification accuracy on the test sets using the PTA method, demonstrating the effectiveness of multimodal fusion and few-shot learning. Subsequently, the optimal PTA method predicted by the model was input into C-SPICE for actual DC simulation and compared with the default PTA method in C-SPICE. Experimental results show that the optimal PTA method recommended in this invention achieves an average speedup of 2.89 times (up to 12.24 times) in the number of PTA steps and an average speedup of 3.45 times (up to 30.39 times) in the number of Newton-Raphson (NR) iterations compared to the default method, significantly improving the computational efficiency of DC analysis.

[0061] S10: Experimental Data Analysis

[0062] Table 1 Comparison of DC analysis efficiency improvement data

[0063]

[0064] S10-1: Table 1 is a graph showing the improvement in DC analysis efficiency brought about by the present invention. Extensive experiments were conducted on 35 transistor-level circuits in the embodiments of the present invention. For each circuit, the performance of the default PTA method of a commercial circuit simulator (C-SPICE) and the predicted optimal PTA method of the present invention were compared in terms of PTA steps and NR counts. In the vast majority of circuits, the present invention effectively reduces the number of PTA steps and NR counts; on average, the present invention can accelerate the number of PTA steps by 2.89 times and the number of NR counts by 3.45 times. The best acceleration effect was observed in the multiplier circuit (smult20) and the bipolar inverter circuit (invbjt), with a maximum acceleration of 12.24 times in the number of PTA steps and a maximum acceleration of 30.39 times in the number of NR counts.

[0065] Table 2. Comparison of the impact of different LLM and context learning methods on the classification accuracy of the PTA method.

[0066]

[0067] S10-2: Table 2 shows the impact of different LLMs and context learning on the classification accuracy of the PTA method in this invention. All experiments in the figure use EdgeAware as the graph encoder, coupled with a gated readout mechanism. Under the 8-sample context learning setting, the performance of several LLMs was compared, including GPT2-Large, LLaMA-2-7B, DeepSeek-R1-Distill-Qwen-7B, and Vicuna-7B-v1.5. The LLaMA-2-7B model achieved the best performance. To further verify the importance of few-sample prompts, this embodiment also compares the performance of the LLaMA-2-7B model under 8-sample and 0-sample settings. The results show that the model performance under the 8-sample setting is significantly better, which confirms that few-sample prompts play a crucial role in guiding the LLM to complete the task.

[0068] Table 3. Comparison of the impact of different graph encoders and Readout strategies on the classification accuracy of the PTA method.

[0069]

[0070] S10-3: Table 3 shows the impact of different graph encoders and Readout strategies on the classification accuracy of the PTA method in this invention. This embodiment compares EdgeAware, Graph Convolutional Network (GCN), Graph Attention Network (GAT), Graph Sampling Aggregation Network (GraphSAGE), and Graph Isomorphism Network (GIN). All experiments were conducted based on the LLaMA-2-7B model with 8-sample cue words. Experimental results show that EdgeAware achieves optimal performance by explicitly incorporating edge features during message passing. Simultaneously, this embodiment also compares the performance of three commonly used Readout strategies (mean, maximum, and summation) with the proposed gated Readout mechanism. Experiments show that the proposed gated Readout strategy achieves the highest accuracy.

[0071] 4. Comparison of the effects of LLM and GNN individually on the classification accuracy of the PTA method

[0072]

[0073] S10-4: Table 4 shows the impact of various LLM and GNNs acting individually on the classification accuracy of the PTA method in this invention. This embodiment conducted ablation experiments on LLM and GNN, and the results verified the performance ceiling of a single module and the synergistic gain of the fusion module.

[0074] Figure 1 This paper presents a schematic diagram of the overall process of optimizing the DC analysis method for transistor-level circuits based on graph-augmented large language models. First, the circuit netlist is mapped to an undirected graph (❶). Then, a high-discrimination topological embedding is extracted using an EdgeAware aggregation strategy and a gated Readout mechanism optimized GNN (❷). Subsequently, spatial alignment between the topological embedding and the LLM text embedding is achieved through a linear projection layer (❸). Staged few-sample prompts are designed to adapt to efficiency and generalization requirements in the training and inference stages, respectively, integrating topological and textual information (❹). Finally, a lightweight training strategy of "freezing LLM + optimizing key modules" is adopted to output the classification results of the PTA method (❺).

[0075] Figure 2 This diagram illustrates the equivalent transformation of multi-port devices and the mapping from netlist to structured graph. The original circuit in the upper left half of the diagram contains multi-port devices such as MOSFETs and BJTs, which would form hyperedges (connecting multiple nodes) in its graph representation. The upper right half uses a T-equivalent model to split these devices into two-port devices, eliminating the hyperedges. The lower left of the diagram shows the mapping from netlist to equivalent elements, and the lower right shows the optimization of the graph structure: the original hyperedge graph is transformed into a standard undirected graph containing only ordinary edges, achieving a concise and standardized representation of the circuit topology, which facilitates subsequent topology feature extraction.

[0076] Figure 3 The composition of multimodal cue words in the training and inference phases is shown.

[0077] It should be noted that the above embodiments are not intended to limit the scope of protection of the present invention. Equivalent transformations or substitutions made based on the above technical solutions all fall within the scope of protection of the claims of the present invention.

Claims

1. A DC analysis and optimization method for transistor-level circuits based on graph-enhanced large language models, characterized in that, Includes the following steps: S1: Circuit Topology Construction: The netlist file of the transistor-level circuit to be analyzed is converted into a structured undirected graph representation. In this representation, nodes in the undirected graph are mapped to electrical nodes in the circuit, and edges are mapped to circuit devices connecting these electrical nodes. Feature vectors containing device type and connection relationships are assigned to both nodes and edges in the graph. S2: Topological Feature Extraction: A graph encoder based on graph neural networks (GNN) is used to extract graph-level topological embeddings from the circuit graph obtained in the circuit topology graph construction step through an edge-aware aggregation strategy and a gated readout mechanism. S3: Multimodal Embedding Alignment: Construct a text-graph alignment module, which maps the topological embeddings obtained from the topological feature extraction step to the text embedding space of the Large Language Model (LLM) through a trainable linear projection layer, generating aligned topological embeddings. S4: Multimodal Prompt Construction: Design a few-shot prompt containing task description, example circuits covering various PTA methods, and target circuit information. The circuit information must explicitly include the circuit name, component statistics, and topology placeholders. The aligned topology embedding obtained in the multimodal embedding alignment step is used to insert these topology placeholders, ultimately forming a comprehensive embedding that integrates textual description and graph topology information, achieving effective integration of multimodal information. S5: Optimization Decision and Model Training: Embed the comprehensive cue words generated in the multimodal cue word construction step into the large language model with frozen parameters; obtain the optimal PTA method category for predicting the target circuit through the output layer of the large language model; update the parameters of the graph encoder, the multimodal embedding aligned linear projection layer and the output layer according to the difference between the prediction results and the real circuit labels to optimize model performance; wherein, the PTA methods include the basic PTA and its variants Damping PTA (DPTA), Ramping PTA (RPTA) and Hybrid Component PTA (CEPTA).

2. The method for DC analysis and optimization of transistor-level circuits based on graph-enhanced large language models according to claim 1, characterized in that, The construction of the S1 circuit topology specifically includes: 1-1. Equivalent Conversion of Multiport Devices: Multiport nonlinear devices (MOSFETs, BJTs) are converted into multiple sets of two-port devices using a T-equivalent small-signal model. 1-2. Graph Structure and Feature Generation: Converting the netlist file of transistor-level circuits into an undirected graph representation. The circuit nodes correspond to the graph node set. The connection relationships between circuit nodes correspond to the graph edge set. For each graph node Assigning feature vectors , For each node feature dimension, the node feature vector contains statistics on the number of various devices (including resistors, independent voltage sources, and independent current sources) connected to that node; for each graph edge... Assigning feature vectors , For edge features, the edge feature vector uniquely identifies the type of connecting devices between corresponding nodes and the number of parallel devices between nodes.

3. The method for DC analysis and optimization of transistor-level circuits based on graph-enhanced large language models according to claim 2, characterized in that, The steps for S2 topological feature extraction are as follows: 2-1: To fully utilize the rich edge information of the graph in the circuit topology graph construction step, EdgeAware incorporates edge information into the information transmission process of the GNN. The EdgeAware aggregation strategy achieves iterative updates of node features in the following ways: in, This represents the current layer number of the GNN. For nodes The set of neighboring nodes, For aggregate functions, This is a mapping function that performs dimensionality reduction using a multilayer perceptron (MLP) after concatenating node embeddings and edge features. For nodes The current GNN layer embedding, and They are nodes , The previous layer of embedding, For the edge eigenvectors. 2-2: The embedded features of each node are dynamically integrated using an adaptive weighting strategy, the expression of which is as follows: in, For graph-level topology embedding, For a set of graph nodes, It is a non-linear activation function. For learnable gating functions based on MLP, For nodes The final embedding.

4. The method for DC analysis and optimization of transistor-level circuits based on graph-enhanced large language models according to claim 1, characterized in that, In the S3 multimodal embedding alignment step, the mathematical expression for the linear projection layer is: in, For graph-level topological embeddings output by GNN, The projection weight matrix is... Represents the field of real numbers OK, The space of real matrices in columns, For bias vectors, The aligned topological embedding has the same dimensions as the text token embedding dimensions in the LLM.

5. The method for DC analysis and optimization of transistor-level circuits based on graph-enhanced large language models according to claim 1, characterized in that, In the S4 multimodal cue word construction process, few-sample cue words are constructed during the training and inference phases as follows: 4-1: Training Phase Cue Word Generation: Generate cue words for model training. Each cue word is specific to a circuit instance and contains only a task description and a target instance portion, without any contextual examples. The target instance portion consists of a text description sub-part and the topology embedding sub-part generated in step 4. 4-2: Inference Stage Cue Generation: Generate few-sample cue words for model inference. Each cue word includes a task description, multiple example instance blocks, and a target instance block. Each instance in the example instance block consists of a text description sub-part, a topological embedding sub-part generated in step 4, and its corresponding PTA method category label. The target instance block has the same format as the example instances but omits the category labels. Guiding text for the classification step is inserted between the example instance blocks and the target instance block. 4-3: Components of the cue word information: The task description sub-part in the cue word generation step during the training and inference phases specifies the overall context and objective of the task selected by the PTA method, and also includes a human-readable summary of circuit names and device composition statistics; the topology embedding sub-part is represented by a pair of specially designed token strings ([Graph Token Start] and [Graph Token End]) as placeholders, and the topology embedding representation generated in step 4... It was inserted between the two marker characters. 4-4: Example Instance Information Composition: Multiple example instances in the prompt word generation step of the inference stage are all selected from the model's training dataset to ensure strict separation from the test data. Furthermore, multiple example instances collectively cover all candidate PTA method categories, thereby enabling the large language model to access all possible prediction results.

6. The method for DC analysis and optimization of transistor-level circuits based on graph-enhanced large language models according to claim 1, characterized in that, In S5, during the optimization decision and model training steps, only the parameters of the graph encoder, multimodal alignment module, and output layer are updated, while the pre-trained parameters of the LLM remain frozen.

7. A DC analysis and optimization system for transistor-level circuits based on a graph-enhanced large language model, used to implement the method described in any one of claims 1-6, the system comprising: Netlist-to-Graph Conversion Module: Used to convert netlist files of transistor-level circuits into undirected graph representations, assigning feature vectors to graph nodes and edges; Topology feature extraction module: Based on graph neural network (GNN), it adopts edge-aware aggregation strategy and gated readout mechanism to extract graph-level topology embedding of circuit diagram; Multimodal alignment module: contains a trainable linear projection layer to map topological embeddings to the text embedding space of a large language model (LLM), thereby aligning text with topological information; The cue word construction module is used to generate training and inference cue words. The cue words include task description, examples of multiple PTA methods, and target circuit information, and reserve topology embedding insertion positions. PTA method selection module: contains an LLM with frozen parameters and an output layer, used to receive prompt words for fusing multimodal information and output the optimal PTA method.

8. An electronic device: comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the program, it implements the transistor-level circuit DC analysis optimization method based on graph-enhanced large language model as described in any one of claims 1 to 7.

9. A computer-readable storage medium storing computer instructions thereon, characterized in that: When executed by the processor, the computer instructions implement the DC analysis and optimization method for transistor-level circuits based on a graph-enhanced large language model as described in any one of claims 1 to 7.

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