Shared memory architecture integrated with register file, data processing method and chip

Abstract

The application provides a shared memory architecture integrated with a register file, a data processing method and a chip, wherein the architecture comprises: a unified physical storage array module, which makes the logical space of the register file and the shared memory share the same storage array through address mapping and access permission control; a mode unification module, which performs address calculation and mode conversion on input instructions to generate control instructions in a unified format; an instruction splitting module, which splits the control instructions into a plurality of sub-requests according to the address distribution of the storage bank; a conflict checking module, which checks the resource conflicts of the sub-requests; and a shared data channel module, which executes the sub-requests and realizes the rearrangement of data between the register file and the shared memory through a unified crossbar network. The application eliminates the dedicated data bus between the register file and the shared memory, reduces the occupation of wiring resources, improves the utilization rate of network resources, and is suitable for vector storage and rearrangement operations in a multi-thread processor.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit design technology, and more specifically, to a shared memory architecture, data processing method, and chip integrated into a register file. Background Technology

[0002] In modern multithreaded processors (such as GPUs, AI accelerators, and network processors), the register file and shared memory are typically separate physical entities. The register file is used to cache thread-private operands, while shared memory is used for data sharing and rearrangement between threads.

[0003] This kind of separation architecture typically has the following problems: 1. Large area overhead: Two independent memory arrays lead to a significant increase in chip area; 2. High overhead of dedicated bus across entities: A dedicated data bus is required to connect the register file and shared memory, which consumes wiring resources and increases path delay; 3. Data rearrangement hardware redundancy: Each of the two storage entities requires an independent crossbar network for data routing and rearrangement, resulting in low hardware resource utilization. 4. Bandwidth bottleneck: The fixed width of the dedicated bus across entities becomes a limiting factor for system throughput; 5. Fixed capacity: The ratio of register file capacity to shared memory capacity is fixed and cannot be dynamically adjusted according to application requirements.

[0004] To address these issues, the industry typically employs methods such as adding cache or optimizing data paths, but these methods cannot fundamentally eliminate the area and power consumption overhead caused by the two storage entities and their dedicated interconnects. Summary of the Invention

[0005] To address the aforementioned shortcomings in the prior art, this invention provides a shared memory architecture, data processing method, and chip integrated into a register file.

[0006] According to a first aspect of the present invention, a shared memory architecture integrated into a register file is provided, comprising: The unified physical storage array module uses a register file containing multiple banks as the basic physical storage space. Through address mapping and access control, any address in the same physical storage array can be resolved to either the register file logical space or the shared memory logical space. The register file logical space and the shared memory logical space physically share the same storage array. The mode unification module is used to perform address calculation and mode conversion on the input instructions to generate control instructions in a unified format. The instruction splitting module is used to split the control instruction into several sub-requests according to the address distribution of the bank; The conflict checking module is used to check for resource conflicts in the sub-requests and merge and send the sub-requests between threads after the check. The shared data path module employs a unified crossbar network to execute the sub-requests and rearrange data between the register file logical space and the shared memory logical space.

[0007] Preferably, in the unified physical storage array module, the register file logical space and the shared memory logical space are physically the same storage space. By modifying the address mapping relationship, the same storage space can be dynamically switched between private access mode and shared access mode.

[0008] Preferably, the mode unification module includes: A format converter unit is used to normalize input instructions with different data widths; The address calculator unit is used to generate a virtual address by performing multi-mode address generation on the normalized input instruction. A mapping preprocessor unit is used to map the virtual address to the physical address of the unified physical memory array module, and to map the register file logic space and the shared memory logic space to different regions of the unified physical memory array module based on the physical address. The instruction packer unit is used to generate instruction packets in a uniform format.

[0009] Preferably, the instruction splitting module includes: The element splitter unit is used to perform bank conflict analysis on a thread-by-thread basis on multiple elements within a thread, splitting an instruction into several sub-requests. The element merger unit is used to identify read operations with the same address within a single thread and merge and distribute them.

[0010] Preferably, the shared data path module has a unified crossbar network that time-multiplexes access to register file logic space and access to shared memory logic space; wherein, the unified crossbar network includes: The first-level crossbar is used to implement data routing from the source logical region to the bank; The second-level crossbar is used to rearrange data from element to element.

[0011] Preferably, the data flow path within the unified physical storage array module is: read from the source location, rearranged via a unified crossbar network, and written to the target location, achieving the following data flow control mode, including: The first mode: Data is read from the source address according to the private access method of the register file logical space, rearranged through a unified crossbar network, and then written to the target address according to the shared access method of the shared memory logical space. The second mode: Data is read from the source address according to the shared access method of the shared memory logical space, rearranged through a unified crossbar network, and then written to the target address according to the private access method of the register file logical space.

[0012] The third mode: Data is read from the source address according to the private access method of the register file logical space, rearranged through a unified crossbar network, and then written to the target address according to the private access method of the register file logical space. The fourth method involves reading data from the source address using the shared access method of the shared memory logical space, rearranging it through a unified crossbar network, and then writing it to the target address using the shared access method of the shared memory logical space.

[0013] According to a second aspect of the present invention, a data processing method for the architecture described in any one of the above claims is provided, comprising: Receive instructions and perform address calculation and mode unification, map logical addresses to physical addresses of unified physical storage array modules, and change access modes so that the same physical address can be resolved into register file logical space or shared memory logical space. The instruction is split into sub-requests based on the bank address distribution; Check for resource conflicts in sub-requests; Sub-requests are executed through the shared data path module. Data is read from the source logical area, rearranged through a unified crossbar network, and written to the target logical area. All operations are completed within the same storage array.

[0014] According to a third aspect of the present invention, a chip is provided that integrates the shared memory architecture integrated into the register file as described in any one of the above-described inventions.

[0015] By adopting the above technical solution, the present invention has at least one of the following beneficial effects compared with the prior art: The shared memory architecture integrated into the register file provided by this invention allows the shared memory and the register file to share the same physical storage array, saving more than 30% of chip area and effectively realizing the reuse of storage entities.

[0016] The shared memory architecture integrated into the register file provided by this invention eliminates the need for a dedicated data bus between the register file and the shared memory, reducing wiring resource consumption and path delay, and achieving the elimination of dedicated buses across entities.

[0017] The shared memory architecture integrated into the register file provided by this invention allows for time-division multiplexing of the unified crossbar network for register file access and shared memory access, saving more than 40% of hardware overhead compared to two independent crossbars and achieving crossbar resource sharing.

[0018] The shared memory architecture integrated into the register file provided by this invention allows data to be read, rearranged, and written within the same storage array without the need for cross-module transmission, reducing access latency and shortening the data migration path.

[0019] The shared memory architecture integrated into the register file provided by this invention enables dynamic switching between private access mode and shared access mode of the same memory space by modifying the address mapping relationship, adapting to different application needs and achieving flexible capacity configuration.

[0020] The shared memory architecture integrated into the register file provided by this invention adopts unified control logic, simplifies the memory access control circuit, and reduces design complexity. Attached Figure Description

[0021] Other features, objects, and advantages of the present invention will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings: Figure 1 This is a schematic diagram of a shared memory architecture integrated into a register file in a preferred embodiment of the present invention.

[0022] Figure 2 This is a schematic diagram illustrating the working principle of a shared memory architecture integrated into a register file in a preferred embodiment of the present invention.

[0023] Figure 3 This is a flowchart of a data processing method based on a shared memory architecture integrated into a register file, according to a preferred embodiment of the present invention. Detailed Implementation

[0024] The embodiments of the present invention are described in detail below: These embodiments are implemented based on the technical solution of the present invention, and provide detailed implementation methods and specific operation processes. It should be noted that those skilled in the art can make several modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention.

[0025] In existing technologies, register files and shared memory are typically separate physical entities. This separate architecture suffers from problems such as large area overhead, large overhead of dedicated buses across entities, hardware redundancy in data rearrangement, bandwidth bottlenecks, and fixed capacity. To address these issues, the art has also employed methods such as adding caches or optimizing data paths, but these methods cannot fundamentally eliminate the area and power consumption overhead caused by the two sets of storage entities and their dedicated interconnects.

[0026] To address the aforementioned issues, one embodiment of the present invention provides a shared memory architecture integrated into a register file. This architecture integrates the shared memory into the same physical storage array as the register file through physical reuse of storage entities and sharing of data paths, eliminating the overhead of two independent storage arrays and their dedicated interconnections. At the same time, it improves resource utilization by realizing data rearrangement through a unified crossbar network, thus realizing a shared memory architecture for multi-threaded processors, and in particular a storage multiplexing structure physically integrated with the register file.

[0027] Specifically, such as Figure 1 As shown, the shared memory architecture integrated into the register file provided in this embodiment may include: The unified physical storage array module uses a register file containing multiple banks as the basic physical storage space. Through address mapping and access control, any address in the same physical storage array is resolved to the register file logical space in thread-private access mode and to the shared memory logical space in thread-shared access mode. The register file logical space and the shared memory logical space physically share the same storage array and have no independent physical partitions. The mode unification module is used to perform address calculation and mode conversion on the input instructions to generate control instructions in a unified format. The instruction splitting module is used to split control instructions into several sub-requests based on the address distribution of the bank. The conflict checking module is used to check for resource conflicts in sub-requests and merge and send the sub-requests between threads after the check. The shared data path module uses a unified crossbar network to execute sub-requests and rearrange data between the register file logical space and the shared memory logical space.

[0028] In some preferred embodiments, in the above-mentioned unified physical storage array module, the register file logical space and the shared memory logical space are physically the same storage space. By modifying the address mapping relationship, the same storage space can be dynamically switched between private access mode and shared access mode.

[0029] In some preferred embodiments, the above-mentioned mode unification module may further include: A format converter unit is used to normalize input instructions with different data widths; The address calculator unit is used to generate a virtual address by performing multi-mode address generation on the normalized input instruction. The mapping preprocessor unit is used to map virtual addresses to physical addresses of the unified physical memory array module, and to map the register file logic space and shared memory logic space to different regions of the unified physical memory array module based on the physical addresses. The instruction packer unit is used to generate instruction packets in a uniform format.

[0030] In some preferred embodiments, the address calculator unit, which generates multi-mode addresses for the normalized input instructions, may further include: Based on the instruction type and operand access mode, generate the base address per thread, the offset address within the thread, and the offset address per element; where: Instruction types include normal vector memory access mode and GATHER / SCATTER mode; in normal vector memory access mode, the offset address of each element is the product of the element number and the data width; in GATHER / SCATTER mode, the offset address of each element is generated by the value of the corresponding element in the vector register of source operand 2 through granularity and sign control operations to achieve vectorized memory access of non-contiguous addresses. Operand access mode is configured in a fine-grained manner for each operand through the following control bits: Granularity control bit, used to select whether to multiply the operand value by the data width; The sign control bit is used to select whether the operand is signed or unsigned. Address width control bits are used to select a 32-bit, 64-bit, or 16-bit address width; Data source type, used to select whether the operand comes from an immediate value, a scalar register, or a vector register; The base address of each thread is obtained by operating on the sign extension value of the source operand 1 and the granularity value, and is controlled by the address type and address width. The intra-thread offset address is generated by granular and sign control operations on the first element of the immediate value of the source operand 2, the scalar register, or the vector register, depending on the instruction type.

[0031] In some preferred embodiments, the mapping preprocessor unit, which maps virtual addresses to physical addresses of the unified physical storage array module, may further include: The virtual address is decomposed into bank ID, bank internal address and warpID. Through virtual address interleaving mapping, the decomposed virtual address is mapped to the physical storage layout of the unified physical storage array module to form the physical address of the unified physical storage array module.

[0032] In some preferred embodiments, the instruction splitting module may further include: The element splitter unit is used to perform bank conflict analysis on a thread-by-thread basis on multiple elements within a thread, splitting an instruction into several sub-requests. The element merger unit is used to identify read operations with the same address within a single thread and merge and distribute them.

[0033] In some preferred embodiments, the shared data path module described above has a unified crossbar network that time-multiplexes access to the register file logical space and access to the shared memory logical space; wherein, the unified crossbar network may further include: The first-level crossbar is used to implement data routing from the source logical region to the bank; The second-level crossbar is used to rearrange data from element to element.

[0034] In some preferred embodiments, the data flow path within the unified physical storage array module is: read from the source location → rearranged via a unified crossbar network → written to the target location, achieving the following data flow control mode, including: The first mode (private write → shared read, v → m mode): Data is read from the source address according to the private access method of the register file logical space, rearranged through a unified crossbar network, and then written to the target address according to the shared access method of the shared memory heap logical space; The second mode (shared write → private read, m → v ​​mode): Data is read from the source address according to the shared access method of the shared memory heap logical space, rearranged through a unified crossbar network, and then written to the target address according to the private access method of the register heap logical space. The third mode (private write → private read, v → v mode): Data is read from the source address according to the private access method of the register file logical space, rearranged through a unified crossbar network, and then written to the target address according to the private access method of the register file logical space. The fourth mode: (shared write → shared read, m → m mode): Data is read from the source address according to the shared access method of the shared memory logical space, rearranged through a unified crossbar network, and then written to the target address according to the shared access method of the shared memory logical space.

[0035] Based on the shared memory architecture provided in the above embodiments of the present invention, an embodiment of the present invention also provides a corresponding data processing method.

[0036] Specifically, such as Figure 3 As shown, the data processing method provided in this embodiment may further include: S1 receives instructions and performs address calculation and mode unification, mapping logical addresses to physical addresses of unified physical storage array modules. By changing the access mode, the same physical address can be resolved into register file logical space or shared memory logical space. S2, split the instruction into sub-requests based on the bank address distribution; S3, check for resource conflicts in sub-requests; S4 executes sub-requests through the shared data path module. Data is read from the source logical space, rearranged through a unified crossbar network, and written to the target logical space. All operations are completed within the same storage array.

[0037] In some preferred embodiments, the above-mentioned S1 may further include: S11 receives the input instruction and its operand information, and buffers the instruction; S12, based on instruction type, data width, address width and granularity mode, performs multi-mode address calculation of base address, in-thread offset and per-element offset to generate a virtual address in a unified format; S13 decomposes the virtual address into bank ID, bank address and warp ID through virtual address interleaving mapping, and maps the register file logic space and shared memory logic space to different areas of the same physical memory array. It outputs an instruction packet containing physical address and unified control information, providing a unified address and control reference for subsequent splitting steps.

[0038] In some preferred embodiments, the above-mentioned S2 may further include: S21, based on the distribution of the physical addresses of each element generated in S1 on the bank, performs bank conflict analysis instruction by instruction; S22 splits an instruction with a bank conflict into several sub-requests without bank conflicts; at the same time, it identifies read operations with the same address within the same thread and merges them into a single sub-request for distribution to reduce redundant access. S23, after the split is completed, output the sub-request sequence and release the instruction flow control signal for upstream modules to perform flow control management; S24, the element mapping relationship, read / write port information and shift control signal in the split result, provide input basis for subsequent conflict checking and data path execution.

[0039] In some preferred embodiments, the above-mentioned S3 may further include: S31, Receive the sub-request sequence generated by S2, and perform resource conflict detection on each sub-request, including: historical conflict detection, that is, check the single-port occupation conflict on the memory bank and the data path write port occupation conflict between the current sub-request and the sub-request that is being executed or scheduled. S32, Current Conflict Detection, which checks for read / write conflicts of multiple sub-requests within the same timeframe on the same bank and data path read / write port conflicts; further, for read requests with the same address and / or the same data shift mode, they are determined to be able to be sent via a shared request and are not counted as conflicts. S33. Sub-requests that are determined to be conflict-free after conflict checking are allowed to be sent to the data path for execution; otherwise, they will be blocked or retried, thus ensuring the orderly scheduling of resources.

[0040] In some preferred embodiments, the above-mentioned S4 may further include: S41 receives the conflict-free sub-request issued by S3 and determines the data flow direction according to the instruction type (from register file logical space to shared memory logical space, or from shared memory logical space to register file logical space); S42, for operations from register file logic space to shared memory logic space, data enters the data path along with the instruction, and after the thread-to-bank and element-to-element rearrangement is completed through a two-level unified crossbar network, it is written to the target shared memory logic space. S43, for operations from shared memory logical space to register file logical space, the instruction first enters the data path, and after delay control, a read request is initiated. The read data is rearranged from bank to thread and from element to element through the same unified crossbar network, and then waits in the corresponding thread until all element data is reclaimed before being written to the register file logical space. S44: All read and write operations are completed within a unified physical storage array, and a response is returned synchronously after the sub-request is executed, allowing the upstream module to confirm the completion of the instruction.

[0041] It should be noted that the steps in the method provided by the present invention can be implemented using the corresponding components in the system. Those skilled in the art can refer to the technical solution of the system to implement the steps of the method, and can also refer to the technical solution of the method to implement the composition of the system. That is, the embodiments in the system and the embodiments in the method can be understood as preferred examples of each other, which will not be elaborated here.

[0042] Based on the shared memory architecture provided in the above embodiments of the present invention, an embodiment of the present invention also provides a chip that integrates the shared memory architecture of any one of the above embodiments of the present invention.

[0043] The shared memory architecture integrated into the register file provided in the above embodiments of the present invention physically integrates the shared memory into the processor's register file, sharing the same physical storage array with the register file. It achieves cross-thread data access through address mapping and realizes physical reuse of storage entities and data path sharing through a unified shared data path. This eliminates the overhead of two independent storage arrays and their dedicated interconnections. Simultaneously, it improves resource utilization by enabling data rearrangement between regions through a unified crossbar network. The specific working principle is as follows: Figure 2 As shown, programmers believe that inter-thread storage can be interleaved according to a certain data granularity and range, and the purpose of virtual address mapping is to map virtual addresses to physical storage addresses. Therefore, the information actually contained in a virtual address is {high bits of the warp_bank address, warpid, bankid, low bits of the warp_bank address}. Figure 2 For example, virtual addresses are interleaved in 16B blocks and mapped to the actual 32B 16-bank.

[0044] In the above embodiments of the present invention: The unified physical storage array module contains multiple banks, and the shared storage and register file data are all located in the same storage array without boundaries.

[0045] The mode unification module receives instruction information, performs address calculation, mode unification, and virtual address mapping, and outputs control information in a unified format to reuse data paths. It also supports unified processing of multiple data widths (8 / 16 / 32bit) and address widths, as well as virtual address interleaving mapping, which maps virtual addresses to physical bank addresses and addresses within the bank. The address mapping is based on a unified physical storage array layout, mapping the logical address space of the shared memory to the physical storage space.

[0046] The instruction splitting module splits instructions into multiple sub-requests based on the distribution of memory access addresses in the bank, and merges accesses to the same address. It supports the merging and issuing of read operations to the same address within and between threads, and outputs the mapping relationship between the elements of the sub-requests, read / write port information, and shift control signals.

[0047] The conflict checking module examines resource conflicts between threads and their sub-requests, including bank access conflict detection and data path resource conflict detection; and merges and distributes the sub-requests between threads after the check. Specifically, it includes the following detection mechanisms: 1. Historical Conflict Detection Historical conflict detection is used to determine whether there is a resource contention between the current sub-request and sub-requests that have been issued but not yet completed, including: Bank access conflict detection: Maintain a record table of the occupancy status of each sub-bank in the future for several periods. Based on the access type (read / write), target bank ID and access period of the sub-request, compare it with the future occupancy information in the record table. If there is a read-write or write-write conflict in the same bank in the same period, it is determined to be a bank access conflict. Data path write port conflict detection: Since the write port occupancy delays of the two types of instructions, v→m and m→v, in the data path are different, the conflict detection module records the occupancy period of the write port for the two types of instructions respectively; when the write port occupancy period of the current sub-request overlaps with the write port occupancy period of the scheduled sub-request, it is determined to be a write port resource conflict.

[0048] 2. Current Conflict Detection Current conflict detection is used to determine resource contention between multiple sub-requests within the same timeframe, including: Same bank read / write conflict detection: If multiple sub-requests initiated within the same clock cycle have the same target bank ID and the access type has a read / write conflict, they are determined to be bank access conflicts. Data path read / write port conflict detection: Each bank is equipped with only one read port and one write port. When multiple sub-requests within the same time frame initiate read or write operations on the same bank, it is determined to be a read / write port resource conflict. The "piggybacking" read mechanism is a special conflict avoidance method. When multiple sub-requests have the same read address and the same data shifting pattern, they are determined to be able to be piggybacked. That is, only one read request is sent, and the read data is broadcast to satisfy the read needs of multiple threads at the same time. This situation is not counted as a conflict.

[0049] 3. Generation of collision detection results The conflict checking module summarizes the above detection results and generates a conflict determination flag for each sub-request, including: No conflict: Sub-requests can be immediately sent to the data path for execution; Resource conflict: The sub-request is blocked and will be retried after the resource is released; Read-by-the-ride matching: Sub-requests are not sent separately; data is obtained through data broadcasting after the matched read request is completed.

[0050] After inspection, inter-thread sub-requests can be merged and sent according to the following scheduling mechanism, the specific scheduling mechanism is as follows: 1. Scheduling of conflict-free sub-requests When a sub-request is determined to be conflict-free, the conflict checking module immediately sends it to the data path for execution and updates the resource usage record table synchronously, providing a basis for conflict detection of subsequent sub-requests; the sending order follows the original splitting order of the sub-requests to ensure the orderliness of storage access.

[0051] 2. Scheduling of resource conflict sub-requests When a sub-request is determined to have a resource conflict, the conflict checking module temporarily stores it in the blocking queue and does not send it down. The conflict checking module continuously monitors the status of the conflicting resources. When the occupied resources are released (i.e., the occupancy mark for the corresponding period in the record table is cleared), the conflict checking of the blocked sub-request is performed again. If the check passes again, the sub-request is sent down for execution. During the blocking period, subsequent non-conflicting sub-requests can continue to be sent down to maximize resource utilization efficiency.

[0052] 3. Hop-in Read Matching Scheduling When multiple read requests meet the conditions for piggybacking reads, the conflict checking module only issues a representative sub-request to the data path for execution, and the remaining matching read requests are not issued separately. After the representative sub-request is executed, the read data is broadcast to all matching threads through a unified crossbar network. The scheduling module records the mapping relationship between each thread and the representative sub-request to ensure that the data can be correctly distributed to the target thread.

[0053] 4. Scheduling in scenarios with multiple interleaved instructions For scenarios where multiple instructions are issued consecutively, the conflict checking module maintains a global resource occupancy view and comprehensively handles the conflict relationships between sub-requests from different instructions and threads. Through joint detection of historical conflicts and current conflicts, it achieves accurate identification and scheduling of resource conflicts in complex and intertwined scenarios, ensuring the orderly execution of storage access.

[0054] The shared data path module executes the split sub-requests, including a unified crossbar network that supports thread-to-bank / bank-to-thread and element-to-element reassembly. It supports four data flow directions: v→m, m→v, v→v, and m→m. The crossbar network uses time-division multiplexing of register file access and shared memory access, eliminating the need for separate crossbars for two logical regions. The data flow path within the unified storage array is: read from source location → rearranged via the unified crossbar network → written to target location; all operations are completed within the same physical storage array. It also includes a response path module, which returns a response after all instructions are completed.

[0055] Furthermore, the data flow control modes implemented through the above architecture include: v→m mode (private write → shared read): Instruction first, data is read from the source address according to the private access method of the register file logical space, rearranged through a unified crossbar network, and written to the target address according to the shared access method of the shared memory logical space. m→v mode (shared write → private read): Instruction first, data is read from the source address according to the shared access mode of the shared memory logical space, rearranged through a unified crossbar network, and written to the target address according to the private access mode of the register file logical space. v→v mode (private write → private read): Instruction first, data is read from the source address according to the private access method of the register file logical space, rearranged through a unified crossbar network, and then written to the target address according to the private access method of the register file logical space. m→m mode (shared write → shared read): Instructions are executed first. Data is read from the source address according to the shared access method of the shared memory logical space. After being rearranged by a unified crossbar network, it is written to the target address according to the shared access method of the shared memory logical space.

[0056] In all four data flow control modes, data flows within the same physical storage array. Data interaction is completed through read-reorder-write, enabling cross-thread data access. Furthermore, the reordering operation is performed by the same crossbar network.

[0057] The shared memory architecture, data processing method, and chip integrated with the register file provided in the above embodiments of the present invention achieve a shared memory architecture for multi-threaded processors, particularly a memory multiplexing structure physically integrated with the register file, through the synergistic effect of a unified physical storage array module, a unified mode module, an instruction splitting module, a conflict checking module, and a shared data path module. The shared memory is a virtual concept with no physical storage entity, but it is a completely identical physical storage array to the register file. Cross-thread data access interaction is achieved through address mapping, forming the shared memory concept. The data path module includes a unified crossbar network, which time-division multiplexes register file access and shared memory access, enabling data read-reordering-write between regions. This invention eliminates the dedicated data bus between the register file and the shared memory, saving more than 30% of chip area, reducing wiring resource consumption, and improving crossbar resource utilization. It is suitable for vector storage and reordering operations in multi-threaded processors.

[0058] Any matters not covered in the above embodiments of the present invention are well-known in the art.

[0059] The specific embodiments of the present invention have been described above. It should be understood that the present invention is not limited to the specific embodiments described above, and those skilled in the art can make various modifications or variations within the scope of the claims, which do not affect the essence of the present invention.

Claims

1. A shared memory architecture integrated into a register file, characterized in that, include: A unified physical storage array module uses a register file containing multiple banks as the basic physical storage space. Through address mapping and access control, any address in the same physical storage array can be resolved to either the register file logical space or the shared memory logical space. The register file logical space and the shared memory logical space physically share the same storage array. The mode unification module is used to perform address calculation and mode conversion on the input instructions to generate control instructions in a unified format. The instruction splitting module is used to split the control instruction into several sub-requests according to the address distribution of the bank; The conflict checking module is used to check for resource conflicts in the sub-requests and merge and send the sub-requests between threads after the check. The shared data path module employs a unified crossbar network to execute the sub-requests and rearrange data between the register file logical space and the shared memory logical space.

2. The shared memory architecture integrated into the register file according to claim 1, characterized in that, In the unified physical storage array module, the register file logical space and the shared memory logical space are physically the same storage space. By modifying the address mapping relationship, the same storage space can be dynamically switched between private access mode and shared access mode.

3. The shared memory architecture integrated into the register file according to claim 1, characterized in that, The mode unification module includes: A format converter unit is used to normalize input instructions with different data widths; The address calculator unit is used to generate a virtual address by performing multi-mode address generation on the normalized input instruction. A mapping preprocessor unit is used to map the virtual address to the physical address of the unified physical memory array module, and to map the register file logic space and the shared memory logic space to different regions of the unified physical memory array module based on the physical address. The instruction packer unit is used to generate instruction packets in a uniform format.

4. The shared memory architecture integrated into the register file according to claim 3, characterized in that, The address calculator unit performs multi-mode address generation on the normalized input instruction, including: Based on the instruction type and operand access mode, generate the base address per thread, the offset address within the thread, and the offset address per element; where: The instruction types include normal vector memory access mode and GATHER / SCATTER mode; in normal vector memory access mode, the offset address of each element is the product of the element index and the data width; in GATHER / SCATTER mode, the offset address of each element is generated by the value of the corresponding element in the vector register of source operand 2 through granularity and sign control operations to realize vectorized memory access of non-contiguous addresses. The operand access mode is configured with fine-grained precision for each operand through the following control bits: Granularity control bit, used to select whether to multiply the operand value by the data width; The sign control bit is used to select whether the operand is signed or unsigned. Address width control bits are used to select a 32-bit, 64-bit, or 16-bit address width; Data source type, used to select whether the operand comes from an immediate value, a scalar register, or a vector register; The base address of each thread is obtained by operating on the sign extension value and granularity value of source operand 1, and combined with address type and address width control; the offset address within the thread is generated by operating on the first element of the immediate value, scalar register or vector register of source operand 2, according to the instruction type, through granularity and sign control.

5. The shared memory architecture integrated into the register file according to claim 3, characterized in that, The mapping preprocessor unit maps the virtual address to the physical address of the unified physical storage array module, including: The virtual address is decomposed into bank ID, bank internal address and warpID. Through virtual address interleaving mapping, the decomposed virtual address is mapped to the physical storage layout of the unified physical storage array module to form the physical address of the unified physical storage array module.

6. The shared memory architecture integrated into the register file according to claim 1, characterized in that, The instruction splitting module includes: The element splitter unit is used to perform bank conflict analysis on a thread-by-thread basis on multiple elements within a thread, splitting an instruction into several sub-requests. The element merger unit is used to identify read operations with the same address within a single thread and merge and distribute them.

7. The shared memory architecture integrated into the register file according to claim 1, characterized in that, The shared data path module has a unified crossbar network that time-multiplexes access to register file logic space and access to shared memory logic space; wherein, the unified crossbar network includes: The first-level crossbar is used to implement data routing from the source logical region to the bank; The second-level crossbar is used to rearrange data from element to element.

8. The shared memory architecture integrated into the register file according to claim 7, characterized in that, The data flow path within the unified physical storage array module is as follows: read from the source location, rearranged via a unified crossbar network, and written to the target location, achieving the following data flow control model, including: The first mode: Data is read from the source address according to the private access method of the register file logical space, rearranged through a unified crossbar network, and then written to the target address according to the shared access method of the shared memory logical space. The second mode: Data is read from the source address according to the shared access method of the shared memory logical space, rearranged through a unified crossbar network, and then written to the target address according to the private access method of the register file logical space. The third mode: Data is read from the source address according to the private access method of the register file logical space, rearranged through a unified crossbar network, and then written to the target address according to the private access method of the register file logical space. The fourth mode: Data is read from the source address according to the shared access method of the shared memory logical space, rearranged through a unified crossbar network, and then written to the target address according to the shared access method of the shared memory logical space.

9. A data processing method for the architecture described in any one of claims 1-8, characterized in that, include: Receive instructions and perform address calculation and mode unification, map logical addresses to physical addresses of unified physical storage array modules, and change access modes so that the same physical address can be resolved into register file logical space or shared memory logical space. The instruction is split into sub-requests based on the bank address distribution; Check for resource conflicts in sub-requests; Sub-requests are executed through the shared data path module. Data is read from the source logical area, rearranged through a unified crossbar network, and written to the target logical area. All operations are completed within the same storage array.

10. A chip, characterized in that, The shared memory architecture integrated into the register file as described in any one of claims 1-8 is integrated.

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