Chip area constraint legality checking method, electronic device and storage medium

Abstract

The present disclosure relates to a chip region constraint legality checking method, an electronic device and a storage medium. The method comprises: obtaining a target type of physical resources to be checked in a chip; dividing the physical resources of the target type in the chip into multiple groups according to a cascading relationship between the physical resources, so that the physical resources in the same group are continuously adjacent in the cascading direction; performing a segmentation operation according to the boundaries of each region constraint, obtaining segmentation information of the multiple groups in each region constraint, and recording the resource capacity of each segment; establishing a linear programming model; solving the linear programming model, if there is a feasible solution, determining that the region constraint legality checking of the physical resources of the target type is passed, otherwise, determining that it is not passed. In this way, the region constraint legality checking in complex scenarios such as multi-region overlap and different logic unit cascading heights can be accurately implemented, and only the feasibility needs to be judged without optimization, and the checking efficiency is considered.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, specifically to a method for checking the legality of regional constraints of a chip, an electronic device, and a storage medium. Background Technology

[0002] In the FPGA placement process, logic cells may be subject to region constraints (derived from user constraint files) to limit their distribution within the chip placement plane. A region may constrain multiple logic cells, and sufficient physical resources must be available within that region; otherwise, placement will fail. Furthermore, logic cells can be vertically cascaded through ports to form larger logic cells, and different numbers of cascades can result in logic cells of varying heights. Cascaded logic cells must be placed on a contiguous segment of physical resources (i.e., cascade lines exist between adjacent physical resources). If cascaded logic cells have region constraints, the height of these constraints must meet the cascading requirements. Therefore, a region constraint validity check is required before placement begins to verify that the region constraints meet resource and cascading height requirements.

[0003] Traditional region constraint validity checks typically employ a greedy approach, performing resource capacity and cascading height checks on each region separately. If multiple regions overlap, they are merged into a new region and checked thereafter. A validity check is considered successful if all checks pass. However, this method is inefficient and cannot handle complex scenarios with overlapping regions and varying logical unit cascading heights. It may even result in a valid validity check passing while subsequent layout processes fail. Summary of the Invention

[0004] Therefore, it is necessary to provide a chip region constraint validity checking method, electronic device, and storage medium capable of accurately checking the validity of region constraints in scenarios with multiple overlapping regions and different cascading heights, addressing the aforementioned technical problems. The following mainly introduces several aspects involved in this disclosure: Firstly, this application provides a method for checking the legality of region constraints in a chip, including: Obtain the target type of the physical resource to be inspected in the chip; Based on the cascading relationship between physical resources, the physical resources of the target type in the chip are divided into multiple groups, so that the physical resources in the same group are continuously adjacent in the cascading direction. Perform segmentation operations based on the boundaries of each region constraint to obtain segmentation information of the multiple groups within each region constraint, wherein each segment is a continuous physical resource interval within the same group defined by the boundary of the region constraint, and record the resource capacity of each segment; Establish a linear programming model; the linear programming model includes: a binary decision variable between a logical unit constrained by a region and using physical resources of the target type and each segment; a uniqueness constraint that each logical unit can be assigned to only one segment; and a resource capacity constraint for each segment, wherein the resource capacity constraint requires that the total resource demand of all logical units assigned to the same segment does not exceed the resource capacity of the corresponding segment; Solve the linear programming model. If a feasible solution exists, the validity check of the regional constraints on the physical resources of the target type is deemed to have passed; otherwise, it is deemed to have failed.

[0005] In a second aspect, this application provides an electronic device, including: a memory and a processor, wherein the memory stores a processing program, and the processing program, when executed by the processor, implements the method described in the first aspect above.

[0006] Thirdly, this application provides a storage medium storing a processing program, which, when executed by a processor, implements the method described in the first aspect above.

[0007] This embodiment of the invention determines the legality of regional constraints by grouping physical resources of the target type in the chip according to cascading relationships, segmenting them according to regional constraint boundaries, and establishing a linear programming model containing binary decision variables, uniqueness constraints, and resource capacity constraints to solve feasible solutions. This enables accurate checks on the legality of regional constraints in complex scenarios such as multiple overlapping regions and different cascading heights of logic units, avoiding misjudgments by traditional greedy methods. At the same time, it only requires feasibility checks without optimization, thus balancing checking efficiency. Attached Figure Description

[0008] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application. To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, those skilled in the art can obtain other drawings based on these drawings without any creative effort.

[0009] Figure 1 This is a schematic flowchart illustrating the method for checking the legality of region constraints of a chip according to an embodiment of this disclosure.

[0010] Figure 2 This is a schematic diagram of physical resource grouping shown in an embodiment of this disclosure.

[0011] Figure 3 This is a segmented schematic diagram illustrating an embodiment of this disclosure. Detailed Implementation

[0012] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. In the following description relating to the drawings, unless otherwise indicated, the same numerals in different drawings denote the same or similar elements.

[0013] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element. Furthermore, components, features, and elements with the same names in different embodiments of this application may have the same meaning or different meanings, the specific meaning of which must be determined by its interpretation in that specific embodiment or further in conjunction with the context of that specific embodiment.

[0014] It should be understood that although the steps in the flowcharts of the embodiments of this application are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some of the steps in the figures may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but can be executed at different times, and their execution order is not necessarily sequential, but can be executed in turn or alternately with other steps or at least some of the sub-steps or stages of other steps. The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments.

[0015] See Figure 1 This is a flowchart illustrating a method for checking the legality of region constraints in a chip according to an embodiment of this application. This method can be executed by a device for checking the legality of region constraints in a chip according to an embodiment of this application. This device can be implemented in software and / or hardware, such as electronic devices like computers or servers. In this embodiment, the executing entity of the method is an electronic device. The method provided in this embodiment includes: Step S101: Obtain the target type of the physical resource to be inspected in the chip.

[0016] In this embodiment, an FPGA chip is used as an example. An FPGA chip contains various types of physical resources, such as lookup tables (LUTs), flip-flops (FFs), block RAM (BRAM), and digital signal processing units (DSPs). Each physical resource has a specific function, and some physical resources can be connected in series via dedicated cascading lines to construct logic functions with larger bit widths or deeper levels. A physical resource refers to the smallest actual unit on the chip that can be configured to implement a specific logic function, such as a LUT or a BRAM block. The physical resources to be checked refer to all instances of physical resources in the chip that belong to the type of resource to be checked. The target type refers to the type selected from all physical resource types that currently needs to be checked for validity.

[0017] It is understandable that, since the cascading relationships between different types of physical resources are independent, and only some types of physical resources have cascading requirements and are subject to regional constraints, the target type of the physical resources to be inspected in the chip can be obtained first to narrow down the inspection scope, avoid unnecessary linear programming modeling for irrelevant resource types, and improve overall inspection efficiency. For example, only those physical resource types whose corresponding logic units have cascading requirements and are subject to regional constraints need to be inspected.

[0018] In some embodiments, step S101: obtaining the target type of the physical resource to be inspected in the chip includes: All logic units are classified according to the type of physical resources required by each logic unit in the chip design, resulting in at least one type of logic unit. The type of physical resources required by the target type logic unit that meets the preset conditions is defined as the target type. The target type logic unit can be any type of logic unit. The preset conditions include: some or all logic units need to be implemented by corresponding physical resources through cascading, and some or all logic units have regional constraints.

[0019] In an FPGA chip, the chip design consists of multiple logic units. A logic unit is a functional module in the chip design that needs to be mapped onto physical resources, such as an adder, a register set, or a memory controller. Each logic unit requires a specific type of physical resource (such as a LUT or BRAM) during implementation and may have cascading requirements (e.g., multiple physical resources of the same type need to be connected in series via cascading lines to form a larger bit width).

[0020] Based on the physical resource type required by each logic unit in the chip design (e.g., Lookup Table (LUT), Block RAM (BRAM), Digital Signal Processing Unit (DSP), etc.), logic units with the same required physical resource type can be grouped into one category, thus obtaining at least one category of logic units. For example, all logic units using LUT resources constitute LUT-class logic units, and all logic units using BRAM resources constitute BRAM-class logic units. For any category of logic units, i.e., the target category of logic units, if the following conditions are met simultaneously: some or all logic units in this category need to be implemented by cascading corresponding physical resources, and some or all logic units in this category have regional constraints, then the type of physical resource required by this category of logic units is determined as the target type. Cascading means that the logic unit needs to connect multiple resources of the same type using dedicated cascading lines between physical resources. For example, multiple cascaded LUTs form a larger-width lookup table, or multiple cascaded BRAMs form a larger memory block. The cascading direction can be vertical (within the same column) or horizontal (within the same row). Region constraints refer to the requirements specified by the user through a constraint file, which restrict the placement of logic units within a certain physical region (such as certain rows or columns of a chip). Typically, this is a rectangular region specified by the constraint file (defined by the row and column boundaries).

[0021] In this way, by classifying logical units according to the required physical resource types and selecting those that simultaneously meet the preset conditions as target types, subsequent checks are performed only on the necessary resource types, reducing unnecessary linear programming modeling and solving, and further improving the overall checking efficiency.

[0022] Step S102: Based on the cascading relationship between physical resources, divide the physical resources of the target type in the chip into multiple groups, so that the physical resources in the same group are continuously adjacent in the cascading direction.

[0023] In this context, cascading refers to the interconnection of similar physical resources via dedicated cascade lines. These cascade lines are pre-laid metal traces within the chip, used to directly connect the output of one physical resource to the input of an adjacent physical resource. The cascading direction refers to the routing of the cascade lines between physical resources. Depending on the FPGA chip architecture, cascade lines can be arranged vertically or horizontally. Vertical cascading means the cascade line extends perpendicularly along the column direction of the chip, meaning there is a cascade line between adjacent physical resources in the same column. Horizontal cascading means the cascade line extends horizontally along the row direction of the chip, meaning there is a cascade line between adjacent physical resources in the same row. It should be noted that the method provided in this embodiment only supports scenarios where the cascading direction is vertical or horizontal, but does not support scenarios with a mixture of both directions.

[0024] Specifically, after determining the target type of the physical resource to be inspected (e.g., LUT or BRAM), all physical resources of that type on the chip are divided into multiple groups according to the cascading relationship between physical resources of that type, so that physical resources in the same group are continuously adjacent in the cascading direction.

[0025] In some embodiments, step S102: dividing the physical resources of type target in the chip into multiple groups according to the cascading relationship between physical resources, such that physical resources within the same group are continuously adjacent in the cascading direction, includes: If the cascading direction is vertical, then the physical resources of the target type in the chip are scanned column by column, and the physical resources connected in series by the vertical cascading line in the same column are merged into a group. If the cascading direction is horizontal, then the physical resources of the target type in the chip are scanned row by row, and the physical resources connected in series in the same row through the horizontal cascading line are merged into a group.

[0026] When the cascading direction is vertical, all physical resources of the target type in the chip are scanned column by column. That is, the horizontal coordinates (column number) of the physical resources are fixed, and the physical resources in the column are traversed sequentially along the vertical coordinates (row number) from smallest to largest or from largest to smallest. Continuous physical resources connected in the same column by vertical cascading lines are merged into a group. Specifically, starting from the beginning row of each column, it is checked whether there is a vertical cascading line between the current physical resource and the next physical resource (adjacent row). If there is, they are considered to belong to the same group, and the check continues downwards; if not (e.g., the cascading line is interrupted), the current group ends, and a new group begins. This process is repeated until all physical resources in the column have been traversed. In this way, each continuous sequence of physical resources connected by cascading lines constitutes an independent group. Multiple groups may be generated in the same column, and groups in different columns are independent of each other. For example, suppose the chip has four columns of LUT resources, each column has 8 LUTs in rows 1 to 8, and there are vertical cascading lines between rows 1 to 4, no cascading line between rows 4 and 5, and vertical cascading lines between rows 5 and 8. Then, the 4 LUTs in rows 1 to 4 of each column are divided into one group, and the 4 LUTs in rows 5 to 8 are divided into another group. Figure 2 As shown, each blue square represents a LUT resource, and each green box represents a group. Figure 2 There are a total of 8 groups, numbered from top left to bottom right as follows: .

[0027] In this process, when the cascading direction is horizontal, all physical resources of the target type in the chip are scanned row by row. That is, the vertical coordinates (row numbers) of the physical resources are fixed, and the physical resources in the row are traversed sequentially from left to right or right to left along the horizontal coordinates (column numbers). Continuous physical resources connected in the same row via horizontal cascading lines are merged into a group. Specifically, starting from the first column of each row, it is checked whether there is a horizontal cascading line between the current physical resource and the next physical resource (adjacent column). If it exists, they are considered to belong to the same group, and the check continues downwards. If it does not exist (e.g., the cascading line is interrupted), the current group ends, and a new group begins. This process is repeated until all physical resources in the row have been traversed. In this way, each continuous sequence of physical resources connected by horizontal cascading lines constitutes an independent group. Multiple groups may be generated within the same row, and groups in different rows are independent of each other.

[0028] In this way, by scanning column-wise or row-wise according to the vertical or horizontal cascading direction, physical resources that are sequentially connected by vertical cascading lines in the same column or by horizontal cascading lines in the same row are merged into a group. This ensures that physical resources within the same group are continuously adjacent in the cascading direction, providing a correct basis for subsequent segmentation operations and supporting both vertical and horizontal cascading scenarios.

[0029] Step S103: Perform segmentation operation according to the boundary of each region constraint to obtain segmentation information of multiple groups within each region constraint. Each segment is a continuous physical resource interval within the same group that is defined by the boundary of the region constraint, and record the resource capacity of each segment.

[0030] In this context, a region constraint refers to the placement range restriction imposed by the user on certain logical units through a constraint file, typically represented by a rectangular region. In cascading scenarios, since the cascading direction is either vertical or horizontal, only the boundaries of the region along the cascading direction actually take effect. For example, for vertical cascading, the boundaries of the region constraint are the top and bottom boundaries (i.e., the start and end row numbers); for horizontal cascading, the boundaries are the left and right boundaries (i.e., the start and end column numbers). The boundaries of a region constraint refer to the two boundary values ​​(e.g., the top and bottom boundaries) that the region constraint has in the cascading direction.

[0031] After grouping the target type of physical resources, a segmentation operation needs to be performed based on the boundaries of each region constraint to obtain the segmentation information of each group within each region constraint. The purpose of segmentation is to divide the continuous physical resources within a group into several sub-intervals, so that each sub-interval corresponds to a set of identical region constraint coverage (i.e., which region constraints contain the interval). Segmentation information may include: the physically continuous interval of each segment, the number of physical resources contained in the segment (i.e., resource capacity), and the set of region constraints to which the segment belongs (because overlapping regions may belong to multiple constraints simultaneously). This information will be used for resource capacity constraints and uniqueness constraints in subsequent linear programming models. Resource capacity refers to the number of physical resource instances contained in a segment, used to constrain the total resource requirements of the logical units allocated to that segment.

[0032] In some embodiments, step S103 involves performing a segmentation operation based on the boundaries of each region constraint to obtain segmentation information for multiple groups within each region constraint, including: Determine the boundary values ​​of all regional constraints covering the target group, as well as the starting and ending boundary values ​​of the target group itself, where the target group is any group; Based on the order of boundary values, the continuous physical resource intervals between every two adjacent boundary values ​​in the target group are formed into a segment; each segment has its own set of regional constraints, spatial boundary range, and the number of physical resources contained in the segment.

[0033] Specifically, firstly, for the target group (i.e., the group currently being processed), based on the two boundaries of each regional constraint in the cascading direction, all regional constraints that spatially intersect with the target group are identified, and their boundary values ​​in the cascading direction are extracted, thereby determining the boundary values ​​of all regional constraints covering the target group. It should be noted that the boundary values ​​represent the start and end positions of the regional constraints, specifically the boundary coordinates (row or column number) of the regional constraints in the cascading direction. Also, a regional constraint may only cover a portion of the group, so its boundary values ​​may fall within the group or coincide with the end of the group. Next, to determine the order of the cutting points to obtain non-overlapping, gap-free continuous intervals, all collected boundary values ​​(including the boundary values ​​of all regional constraints covering the target group, as well as the start and end boundary values ​​of the target group itself) need to be arranged in ascending (smallest to largest) or descending (largest to smallest) order, and duplicates are removed. Then, for any two adjacent boundary values ​​after sorting, the continuous physical resource interval between these two adjacent boundary values ​​is segmented.

[0034] In this design, no region constraint boundary crosses the boundaries of any segment. Therefore, all physical resources within a segment have the exact same region constraint affiliation, meaning they are covered by the same set of region constraints. Furthermore, the segment boundary is aligned with the boundary of a region constraint or with the natural boundary (start or end) of the grouping. The set of region constraints to which each segment belongs refers to which region constraints the segment is located within. For example, in vertical concatenation, if the entire row interval of a segment is within the row range of a region constraint, then the segment belongs to that region constraint. The spatial boundary range of a segment refers to its physical location; in vertical concatenation, the start and end row numbers are recorded, while in horizontal concatenation, the start and end column numbers are recorded. The number of physical resources contained within a segment refers to the length of the segment in the concatenation direction (number of rows or columns), which is also equal to the number of physical resources within the segment. For example, if there are 3 rows from row 3 to row 5, the resource capacity can be represented as 3.

[0035] For example, suppose there are two region constraints R0 and R1, such as Figure 3 As shown in the orange box in (a), for each vertical group, taking the first group in the upper left as an example, the segmentation operation is as follows: (1) Collect boundary values: the boundary value corresponding to R0 is The boundary value corresponding to R1 is ( The boundary value of the first column group itself is... Then the boundary value set is { , , , , , };(2)Ascending order sorting: Sort the boundary values ​​as , , , , , here equal And the choice is only right Sort; (3) A continuous physical resource interval between every two adjacent boundary values ​​constitutes a segment: boundary value ~ The physical resources between them constitute segment S0, and the region to which segment S0 belongs is constrained by R0, with a boundary range ( , Boundary values ~ The physical resources between them constitute segment S8, and the region to which segment S8 belongs is constrained by R1, with a boundary range ( , And so on, the segmented results are as follows: Figure 3 As shown in (b), each purple box represents a segment. Region constraints R0 and R1 each have 8 segments. The mapping relationship between region constraints and segments is as follows: , .

[0036] In this way, by collecting all regional constraint boundary values ​​covering the target group and sorting them in order of size, the continuous physical resource interval between every two adjacent boundary values ​​is formed into a segment, and the regional constraint set, spatial boundary range and resource capacity of each segment are recorded, thereby accurately cutting out segments with unified affiliation, providing accurate resource containers for the linear programming model, and naturally handling overlapping areas.

[0037] Step S104: Establish a linear programming model; the linear programming model includes: a binary decision variable between a logical unit constrained by the region and using physical resources of the target type and each segment; a uniqueness constraint that each logical unit can be assigned to only one segment; and a resource capacity constraint for each segment, which requires that the total resource demand of all logical units assigned to the same segment does not exceed the resource capacity of the corresponding segment.

[0038] After completing the segmentation operation and obtaining the resource capacity of each segment, a linear programming model can be established to determine whether there exists an allocation scheme such that all logical units subject to region constraints can be allocated to segments that satisfy the resource capacity limits. Linear programming is a method of mathematical optimization used to find feasible solutions for decision variables while satisfying a set of linear inequality constraints. In this embodiment, the goal of the linear programming model is not to find the optimal value, but to determine whether a feasible solution exists, and thus whether the region constraint validity check passes.

[0039] The linear programming model comprises three core components: binary decision variables, uniqueness constraints, and resource capacity constraints. For binary decision variables, a binary decision variable can be defined as the relationship between each logical unit constrained by the region and using physical resources of the current target type and each segment. This is typically denoted as... subscript Indicates the number of the logic unit, subscript This indicates the segment number. For ease of calculation, it is usually... Indicates logical unit Assign (place) to segments Up, and This indicates no allocation. Since a logical unit is indivisible and can only be placed entirely on a contiguous segment of physical resources, the values ​​of the decision variables can only be integers, such as 0 or 1; decimals are not allowed. If the constrained logical unit has... There are 1, segmented into 1 One, then at most need One variable.

[0040] The purpose of the uniqueness constraint is to ensure that each logical unit can be assigned to one and only one segment; it cannot be assigned to multiple segments simultaneously, nor can it be left unassigned. Each logical unit... All allocable segments The sum of the decision variables equals 1, that is... Assuming logical units Can be assigned to segments , , Then the constraint is Since the variables are 0-1, the sum equals 1, meaning that exactly one variable is 1 and the rest are 0.

[0041] The purpose of resource capacity constraints is to ensure that the total resource demand of all logical units allocated within each segment does not exceed the physical resource quantity (i.e., resource capacity) of that segment. Resource demand. Refers to a logic unit Number of physical resources required, resource capacity Cj This refers to the number of physical resources contained in segment j. For each segment... The sum of the resource requirements of all logical units allocated to this segment shall not exceed That is, satisfying For example, for a segment In other words, if there are logical resources that can be allocated Corresponding to four variables Then the resource capacity constraint is .

[0042] It should be noted that resource requirements correspond to cascading height: for some physical resources (such as BRAM), resource requirements may be equal to cascading height; for others (such as LUTs), resource requirements may be integer multiples of cascading height (because a LUT cascading height may contain multiple LUT resources). Therefore, resource requirements implicitly include cascading height requirements.

[0043] Furthermore, linear programming typically requires an objective function. Since this embodiment only concerns whether a feasible solution exists, and does not need to optimize a specific metric, a simple objective function can be set, such as minimizing the sum of all decision variables, i.e. Since each logical unit must be assigned to a unique segment (uniqueness constraint), the sum equals the total number of logical units, which is a constant. Minimizing this constant does not affect the feasibility of the solution, but it conforms to the standard form of linear programming.

[0044] In some embodiments, the linear programming model further includes overlapping region capacity constraints; when multiple region constraints have spatial overlap within the same group, the segments within the overlapping interval are merged into a merged segment, and a resource capacity constraint is added to the merged segment so that the total resource demand of all possible logical units allocated to the overlapping interval does not exceed the actual physical resource capacity of the merged segment.

[0045] It is understandable that in FPGA layout, multiple region constraints may spatially overlap, causing the same physical resource to be covered by multiple region constraints simultaneously. For example, see [link to relevant documentation]. Figure 3In the first group at the top left of (a) in the diagram, region constraint R0 covers all physical resources of the group, and R1 covers a portion of the physical resources of the group. There is some physical resource overlap between R0 and R1. During segmentation, this overlapping area is identified as an independent segment that belongs to both R0 and R1. For such a shared segment, its physical resources must simultaneously meet the resource requirements of logical units from both R0 and R1. If resource capacity constraints are applied separately to each region constraint, the resources in the overlapping portion will be calculated repeatedly (each region constraint independently requires its own resource capacity, while the actual physical resources can only be used once). Therefore, additional overlapping region capacity constraints must be added to the merged segments within the overlapping intervals to ensure that the total resource requirements of all logical units that may be allocated to this overlapping interval do not exceed the actual physical resource capacity of that segment.

[0046] In this context, "merging segments" refers to a segment created within the same group by overlapping constraints of multiple regions. For example, see [link to relevant documentation]. Figure 2 and Figure 3 Since the region constraints R0 and R1 overlap, after segmentation, exist Corresponding segment Boundary range , and Corresponding segment Boundary range This means that the two segments overlap, so they are merged into a new segment and numbered S. 16 Boundary range Calculate the resource capacity of the new segment as , The corresponding variable is and set of variables The added resource capacity constraints are:

[0047] It is a merged segment S 16 The actual physical resource capacity (by traversing S4 and S) 12 (This is obtained by covering physical resources and counting the number of resources located within the boundary). Merge segment S. 16 Physical resource capacity The calculation process can be understood as follows: given The boundary, and The boundary and and The physical resources contained therein, traversed and Physical resources in, if a certain physical resource is in Within the boundary, then Add 1.

[0048] Thus, by merging segments within the overlapping regions into a single merged segment when multiple regions have spatial overlap within the same group, and adding resource capacity constraints to it, we can ensure that the physical resources of the overlapping regions are not repeatedly calculated. This solves the problem of losing internal constraints after merging in the traditional greedy method, enabling the linear programming model to truly reflect the capacity limitations of shared resources.

[0049] In some embodiments, the actual physical resource capacity of the merged segments is calculated as follows: Determine the boundary range of the merged segments. The boundary range is the union of the boundary ranges of each segment participating in the merge. The number of physical resources located within the boundary range is counted and used as the actual physical resource capacity of the merged segment.

[0050] When multiple regions constrained within the same group have spatial overlap, these overlapping segments need to be merged into a single merged segment. To add resource capacity constraints to each merged segment, its actual physical resource capacity must be accurately calculated, i.e., the number of physical resource instances contained within the merged segment. The segments involved in the merge refer to multiple segments within the same group that need to be merged due to overlapping constraints from multiple regions. For example, ... Figure 3 In the middle, S4 (from R0) and S 12 (From R1) Spatially overlapping, they need to be merged into a single merged segment. Since each segment has its own start and end boundaries in the cascading direction (e.g., the upper and lower boundary row numbers in vertical cascading), these boundary values ​​define the physical resource range covered by the segment. Therefore, the union of the boundary ranges of all segments participating in the merge can be taken; that is, the merged physical resource range should cover all areas covered by the original segments. For example, the boundary range of S4 is ( , ), S 12 The boundary range is ( , Then the boundary range of the union is ( ). , ).

[0051] After determining the boundary range of the merged segments, all physical resources covered by each segment participating in the merge can be traversed. Each physical resource is checked one by one to see if it lies within the boundary range of the merged segment (i.e., whether its coordinates fall within the union interval). If it does, a counter is incremented by 1. The final count represents the actual physical resource capacity of the merged segment. Continuing with the example above, if the segments... There are four covered physical resources, divided into segments. There are 4 covered physical resources and 2 overlapping physical resources, so the actual physical resource capacity of the corresponding merged segment is 6.

[0052] In this way, by determining the boundary range of the merged segment as the union of the boundary ranges of each segment participating in the merge, and traversing all physical resources covered by these segments, the number of physical resources located within the boundary range is counted as the resource capacity of the merged segment, thereby realizing the accurate calculation of the resource capacity of the merged segment and ensuring the accuracy of the capacity constraint of the overlapping area.

[0053] Step S105: Solve the linear programming model. If a feasible solution exists, the validity check of the regional constraints on the physical resources of the target type is passed; otherwise, it is deemed unsuccessful.

[0054] After establishing the linear programming model (including binary decision variables, uniqueness constraints, resource capacity constraints, and optional overlapping region capacity constraints), the existing solver needs to be invoked to solve the model. The goal of the solution is to determine whether there exists a set of variable values ​​that satisfy all constraints (i.e., a feasible solution). If a feasible solution exists, it means that all logical units subject to region constraints can be uniquely allocated without exceeding the resource capacity of each segment, thus the region constraint validity check for this physical resource type passes; otherwise, if no feasible solution exists, it fails.

[0055] A feasible solution refers to the combination of variable values ​​that satisfies all constraints in the model. In this embodiment, it can be specifically understood as: each binary decision variable Assigned either 0 or 1; the uniqueness constraint guarantees that each logical unit has exactly one Resource capacity constraints ensure that the sum of the resource requirements of all allocated logical units within each segment does not exceed the resource capacity of that segment.

[0056] In some embodiments, the method further includes: After all types of physical resources to be checked have been checked, if the regional constraint validity check of all types of physical resources to be checked passes, a message indicating that the regional constraint validity check of the chip has passed is output; otherwise, the user is prompted to modify the regional constraints.

[0057] At the start of the inspection process, all physical resource types required by logical units that meet preset conditions can be added to a queue (or list). Then, one physical resource type is sequentially retrieved from the queue, and the methods described in steps S101 to S105 are executed. After each physical resource type is checked, it is removed from the queue until it is empty. If a feasible solution exists for the linear programming model of each physical resource type in the queue, it means that under the current user-defined regional constraints, all cascading physical resource types can find a valid physical resource allocation scheme. At this point, a message indicating that the regional constraint validity check has passed is output. This message can be a log, a return value, or a graphical interface prompt, indicating that the user-defined regional constraints are feasible and the subsequent layout process can continue. If no feasible solution exists for the linear programming model of a certain physical resource type in the queue, the entire regional constraint validity check is deemed unsuccessful. At this point, a message prompting the user to modify the regional constraints can be output. This information can help the user locate the problem, such as indicating which physical resource type or which regional constraints caused the conflict. Modifying region constraints refers to the user needing to adjust the scope of region constraints (enlarging the region to increase resource capacity or height), reduce the number of logical units constrained within that region, or decompose overlapping regions to avoid excessive resource contention.

[0058] It should be noted that once a certain physical resource type fails, you can immediately stop checking subsequent physical resource types, or you can continue checking all physical resource types to collect more error information, but the final result will be failure.

[0059] In this way, after checking all physical resource types in sequence, if all pass, a message indicating that the area constraint validity check has passed is output; otherwise, the user is prompted to modify the area constraint. This provides a clear overall check result, making it easier for the user to decide whether to proceed to the subsequent layout process, and providing directions for modification if the check fails.

[0060] In some embodiments, the user is prompted to modify the region constraints, including outputting the region constraint identifier and physical resource type that cannot pass the inspection.

[0061] It is understandable that simply informing the user that a region constraint fails a validity check is often insufficient to pinpoint the root cause of the problem. To improve the efficiency of users modifying constraint files, this embodiment can further output the identifier of the region constraint that failed the check, along with its corresponding physical resource type. This helps users quickly identify which region constraint and resource type caused the insufficient resource capacity or cascade height non-compliance. Each region constraint typically has a unique name or ID in the user's constraint file, i.e., the region constraint identifier. When establishing a linear programming model, the set of region constraints to which each segment belongs is recorded. When no feasible solution is found, the cause of the conflict (such as a violation of resource capacity constraints) can be analyzed to trace back to the region constraint that caused the infeasibility, and the identifiers of these region constraints, such as R1, can be output.

[0062] Furthermore, since different types of physical resources are checked independently, when a certain type of physical resource fails the check, the user can be clearly informed which type of physical resource has the problem, for example, outputting "BRAM resource type check failed." Of course, the identifier of the region constraint that failed the check and the corresponding physical resource type can also be output simultaneously. For example, suppose that both LUT and BRAM in the chip need to be checked, the linear programming model passes the LUT type check, but there is no feasible solution for the BRAM type check, and the conflict mainly involves the overlapping part of region constraints R0 and R1, then the output message could be "Region constraint validity check failed because the BRAM physical resource type has insufficient resource capacity in the overlapping area of ​​region constraints R0 and R1. Please modify."

[0063] Thus, by further outputting the identifier of the region constraint that failed the check and the corresponding physical resource type when prompting the user to modify the region constraint, the user can quickly locate the specific region constraint and resource type that caused the validity failure, thereby improving the targeting and efficiency of constraint modification and reducing debugging time.

[0064] This application also provides an electronic device, including a memory and a processor. The memory stores a processing program, and when the processing program is executed by the processor, it implements the chip region constraint legality check method in any of the above embodiments.

[0065] This application also provides a storage medium storing a processing program, which, when executed by a processor, implements the region constraint legality check method for the chip in any of the above embodiments.

[0066] In the embodiments of the electronic devices and storage media provided in this application, all the technical features of any of the above-mentioned chip region constraint legality checking method embodiments may be included. The extended and explanatory content of the specification is basically the same as the various embodiments of the above-mentioned methods, and will not be repeated here.

[0067] This application also provides a computer program product, which includes computer program code. When the computer program code is run on a computer, it causes the computer to perform the methods described in the various possible implementations above.

[0068] This application also provides a chip, including a memory and a processor. The memory is used to store a computer program, and the processor is used to call and run the computer program from the memory, so that a device with the chip installed performs the methods described in the various possible implementations above.

[0069] It is understood that the above scenarios are merely examples and do not constitute a limitation on the application scenarios of the technical solutions provided in the embodiments of this application. The technical solutions of this application can also be applied to other scenarios. For example, as those skilled in the art will know, with the evolution of system architecture and the emergence of new business scenarios, the technical solutions provided in the embodiments of this application are also applicable to similar technical problems.

[0070] The sequence numbers of the embodiments in this application are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0071] The steps in the method of this application embodiment can be adjusted, combined, or deleted according to actual needs.

[0072] The units in the device of this application embodiment can be merged, divided, and deleted according to actual needs.

[0073] In this application, the same or similar terms, concepts, technical solutions and / or application scenario descriptions are generally described in detail only when they appear for the first time. When they appear again, they are generally not repeated for the sake of brevity. When understanding the technical solutions and other contents of this application, the same or similar terms, concepts, technical solutions and / or application scenario descriptions that are not described in detail later can be referred to their previous relevant detailed descriptions.

[0074] In this application, the descriptions of the various embodiments have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0075] The technical features of the present application can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of the present application.

[0076] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) as described above, and includes several instructions to cause a terminal device (which may be a mobile phone, computer, server, controlled terminal, or network device, etc.) to execute the methods of each embodiment of this application.

[0077] In the above embodiments, implementation can be achieved, in whole or in part, through software, hardware, firmware, or any combination thereof. When implemented in software, it can be implemented, in whole or in part, as a computer program product. A computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the flow or function according to the embodiments of this application is generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a storage medium or transmitted from one storage medium to another. For example, computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line) or wireless (e.g., infrared, wireless, microwave, etc.) means. The storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that integrates one or more available media. The available medium can be a magnetic medium (e.g., floppy disk, storage disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., solid state disk (SSD)).

[0078] The above are merely preferred embodiments of this application and do not limit the patent scope of this application. Any equivalent structural or procedural modifications made based on the description and drawings of this application, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application. The above embodiments merely illustrate several implementation methods of this disclosure, and their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this disclosure, and these all fall within the protection scope of this disclosure. Therefore, the protection scope of this disclosure should be determined by the appended claims.

Claims

1. A method for checking the legality of region constraints in a chip, characterized in that, The method includes: Obtain the target type of the physical resource to be inspected in the chip; Based on the cascading relationship between physical resources, the physical resources of the target type in the chip are divided into multiple groups, so that the physical resources in the same group are continuously adjacent in the cascading direction. Perform segmentation operations based on the boundaries of each region constraint to obtain segmentation information of the multiple groups within each region constraint, wherein each segment is a continuous physical resource interval within the same group defined by the boundary of the region constraint, and record the resource capacity of each segment; Establish a linear programming model; the linear programming model includes: a binary decision variable between a logical unit constrained by a region and using physical resources of the target type and each segment; a uniqueness constraint that each logical unit can be assigned to only one segment; and a resource capacity constraint for each segment, wherein the resource capacity constraint requires that the total resource demand of all logical units assigned to the same segment does not exceed the resource capacity of the corresponding segment; Solve the linear programming model. If a feasible solution exists, the validity check of the regional constraints on the physical resources of the target type is deemed to have passed; otherwise, it is deemed to have failed.

2. The method according to claim 1, characterized in that, The target types for acquiring the physical resources to be inspected in the chip include: All logic units are classified according to the type of physical resources required by each logic unit in the chip design, resulting in at least one type of logic unit. The type of physical resources required by the target logic unit that meets the preset conditions is determined as the target type, and the target logic unit is any type of logic unit; the preset conditions include: some or all logic units need to be implemented by corresponding physical resources through cascading, and some or all logic units have regional constraints.

3. The method according to claim 1, characterized in that, The cascading direction is either vertical or horizontal; the step of dividing the physical resources of the target type in the chip into multiple groups according to the cascading relationship between physical resources, such that physical resources within the same group are continuously adjacent in the cascading direction, includes: If the cascading direction is vertical cascading, then the physical resources of the target type in the chip are scanned by column, and the physical resources connected in series by the vertical cascading line in the same column are merged into a group; If the cascading direction is horizontal cascading, then the physical resources of the target type in the chip are scanned row by row, and the physical resources connected in series in the same row through the horizontal cascading line are merged into a group.

4. The method according to any one of claims 1 to 3, characterized in that, The step of performing segmentation operations based on the boundaries of each region constraint to obtain segmentation information for the multiple groups within each region constraint includes: Determine the boundary values ​​of all regional constraints covering the target group, as well as the start and end boundary values ​​of the target group itself, where the target group is any group; Based on the order of boundary values, the continuous physical resource intervals between every two adjacent boundary values ​​in the target group are formed into a segment; wherein, each segment has its own set of regional constraints, spatial boundary range, and the number of physical resources contained in the segment.

5. The method according to claim 1, characterized in that, The linear programming model further includes: overlapping region capacity constraints; when multiple region constraints have spatial overlap within the same group, the segments within the overlapping interval are merged into a merged segment, and a resource capacity constraint is added to the merged segment, so that the total resource demand of all logical units that may be allocated to the overlapping interval does not exceed the actual physical resource capacity of the merged segment.

6. The method according to claim 5, characterized in that, The calculation method for the actual physical resource capacity of the merged segments is as follows: Determine the boundary range of the merged segments, wherein the boundary range is the union of the boundary ranges of each segment participating in the merge; The number of physical resources located within the boundary range is counted and used as the actual physical resource capacity of the merged segment.

7. The method according to claim 1, characterized in that, The method further includes: After all types of physical resources to be checked have been checked, if the regional constraint validity check of all types of physical resources to be checked passes, a message indicating that the regional constraint validity check of the chip has passed is output; otherwise, the user is prompted to modify the regional constraints.

8. The method according to claim 7, characterized in that, The prompt to the user to modify the region constraints includes outputting the region constraint identifier and physical resource type that cannot pass the check.

9. An electronic device, characterized in that, include: A memory and a processor, wherein the memory stores a processing program, and the processing program, when executed by the processor, implements the chip region constraint legality check method as described in any one of claims 1 to 8.

10. A storage medium, characterized in that, The storage medium stores a processing program, which, when executed by a processor, implements the chip region constraint legality check method as described in any one of claims 1 to 8.

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