A long-term memory construction method and system based on a design experience backbone network

Abstract

A long-term memory construction method and system based on a design experience backbone network, the method comprising: generating a standardized design event sequence based on collected multi-source heterogeneous data; constructing a multi-granularity time sequence design evolution graph based on the standardized design event sequence; extracting five layers of nodes of a design target layer, a problem layer, a reason layer, a strategy layer and a result layer from the multi-granularity time sequence design evolution graph, establishing causal association edges between the layers, calculating causal influence strength, and generating a design causal evolution network; based on the design causal evolution network, structurally fusing problem discovery, cause analysis, optimization measures, result verification and experience labels, encapsulating them as independent scenario memory units, and forming transferable design experience; performing experience abstraction, clustering fusion and backbone scoring screening on the scenario memory units, retaining high-value causal experience paths, and constructing a skeletonized design experience backbone network.

Description

Technical Field

[0001] This invention belongs to the fields of artificial intelligence, electronic design automation and knowledge engineering technology, and relates to intelligent agent long-term memory management, design process modeling and experience reasoning technology. Specifically, it relates to a long-term memory construction method and system based on a design experience backbone network. Background Technology

[0002] With the development of Large Language Model (LLM) and agent technologies, intelligent design systems for Electronic Design Automation (EDA) have gradually become an important research direction for intelligent chip design. Radio frequency (RF) chip design agents can combine design rules, simulation tools, and engineering knowledge to assist in completing complex tasks such as circuit design, parameter optimization, performance analysis, fault location, and design verification, thereby improving chip design efficiency and reducing manual design costs.

[0003] In actual chip design, a complete design task typically involves multiple stages, including requirements analysis, scheme formulation, parameter tuning, simulation verification, problem fixing, and result confirmation. This process is accompanied by a continuous stream of design decisions, tool calls, parameter modifications, and performance feedback. This process data contains rich design experience and engineering knowledge, representing a significant source of experience accumulated by senior design engineers over time. However, existing RF intelligent agents generally lack the ability to organize and continuously utilize this design process experience over the long term.

[0004] Currently, long-term memory systems for intelligent agents primarily employ techniques such as vector databases, text storage, knowledge base management, and retrieval-augmented generation (RAG) to store and retrieve historical information. These methods typically involve vectorizing historical documents, dialogue records, or task logs and utilizing similarity retrieval mechanisms to recall historical information, thereby providing a reference for the current task.

[0005] However, the aforementioned methods primarily focus on information storage and retrieval processes. Their long-term memory essentially remains at the level of historical data management, making it difficult to effectively express the temporal evolution of design behaviors in complex engineering design processes, the causal relationships between problem causes and optimization measures, and the formation patterns of design experience. As design tasks continue, the system accumulates a large amount of design logs, design records, and simulation results. Although historical information can be preserved, it is difficult to automatically extract transferable and reusable design experience from it.

[0006] On the other hand, chip design is a typical complex engineering design activity. The same design goal often corresponds to multiple design strategies, and different adjustments to design parameters may lead to different performance changes. Design experience usually manifests as a continuous evolutionary process of "design goal - problem discovery - cause analysis - optimization strategy - result verification," rather than an isolated single design event. Existing long-term memory technologies lack the ability to uniformly model the continuity and causality of the design process, making it difficult for intelligent agents to understand the mechanism of design experience formation and to achieve cross-project experience transfer and interpretable reasoning.

[0007] Furthermore, as the scale of design tasks continues to expand, the amount of information stored in the long-term memory system continues to grow. A large amount of repetitive, low-value, or outdated information will cause storage redundancy and a decrease in retrieval efficiency, making it easy for intelligent agents to encounter problems such as low efficiency in utilizing experience, weak knowledge transfer ability, and unclear decision-making basis in complex design tasks. Summary of the Invention

[0008] To address the aforementioned technical problems, this invention provides a method and system for constructing long-term memory based on a design experience backbone network. By constructing a standardized design event model, a temporal design evolution graph, a design causal evolution network, and contextual memory units, it achieves automatic extraction, continuous accumulation, and structured organization of design experience. Furthermore, it constructs a design experience backbone network, forming a design experience skeleton structure with long-term stability and cross-task transferability. This enables unified modeling of a large number of discrete design events generated during the design process, uncovering the temporal evolution patterns and causal relationships between design behaviors and design results, and forming a design experience system that is sustainably accumulated, transferable, reusable, and interpretable for reasoning. This enhances the agent's continuous learning ability, autonomous decision-making ability, and knowledge transfer ability in complex chip design tasks.

[0009] To achieve the above objectives, the present invention adopts the following technical solution:

[0010] Firstly, a method for constructing long-term memory based on a backbone network designed with experience includes the following steps:

[0011] S1. Generate a standardized design event sequence based on the collected multi-source heterogeneous data;

[0012] S2. Based on standardized design event sequences, construct a multi-granularity temporal design evolution map that includes micro-event-level sequences, meso-level dependency networks, and macro-level context aggregation branches;

[0013] S3. Extract five layers of nodes—design target layer, problem layer, cause layer, strategy layer, and result layer—from the multi-granularity time-series design evolution graph, establish causal relationship edges between each layer, calculate the causal influence strength, and generate a design causal evolution network.

[0014] S4. Based on the design causal evolution network, the problem discovery, cause analysis, optimization measures, result verification and experience labeling are structurally integrated and encapsulated into independent context memory units to form transferable design experience.

[0015] S5. The contextual memory units are subjected to experience abstraction, clustering and fusion, and backbone scoring and screening to retain high-value causal experience paths and construct a skeletonized design experience backbone network. The design experience backbone network is used to support experience retrieval, causal reasoning and strategy recommendation for new design tasks.

[0016] Preferably, S1 includes:

[0017] S11. Collect and integrate multi-source heterogeneous data, including design requirements, design decisions, EDA call records, parameter adjustments, simulation results, verification results, and user feedback; stitch the multi-source heterogeneous data into a design data stream with a unified timeline;

[0018] S12. The time-interval-based sliding window algorithm and state machine matching rules cut and aggregate the design data stream into design behavior segments with independent engineering significance according to the context dependency of EDA operations.

[0019] S13. Extract the design target features, design action features, and performance result features of each design behavior segment;

[0020] S14. Semantically encode the design target features, design action features, and performance result features, map them into high-dimensional continuous semantic vectors, and encapsulate the output as a standardized design event sequence.

[0021] Preferably, S2 includes:

[0022] S21. Extract the timestamp of each design event in the standardized design event sequence, sort them according to the order of occurrence, import the design events as nodes into the graph database, and connect adjacent events end to end through directed time edges to form a micro-event level sequence that is linearly progressive in time.

[0023] S22. Compare and analyze the overlap and physical correlation of events before and after in the micro-event-level sequence in terms of the change of the operation object and parameters, and calculate the dependency score; based on the dependency score, characterize the dependency relationship and generate the meso-level dependency relationship network;

[0024] S23. Monitor changes in the context and design goals in the event stream. If the context remains consistent, the corresponding sequence is abstracted and aggregated upwards into macro-strategy nodes. If the context undergoes a sudden change, new evolution path branches are split off, generating macro-context aggregation branches.

[0025] S24. Perform structural mapping and topological fusion of micro-event-level sequences, meso-level dependency networks, and macro-level context aggregation branches in the same graph space to form a multi-granularity temporal design evolution map.

[0026] Preferably, S3 includes:

[0027] S31. Extract macroscopic design constraints from the multi-granularity temporal design evolution graph and construct the design target layer. If the agent detects that the actual performance parameters fail to meet the design target, it triggers a constraint violation event and maps it down to the problem layer to generate the corresponding concrete problem node.

[0028] S32. For the design defects extracted from the problem layer, perform reverse tracing in conjunction with the pre-built RF engineering knowledge graph to construct the cause layer;

[0029] S33. Based on the actual design actions recorded in the multi-granularity temporal design evolution graph, aggregate them and abstract them upwards into strategy layer nodes; utilize dependencies to establish connections between the cause layer and the strategy layer using associated edges;

[0030] S34. Extract performance index migration data from the associated simulation report and generate result layer nodes.

[0031] As a preferred option, in S3:

[0032] The target layer and the problem layer are connected by a unidirectional directed edge;

[0033] Based on the characteristics of the problem nodes, the cause layer is broken down into specific causes at the underlying physical and circuit topology levels, and corresponding cause nodes are generated; causal relationship edges are established between the problem layer and the cause layer.

[0034] The connection between the cause layer and the strategy layer includes solid lines and dashed lines; solid lines represent strong causal relationships and direct targeted strategies; dashed lines represent cross- or weakly coupled strategy attempts with exploratory nature.

[0035] The results layer records the performance improvement of various specific RF indicators; the performance improvement nodes are summarized and converge to the final state node, forming a complete engineering closed loop with the design target layer.

[0036] As a preferred option, S3 also includes:

[0037] S35, Parameter adjustment action in the calculation strategy layer Its resulting performance The strength of causal influence between them (CI):

[0038]

[0039] in, The physical sensitivity gradient of the simulation results to parameter adjustments, This represents the co-occurrence frequency of the causal pair in the historical graph database and the environmental moderating factors; The semantic vector dimension representing the design event; The normalization function is used to map the influence intensity of different causal paths to a unified probability space; based on the influence intensity of each causal path, the associated edges are weighted and the topology is pruned to generate the causal evolution network.

[0040] As a preferred embodiment, the episodic memory unit in S4 includes:

[0041] Problem Discovery: When a performance metric is detected to violate design constraints, long-term memory recording is triggered, and problem layer nodes are extracted from the design causal evolution network as entry points;

[0042] Cause analysis: Tracing back along the causal path to locate the physical root cause of the problem and extracting the logical deduction path from the problem's symptoms to its root cause;

[0043] Optimization measures: Extract the strategy chain taken to eliminate the root cause, while retaining comparative data of successful strategies and failed attempts;

[0044] Results verification: Extract the simulation feedback results after the strategy is executed, compare them with the initial constraints to verify the effectiveness of the optimization;

[0045] Experience tags: Additional metadata tags including process node, operating frequency band, circuit topology type, and core operating objects.

[0046] As a preferred embodiment, S5 includes:

[0047] S51. Perform statistical analysis on the closed-loop links in each context memory unit to uncover causal evolution paths that are frequently repeated and verified across tasks.

[0048] S52. Calculate the semantic similarity and structural similarity between different causal evolution paths, aggregate the causal evolution paths, and perform topological graph fusion and node standardization update.

[0049] S53. Use the main scoring function to quantify and score each abstracted causal evolution path;

[0050] S54. Set a backbone retention threshold. Paths with backbone scores exceeding the backbone retention threshold are identified as core knowledge skeletons and retained. Fragmented paths with backbone scores below the backbone retention threshold are automatically pruned and eliminated.

[0051] S55. The selected causal evolution paths are reorganized into graph topology according to their internal logic to construct the backbone network of design experience.

[0052] As a preferred option, it also includes the dynamic evolution of S6 and the design experience backbone network, specifically including:

[0053] S61. Receive the target, constraint and environmental parameters of the new design task and encapsulate them as a query probe;

[0054] S62. Input the query probe into the design experience backbone network, locate the most similar experience starting node, perform path reasoning along the directed causal link, and calculate the recommendation score of each potential strategy path.

[0055] S63. Based on the recommendation scores, output structured optimization paths and design suggestions to the agent. The agent adopts the recommendations and executes the design task.

[0056] S64. Extract the performance improvement, verification results, and user feedback after the design task is completed;

[0057] S65. Based on the actual execution results, strengthen or weaken the corresponding experience paths, and the derived new strategies are then abstracted and integrated into the backbone network; when the experience weight is lower than the retention threshold, it is eliminated from the backbone network.

[0058] Secondly, a long-term memory construction system based on a design experience backbone network includes:

[0059] The design event acquisition and standardized modeling module is used to collect multi-source heterogeneous data and generate standardized design event sequences.

[0060] The multi-granularity temporal design evolution graph construction module is used to construct a multi-granularity temporal design evolution graph based on standardized design event sequences, which includes micro-event-level sequences, meso-dependency networks, and macro-context aggregation branches.

[0061] The design causal evolution network construction module is used to extract five layers of nodes—design target layer, problem layer, cause layer, strategy layer, and result layer—from the multi-granularity time-series design evolution graph, establish causal relationship edges between each layer, calculate the causal influence strength, and generate the design causal evolution network.

[0062] The context memory unit encapsulation module is used to structurally integrate problem discovery, cause analysis, optimization measures, result verification and experience labels based on the design causal evolution network, and encapsulate them into independent context memory units to form transferable design experience;

[0063] The design experience backbone network construction module is used to perform experience abstraction, clustering and fusion, and backbone scoring and screening of contextual memory units, retaining high-value causal experience paths, and constructing a skeletonized design experience backbone network; the design experience backbone network is used to support experience retrieval, causal reasoning, and strategy recommendation for new design tasks.

[0064] The aforementioned long-term memory construction system based on a design experience backbone network is used to implement the long-term memory construction method and steps based on a design experience backbone network as described in the first aspect.

[0065] Compared with the prior art, the present invention has the following significant advantages:

[0066] (1) Design the Experience Backbone Network (DEBN) as the core structure of long-term memory.

[0067] This invention proposes for the first time a Design Experience Backbone Network (DEBN) as the core organizational structure of an agent's long-term memory. It integrates standardized design events, episodes, and abstract design experiences layer by layer, realizing the progressive abstraction from discrete design behavior to transferable experience. This breaks through the limitation of traditional long-term memory, which only stores historical information and is difficult to form structured experiential knowledge.

[0068] (2) Multi-granular temporal and causal relationship expression improves decision interpretability

[0069] By constructing a multi-granularity temporal design evolution map and a design causal evolution network, the intelligent agent can not only remember the events that occur during the design process, but also understand the causal relationships and evolutionary laws between events, thereby providing an interpretable basis for optimizing design decisions and significantly enhancing the credibility and accuracy of design decisions.

[0070] (3) Closed-loop design problem of episode memory unit (Episode) encapsulation

[0071] This invention encapsulates problem discovery, cause analysis, optimization strategies, and result verification entirely through a contextual memory unit, enabling automatic extraction and closed-loop recording of design experience. This allows intelligent agents to form systematic solutions to complex design problems, avoiding isolated storage of single events and improving knowledge reuse efficiency.

[0072] (4) Experience dynamic evolution and cross-task transfer capability

[0073] By designing a backbone scoring mechanism and dynamic update strategy for the experience backbone network, the system can strengthen, decay, eliminate, or merge experience nodes and experience links, achieving long-term accumulation and adaptive optimization of experience. At the same time, it supports experience transfer across projects and tasks, enabling the agent to have continuous learning and self-evolution capabilities.

[0074] (5) Structured compression and efficient retrieval of long-term memory

[0075] The design of the experience backbone network constructs high-value experience nodes into a skeletonized structure, which reduces storage redundancy and optimizes retrieval efficiency while ensuring the integrity of experience and causal relationships, thereby achieving efficient management of the agent's long-term memory.

[0076] (6) Wide range of engineering application value

[0077] This invention can be applied to radio frequency circuit design, monolithic microwave integrated circuit design, analog integrated circuit design, chip verification and optimization, and other complex engineering design scenarios. It provides a long-term design experience system for radio frequency intelligent agents that can be continuously accumulated, explained, and made intelligent decisions, and has good engineering application prospects and promotion value. Attached Figure Description

[0078] Figure 1 This is a flowchart illustrating the overall process of the method in Embodiment 1 of the present invention.

[0079] Figure 2 This is a flowchart of the event acquisition and standardized modeling process for the radio frequency chip design intelligent agent in Embodiment 1 of the present invention;

[0080] Figure 3 This is a flowchart of the multi-granularity temporal design evolution map construction method of Embodiment 1 of the present invention;

[0081] Figure 4 This is a schematic diagram of the design causal evolution network structure based on the temporal design evolution graph in Embodiment 1 of the present invention;

[0082] Figure 5 This is a schematic diagram of the scenario memory unit structure based on design problem closed loop in Embodiment 1 of the present invention;

[0083] Figure 6 This is a schematic diagram of the design experience backbone network construction method based on context memory units in Embodiment 1 of the present invention;

[0084] Figure 7 This is a schematic diagram of the empirical reasoning and dynamic evolution process based on the design experience backbone network in Embodiment 1 of the present invention. Detailed Implementation

[0085] To make the technical means, inventive features, objectives, and effects of the invention readily understandable, the invention is further described below with reference to specific illustrations. However, the invention is not limited to the embodiments described below.

[0086] It should be understood that the structures, proportions, sizes, etc., shown in the accompanying drawings of this specification are only used to complement the content disclosed in the specification for those skilled in the art to understand and read, and are not intended to limit the conditions under which the present invention can be implemented. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in the proportions, or adjustments to the size, without affecting the effects and objectives that the present invention can produce, should still fall within the scope of the technical content disclosed in the present invention.

[0087] This invention addresses the problem that existing long-term memory systems for radio frequency chip design agents mainly rely on vector databases, text storage, or retrieval-enhanced generation (RAG) technology, which are insufficient to effectively express the temporal evolution, causal relationships, and experience formation mechanisms of design behaviors during complex chip design processes. As a result, the agent can only store historical design information and cannot form sustainable, transferable, reusable, and interpretable design experience knowledge. This invention proposes a long-term memory construction method and system based on Design Experience Backbone Network (DEBN).

[0088] This invention achieves automatic extraction, continuous accumulation, and structured organization of design experience by constructing a standardized design event model, a time-series design evolution map, a design causal evolution network, and an episode memory unit. Furthermore, it constructs a design experience backbone network, forming a design experience skeleton structure with long-term stability and cross-task transferability. When a new design task is received, the agent performs experience retrieval, causal reasoning, and strategy recommendation based on the design experience backbone network, realizing the dynamic transfer and continuous evolution of design experience. This enhances the RF agent's autonomous decision-making ability, continuous learning ability, and knowledge transfer ability in complex chip design tasks.

[0089] This invention provides a method for constructing, storing, and reasoning about long-term memory for an intelligent agent in radio frequency chip design based on a Design Experience Backbone Network (DEBN). This method aims to overcome the shortcomings of traditional vector retrieval methods in logical causal expression by deeply abstracting complex and heterogeneous chip design process data, thereby constructing a long-term memory system capable of simulating the thinking logic of experienced engineers. The specific implementation logic, algorithm flow, and application scenarios of this invention are described in detail below with reference to the accompanying drawings.

[0090] Example 1:

[0091] A method for constructing long-term memory based on a backbone network with design experience includes the following steps:

[0092] S1. Generate a standardized design event sequence based on the collected multi-source heterogeneous data;

[0093] Combination Figure 2 In step S1, the acquisition and standardized modeling of RF chip design events are performed. This step aims to transform discrete, messy low-level engineering logs into machine-readable, semantically related high-dimensional structured data. Its specific implementation process includes the following sub-steps:

[0094] S11. Multi-source data acquisition and heterogeneous design data fusion:

[0095] During the execution of the RF chip design task, the intelligent agent continuously collects multi-dimensional raw data through a pre-set listening interface and log parsing probe. The data sources collected specifically include: design requirements at the beginning of the project, design decisions and EDA tool (such as Cadence Virtuoso) call records during the design process, parameter adjustment records at the component level, simulation analysis results and design verification results after each iteration, and user feedback information.

[0096] To address the aforementioned multi-source heterogeneous data, the system records the precise time nodes of each interaction through a global clock synchronization mechanism. It also employs a structured data verification and cleaning module (such as a Pydantic-based verification stream) to eliminate redundant operations with incorrect or invalid formats, aligning various log streams, text, or chart nodes with different formats and stitching them together into a design data stream with a unified timeline.

[0097] S12, Design Behavior Recognition:

[0098] Based on the fused design data stream, the system performs design behavior identification. Specifically, the system uses a time-interval-based sliding window algorithm and state machine matching rules to segment and aggregate continuous data streams into behavioral fragments with independent engineering significance according to the contextual dependencies of EDA operations. For example, fragmented logs such as "selecting a component," "modifying aspect ratio parameters," and "saving the schematic diagram" that occur continuously within a certain time window are identified and merged into a complete "dimensional parameter tuning" design behavior.

[0099] S13. Parallel Extraction of Key Elements: For each identified design behavior fragment, the system triggers an information extraction engine based on rule templates and regular expression matching to perform feature extraction in parallel across the following three dimensions:

[0100] Design goal extraction: Extract the core objective of the current behavior from the preceding design constraints and task instructions;

[0101] Action extraction: Extract the specific operation instructions, the objects of action, and their physical changes from the current behavior;

[0102] Performance result extraction: After the action is executed, the specific numerical fluctuations of key RF performance indicators are extracted from the associated simulation reports and verification results.

[0103] S14. Design Event Semantic Encoding: To eliminate the diversity of expressions caused by differences in different EDA tool platforms or human naming, the system inputs the extracted feature information into the semantic encoding module. This step utilizes a pre-built RF domain expert dictionary and basic text vectorization algorithms (such as TF-IDF or standardized embedding models) to map discrete text strings into unified high-dimensional continuous semantic vectors, enabling the system to identify similar design behaviors across tasks.

[0104] After the aforementioned data fusion, behavior recognition, key element extraction, and semantic encoding processes, the system ultimately encapsulates and outputs each complete design operation and its causes and consequences as a highly structured, standardized design event. In this invention, this standardized design event is defined as a seven-dimensional tuple. The specific meanings of each parameter are as follows:

[0105] (Design Goal): Indicates the specific RF performance indicators or functional constraints that the current design behavior aims to achieve (such as "improving input return loss" or "increasing center frequency gain").

[0106] (Design Action): Indicates the specific operation instruction executed by the agent or designer (such as "increase size", "replace topology", "adjust bias", etc.);

[0107] (Operated Object): Represents the physical entity or circuit node to which the action actually takes place (such as a specific MOSFET model, microstrip line element, capacitor C1, etc.);

[0108] (Parameter Change): Represents the specific numerical offset or state change of the operated object before and after the action is executed;

[0109] (Context): Records the macroscopic design state at the time the current operation occurs, including strongly relevant background information such as the process library node used (e.g., 28nm CMOS), ambient temperature configuration, and operating frequency band;

[0110] (Performance Results): Record the actual numerical fluctuations or state transitions of various key RF performance indicators after the completion of this design action and simulation;

[0111] (Timestamp): Records the absolute time when the design event occurred (e.g., in the format "YYYY-MM-DD HH:MM:SS:ms"). This parameter is the core basis for connecting discrete events, calculating the time interval between actions, and subsequently constructing the time-series design evolution map, ensuring the directionality and time dependence of the event sequence.

[0112] The standardized design event sequence generated above will serve as the underlying knowledge base, providing high-quality node and edge attribute inputs for the subsequent construction of a multi-granularity temporal graph (step S2).

[0113] S2. Based on standardized event sequences, construct a three-layer graph structure that includes micro-level event sequences, meso-level dependency networks, and macro-level context aggregation branches;

[0114] Combination Figure 3 In step S2, based on the standardized design event sequence output in step S1, the system specifically constructs a multi-granularity temporal design evolution graph. This step aims to utilize graph databases and graph computing algorithms to transform isolated events into a structured network with temporal dimensions and logical connections. Its specific implementation process includes the following sub-steps:

[0115] S21. Temporal sequence modeling and event-level sequence construction:

[0116] First, the system receives the standardized design event sequence output from step S1 as its basic input. The system extracts the timestamp from each event tuple, performs time-sequence modeling, and precisely sorts all unordered discrete events according to their absolute chronological order. Then, the system directly constructs an event-level sequence based on the sorting results. In terms of the underlying data structure, the system imports these events as low-level nodes into a graph database and connects adjacent time points with simple directed temporal edges, thus forming a basic, linearly progressive one-dimensional micro-event-level sequence.

[0117] S22. Dependency Analysis and Dynamic Edge Weight Processing:

[0118] While establishing the basic time series, the system extracts event sequences in parallel and performs dependency analysis. Specifically, the system compares and analyzes successive events in relation to the objects being operated on. and parameter change The system considers the overlap and physical correlation between the events. For example, if the preceding event is "modifying capacitor C1" and the following event is "fine-tuning inductor L1 in the same matching network," there is a potential physical cascading effect. Next, the system uses a preset association rule scoring mechanism to determine the significance of the dependency relationship. If the dependency score is higher than a set threshold, the system strengthens the dependency edge weight, generating a strong logical dependency edge with a higher weight between the two event nodes in the graph database to represent that the following operation is strongly dependent on the preceding operation in engineering logic. If the dependency score is lower than the threshold, the system determines that the two operations are loosely coupled or accidental independent attempts, performing a dependency weakening / filtering operation to prevent the generation of additional logical connections between them. This effectively filters out "noise" edges generated in long-term logs, reducing graph complexity.

[0119] S23, Contextual Analysis and Branch Management:

[0120] Simultaneously, the system considers the context and design goals within the event flow. Feature-based contextual analysis is employed. In RF chip design, engineers may conduct repeated tests under different frequency bands, process corners, or bias conditions. Based on this, the system monitors and determines in real-time whether the context of consecutive event flows is consistent. If the context parameters remain consistent, it indicates that the current series of operations belong to a continuous optimization phase under a specific goal. The system will merge the event contexts, abstracting and aggregating this sequence into a higher-level "macro-strategy node." If a sudden change in context is detected (such as switching the operating frequency band from S-band to millimeter wave, or a change in power supply voltage settings), it indicates that the design has entered a new phase or testing branch. In this case, the system will retain the independent context branch, splitting a new evolution path in the graph to accurately and completely record the independent exploration process under different design environments.

[0121] S24. Multi-granularity fusion modeling and map generation:

[0122] Finally, the system aggregates the processing results from the above three dimensions and performs multi-granularity fusion modeling. This step maps and topologically fuses the micro-level "event-level time series" (output of step S21), the meso-level "weighted dependency network" (output of step S22), and the macro-level "context aggregation branch" (output of step S23) within the same graph space.

[0123] After the above processing, the system finally outputs a complete multi-granularity time-series design evolution map. Through this multi-level graph structure, the system not only fully memorizes the surface data of "what did the RF agent do first and what did it do next", but also deeply depicts the deep design evolution path made "for what goal, under what constraints, and based on what parameter dependencies", laying a structured foundation for subsequent causal reasoning and experience extraction (step S3).

[0124] S3. Extract five layers of nodes—design target layer, problem layer, cause layer, strategy layer, and result layer—from the granular temporal design evolution graph, establish causal relationship edges between each layer, calculate the causal influence strength, and form a five-layer causal topology network.

[0125] Combination Figure 4 In step S3, based on the multi-granularity temporal design evolution map output in step S2, the system specifically constructs the design causal evolution network. This step aims to go beyond simple temporal records and, by mining the underlying physical logic between design behavior and design results, construct an interpretable five-layer causal topological framework. Its specific implementation process includes the following sub-steps:

[0126] S31. Design Goals and Problem Extraction:

[0127] The system first extracts macroscopic design constraints from the time-series evolution graph to construct a design target layer. As shown in the figure, the nodes in this layer represent the core optimization directions of the current RF circuit (e.g., nodes "G1: Increase gain" and "G2: Reduce noise"). During simulation iteration, once the agent detects that the actual performance parameters fail to meet the design target, the system automatically triggers a constraint violation event in the graph and maps it down to the design problem layer, generating corresponding concrete problem nodes (e.g., "P1: Insufficient gain" or "P2: High noise"). The target layer and the problem layer are connected by a unidirectional directed edge, establishing the initial driving force of the "expectation-reality gap".

[0128] S32. Root cause analysis and cause layer construction:

[0129] For design defects extracted from the problem layer, the system performs reverse tracing using a pre-built RF engineering knowledge graph (such as PDK device physical models and RF circuit theory rules) to construct a cause layer. Based on the characteristics of the problem nodes, the system breaks them down into specific causes at the underlying physical or circuit topology level and generates corresponding cause nodes in the graph (e.g., "C1: Inappropriate transistor size", "C2: Bias point deviation", and "C3: Matching network mismatch"). Causal relationships are established between the problem layer and the cause layer. For example, the system identifies that "insufficient gain (P1)" may be caused by either "inappropriate transistor size (C1)" or "bias point deviation (C2)", thus forming a one-to-many mesh mapping relationship.

[0130] S33. Action Mapping and Strategy Layer Construction: Based on the actual design actions recorded in the time sequence graph, the system aggregates them and abstracts them upwards into strategy layer nodes. Strategy layer nodes represent the systematic solutions taken by the agent to eliminate the aforementioned root causes (e.g., "S1: Adjust device size", "S2: Optimize bias parameters", and "S3: Reconstruct matching network"). At this point, the system utilizes the underlying data dependency calculation mechanism (the product of step S22) to establish a connection between the cause layer and the strategy layer. As shown in the figure, the associated edges are distinguished as solid and dashed edges: solid edges represent strong causal relationships and directly targeted strategies (e.g., directly "adjust device size S1" because of "unreasonable transistor size C1"); dashed edges represent cross-domain or weakly coupled strategy attempts with exploratory nature (e.g., when an unreasonable size C1 is found, the system may also try to "optimize bias parameters S2" across domains as a compensation means).

[0131] S34. Result Feedback and Result Layer Closed Loop: After the strategy node is executed, the system extracts performance indicator migration data from the associated simulation report to generate result layer nodes. The result layer records in detail the actual improvement of each specific RF indicator (such as "R1: Gain Improvement" and "R2: Noise Reduction"). These specific performance improvement nodes eventually converge to the macroscopic final state node ("R3: Performance Meets Indicators"), thus forming a complete engineering closed loop with the initial design goal layer.

[0132] S35. Causal Relationship Strength Calculation and Edge Weight Fixing: After generating the above five-layer node system, in order to quantify the reliability of each causal link in the graph, the system introduces the causal influence strength. Calculation mechanism. Adjustment action for any given parameter. The performance results it leads to The strength of its causal influence is defined as:

[0133]

[0134] in, The physical sensitivity gradient representing the simulation results to parameter adjustments. This represents the co-occurrence frequency of the causal pair in the historical graph database and the environmental moderating factors; The semantic vector dimension representing the design event; This represents the normalization function, used to map the influence intensity of different causal paths to a unified probability space.

[0135] The system calculates the cumulative value of each path. The algorithm assigns weights and performs topology pruning on the solid and dashed edges in the five-layer network. The final output is a well-structured and logically rigorous causal evolution network. This network not only tells the agent "how to adjust," but also clearly explains "why to adjust it this way" through the five-layer links, providing a solid underlying knowledge graph structure for the subsequent encapsulation of contextual memory units and cross-task knowledge transfer.

[0136] S4. Based on the design causal evolution network, the problem discovery, cause analysis, optimization measures, result verification and experience labeling are structurally integrated and encapsulated into independent context memory units to form transferable design experience.

[0137] Combination Figure 5 In step S4, the system, based on the previously constructed design causal evolution network, specifically executes the construction of the Episode memory unit. In complex electronic design automation engineering practices, the solution of a single problem typically presents as a logical closed loop containing multiple steps. This step aims to aggregate and encapsulate the scattered actions and states within this closed loop, refining them into final transferable design experience. Its specific implementation process strictly corresponds to the five core element modules in the diagram:

[0138] S41. Problem Discovery: Whenever the agent detects that the performance indicators of the current circuit violate the preset design constraints during the simulation, the system will automatically trigger the long-term memory recording mechanism. This module extracts the "Design Problem Layer" node from step S3 as the entry point and clearly records the specific performance deviations faced by the current design (such as "noise figure exceeding the standard in a specific frequency band").

[0139] S42. Root Cause Analysis: The system relies on the underlying causal evolution network to trace back along the timeline and dependency edges. In practical implementation, the system can perform a depth-first traversal of the graph library using a graph query language to find the physical root cause of the aforementioned problem. This module is responsible for extracting and solidifying the logical deduction path that maps from the problem's manifestations down to the underlying component parameter mismatch or topological defects.

[0140] S43. Optimization Measures: This module fully extracts the strategy chain adopted by the agent to eliminate the aforementioned root causes. In particular, to endow the agent with the ability of "negative feedback obstacle avoidance," the system not only records the successful strategies that ultimately converged the goal, but also simultaneously retains the failed attempts that triggered performance degradation or ineffectiveness during the exploration process. This data record of positive and negative comparisons constitutes the core of expert-level troubleshooting experience.

[0141] S44. Result Verification: Extract the new round of simulation feedback generated after the strategy actions are executed, and compare it with the initial constraints in the "Problem Discovery" phase to verify the actual effectiveness of the optimization measures. This module records in detail the final improvement of each performance indicator, thus forming a physically and logically self-consistent data loop.

[0142] S45. Experience Tags: To ensure high-precision retrieval of the generated experience within the vast database, the system attaches multi-dimensional metadata tags to the collected closed-loop data. The tags cover key contextual environments such as the current process library node (e.g., specific PDK ontology constraints), operating frequency band, circuit topology type, and core operation objects.

[0143] S46, Episode Packaging and Transferable Design Experience Generation:

[0144] Finally, the system structurally integrates the heterogeneous information from the five dimensions of "problem discovery", "cause analysis", "optimization measures", "result verification" and "experience tags", and encapsulates them into an independent episode memory unit.

[0145] In engineering deployment, the encapsulated episode can be serialized and stored in a document-oriented database using an Object Document Mapping (ODM) framework (such as Python-based tools like Beanie), while internally retaining index pointers to graph database nodes. This comprehensive encapsulation model transforms fragmented design logs into systematic, transferable design experience. When the agent faces similar RF design scenarios in the future, it can directly access this entire verified logic chain, avoiding repeated trial-and-error iterations and greatly improving the efficiency of solving complex engineering problems.

[0146] S5. Perform experience abstraction, clustering and fusion, and backbone scoring and screening on the contextual memory units to retain high-value causal experience paths and construct a skeletonized design experience backbone network.

[0147] Combination Figure 6In step S5, the system, based on the Episode set generated in step S4, specifically performs the abstraction of design experience and the construction of the Design Experience Backbone Network (DEBN). This step aims to remove redundant operational noise by structurally compressing and refining massive, fragmented contextual memory units, forming an expert-level design experience skeleton with long-term stability and cross-task transferability. Its specific implementation process includes the following sub-steps:

[0148] S51. Design Experience Abstraction and Pattern Discovery: The system uses a long-term accumulated set of episodes as its underlying input source. First, the system performs statistical analysis and design experience abstraction on the closed-loop link of "problem-cause-strategy-result" in each independent scenario unit. Utilizing topological subgraph mining algorithms (such as frequent pattern mining based on graph structures), the system discovers experience patterns in massive historical episodes, automatically identifying common causal evolution paths that frequently recur across projects and tasks and have been verified as effective.

[0149] S52. Experience Clustering and Fusion: After discovering common experience patterns, the system triggers the experience clustering and fusion module. Since there may be slight differences in the descriptions given by different design tasks or engineers when recording logs, the system uses the basic vectorized representation and RF domain dictionary established in step S14 to calculate the semantic and structural similarity between different experience patterns. The system clusters experience fragments with highly similar topologies and similar physical meanings into the same cluster, and performs topology graph fusion and node standardization updates, thereby eliminating the limitations of locally fragmented experiences and achieving preliminary storage redundancy compression.

[0150] S53. Quantitative Assessment Based on the Backbone Scoring Mechanism: The integrated experience chain will be input into the backbone scoring mechanism module. The system comprehensively considers multiple dimensions such as importance, confidence, recurrence frequency, duration of effectiveness, and cross-project transferability, utilizing a preset backbone scoring function. Each abstracted experience path is precisely quantified and scored:

[0151]

[0152] The specific parameters and calculation logic are as follows: This indicates the number of contextual memory units contained in the current experience path; Indicates the first in the experience path One contextual memory unit; Indicates the first The frequency of recurrence of an experience unit in different design tasks; Indicates the first Success rate of each experience unit; Indicates the first Cross-task transfer factor for each experience unit; , , These represent the weighting coefficients corresponding to reproduction frequency, success rate, and transferability, respectively. Indicates the current time point. Indicates the first The generation time of each experience unit; This represents the time decay factor, used to describe the decay process of the influence of historical experience over time. This represents the experience forgetting decay coefficient. By comprehensively considering the degree of experience reproducibility, effectiveness, transferability, and time factors, it enables the quantitative screening of high-value design experience paths.

[0153] S54. High-Value Experience Screening: Based on the comprehensive score calculated using the backbone scoring function, the system performs high-value experience screening. The system sets a fixed backbone retention threshold. Only when the score of a causal experience path is high enough will the high-value experience be selected. Only when the threshold is exceeded is it judged as a "core knowledge skeleton" with universal guiding value and retained; while those low-scoring, occasional trial and error in specific projects or highly limited fragmented operation paths are automatically pruned and eliminated by the system, thereby achieving a high proportion of structured compression of long-term memory while ensuring the integrity of experience and causal relationships.

[0154] S55. Design Experience Backbone Network (DEBN) Generation: Finally, the system reorganizes the selected high-value experience nodes according to the inherent RF engineering logic to formally build and solidify the Design Experience Backbone Network (DEBN).

[0155] like Figure 6 As shown in the right-hand box, the final generated DEBN presents a stable backbone network, composed of multiple interconnected high-value experience nodes (such as experience node A, experience node B, experience node C, experience node D, and experience node E). At the specific network hierarchy, these nodes strictly follow a causal network topology consisting of target nodes, problem nodes, policy nodes, and result nodes. The nodes are connected in a directed manner through computationally fixed causal links, forming a long-term stable knowledge backbone platform capable of simulating the thinking logic of senior engineers, possessing high-level causal reasoning capabilities, and providing the core navigation framework for experience retrieval and dynamic evolution under subsequent new tasks (steps S6 and S7).

[0156] S6. Dynamic evolution of the design experience backbone network.

[0157] Combination Figure 7In step S6, the system, based on the constructed Design Experience Backbone Network (DEBN), specifically performs experience retrieval and strategy recommendation for new tasks, and completes closed-loop dynamic evolution update of long-term memory based on the actual execution results. Its specific implementation process includes the following sub-steps:

[0158] S61. New Design Task Parameter Analysis: When the agent receives a new RF chip design project, the system first performs structured analysis on the input design goals, design constraints and environmental parameters (such as target process node, operating frequency band, etc.), and encapsulates them into query probe vectors as the initial conditions for triggering long-term memory retrieval.

[0159] S62. DEBN Experience Retrieval and Causal Inference: The system inputs a query probe into the DEBN and uses a target matching algorithm to quickly locate the experience starting point node in the skeleton network that is most similar to the current task context. After localization, the system performs causal inference downwards along the directed links of the graph, calculating the recommendation score for each potential policy path. :

[0160]

[0161] in, The semantic and environmental similarity between the current new task and the starting point of the main experience. For this path The cumulative confidence level of each causal edge. This represents candidate causal reasoning paths in the backbone network of design experience; This indicates the new design task being input. Indicates the starting experience node of the candidate experience path; It represents the comprehensive similarity between the current design task and the experience starting point node, including the semantic similarity of the design target and the similarity of contextual conditions such as process environment and operating frequency band; This represents the causal influence strength of the e-th causal relationship edge inherited from step S35, and is used to characterize the reliability of each causal relationship in path P. This represents the overall path confidence score, calculated by accumulating the influence strength of each causal edge in the path. By combining the task matching degree with the reliability of empirical paths, it enables the ranking and recommendation of candidate design experiences.

[0162] S63, Strategy Recommendation and Execution Design Task: Based on Based on the ranking of scores, the system outputs a structured optimization path and design suggestions to the agent. These suggestions not only include specific parameter adjustment instructions but also provide interpretable causal analysis based on the underlying causal chain. Subsequently, the agent adopts the recommended strategy and executes the design task in a real EDA environment.

[0163] S64. Task Execution Result Acquisition: After the design operation is executed and the simulation iteration is completed, the system background automatically extracts the latest RF performance index improvement, DRC / LVS verification results, and user feedback during manual intervention, transforming theoretical recommendations into objective verification closed-loop data.

[0164] S65, DEBN Dynamic Evolution Update: The system compares the actual execution results with the initial design goals, generates positive or negative feedback signals, and sends them back to the core graph through the feedback loop to trigger dynamic updates.

[0165] Reinforcement and Integration: If the recommended strategy is verified to be effective (especially if it is successfully reproduced across process nodes), the system strengthens the edge weights of the empirical path; if a better fine-tuning operation is derived during execution, the system abstracts it as a new node and integrates it into the backbone network.

[0166] Decay and Elimination: If the recommendation strategy fails or causes performance degradation, the system decays the weight of the causal edge; when the weight of an experience falls below the retention threshold, the system removes it from the backbone network.

[0167] Finally, the system periodically monitors the empirical entropy of the entire network. To assess memory stability. Among them, This represents the total number of experience categories in the current design experience backbone network; Indicates the first Experience-based pattern; Indicates the first The probability distribution of a class of experience patterns in the overall experience network is used to describe the proportion of that class of experience in long-term memory. This represents the logarithmic function in information entropy calculation. When the empirical entropy is within a stable range, it indicates that the core empirical structure in the design empirical backbone network remains stable. When the empirical entropy continues to increase, it indicates that more new empirical patterns are added to the network and the empirical distribution tends to be discrete. Based on the changes in empirical entropy, the system triggers empirical clustering operations to divide empirical nodes with similar semantic features and similar topological structures into the same empirical cluster in order to maintain the long-term stability of the design empirical backbone network.

[0168] Through the above series of steps, the present invention successfully constructs a long-term memory platform for radio frequency chip design intelligent agents that has self-organizing and self-evolving capabilities and can support high-level causal reasoning.

[0169] To objectively evaluate the performance of the agent based on the Design Experience Backbone Network (DEBN) of this invention in complex chip design tasks, this embodiment constructs a standardized comparative experimental scheme. The experiment selects "Automated Design of Radio Frequency Power Amplifiers (PA)" as the benchmark task, and the comparison objects include: traditional retrieval schemes based on vector databases and inference schemes based on pure large-model chain-of-thought (CoT).

[0170] The evaluation metrics were selected with reference to common standards in the fields of knowledge graph reasoning and reinforcement learning optimization, including: average convergence steps, causal link prediction accuracy, and memory retrieval response latency. Experimental results are shown in Table 1.

[0171] Table 1: Comparison of Objective Performance Indicators of DEBN-based Agents in PA Design Tasks

[0172]

[0173] In the experimental data above, the causal link prediction accuracy (Hit@3) reflects the agent's ability to accurately infer the "failure cause - optimization strategy" path from long-term memory when facing design problems. Experimental results show that the DEBN scheme achieves 0.89, significantly higher than the traditional RAG scheme. This indicates that through the skeletal organization of the "experience backbone," the system eliminates random noise in massive redundant logs and can accurately capture the essential causal relationship between design parameters and performance indicators.

[0174] The average number of iterations (Steps) required to achieve the goal is a core metric for measuring the decision-making efficiency of an agent. The proposed solution requires only 38 simulation iterations to converge the design goal, reducing simulation time by approximately 75% compared to the Vector-RAG approach. This is primarily due to the structured strategy guidance provided by DEBN, which enables the agent to avoid historically proven ineffective "search blind spots."

[0175] Finally, quantitative data on memory retrieval response latency show that, because DEBN compresses the massive, linearly growing design log into a topologically stable skeleton network, its retrieval space complexity is reduced from... Reduced to approximately This enables intelligent agents to maintain millisecond-level real-time response capabilities even when processing massive long-term memories. The aforementioned objective indicators fully demonstrate the technological advancement and engineering practicality of this invention in solving complex EDA design problems.

[0176] In practical applications, such as performance optimization of monolithic microwave integrated circuits (MMICs), this invention can significantly shorten the iteration cycle. Traditional AI optimizers may require hundreds of simulations to understand circuit characteristics, while an agent with DEBN can directly identify the main contradictions of the current mismatch from the "experience backbone," skipping invalid search regions and converging to the optimal solution with only a few simulations. This fully demonstrates the great application value of this invention in complex engineering practices.

[0177] Example 2:

[0178] A long-term memory construction system based on a design experience backbone network includes:

[0179] The design event acquisition and standardized modeling module is used to collect multi-source heterogeneous data and generate standardized design event sequences.

[0180] The multi-granularity temporal design evolution graph construction module is used to construct a multi-granularity temporal design evolution graph based on standardized design event sequences, which includes micro-event-level sequences, meso-dependency networks, and macro-context aggregation branches.

[0181] The design causal evolution network construction module is used to extract five layers of nodes—design target layer, problem layer, cause layer, strategy layer, and result layer—from the multi-granularity time-series design evolution graph, establish causal relationship edges between each layer, calculate the causal influence strength, and generate the design causal evolution network.

[0182] The context memory unit encapsulation module is used to structurally integrate problem discovery, cause analysis, optimization measures, result verification and experience labels based on the design causal evolution network, and encapsulate them into independent context memory units to form transferable design experience;

[0183] The design experience backbone network construction module is used to perform experience abstraction, clustering and fusion, and backbone scoring and screening of context memory units, retaining high-value causal experience paths and constructing a skeletonized design experience backbone network; the design experience backbone network is used to support experience retrieval, causal reasoning, and strategy recommendation for new design tasks.

Claims

1. A method for constructing long-term memory based on a backbone network of design experience, characterized in that, Includes the following steps: S1. Generate a standardized design event sequence based on the collected multi-source heterogeneous data; S2. Based on standardized design event sequences, construct a multi-granularity temporal design evolution map that includes micro-event-level sequences, meso-level dependency networks, and macro-level context aggregation branches; S3. Extract five layers of nodes—design target layer, problem layer, cause layer, strategy layer, and result layer—from the multi-granularity time-series design evolution graph, establish causal relationship edges between each layer, calculate the causal influence strength, and generate a design causal evolution network. S4. Based on the design causal evolution network, the problem discovery, cause analysis, optimization measures, result verification and experience labeling are structurally integrated and encapsulated into independent context memory units to form transferable design experience. S5. The contextual memory units are subjected to experience abstraction, clustering and fusion, and backbone scoring and screening to retain high-value causal experience paths and construct a skeletonized design experience backbone network. The design experience backbone network is used to support experience retrieval, causal reasoning and strategy recommendation for new design tasks.

2. The long-term memory construction method based on a design experience backbone network according to claim 1, characterized in that, S1 includes: S11. Collect and integrate multi-source heterogeneous data, including design requirements, design decisions, EDA call records, parameter adjustments, simulation results, verification results, and user feedback; Multi-source heterogeneous data is stitched together into a design data stream with a unified timeline; S12. The time-interval-based sliding window algorithm and state machine matching rules cut and aggregate the design data stream into design behavior segments with independent engineering significance according to the context dependency of EDA operations. S13. Extract the design target features, design action features, and performance result features of each design behavior segment; S14. Semantically encode the design target features, design action features, and performance result features, map them into high-dimensional continuous semantic vectors, and encapsulate the output as a standardized design event sequence.

3. The long-term memory construction method based on a design experience backbone network according to claim 1, characterized in that, S2 include: S21. Extract the timestamp of each design event in the standardized design event sequence, sort them according to the order of occurrence, import the design events as nodes into the graph database, and connect adjacent events end to end through directed time edges to form a micro-event level sequence that is linearly progressive in time. S22. Compare and analyze the overlap and physical correlation of events before and after in the micro-event-level sequence in terms of the change of the operation object and parameters, and calculate the dependency score; based on the dependency score, characterize the dependency relationship and generate the meso-level dependency relationship network; S23. Monitor changes in the context and design goals in the event stream. If the context remains consistent, the corresponding sequence is abstracted and aggregated upwards into macro-strategy nodes. If the context undergoes a sudden change, new evolution path branches are split off, generating macro-context aggregation branches. S24. Perform structural mapping and topological fusion of micro-event-level sequences, meso-level dependency networks, and macro-level context aggregation branches in the same graph space to form a multi-granularity temporal design evolution map.

4. The method for constructing long-term memory based on a backbone network of design experience according to claim 1, characterized in that, S3 includes: S31. Extract macroscopic design constraints from the multi-granularity temporal design evolution graph and construct the design target layer. If the agent detects that the actual performance parameters fail to meet the design target, it triggers a constraint violation event and maps it down to the problem layer to generate the corresponding concrete problem node. S32. For the design defects extracted from the problem layer, perform reverse tracing in conjunction with the pre-built RF engineering knowledge graph to construct the cause layer; S33. Based on the actual design actions recorded in the multi-granularity temporal design evolution graph, aggregate them and abstract them upwards into strategy layer nodes; utilize dependencies to establish connections between the cause layer and the strategy layer using associated edges; S34. Extract performance index migration data from the associated simulation report and generate result layer nodes.

5. The method for constructing long-term memory based on a backbone network of design experience according to claim 4, characterized in that, In S3: The target layer and the problem layer are connected by a unidirectional directed edge; Based on the characteristics of the problem nodes, the cause layer is broken down into specific causes at the underlying physical and circuit topology levels, and corresponding cause nodes are generated; causal relationship edges are established between the problem layer and the cause layer. The connection between the cause layer and the strategy layer includes solid lines and dashed lines; solid lines represent strong causal relationships and direct targeted strategies; dashed lines represent cross- or weakly coupled strategy attempts with exploratory nature. The results layer records the performance improvement of various specific RF indicators; the performance improvement nodes are summarized and converge to the final state node, forming a complete engineering closed loop with the design target layer.

6. The method for constructing long-term memory based on a backbone network of design experience according to claim 4, characterized in that, S3 also includes: S35, Parameter adjustment action in the calculation strategy layer Its resulting performance The strength of causal influence between them (CI): ； in, The physical sensitivity gradient of the simulation results to parameter adjustments, This represents the co-occurrence frequency of the causal pair in the historical graph database and the environmental moderating factors; The semantic vector dimension representing the design event; This represents the normalization function, used to map the influence intensity of different causal paths to a unified probability space.

7. The method for constructing long-term memory based on a backbone network of design experience according to claim 1, characterized in that, Episodic memory units in S4 include: Problem Discovery: When a performance metric is detected to violate design constraints, long-term memory recording is triggered, and problem layer nodes are extracted from the design causal evolution network as entry points; Cause analysis: Tracing back along the causal path to locate the physical root cause of the problem and extracting the logical deduction path from the problem's symptoms to its root cause; Optimization measures: Extract the strategy chain taken to eliminate the root cause, while retaining comparative data of successful strategies and failed attempts; Results verification: Extract the simulation feedback results after the strategy is executed, compare them with the initial constraints to verify the effectiveness of the optimization; Experience tags: Additional metadata tags including process node, operating frequency band, circuit topology type, and core operating objects.

8. The method for constructing long-term memory based on a backbone network of design experience according to claim 1, characterized in that, S5 include: S51. Perform statistical analysis on the closed-loop links in each episodic memory unit to identify frequently repeated and validated cross-task links. The causal evolutionary path; S52. Calculate the semantic similarity and structural similarity between different causal evolution paths, aggregate the causal evolution paths, and perform topological graph fusion and node standardization update. S53. Use the main scoring function to quantify and score each abstracted causal evolution path; S54. Set a backbone retention threshold. Paths with backbone scores exceeding the backbone retention threshold are identified as core knowledge skeletons and retained. Fragmented paths with backbone scores below the backbone retention threshold are automatically pruned and eliminated. S55. The selected causal evolution paths are reorganized into graph topology according to their internal logic to construct the backbone network of design experience.

9. The method for constructing long-term memory based on a backbone network of design experience according to claim 1, characterized in that, It also includes the dynamic evolution of S6 and the design experience backbone network, specifically including: S61. Receive the target, constraint and environmental parameters of the new design task and encapsulate them as a query probe; S62. Input the query probe into the design experience backbone network, locate the most similar experience starting node, perform path reasoning along the directed causal link, and calculate the recommendation score of each potential strategy path. S63. Based on the recommendation scores, output structured optimization paths and design suggestions to the agent. The agent adopts the recommendations and executes the design task. S64. Extract the performance improvement, verification results, and user feedback after the design task is completed; S65. Based on the actual execution results, strengthen or weaken the corresponding experience paths, and the derived new strategies are then abstracted and integrated into the backbone network; when the experience weight is lower than the retention threshold, it is eliminated from the backbone network.

10. A long-term memory construction system based on a design experience backbone network, characterized in that, include: The design event acquisition and standardized modeling module is used to collect multi-source heterogeneous data and generate standardized design event sequences. The multi-granularity temporal design evolution graph construction module is used to construct a multi-granularity temporal design evolution graph based on standardized design event sequences, which includes micro-event-level sequences, meso-dependency networks, and macro-context aggregation branches. The design causal evolution network construction module is used to extract five layers of nodes—design target layer, problem layer, cause layer, strategy layer, and result layer—from the multi-granularity time-series design evolution graph, establish causal relationship edges between each layer, calculate the causal influence strength, and generate the design causal evolution network. The context memory unit encapsulation module is used to structurally integrate problem discovery, cause analysis, optimization measures, result verification and experience labels based on the design causal evolution network, and encapsulate them into independent context memory units to form transferable design experience; The design experience backbone network construction module is used to perform experience abstraction, clustering and fusion, and backbone scoring and screening of contextual memory units, retaining high-value causal experience paths, and constructing a skeletonized design experience backbone network; the design experience backbone network is used to support experience retrieval, causal reasoning, and strategy recommendation for new design tasks. The aforementioned long-term memory construction system based on a design experience backbone network is used to implement the long-term memory construction method and steps based on a design experience backbone network as described in claim 1.

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