A two-dimensional material transistor-based spiking neural network system

Abstract

The application discloses a kind of pulse neural network systems based on two-dimensional material transistor, including tactile sensor, pulse coding unit, synapse transistor array, signal acquisition unit, controller and voltage driving unit connected in turn, voltage driving unit is also connected with pulse coding unit and synapse transistor array;Pulse coding unit includes leaky integrate-and-fire (LIF) neuron circuit and pulse coding transistor with double-gate structure;LIF neuron circuit based on pulse coding transistor converts tactile sensing signal into standard pulse signal, and the threshold potential and firing frequency of output pulse are controlled by adjusting the bottom gate voltage of pulse coding transistor;Synapse transistor array is constructed by synapse transistor with non-volatility, for receiving standard pulse signal and carrying out multiply-accumulate (MAC) dynamic calculation;Synapse transistor array adopts grouping differential topology structure, to realize the configuration of positive and negative weight.

Description

Technical Field

[0001] This invention belongs to the fields of neuromorphic computing and two-dimensional semiconductor devices, specifically relating to a spiking neural network system based on two-dimensional material transistors. Background Technology

[0002] Spiking Neural Networks (SNNs), as the third generation of artificial neural networks, have become a core technological path to break through the bottlenecks of the traditional von Neumann architecture and achieve integrated tactile sensing and computing, thanks to their event-driven, low-power, and biomimetic characteristics. They hold irreplaceable application value in fields such as precise manipulation of intelligent robots, wearable devices, and human-computer interaction. Traditional sensing and processing systems employ a separate architecture, transmitting large amounts of data over long distances, resulting in high latency, high energy consumption, slow computational efficiency, and high hardware complexity, making them unsuitable for miniaturized, low-power, and intelligent application scenarios. Compared to optoelectronic sensing and computing systems, which often require bulky laser equipment, tactile sensing and computing systems are easier to integrate deeply with robotics in terms of physical form and interaction methods. However, current patents and research in the field of sensing and computing are mostly focused on optoelectronics, image processing, and computing itself; the underlying hardware architecture truly integrated with tactile perception is still in its early stages.

[0003] Currently, memristors are commonly used as core processing devices in neural network hardware systems. For example, in the construction of tactile memory systems, almost all functional modules are implemented based on memristors. However, memristors have inherent defects such as poor device consistency, limited durability, and high randomness, which severely restrict the computational accuracy and long-term stability of the system. Especially in the neuron pulse coding stage, the excitation threshold of the memristor is highly dependent on its own physical characteristics, making it extremely difficult to dynamically and flexibly adjust in practical applications, and unable to perfectly adapt to changing external stimuli.

[0004] At the pulse coding and neuron circuit level, existing pulse coding units mostly rely on highly complex pure circuits or complex combinations of multiple transistors. For example, for input signals from tactile or photoelectric sensors, current technologies typically require building pure analog / digital circuits containing numerous components for pulse shaping and encoding; or combining complex logic control and forward / reverse drive circuits around memristors; or using dual-gate transistors combined with comparators and other peripheral devices to construct the encoding unit. This design results in an insufficiently simple hardware architecture, and current LIF (Leaky Integrate-and-Fire) neuron circuits fail to fully utilize the intrinsic electrical characteristics of transistors themselves. This not only leads to the need to improve the stability and response speed of pulse shaping and integration reset, but also makes the encoding unit, storage unit, and computing unit usually independent of each other, making it difficult to truly achieve integrated near-sensor integration, further exacerbating the system's size and power consumption burden.

[0005] In synaptic transistor array architectures and Multiply Accumulate (MAC) operations, the implementation of positive and negative weights often heavily relies on differential arrays and associated circuitry. While existing single-column output architectures save area (outputting one signal per column), their effectiveness in implementing positive and negative weights is extremely poor. Traditional dual-column differential output architectures (outputting one signal per two columns), while effectively implementing positive and negative weights, significantly increase the area of ​​the core array, resulting in high hardware redundancy and a relatively complex architecture. Furthermore, some existing technologies propose adding a global reference signal to the single-column output architecture for subtraction with all signal columns. While this architecture is suitable when the differences in row input signals are small, the tactile sensing signals often exhibit dramatic fluctuations and significant differences in timing, amplitude, and other characteristics. Using a single reference column would introduce substantial computational errors, while using dual-column differential arrays exclusively would lead to an overly bloated system.

[0006] At the level of underlying physical devices and materials, two-dimensional materials, with their advantages such as atomic-level thickness, high carrier mobility, and excellent electrostatic control capabilities, have become an ideal choice for constructing high-performance neuromorphic devices. Although some neural network elements based on two-dimensional materials or ferroelectric floating gate structures have been proposed in the industry, the current material selection and structural design of two-dimensional material transistors lack specificity and fail to fully adapt to the special input characteristics and encoding requirements of tactile sensing signals. In particular, in synaptic transistors, there is a problem of poor interface matching between two-dimensional materials and ferroelectric materials, resulting in insufficient non-volatility and polymorphic tunability. The operation of synaptic transistor arrays fails to fully utilize the intrinsic advantages of two-dimensional material transistors in in-memory computing, seriously affecting computational accuracy and in-memory computing synergy.

[0007] In summary, overcoming the inherent limitations of memristors and complex peripheral circuits, and fully utilizing the device-level physical characteristics of novel two-dimensional materials and dual-gate / floating-gate structures to achieve flexible threshold and frequency control; overcoming the precision and redundancy contradiction of traditional single / dual-row synaptic transistor arrays when processing highly differential tactile signals; and developing a highly integrated, hardware-simple, low-latency, low-power, and perfectly simulated near-sensor computing intelligent tactile perception processing system based on novel pulse-coded neurons and synaptic device arrays have become key technological bottlenecks that urgently need to be addressed in this field. Summary of the Invention

[0008] The purpose of this invention is to overcome the shortcomings of the prior art and provide a spiking neural network system based on two-dimensional material transistors, realizing the integrated fabrication of pulse coding units and synaptic transistor arrays, and solving the shortcomings of existing spiking neural network hardware systems such as complex coding circuit structure, high power consumption, large delay, low integration and poor device stability.

[0009] The objective of this invention is achieved through the following technical solution: A pulse neural network system based on two-dimensional material transistors is used to encode, store and compute tactile sensing signals for pulse neural networks. It includes a tactile sensor, a pulse coding unit, a synaptic transistor array, a signal acquisition unit, a controller and a voltage driving unit connected in sequence. The voltage driving unit is also connected to the pulse coding unit and the synaptic transistor array. The pulse coding unit includes a leaky integral firing (LIF) neuron circuit and a pulse coding transistor with a dual-gate structure; the LIF neuron circuit based on the pulse coding transistor converts the tactile sensing signal into a standard pulse signal, and controls the threshold potential and firing frequency of the output pulse by adjusting the bottom gate voltage of the pulse coding transistor; The synaptic transistor array is constructed from non-volatile synaptic transistors and is used to receive the standard pulse signal and perform multiply-accumulate MAC dynamic calculations. The synaptic transistor array adopts a grouped differential topology to configure positive and negative weights.

[0010] Furthermore, the LIF neuron circuit includes an input resistor R1, an integrating capacitor C1, a leakage resistor R2, a pulse-coded transistor T1, and an output resistor R3. The integrating capacitor C1 is used to store charge to simulate the neuron membrane potential. The input resistor R1 and the integrating capacitor C1 form an RC charging circuit to control the rise rate of the neuron membrane potential. The leakage resistor R2 provides a discharge path to achieve passive leakage of the neuron membrane potential. The top gate and drain of the pulse-coded transistor T1 are connected to the integrating capacitor C1 as signal input terminals. The source is grounded through the output resistor R3, and a standard pulse signal is output between the source and the output resistor R3.

[0011] Furthermore, the pulse-coded transistor is a two-dimensional transition metal sulfide material transistor with a top-gate and bottom-gate dual-layer gate structure; the channel material of the pulse-coded transistor is MoS2, the top-gate dielectric is Al2O3, and an h-BN layer is provided between the channel material and the substrate.

[0012] Furthermore, the synaptic transistor has a bottom gate and a floating gate structure, using a two-dimensional material as the channel and a ferroelectric material as the gate dielectric; the channel material is WSe2, the ferroelectric material is α-In2Se3, the bottom gate and the floating gate are made of TiN, and an h-BN layer is provided between WSe2 and the floating gate; the polarization of α-In2Se3 is controlled by the bottom gate, and the conductance of WSe2 is controlled by the TiN floating gate, thereby achieving non-volatile storage of multi-state conductance.

[0013] Furthermore, the grouped differential topology of the synaptic transistor array is characterized by the following: each row of the array includes several computing units, and each computing unit includes one reference transistor and two signal processing transistors; after the output currents of the transistors in the same column are summarized, the current in the column where the signal processing transistor is located is differentially divided with the current in the column where the reference transistor is located, so as to realize the storage and calculation of positive and negative weights.

[0014] Furthermore, the source of the pulse-coded transistor is connected to the drain of the synaptic transistor as an input signal, and the pulse-coded transistor and the synaptic transistor array are integrated and fabricated on the same substrate.

[0015] Furthermore, the LIF neuron circuit is used to shape and integrate the tactile sensing signal, converting it into a standard pulse signal that meets the processing requirements of the synaptic transistor array. When the gate potential of the pulse coding transistor T1 reaches the threshold, T1 switches from off to on and generates a discharge current. Subsequently, it completes a reset and enters the refractory period, simulating the leakage integral discharge behavior of biological neurons.

[0016] Furthermore, by adjusting the bottom gate voltage of the synaptic transistors, the conductance of each synaptic transistor in the synaptic transistor array is set sequentially, thereby achieving weight updates and calibration; the input signal for each row is the pulse signal TS output by the pulse-coded transistor. OUT The number of array rows is the same as the number of pulse coding units. The synaptic transistor array adopts row activation and column reading. The pulse voltage of the pulse coding unit is multiplied by the synaptic conductance of the corresponding synaptic transistor to generate current. The current in the same column is naturally accumulated. After passing through the grouped differential topology, MAC operation is realized.

[0017] Compared with the prior art, the beneficial effects of the technical solution of the present invention are: 1. The pulse coding unit of this invention is constructed based on a LIF neuron circuit and a dual-gate pulse coding transistor. The LIF neuron circuit simulates the leakage integral characteristics of biological neurons, possessing advantages such as simplified structure, fast response speed, and low power consumption. The pulse coding transistor allows for flexible adjustment of the threshold potential and frequency. The pulse coding unit can convert the analog voltage signal output by the sensor into a pulse sequence recognizable by the SNN, possessing both fast and slow adaptive coding capabilities, and can distinguish between pressure magnitude and contact time. Furthermore, this invention integrates the dual-gate transistor into the LIF circuit, directly controlling the threshold and frequency using the bottom gate voltage. The device itself undertakes part of the circuit function, significantly simplifying the hardware structure and reducing encoding power consumption and latency.

[0018] 2. The synaptic transistor array of this invention adopts a grouped differential topology architecture to realize the storage and calculation of positive and negative weights. Compared with the high area overhead of the traditional global dual-column differential structure which uses two columns to output one signal, the grouped differential reduces the number of differential circuits while ensuring accurate calculation of positive and negative weights by reusing reference columns, thereby reducing hardware complexity and power consumption. The high computational efficiency helps to improve the hardware MAC operation speed and system stability.

[0019] 3. The two-dimensional material transistor of this invention, by optimizing the materials and structure of the pulse-coded transistor and the synaptic transistor, significantly improves the device consistency, integration, flexibility and durability compared to the memristor solution; the pulse-coded transistor uses two-dimensional materials to construct a dual-gate structure transistor, which has excellent carrier mobility, on / off ratio and stability; the synaptic transistor uses two-dimensional materials and ferroelectric materials, which have the advantages of non-volatility and ferroelectric polarization stability, and achieve stable and continuously adjustable conductance.

[0020] 4. This invention highly integrates pulse-coded transistors and synaptic transistors, designed on a micrometer-level lateral scale and a nanometer-level vertical scale. The output of the pulse-coded unit directly serves as the input signal to the synaptic transistor array. Through the integrated architecture of pulse coding and synaptic transistor array, the output of the pulse-coded transistor is directly coupled to the input of the synaptic transistor array, avoiding the overhead of long-distance transmission of massive analog data and analog-to-digital conversion, making integrated processing of the entire process possible. It achieves the integration of signal input, storage, and proximity calculation, breaking the von Neumann bottleneck. Data does not need to be transmitted over long distances, optimizing response speed and overall power consumption, and adapting to low-power, miniaturized, and low-latency application scenarios. Attached Figure Description

[0021] Figure 1 The diagram shows the structure of a spiking neural network system based on two-dimensional material transistors, as provided in an embodiment of the present invention.

[0022] Figure 2 This is a schematic diagram of a grouped differential topology architecture for a synaptic transistor array provided in an embodiment of the present invention.

[0023] Figure 3 This is a schematic diagram of the LIF neuron circuit provided in an embodiment of the present invention.

[0024] Figure 4 This is a simulation diagram of the LIF neuron circuit provided in an embodiment of the present invention.

[0025] Figure 5 This is a schematic diagram of a pulse-coded transistor structure provided in an embodiment of the present invention.

[0026] Figure 6 This is a schematic diagram of a synaptic transistor structure provided in an embodiment of the present invention. Detailed Implementation

[0027] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only for explaining the present invention and are not intended to limit the present invention.

[0028] Example 1 See Figure 1 The pulse neural network system based on two-dimensional material transistors provided in this embodiment includes a tactile sensor, a pulse coding unit, a synaptic transistor array, a signal acquisition unit, a controller, and a voltage driving unit connected in sequence. The voltage driving unit is also connected to the pulse coding unit and the synaptic transistor array. The modules work together to realize the integrated encoding, storage, and calculation of tactile sensing signals.

[0029] The tactile sensor is used to sense external stimuli and output corresponding signals to the pulse coding unit. The tactile sensor can be a triboelectric sensor, a resistive sensor, or a capacitive sensor. Among them, the triboelectric sensor is suitable for low power consumption and dynamic pressure detection scenarios, while the resistive and capacitive sensors are suitable for static pressure detection scenarios. The signals generated by the tactile sensor are preprocessed before entering the next stage. The transient spike signals generated by the triboelectric sensor are converted into stable analog signals by a field-effect transistor circuit. The signals generated by the resistive sensor are filtered by an RC circuit. The signals generated by the capacitive sensor are converted into analog signals by a charge amplifier. The processed tactile sensing signals are input to the pulse coding unit. Each pulse coding unit corresponds to one tactile sensor unit, realizing parallel encoding of multiple tactile sensing signals. The LIF neuron circuit based on pulse-code transistors shapes and integrates tactile sensing signals, converting them into standard pulse signals that meet the processing requirements of synaptic transistor arrays. The LIF neuron circuit simulates the leakage integral firing behavior of biological neurons. Synaptic transistors with non-volatile multi-level conductance storage characteristics can store weights for a long time. The synaptic transistor array adopts a grouped differential topology architecture, which can realize MAC operation that supports positive and negative weights. By constructing a synaptic transistor array and cooperating with corresponding circuits, the storage and computation of pulse signals can be completed. The voltage driving unit includes a control circuit and a weight setting circuit, mainly constructed by a digital-to-analog converter (DAC) and an operational amplifier (OPA), which outputs pulse signals with adjustable amplitude and frequency. The control circuit is connected to the bottom gate of the pulse code transistor to adjust the threshold potential and firing frequency of the output pulse. The weight setting circuit is connected to the bottom gate of the synaptic transistor and writes and updates the synaptic conductance by outputting pulse signals with specified amplitude and frequency within a preset duration. The signal acquisition unit is used to acquire the current output by the synaptic transistor array. It mainly consists of a transimpedance amplifier (TIA), an RC circuit, a subtractor, and an analog-to-digital converter (ADC). The TIA is used to convert the current signal into a voltage signal and amplify it. The RC circuit performs filtering. The subtractor performs differential operations. The ADC converts the operation result into a standard digital signal and outputs it to the controller. The controller uses a field-programmable gate array (FPGA) as its hardware carrier and completes the internal logic configuration. The software program includes a signal analysis module, a drive control module, and an SNN operation module, which are responsible for real-time analysis of current signals, precise control of voltage amplitude and drive timing, and weight training and inference operation of SNN, respectively. Through the mutual coordination of pulse coding unit, synaptic transistor array, corresponding hardware circuit and FPGA software program, the proximity calculation of tactile perception is realized.

[0030] See Figure 2 This diagram illustrates the grouped differential topology architecture of the synaptic transistor array in this embodiment. Each row of the synaptic transistor array includes multiple computing units. Each computing unit includes one reference transistor and two signal processing transistors. Using the conductance of the reference transistor as a reference point, when the conductance of the signal processing transistor is greater than that of the reference transistor, it corresponds to a positive weight in the neural network; when the conductance of the signal processing transistor is less than that of the reference transistor, it corresponds to a negative weight in the neural network. The output currents of transistors in the same column are accumulated. The outputs of the two columns of signal processing transistors are differentially analyzed with the output of the column containing the reference transistor. Each computing unit outputs two valid signals. The input signal for each row is the pulse signal TS output by the pulse code transistor. OUT The number of rows in the synaptic transistor array is equal to the number of pulse coding units and they are connected one-to-one. The synaptic transistor array adopts a row-line input activation and column-line parallel reading method. Utilizing Ohm's law and Kirchhoff's law, the pulse voltage output by the pulse coding unit is applied to the row line, multiplied by the synaptic conductance at the intersection point to generate current. The current generated by each synaptic transistor in the same column is fully converged on the corresponding column line to achieve accumulation. Then, the output current signal is read and input to the subsequent grouped differential topology structure for difference processing, thereby realizing multiply-accumulate MAC operation that supports positive and negative weights. In-memory computing can be achieved without additional multipliers and adders, which significantly improves computing efficiency and reduces power consumption. During the system training phase, the DAC, OPA, and MUX of the weight setting circuit sequentially apply a corresponding number of electrical pulses to the bottom gate of each synaptic transistor in the synaptic transistor array to adjust the conductance of the synaptic transistors and initialize the SNN weights. The signal collected by the tactile sensor is converted into a pulse voltage signal by the pulse coding unit and input to the synaptic transistor array for hardware MAC operation. The column line current sequentially passes through the TIA, RC circuit, subtractor, and ADC of the signal acquisition unit to read the accumulated current. The processing result is transmitted to the controller for analysis and calculation. The controller calculates the error and solves the weight update gradient based on the substitution gradient method. The positive and negative gradients correspond to the increase and decrease of the synaptic transistor conductance, respectively. The gradient value matches and controls the amplitude, frequency, and duration of the control pulse. The controller sends the weight update command after gradient conversion to the weight setting circuit to adjust the conductance of the synaptic transistors. By cyclically executing MAC operation, current acquisition, gradient solution, and weight iterative update, the training of the SNN is completed. During the system inference phase, only forward propagation is performed. The signal input from the pulse coding unit is fed into the synaptic transistor array. Since the synaptic transistors can store conductance, there is no need to write or update weights at this time. The current is read by the signal acquisition unit, and the controller calculates and outputs the tactile classification prediction result. In this embodiment, the pulse-coded transistor and the synaptic transistor array are integrated and fabricated on the same silicon wafer, with the source of the pulse-coded transistor connected to the drain of the synaptic transistor. By deeply integrating pulse coding with neural computing, the limitations of the traditional discrete architecture are broken, avoiding the long-distance transmission of massive amounts of data, and realizing the integrated processing of tactile sensing signals from acquisition to recognition, which significantly improves the system response speed and reduces power consumption.

[0031] See Figure 3 The schematic diagram of the LIF neuron circuit in this embodiment includes an input resistor R1, an integrating capacitor C1, a leakage resistor R2, a pulse code transistor T1, and an output resistor R3. The specific connection relationship is as follows: Input signal terminal TS in Connect to the first terminal of the first resistor R1.

[0032] The second terminal of the first resistor R1, the first terminal of the first capacitor C1, the first terminal of the second resistor R2, and the top gate of the pulse code transistor T1 are all connected to the first intermediate node.

[0033] The second terminal of the first capacitor C1, the second terminal of the second resistor R2, and the first terminal of the third resistor R3 are all connected to the reference ground GND.

[0034] The source of pulse-coded transistor T1, the second terminal of the third resistor R3, and the output signal terminal TS OUT They are all connected to the output node.

[0035] The drain of pulse-encoded transistor T1 is connected to the top gate; the bottom gate of pulse-encoded transistor T1 is connected to the control voltage terminal V. BG .

[0036] In this circuit, C1 acts as an integrating capacitor to store charge and simulate the neuron's membrane potential. R1 and C1 form an RC charging circuit to control the rate of membrane potential rise. R2 provides a discharge path to achieve passive leakage of the membrane potential. The top gate and drain of the pulse-coded transistor T1 serve as signal input terminals, and the conduction threshold and firing frequency are dynamically adjusted by the bottom gate of T1. After the pulse-coded transistor T1 is turned on, the source-drain channel of T1 and R3 provide a discharge path to achieve rapid leakage of the membrane potential.

[0037] The voltage signal output by the tactile sensor is input to C1, the integrating capacitor begins to charge, the membrane potential gradually rises, and when the potential of the top gate connected to C1 reaches the threshold, the transistor switches from off to on and generates a discharge current. Then it completes the reset and enters the refractory period, thereby simulating the leakage integral characteristics of biological neurons through biomimetic hardware architecture design. Pulse working principle: The tactile sensing signal is input to the integrating capacitor C1 via the input resistor R1. The external input charges C1, causing the top gate potential of the transistor connected to C1 to gradually rise. At this time, T1 is in the off state, simulating the accumulation process of membrane potential in biological neurons. A leakage resistor R2 is connected in parallel across the integrating capacitor C1. Under normal conditions, there is a weak leakage current flowing from C1 to the reference ground through R2, simulating the leakage integration characteristic of the inherent leakage current of the neuron membrane. When the top gate potential corresponding to C1 reaches the conduction threshold voltage of transistor T1, the transistor is in the conducting state. The charge stored in C1 flows to the reference ground through the source-drain channel of T1 and the current-limiting resistor R3, realizing the rapid release of capacitor charge and rapid drop of top gate potential, completing the forced reset of membrane potential. After the reset, the transistor returns to the off state. At this time, the input signal needs to recharge C1 through R1 to raise the top gate potential to the conduction threshold again. This charging interval simulates the refractory period of a neuron. The output voltage V of the control circuit is controlled by an external controller. BG When V BG When the potential shifts to the negative, the top gate needs to be charged to a higher voltage to trigger T1 to conduct. The longer charging time reduces the pulse firing frequency, which is suitable for high-intensity touch scenarios; when V BG When the potential shifts to the positive direction, the top gate can be charged to a lower voltage to trigger T1 to turn on. The shorter charging time increases the pulse firing frequency, and the higher sensitivity is suitable for light touch scenarios. The LIF neuron circuit simulates the leakage integral firing characteristics of biological neurons through the above charging and discharging and charge leakage timing.

[0038] See Figure 4The following is a simulation diagram of the LIF neuron circuit after encoding in the embodiment. When tactile sensing signals of different intensities and timings are input, the LIF neuron circuit based on pulse-coded transistors can continuously perform charge accumulation and leakage release processes according to the input signals to realize temporal pulse encoding of tactile information. The signal processed by the pulse encoding unit is a pulse sequence with regular waveforms, which can be used as an effective input to the subsequent synaptic transistor. The LIF neuron circuit completes the tactile feature representation based on the pulse timing. The pulse frequency and density represent the pressure magnitude and contact duration. The pulse frequency is positively correlated with the tactile pressure magnitude, and the pulse sequence duration is positively correlated with the contact duration. Furthermore, based on the pulse firing interval and timing distribution characteristics, it can distinguish tactile physical information such as object sliding, surface material, softness and hardness, and surface curvature, adapting to the event-driven operation logic of the spiking neural network.

[0039] Example 2 This embodiment provides a detailed description of the pulse-coded transistor based on Embodiment 1.

[0040] See Figure 5 The pulse-coded transistor provided in this embodiment is a two-dimensional dual-gate field-effect transistor, employing a top-gate-bottom-gate dual-gate coordinated control architecture. The conductive channel material is molybdenum disulfide (MoS2), a transition metal sulfide, transferred using a dry transfer process. The thickness of the few-layer MoS2 is controlled at 1.3–3 nm, exhibiting intrinsically high carrier mobility, high on / off ratio, low subthreshold swing, and low short-channel effect. A 15–20 nm thick hexagonal boron nitride (h-BN) buffer layer is placed between the substrate and the MoS2 channel. Utilizing the interface characteristics of the h-BN layer without dangling bonds, it can passivate the charge traps on the SiO2 surface, effectively suppressing interface Coulomb scattering and optimizing carrier transport efficiency. The top gate dielectric is high-dielectric-constant alumina (Al2O3), with a thickness of 8–10 nm obtained through atomic layer deposition (ALD). The dense dielectric layer of the nanometer-thick thin film can suppress gate tunneling leakage current and optimize the gate voltage's ability to regulate channel carriers. The device substrate uses p-doped silicon (Si) and silicon dioxide (SiO2), with Si serving as the bottom gate to connect to the external voltage control port and SiO2 serving as the dielectric layer. Gold (Au) and titanium (Ti) thin films are deposited by electron beam evaporation to form the source, drain, and top gate electrodes of the device.

[0041] The sensitivity of the device can be flexibly adjusted by controlling the threshold voltage and firing frequency of the output signal through adjusting the bottom gate voltage. The top gate and drain of the device receive the signal processed by the RC charging circuit. The dynamic potential of the top gate and the static potential of the bottom gate are coupled to each other and jointly determine the conduction and cutoff of the conductive channel. The tactile signal is pulse-coded by the LIF neuron circuit based on the pulse-coded transistor, and the source outputs a pulse signal corresponding to the intensity and timing of the tactile stimulus.

[0042] Example 3 This embodiment provides a detailed description of the synaptic transistor based on Embodiment 1.

[0043] See Figure 6 This invention relates to a synaptic transistor based on heterogeneous integration of two-dimensional and ferroelectric materials, possessing non-volatile multi-state conductance storage characteristics. The conductive channel material is WSe2, a two-dimensional material transferred using a dry transfer process, with a thickness controlled at 2–8 nm. This layer exhibits bipolar transport characteristics, a low contact barrier, and a low subthreshold swing. An h-BN isolation layer is placed between the WSe2 channel and the floating gate, forming a high tunneling barrier to block charge leakage between the floating gate and the channel, suppressing conductance drift and improving charge storage stability. The gate dielectric between the floating gate and the bottom gate is indium selenide (α-In2Se3), a ferroelectric material with a thickness controlled at 8–12 nm. This layer possesses ultra-thin ferroelectric stability, low coercivity voltage, and bidirectional polarization coupling characteristics, enabling stable and reversible ferroelectric polarization switching at a low coercivity voltage of approximately 0.9 V. Both the bottom gate and the floating gate are made of titanium nitride (TiN). The TiN bottom gate is sputtered onto a SiO2 surface and connected to an external voltage control port. TiN floating gates are sputtered onto the In2Se3 surface to capture and store charge; the device substrate is Si / SiO2; Au / Ti thin films are deposited by electron beam evaporation to form the source and drain of the device; by applying a pulse voltage to the bottom gate, the ferropolarization of α-In2Se3 is driven to reverse, and the polarization charge is stored by the TiN floating gate, thereby controlling the carrier concentration of the WSe2 channel, changing the conductance of the synaptic transistor, and the source outputs a corresponding pulse current signal; By applying positive or negative pulses with amplitudes exceeding the coercive voltage to the bottom gate, the degree of ferropolarization reversal is controlled, thereby regulating the channel carrier concentration and causing changes in the transistor's conductance. Increased conductance corresponds to long-term boost (LTP), while decreased conductance corresponds to long-term suppression (LTD). When there is no gate voltage, the ferropolarization remains stable, achieving non-volatile storage of conductance and multi-level conductance regulation. This process simulates the plastic behavior of biological synapses.

[0044] This invention is not limited to the embodiments described above. The above description of specific embodiments is intended to illustrate and explain the technical solutions of this invention. The specific embodiments described above are merely illustrative and not restrictive. Without departing from the spirit and scope of the claims, those skilled in the art can make many specific modifications based on the teachings of this invention, and these modifications all fall within the scope of protection of this invention.

Claims

1. A pulse neural network system based on two-dimensional material transistors, characterized in that, It is used for encoding, storing and computing tactile sensing signals for spiking neural networks, including a tactile sensor, a pulse coding unit, a synaptic transistor array, a signal acquisition unit, a controller and a voltage driving unit connected in sequence. The voltage driving unit is also connected to the pulse coding unit and the synaptic transistor array. The pulse coding unit includes a leaky integral discharge LIF neuron circuit and a pulse coding transistor with a dual-gate structure; The LIF neuron circuit based on the pulse-code transistor converts the tactile sensing signal into a standard pulse signal, and controls the threshold potential and firing frequency of the output pulse by adjusting the bottom gate voltage of the pulse-code transistor. The synaptic transistor array is constructed from non-volatile synaptic transistors and is used to receive the standard pulse signal and perform multiply-accumulate MAC dynamic calculations. The synaptic transistor array adopts a grouped differential topology to configure positive and negative weights.

2. The pulse neural network system based on two-dimensional material transistors according to claim 1, characterized in that, The LIF neuron circuit includes an input resistor R1, an integrating capacitor C1, a leakage resistor R2, a pulse-coded transistor T1, and an output resistor R3. The integrating capacitor C1 stores charge to simulate the neuron's membrane potential. The input resistor R1 and the integrating capacitor C1 form an RC charging circuit to control the rise rate of the neuron's membrane potential. The leakage resistor R2 provides a discharge path to achieve passive leakage of the neuron's membrane potential. The top gate and drain of the pulse-coded transistor T1 are connected to the integrating capacitor C1 as signal input terminals. The source is grounded through the output resistor R3, and a standard pulse signal is output between the source and the output resistor R3.

3. The pulse neural network system based on two-dimensional material transistors according to claim 1, characterized in that, The pulse-coded transistor is a two-dimensional transition metal sulfide material transistor with a top-gate and bottom-gate dual-layer gate structure; the channel material of the pulse-coded transistor is MoS2, the top-gate dielectric is Al2O3, and an h-BN layer is provided between the channel material and the substrate.

4. The pulse neural network system based on two-dimensional material transistors according to claim 1, characterized in that, The synaptic transistor has a bottom gate and a floating gate structure, using a two-dimensional material as the channel and a ferroelectric material as the gate dielectric; the channel material is WSe2, the ferroelectric material is α-In2Se3, the bottom gate and the floating gate are made of TiN, and an h-BN layer is provided between WSe2 and the floating gate; the polarization of α-In2Se3 is controlled by the bottom gate, and the conductance of WSe2 is controlled by the TiN floating gate, so as to achieve non-volatile storage of multi-state conductance.

5. The pulse neural network system based on two-dimensional material transistors according to claim 1, characterized in that, The grouped differential topology of the synaptic transistor array is characterized by the following: each row of the array includes several computing units, and each computing unit includes one reference transistor and two signal processing transistors; after the output current of the transistors in the same column is summarized, the current of the column where the signal processing transistor is located is differentially divided with the current of the column where the reference transistor is located, so as to realize the storage and calculation of positive and negative weights.

6. The pulse neural network system based on two-dimensional material transistors according to claim 1, characterized in that, The source of the pulse-coded transistor is connected to the drain of the synaptic transistor as an input signal, and the pulse-coded transistor and the synaptic transistor array are integrated and fabricated on the same substrate.

7. The pulse neural network system based on two-dimensional material transistors according to claim 1 or 2, characterized in that, The LIF neuron circuit is used to shape and integrate the tactile sensing signal, converting it into a standard pulse signal that meets the processing requirements of the synaptic transistor array. When the gate potential of the pulse coding transistor T1 reaches the threshold, T1 switches from off to on and generates a discharge current. Subsequently, it completes the reset and enters the refractory period, simulating the leakage integral discharge behavior of biological neurons.

8. The pulse neural network system based on two-dimensional material transistors according to claim 5, characterized in that, By adjusting the bottom gate voltage of the synaptic transistors, the conductance of each synaptic transistor in the synaptic transistor array is set sequentially, thereby achieving weight updates and calibration; the input signal for each row is the pulse signal TS output by the pulse-coded transistor. OUT The number of array rows is the same as the number of pulse coding units. The synaptic transistor array adopts row activation and column reading. The pulse voltage of the pulse coding unit is multiplied by the synaptic conductance of the corresponding synaptic transistor to generate current. The current in the same column is naturally accumulated. After passing through the grouped differential topology, MAC operation is realized.

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