A constraint feasibility and simulated annealing hybrid search method and system for neural network lookup table compression

Abstract

The application discloses a constraint feasibility and simulated annealing hybrid search method and system for neural network lookup table compression, and relates to the technical field of neural network hardware acceleration and lookup table compression. In order to solve the problem of large storage of a lookup table and large hardware resource consumption in deployment of a lookup table neural network, a model truth table and a calibration address track are obtained, an irrelevant item mask is generated, lookup table decomposition, constraint feasibility checking, dependent re-distribution and simulated annealing refinement are performed, a compression state is selected according to a packing bit cost, and a hardware description is generated, so that the method is mainly used for compressed deployment of a lookup table neural network.

Description

Technical Field

[0001] This invention relates to the fields of neural network hardware acceleration and look-up table (LUT) compression technology, and particularly to a LUT compression system, method, electronic device, and computer-readable storage medium for look-up table neural networks (LUT-NN). Background Technology

[0002] LUT-NN can map neurons or sub-functions in a quantized neural network to LUTs, enabling low-latency inference on reconfigurable hardware such as Field Programmable Gate Arrays (FPGAs) using a lookup table approach. For neuron-level functions with large input bit widths, the storage size of a direct LUT grows exponentially with the input bit width; when the network contains a large number of neuron-level LUTs, LUT storage and the resulting hardware resource overhead may become a deployment bottleneck.

[0003] Existing LUT compression methods can decompose the original LUT into structures such as a low-order table, a high-order sub-table, an offset table, a unique sub-table, an index table, and a right-shift table, and reduce the storage of the unique sub-table by utilizing the right-shift similarity between different sub-tables. Furthermore, existing techniques also utilize training or calibration of input trajectories to identify don't-care addresses, allowing modification of unobserved or low-frequency addresses while keeping the output of observed addresses unchanged, thereby creating more sub-table similarities.

[0004] However, existing don't-care aware LUT compression typically relies on greedy search. For the candidate "generator subtable, target subtable, and right shift" relationship, once the greedy search commits a locally feasible relationship, it may prematurely consume modifiable addresses and change the dependency graph structure, preventing the formation of subsequent better relationships. Especially when the target subtable to be collapsed is itself still used as a generator for other dependent subtables, if the reallocation of dependent subtables is not considered before committing, it is easy to produce an unreconstructable state or miss a better compression structure.

[0005] Furthermore, purely greedy search cannot accept intermediate moves that do not reduce bit costs in the short term but create conditions for subsequent root-collapse, such as separating a dependency sub-table from the current root sub-table and reassigning it to another generator sub-table. Therefore, an end-to-end LUT-NN compression scheme is needed that can uniformly manage constraints on don't-care reassignment, dependency graph reassignment, and non-greedy search while keeping the observed address behavior unchanged. Summary of the Invention

[0006] The technical problem to be solved by this invention is: under the condition that the LUT-NN has been trained and the neuron-level LUT has been determined, how to reduce the number of bits in the final compressed table and the hardware resource consumption by utilizing the don't-care degrees of freedom in the training or calibration input trajectory without changing the compressed table reconstruction structure based on the reduced LUT, while keeping the output of the observed addresses in the calibration trajectory unchanged, and forming an end-to-end closed loop from model, truth table, address trajectory, compressed hardware description to verification and evaluation.

[0007] To address the aforementioned technical problems, this invention provides a LUT compression system for LUT-NN. The system includes a model and truth table acquisition module, a calibration trajectory recording module, a tabular format conversion module, a don't-care mask generation module, a LUT decomposition module, a constraint feasibility search module, a dependency graph redistribution module, a simulated annealing refinement module, a compression state selection module, and a hardware description generation and verification evaluation module.

[0008] The model and truth table acquisition module acquires the trained LUT-NN model and generates the LUT truth table corresponding to each neuron or sub-function. The calibration trajectory recording module performs inference based on the training dataset or calibration dataset and records the actual input address trajectories of each neuron or sub-function. The table conversion module converts the LUT truth table into a table file readable by the compressor and records or transmits the input bit width and output bit width of the LUT.

[0009] The don't-care mask generation module generates a modifiable address mask based on the input address trajectory. Addresses not observed by the input address trajectory or with an observation frequency below a preset rarity threshold are marked as modifiable addresses, while observed addresses that do not meet the low-frequency condition are marked as non-modifiable addresses. The LUT decomposition module splits the LUT truth table into a low-order table and a high-order table, further dividing the high-order table into multiple sub-tables, and performs bias normalization on each sub-table to construct an initial similarity matrix and a right-shift matrix.

[0010] The constraint feasibility search module performs pre-submission constraint checks on candidate generator sub-tables, target sub-tables, and right shift relationships. For each position in the target sub-table, the required value after right shifting the corresponding position in the generator sub-table is calculated. If the position corresponds to an unmodifiable address, the original value in the target sub-table must be equal to the required value. If the position corresponds to a modifiable address, reassigning the original value in the target sub-table to the required value is allowed. If the required value exceeds the range that the high bits of the output can represent, the candidate relationship is rejected. Thus, candidate relationships are only introduced if they do not change the output of the observed address and the reassignment is valid.

[0011] When the target subtable to be collapsed still generates other dependent subtables, the dependency graph reassignment module collects the set of dependent subtables of that target subtable and searches for a new generator and right shift for each dependent subtable. During the search, applied don't-care reassignments are written to a temporary state and their corresponding positions are fixed, allowing subsequent reassignments to continue checking on the updated temporary state. If no feasible new generator exists for any dependent subtable, the entire composite move is rolled back.

[0012] The simulated annealing refinement module continues the search in the feasible compressed state space based on root-collapse and dependent-detachment. Root-collapse attempts to collapse the stored root subtable under another generator subtable to reduce the number of unique roots; dependent-detachment separates dependent subtables from the current root subtable and reassigns them to another generator subtable to change the dependency graph structure and create conditions for subsequent root-collapses. Each move undergoes constraint feasibility checks and similar edge verification before entering the annealing acceptance criterion.

[0013] The compression state selection module chooses the effective and lowest-cost compression state from the baseline compression state (without don't-care modifications), the constraint search compression state, and the best state in simulated annealing history based on the packet bit cost. When a search state containing don't-care modifications is invalid or its cost is not lower than the baseline compression state, the baseline compression state is selected to avoid compression result degradation. The hardware description generation and verification evaluation module generates a hardware description based on the selected compression state, performs inference verification, and outputs hardware resource evaluation results based on the synthesis results.

[0014] This invention also provides a LUT compression method for LUT-NN, comprising: acquiring a trained LUT-NN model and generating a LUT truth table; recording the calibration input address trajectory; generating a modifiable address mask; performing LUT decomposition and bias normalization; constructing a similarity matrix and a right-shift matrix; performing constraint feasibility checks on candidate generation relations; performing dependency reallocation on root-collapse with dependent sub-tables; performing simulated annealing refinement; selecting a compression state based on the packet bit cost; and generating a hardware description.

[0015] The present invention also provides an electronic device and a computer-readable storage medium, wherein the electronic device or the computer-readable storage medium is used to perform the above-described LUT compression method.

[0016] Compared with existing technologies, this invention has at least the following beneficial effects: First, this invention improves the search process without changing the compressed table reconstruction structure of ReducedLUT, thus it is compatible with existing hardware reconstruction interfaces such as low-order tables, bias tables, unique sub-tables, index tables, and right-shift tables; Second, this invention performs position-level constraint checks on candidate generation relations, ensuring that the output of unmodifiable addresses remains unchanged and that the reassignment of modifiable addresses satisfies the output bit width constraint, thereby reducing the risk of "don't-care" reassignment disrupting calibration behavior; Third, this invention treats root-collapse with dependent sub-tables as composite graph movement, where only root-collapse relations and The invention only commits the dependency sub-table reassignment plan when all options are feasible, thus avoiding the generation of non-reconstructable dependency graph states. Fourth, the invention utilizes simulated annealing to accept some non-improved intermediate moves in the feasible state space, which can reduce the sensitivity of greedy search to candidate order and discover better dependency graph structures. Fifth, the invention ensures that the final output state is valid and the bit cost of packing is not inferior to the baseline state through baseline backoff and historical best selection mechanisms. Sixth, the invention integrates model truth table generation, calibration trajectory recording, tabular conversion, neuron-by-neuron compression, compressed hardware description generation, inference verification, and comprehensive resource evaluation into an end-to-end closed loop, which facilitates the simultaneous evaluation of compression rate and accuracy risks in actual LUT-NN deployments. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of the overall structure of the LUT compression system for LUT-NN proposed in this invention.

[0018] Figure 2 This is a schematic diagram of the LUT compression method proposed in this invention. Detailed Implementation

[0019] The present invention will be further described below with reference to the accompanying drawings and steps. It should be understood that the following steps are used to explain the present invention, and not to limit the scope of protection of the present invention. Where there is no conflict, the technical features in the following steps can be combined with each other. Figure 1 Corresponding to the overall system structure, Figure 2 Corresponding method steps; Figure 2 The sequence from top to bottom illustrates the input acquisition, table decomposition and mask generation, candidate feasibility check, dependency reallocation, packaging cost evaluation, simulated annealing refinement, state selection, compressed hardware description generation, and verification process. Steps one through five below follow... Figure 2 The processes shown are carried out sequentially, with step six being an example of dataset verification.

[0020] Step 1: Overall System Structure.

[0021] like Figure 1As shown, this step provides a LUT compression system for LUT-NN. This system can run on general-purpose computers, servers, workstations, or development environments for FPGA design. System inputs include the trained LUT-NN model, the neuron-level LUT truth table, training or calibration set input data, compression parameters, and optional simulated annealing parameters. System outputs include the compressed neuron-level hardware description, full model compression bit statistics, inference verification results, and comprehensive hardware resource statistics.

[0022] In one configuration, the model and truth table acquisition module loads the trained neural network weights, converts the neural network into a LUT inference model, and generates a hardware description language (Verilog) LUT truth table for each neuron. The tabular conversion module parses the Verilog LUT, writes the output value corresponding to each address into a hexadecimal table file in address order, and writes the input and output bit widths into a metadata file. When the LUT is a constant table, the system can determine the actual output bit width through the metadata or the hardware description port width, avoiding the inference of an incorrect output bit width due to an excessively small maximum table value.

[0023] The calibration trajectory recording module performs one or more inferences on the training or calibration set. For each neuron, the module records the actual input addresses that occur. If the input address space can be directly mapped to integer addresses, the module can aggregate the addresses using a counting array; if the input address space needs to be concatenated from multiple input codes, the module generates binary addresses according to the input quantization bit width and fan-in order. The recording results can be written to an address log file distinguished by neuron name.

[0024] The don't-care mask generation module reads the address log and counts the frequency of each address. Let the rarity threshold be... If the frequency of occurrence of a certain address is lower than If the condition is met, the address is marked as a modifiable address; otherwise, it is marked as a non-modifiable address. In one step configuration, Therefore, unobserved addresses are marked as modifiable addresses, and all observed addresses are marked as immutable addresses.

[0025] The LUT decomposition module splits the original LUT into low-order tables. and high-level table Let the width of the lower-order split be... The unit is bit, where Represents the original LUT, Address The corresponding original output value, then , .

[0026] Furthermore, the LUT decomposition module determines the sub-table's internal address width based on... Divide the high-level table into There are several sub-tables, among which... This represents the original LUT input bit width. Each sub-table has a length of [length value missing]. For the first Extracting bias values ​​from each subtable And form a bias-normalized subtable. ,in, Indicates the position number within the sub-table. Indicates the first Each bias-normalized subtable is located at... The value of the table entry, then , .

[0027] Subsequently, the LUT decomposition module scans any two sub-tables and candidate right shifts to construct an initial similarity matrix and a right shift matrix. The edges in the similarity matrix... Represents the target sub-table Able to generate sub-tables Right shift amount generate.

[0028] Step 2: Constraint Feasibility Search.

[0029] This step explains the specific working method of the constraint feasibility search module, corresponding to... Figure 2 The candidate feasibility check phase in the process. Regarding candidate relationships... Position within the target sub-table The required value at the location is denoted as ,but .

[0030] If the output high-bit width is ,in Indicating the original LUT output bit width, the higher-order bits can represent the maximum value, denoted as: ,but .

[0031] Constraint Feasibility Search Module Traversal .like or If the position is not specified, then the candidate relationship is rejected. For addresses that cannot be modified, the following is required: If the location Corresponding to the modifiable address and Then record a don't-care reassignment, and In the experimental state, it is written as .

[0032] Using the above method, candidate relations and their reassignment results can only be written into the test state if all unmodifiable addresses retain their original output and all reassigned values ​​of modifiable addresses are within the bit width range. This design transforms don't-care reassignment into explicit constraint checks, avoiding the submission of unsafe candidate relations based solely on the overall similarity of sub-tables.

[0033] Step 3: Dependency graph reallocation.

[0034] This step explains the specific working method of the dependency graph reassignment module, corresponding to... Figure 2 The dependency determination, reallocation plan construction, and test state submission phases in the middle. If a certain root subtable Currently, several dependent sub-tables are generated, and the system intends to convert the root sub-table... Fold into another generator subtable Under these circumstances, the root child table cannot be deleted directly. Outgoing edges. The dependency graph reallocation module first collects the dependency set. ,in Representing the root table The currently generated set of dependency sub-tables .

[0035] Then, for sets Each dependency sub-table in Search for new generators and right shift amount , making candidate relationships Feasibility checks are performed by constraining the search. During the search, the reassignment of previously dependent subtables is applied to the temporary bias-normalized subtable, and the corresponding positions are fixed. Subsequent dependent subtables must continue to be checked in this temporary state.

[0036] If a viable new generator and right shift are found for all dependent subtables, the dependency graph reassignment module commits a composite move: clearing the root subtable. Establish related edges The new edges are established, and new redistribution edges are created for each dependent subtable. If no feasible redistribution exists for any dependent subtable, the entire composite move is rolled back, and the current table value, mask, similarity matrix, and right shift matrix remain unchanged.

[0037] Step 4: Candidate sorting, forward pruning, and simulated annealing.

[0038] In one step configuration, the system sets ranking scores for candidate relations, corresponding to... Figure 2The process involves stages such as packaging cost evaluation, simulated annealing move generation, move feasibility assessment, and state update. The ranking score can be related to the following factors: whether the candidate relation is an existing similar edge in the initial similarity matrix, the number of dependencies currently generated by the generator subtable, the number of "don't-care" entries required to write to the candidate relation, and whether the generator subtable is currently the only unique root. The system prioritizes candidate relations with higher scores to improve search efficiency.

[0039] For dependency reallocation issues that may occur repeatedly during the folding of the same root subtable, the system can cache the reallocation plan according to the index of the skipped dependent subtable. If the caching plan is not feasible, the system directly prunes the corresponding candidate relationship and does not construct a complete experimental state or perform a packaging cost evaluation.

[0040] The simulated annealing refinement module operates on feasible states obtained through greedy search or constraint search. These states include bias-normalized subtables, modifiable masks, similarity matrices, right-shift matrices, and packing costs. The simulated annealing refinement module generates two types of moves. The first is root-collapse, which collapses a stored root subtable under another generator subtable. The second is dependent-detachment, which detaches a dependent subtable from the current root subtable and reassigns it to another feasible generator subtable.

[0041] For any move, the system first performs constraint feasibility checks and similar edge verification. Only feasible moves are considered for acceptance under the annealing criterion. If the energy of the trial state is lower than the current state, the trial state is accepted; if the energy of the trial state is higher than the current state, the trial state is accepted with temperature-dependent probability. Throughout the search process, the system continuously records the state corresponding to the lowest historical packed bit cost and uses this historical best state as a candidate output.

[0042] In one step configuration, the energy function can be expressed as: ,in, Indicates compressed search status. For state The cost of packing bits, For state The number of valid edges in the dependency graph. For normalized temperature, Optional energy shaping weights. When At that time, the energy function is the cost of packing bits.

[0043] Step 5: State selection, hardware generation, and verification.

[0044] This step corresponds to Figure 2The compression state selection module compares at least two types of states: a baseline compressed state without don't-care modifications, and a search compressed state that includes don't-care modifications. When simulated annealing is enabled, the best state in the simulated annealing history is also compared. The system performs packaging for each type of state to obtain a unique sub-table, index table, right-shift table, and corresponding bit cost. If the search state is invalid, or the packaged bit cost of the search state is not lower than that of the baseline state, the baseline state is selected; otherwise, the search state or the best state in the simulated annealing history is selected.

[0045] The hardware description generation module generates a hardware description based on the selected state. In one step configuration, the hardware description includes a low-order table module, an offset table module, a unique sub-table module, an index table module, and a right-shift table module. During inference, a portion of the input address is used to address the index table and the right-shift table, and another portion is used to retrieve a value from the unique sub-table. The retrieved unique sub-table value is right-shifted, added to the offset value, and then concatenated or added to the low-order table output to obtain the final output.

[0046] The verification and evaluation module performs Verilog-level inference simulations on the compressed LUT-NN and compares the output accuracy with the uncompressed model or the LUT inference model. The module can also invoke the hardware synthesis process to statistically analyze hardware LUT resources, flip-flops (FFs), block random access memory (BRAM), timing margins, and estimated highest frequency. For different scarcity thresholds, rarity, number of candidates, number of temperature layers, and move budget configurations, the system can select the configuration that best balances bit cost or hardware resources under accuracy constraints. Specifically, exiguity controls the LUT compression candidate relationships or the compression search range; the number of candidates represents the number of candidate relationships participating in ranking, feasibility checks, or simulated annealing attempts; the number of temperature layers represents the number of discrete levels where the temperature changes from high to low during simulated annealing; and the move budget represents the upper limit of the number of search moves allowed.

[0047] Step 6: Dataset validation and parameter configuration (as an application example of Step 5).

[0048] In the LUT-NN validation step using a handwritten digit dataset (Modified National Institute of Standards and Technology database, MNIST), the system loads the trained model weights, converts the model into a LUT inference model, and generates a neuron-level Verilog LUT. The system performs log inference on the training or calibration set, recording the actual input addresses of each neuron. It then converts the neuron-level Verilog LUT into a hexadecimal table, saving the input and output bit width metadata. Subsequently, the system calls the compressor for each neuron, passing in the hexadecimal table, input address log, rarity, efficiency, table name, output path, and output bit width to generate a compressed Verilog module.

[0049] In one configuration, with an efficiency of 250, the original Reduced LUT of the MNIST benchmark has a final bit count of 2,797,816 bits. After using a hybrid search combining constraint feasibility and simulated annealing, the final bit count is 2,274,932 bits, a reduction of 18.69%; the Verilog-level accuracy decreases from 95.24% to 95.31%. Under the same efficiency, the two-layer configuration JSC-2L of the Jet Substructure Classification (JSC) benchmark network reduces the final bit count from 408,688 bits to 382,928 bits, a reduction of 6.30%; the five-layer configuration JSC-5L reduces the final bit count from 6,299,908 bits to 6,069,900 bits, a reduction of 3.65%. Here, 250 is an example value for exiguity, 18.69%, 6.30% and 3.65% are the relative reduction percentages relative to the original ReducedLUT bit count, and 95.24% and 95.31% are example values ​​for inference precision.

[0050] The above steps demonstrate that this invention, while maintaining the hardware reconfiguration interface of ReducedLUTs, further reduces the bit cost of LUT compression through constraint feasibility checks, dependency graph reallocation, and simulated annealing refinement. In practical deployments, compression parameters can be selected based on calibration coverage, Verilog-level accuracy, and overall hardware resources.

Claims

1. A hybrid search system combining constraint feasibility and simulated annealing for neural network lookup table compression, characterized in that, include: The model and truth table acquisition module is used to acquire the trained lookup table neural network model and generate the lookup table truth table corresponding to at least one neuron or sub-function in the lookup table neural network. The calibration trajectory recording module is used to perform inference of the lookup table neural network based on the training dataset or calibration dataset, and to record the actual input address trajectory of the at least one neuron or sub-function during the inference process; The table conversion module is used to convert the lookup table truth table into a table file that can be read by the compressor, and to record or transmit the input bit width and output bit width of the lookup table truth table. The irrelevant item mask generation module is used to generate a modifiable address mask based on the input address trajectory. Addresses that are not observed by the input address trajectory or whose observation frequency is lower than a preset rarity threshold are marked as modifiable addresses, and addresses that have been observed but do not meet the low frequency condition are marked as non-modifiable addresses. The lookup table decomposition module is used to split the truth table of the lookup table into a low-order table and a high-order table, divide the high-order table into multiple sub-tables, and perform bias normalization on each sub-table to obtain a bias normalized sub-table. The constraint feasibility search module is used to perform pre-submission constraint checks on candidate relations. The candidate relations include a candidate generator sub-table, a target sub-table, and a right shift amount. It constructs a test state for temporarily storing the candidate relations and the reassignment results of their irrelevant items. When the unmodifiable address of the target sub-table retains the original output value and the reassignment of the modifiable address satisfies the output bit width constraint, the candidate relations and the reassignment results of their irrelevant items are written into the test state. The dependency graph reallocation module is used to construct a new generator and right shift reallocation plan for the dependent subtable when the target subtable is used as a generator for other dependent subtables, and to submit a composite dependency graph update when all the reallocation plans are feasible. The simulated annealing refinement module is used to refine the dependency graph in the feasible compressible state space based on root folding moves and dependency separation moves. The compression state selection module is used to select the effective and lowest cost compression state from the baseline compression state, the constraint search compression state, and the best state in the simulated annealing history based on the packet bit cost. The hardware description generation and verification evaluation module is used to generate a hardware description compatible with the original lookup table interface based on the selected compression state, perform inference verification on the compressed lookup table neural network, and output hardware resource evaluation results based on the comprehensive results.

2. The constraint feasibility and simulated annealing hybrid search system for neural network lookup table compression according to claim 1, characterized in that, The model and truth table acquisition module is used to map neuron-level functions in the neural network into lookup tables, and output the output values, input bit widths, and output bit widths of the lookup tables arranged by address. The table conversion module is used to convert the branch items in the neuron-level hardware description language lookup table into a hexadecimal table file, and check the address coverage integrity, address repetition, and whether the output value exceeds the output bit width range. The output bit width is obtained through bit width metadata in the truth table generation process, or by parsing the output port bit width in the corresponding hardware description.

3. The constraint feasibility and simulated annealing hybrid search system for neural network lookup table compression according to claim 1, characterized in that, The calibration trajectory recording module is used to record the input address for each neuron or subfunction, and write the input address into the corresponding log file in binary form consistent with the input bit width of the lookup table of the neuron or subfunction; the calibration trajectory recording module is also used to count and aggregate the input addresses, and limit the frequency of the same input address to a range not exceeding a preset repetition limit, so as to form address frequency information for irrelevant item determination.

4. The constraint feasibility and simulated annealing hybrid search system for neural network lookup table compression according to claim 1, characterized in that, The lookup table decomposition module is used to enumerate the low-order split width and the internal address width of the sub-table, split the original lookup table output into a low-order table and a high-order table, and extract the bias value for each sub-table in the high-order table so that the table entry in the bias-normalized sub-table is the difference between the corresponding high-order table entry and the bias value of the sub-table; the lookup table decomposition module is also used to construct an initial similarity matrix and a right shift matrix, wherein an edge in the initial similarity matrix represents that a target sub-table can be generated by a generator sub-table by a corresponding right shift amount, and the right shift matrix records the right shift amount corresponding to the edge.

5. The constraint feasibility and simulated annealing hybrid search system for neural network lookup table compression according to claim 1, characterized in that, The constraint feasibility search module performs the following checks on the internal position of each sub-table in the candidate relation: if the required value of the generator sub-table after right shifting at that position is less than zero or greater than the maximum value that can be represented by the high-order output, then the candidate relation is determined to be infeasible; if the target sub-table corresponds to an unmodifiable address at that position, then the original value of the target sub-table is required to be equal to the required value. If the target sub-table corresponds to a modifiable address at this position and the original value of the target sub-table is different from the required value, then the irrelevant item at this position is reassigned, and the irrelevant item reassignment is applied in the test state.

6. The constraint feasibility and simulated annealing hybrid search system for neural network lookup table compression according to claim 1, characterized in that, The dependency graph reassignment module is used to collect the set of currently generated dependency sub-tables of the root sub-table when the root sub-table is to be collapsed to another generator sub-table; for each dependency sub-table in the set of dependency sub-tables, search for a new generator and right shift amount while excluding the root table as a new generator; and roll back the folding of the root table when no feasible new generator exists for any dependency sub-table.

7. The constraint feasibility and simulated annealing hybrid search system for neural network lookup table compression according to claim 1, characterized in that, The system also includes a candidate sorting and forward pruning module. This module sorts the candidate relations output by the constraint feasibility search module based on whether the candidate relation is an existing similar edge in the initial similarity matrix, the number of dependencies currently generated by the generator sub-table, the number of irrelevant items to be written for the candidate relation, and whether the generator sub-table is currently a unique root. It also caches dependency reallocation plans that occur repeatedly during the folding process of the same root sub-table. The simulated annealing refinement module generates root folding moves and dependency separation moves, performs feasibility checks and similar edge verifications on the generated moves, and accepts feasible experimental states where energy has not decreased based on temperature-related acceptance probabilities.

8. A hybrid search method combining constraint feasibility and simulated annealing for neural network lookup table compression, characterized in that, include: Obtain the trained lookup table neural network model and generate a truth table for at least one neuron or sub-function. Inference is performed based on a training dataset or a calibration dataset, and the actual input address trajectory of the at least one neuron or subfunction is recorded. A modifiable address mask is generated based on the input address trajectory; The lookup table truth table is split into a low-order table and a high-order table. The high-order table is further divided into multiple sub-tables, and bias normalization is performed on each sub-table. Construct the initial similarity matrix and the right shift matrix; Perform constraint feasibility checks on the candidate generator sub-table, target sub-table, and right shift relationship; When the target sub-table to be folded has dependent sub-tables, construct a new generator and right shift reallocation plan for the dependent sub-tables, and submit a composite dependency graph update when all of the reallocation plans are feasible. Perform simulated annealing refinement in the feasible compressible state space; Select the effective and lowest cost compression state based on the cost of packed bits; A hardware description compatible with the original lookup table interface is generated based on the selected compression state.

9. An electronic device, characterized in that, The electronic device includes a processor and a memory, the memory storing a computer program that, when executed by the processor, implements the method of claim 8.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, implements the method of claim 8.

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