A voltage generation circuit, a display device, and a driving method

Abstract

The present disclosure relates to the technical field of display, and discloses a voltage generation circuit, a display device and a driving method. The voltage generation circuit comprises a delay sub-circuit, a conduction control sub-circuit and a voltage generation sub-circuit. The delay sub-circuit provides an initial voltage input by an initial voltage terminal to the conduction control sub-circuit after delaying the initial voltage for a set time length. The conduction control sub-circuit generates a conduction control signal in response to the initial voltage. The voltage generation sub-circuit provides an input voltage input by a voltage input terminal to a voltage output terminal in response to the conduction control signal. In the process of power-on starting on the display panel, the delay of the set time length can ensure that the driving chip has a long enough time to perform initialization setting, and after the initialization setting is completed, the voltage signal for generating a scan signal is provided to a shift register unit, so that the timing of the gate line scanning is matched with the initialization setting, and the abnormal display of the display panel in the power-on starting process is avoided.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and provides a voltage generation circuit, a display device, and a driving method. Background Technology

[0002] In related technologies, during the power-on startup of a display panel, a period of time is required for the initialization settings of the display panel. However, during the power-on startup process, some voltages are usually provided directly to the display panel before the initialization settings are completed, such as the VGL voltage and VGH voltage. In this way, the VGL voltage and VGH voltage are provided to the shift register unit used to generate the scan signal in advance, causing the timing of the grid line scan to be mismatched with the initialization settings. As a result, abnormal display conditions such as black screen or distorted screen appear on the display panel during the power-on startup process. Summary of the Invention

[0003] This disclosure provides a voltage generation circuit, a display device, and a driving method, which use a set delay time to ensure that the driver chip has enough time to perform initialization settings, thereby avoiding abnormal display on the display panel during power-on startup.

[0004] The specific technical solution provided in this disclosure is as follows: In a first aspect, embodiments of this disclosure provide a voltage generation circuit, including: a delay sub-circuit, a conduction control sub-circuit, and a voltage generation sub-circuit; The delay sub-circuit is coupled to the initial voltage terminal and the turn-on control sub-circuit, and is configured to provide the initial voltage input to the initial voltage terminal to the turn-on control sub-circuit after a set time delay. The turn-on control subcircuit is coupled to the voltage generation subcircuit and is configured to generate a turn-on control signal in response to an initial voltage; The voltage generation sub-circuit is coupled between the voltage input terminal and the voltage output terminal and is configured to provide the input voltage of the voltage input terminal to the voltage output terminal in response to a conduction control signal.

[0005] In some possible implementations, the delay sub-circuit includes: a first resistor and a first capacitor; The first end of the first resistor is coupled to the initial voltage terminal, and the second end of the first resistor is coupled to the first end of the first capacitor. The second terminal of the first capacitor is coupled to the ground terminal.

[0006] In some possible implementations, the voltage input terminal includes a positive voltage input terminal and a negative voltage input terminal, the voltage output terminal includes a positive voltage output terminal and a negative voltage output terminal, and the voltage generation sub-circuit includes a positive voltage generation sub-circuit and a negative voltage generation sub-circuit. The forward voltage generation sub-circuit is coupled between the forward voltage input terminal and the forward voltage output terminal; The negative voltage generating sub-circuit is coupled between the negative voltage input terminal and the negative voltage output terminal.

[0007] In some possible implementations, the voltage generation subcircuit is a forward voltage generation subcircuit, and the conduction control subcircuit includes a forward conduction control subcircuit. The forward conduction control sub-circuit includes: a first transistor, a second resistor, and a third resistor; The control terminal of the first transistor is coupled to the second terminal of the first resistor, the first terminal of the first transistor is coupled to the second terminal of the second resistor, and the second terminal of the first transistor is coupled to the ground terminal. The first terminal of the second resistor is coupled to the positive voltage generation sub-circuit. The first end of the third resistor is coupled to the control terminal of the first transistor, and the second end of the third resistor is coupled to the ground terminal.

[0008] In some possible implementations, the voltage generation sub-circuit is a negative voltage generation sub-circuit, and the conduction control sub-circuit includes a negative conduction control sub-circuit. The negative conduction control sub-circuit includes: a second transistor, a fourth resistor, and a fifth resistor; The control terminal of the second transistor is coupled to the second terminal of the first capacitor, the first terminal of the second transistor is coupled to the second terminal of the fifth resistor, and the second terminal of the second transistor is coupled to the first terminal of the fourth resistor. The second end of the fourth resistor is coupled to the ground terminal, and the first end of the fifth resistor is coupled to the negative voltage generating sub-circuit.

[0009] In some possible implementations, the polarity of the second transistor is opposite to that of the first transistor.

[0010] In some possible implementations, the forward voltage generation sub-circuit includes: a third transistor, a sixth resistor, and a second capacitor; The control terminal of the third transistor is coupled to the first terminal of the second resistor, the first terminal of the third transistor is coupled to the positive voltage input terminal, and the second terminal of the third transistor is coupled to the positive voltage output terminal. The first end of the sixth resistor is coupled to the positive voltage input terminal, and the second end of the sixth resistor is coupled to the first end of the second resistor; The first terminal of the second capacitor is coupled to the positive voltage input terminal, and the second terminal of the second capacitor is coupled to the first terminal of the second resistor.

[0011] In some possible implementations, the negative voltage generating sub-circuit includes: a fourth transistor, a seventh resistor, and a third capacitor; The control terminal of the fourth transistor is coupled to the first terminal of the fifth resistor, the first terminal of the fourth transistor is coupled to the negative voltage input terminal, and the second terminal of the fourth transistor is coupled to the negative voltage output terminal. The first terminal of the seventh resistor is coupled to the negative voltage input terminal, and the second terminal of the seventh resistor is coupled to the first terminal of the fifth resistor. The first terminal of the third capacitor is coupled to the negative voltage input terminal, and the second terminal of the third capacitor is coupled to the first terminal of the fifth resistor.

[0012] In some possible implementations, the polarity of the fourth transistor is opposite to that of the third transistor.

[0013] In some possible implementations, a bleed sub-circuit is also included, which is coupled between the voltage output terminal and the ground terminal.

[0014] In some possible implementations, the voltage generation sub-circuit is a positive voltage generation sub-circuit, and the discharge sub-circuit includes: an eighth resistor; The first end of the eighth resistor is coupled to the positive voltage output terminal, and the second end of the eighth resistor is coupled to the ground terminal.

[0015] In some possible implementations, the voltage generation sub-circuit is a negative voltage generation sub-circuit, and the discharge sub-circuit includes: a ninth resistor; The first end of the ninth resistor is coupled to the negative voltage output terminal, and the second end of the ninth resistor is coupled to the ground terminal.

[0016] Secondly, this disclosure also provides a voltage generation circuit, including: a microcontroller and a voltage generation sub-circuit coupled together; The microcontroller is configured to delay the initial voltage input at the initial voltage terminal for a set time, and generate a conduction control signal based on the delayed initial voltage; The voltage generation sub-circuit is coupled between the voltage input terminal and the voltage output terminal and is configured to provide the input voltage of the voltage input terminal to the voltage output terminal in response to a conduction control signal.

[0017] Thirdly, embodiments of this disclosure also provide a display device, including: a voltage generation circuit and a driver chip as described in any of the above; The voltage generation circuit is located in the driver chip.

[0018] Fourthly, embodiments of this disclosure also provide a method for driving the voltage generation circuit of any of the above claims, comprising: The delay sub-circuit delays the initial voltage input at the initial voltage terminal for a set time before providing it to the conduction control sub-circuit; The turn-on control sub-circuit responds to the initial voltage and generates a turn-on control signal; The voltage generation sub-circuit responds to the turn-on control signal and provides the input voltage at the voltage input terminal to the voltage output terminal.

[0019] Fifthly, embodiments of this disclosure also provide a method for driving the voltage generation circuit of any of the above claims, comprising: The microcontroller delays the initial voltage input at the initial voltage terminal for a set time and generates a conduction control signal based on the delayed initial voltage. The voltage generation sub-circuit responds to the turn-on control signal and provides the input voltage at the voltage input terminal to the voltage output terminal.

[0020] The beneficial effects of this disclosure are as follows: In summary, this disclosure provides a voltage generation circuit, a display device, and a driving method. The voltage generation circuit includes a delay sub-circuit, a conduction control sub-circuit, and a voltage generation sub-circuit. The delay sub-circuit is coupled to an initial voltage terminal and the conduction control sub-circuit. The delay sub-circuit delays the initial voltage input to the initial voltage terminal for a set time before providing it to the conduction control sub-circuit. The conduction control sub-circuit is coupled to the voltage generation sub-circuit and generates a conduction control signal in response to the initial voltage. The voltage generation sub-circuit is coupled between a voltage input terminal and a voltage output terminal. In response to the conduction control signal, the voltage generation sub-circuit provides the input voltage from the voltage input terminal to the voltage output terminal. Thus, during the power-on startup of the display panel, the aforementioned set delay time ensures that the driver chip has sufficient time for initialization settings. After the initialization settings are completed, the voltage signal used to generate the scanning signal is provided to the shift register unit, thereby ensuring that the timing of the gate line scanning matches the initialization settings and avoiding abnormal display of the display panel during the power-on startup process.

[0021] Other features and advantages of this disclosure will be set forth in the following description and will be apparent in part from the description or may be learned by practicing the disclosure. The objects and other advantages of this disclosure may be realized and obtained by means of the structures particularly pointed out in the written description, claims, and drawings. Attached Figure Description

[0022] The accompanying drawings, which are included to provide a further understanding of this disclosure and form part of this disclosure, illustrate exemplary embodiments of the present disclosure and are used to explain the disclosure, but do not constitute an undue limitation of the disclosure. In the drawings: Figure 1 A schematic diagram illustrating the time required to initialize a driver chip in a related technology. Figure 2 This is a connection diagram of the first voltage generation circuit in the embodiments of this disclosure; Figure 3This is a connection diagram of the second voltage generation circuit in an embodiment of this disclosure; Figure 4 This is a connection diagram of the third voltage generation circuit in the embodiments of this disclosure; Figure 5 This is a connection diagram of the fourth voltage generation circuit in the embodiments of this disclosure; Figure 6 This is a circuit connection diagram of the first voltage generation circuit in the embodiments of this disclosure; Figure 7 This is a circuit connection diagram of the second voltage generation circuit in an embodiment of this disclosure; Figure 8 This is a circuit connection diagram of the third voltage generation circuit in the embodiments of this disclosure; Figure 9 This is a connection diagram of the fifth voltage generation circuit in the embodiments of this disclosure; Figure 10 This is a circuit connection diagram of the fourth voltage generation circuit in the embodiments of this disclosure; Figure 11 This is a connection diagram of the sixth voltage generation circuit in the embodiments of this disclosure; Figure 12 This is a connection diagram of a display device according to an embodiment of the present disclosure; Figure 13 This is a flowchart of a first driving method applied to a voltage generation circuit in an embodiment of this disclosure; Figure 14 This is a flowchart of a second driving method applied to a voltage generation circuit in an embodiment of this disclosure. Detailed Implementation

[0023] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the technical solutions of this disclosure, and not all embodiments. Based on the embodiments recorded in this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the technical solutions of this disclosure.

[0024] The terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of the invention described herein can be implemented in sequences other than those illustrated or described herein.

[0025] In related technologies, during the power-on startup process of a display panel, a period of time is required for initialization settings. For example, the display driver chip or the integrated display touch driver chip in an automotive display module needs to load pre-defined initialization code for initialization settings after power-on. (See [link to relevant documentation]). Figure 1 As shown, automotive display modules typically require varying amounts of time to load voltages such as VCC, LVDS, RESETB, STBYB, OTP / Flash, VSP, VSN, VGL, and VGH. Each of these voltage loading processes requires a certain amount of time. (See [link to relevant documentation]). Figure 1 As shown, the total time required to complete the loading of all the above voltages is at least 110ms. Only after all the above voltages have been loaded can the vehicle display module perform normal display.

[0026] However, during the power-on startup process, the aforementioned VGL and VGH voltages are usually provided directly to the display panel before the initialization settings are completed. As a result, the VGL and VGH voltages are provided to the shift register unit used to generate the scan signal in advance, causing the timing of the grid line scan to be mismatched with the initialization settings. This results in abnormal display conditions such as black screen or distorted screen on the display panel during the power-on startup process.

[0027] The preferred embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0028] See Figure 2 As shown in the embodiment of this application, a voltage generation circuit 00 includes: a delay sub-circuit 01, a conduction control sub-circuit 02, and a voltage generation sub-circuit 03.

[0029] The aforementioned delay sub-circuit 01 is coupled to the initial voltage terminal Vint and the turn-on control sub-circuit 02, and is configured to delay the initial voltage input to the initial voltage terminal Vint for a set time before providing it to the turn-on control sub-circuit 02.

[0030] First, in this embodiment, the initial voltage terminal Vint signal indicates that the display panel starts power-on under the action of an initial voltage. For example, the power-on signal PON or the STBYB signal can be used as the initial voltage. Typically, the moment when the display panel receives a valid initial voltage (for example, a power-on signal) from the aforementioned initial voltage terminal Vint is the moment when the display panel starts power-on.

[0031] During implementation, the delay sub-circuit 01 will only start delaying after receiving a valid initial voltage from the initial voltage terminal Vint, i.e., after confirming that the display panel has been powered on and started. It should be noted that the delay sub-circuit 01 can delay the initial voltage for a set duration through RC delay, 555 timer, or microcontroller software delay.

[0032] For example, in the embodiment of this application, after receiving the initial voltage input from the initial voltage terminal Vint, the delay sub-circuit 01 provides the initial voltage to the conduction control sub-circuit 02 after the initial voltage is delayed for a set time by the delay effect of RC delay.

[0033] It should be added that the above-mentioned setting time is calculated in advance based on the display panel model and the initialization setting process. That is, the initialization setting is the entire process from the moment the display panel is powered on until the display panel has loaded the aforementioned voltages and matching code settings. The time required for the initialization setting process is less than or equal to the setting time in the embodiment of this application. This ensures that the loading sequence of each voltage matches the initialization setting, thereby avoiding abnormal display during the power-on process of the display panel.

[0034] In order to ensure that voltage signals (e.g., VGL voltage and VGH voltage) are generated normally in the display panel, the embodiments of this application also include a conduction control sub-circuit 02 and a voltage generation sub-circuit 03.

[0035] The aforementioned conduction control sub-circuit 02 is coupled to the voltage generation sub-circuit 03 and is configured to generate a conduction control signal in response to an initial voltage.

[0036] During implementation, after the delay sub-circuit 01 delays the initial voltage for a set time and outputs it to the conduction control sub-circuit 02, the conduction control sub-circuit 02 can generate a conduction control signal under the action of the initial voltage. This conduction control signal is used to control when the voltage generation sub-circuit 03 generates and outputs the output voltage.

[0037] The voltage generation sub-circuit 03 described above is coupled between the voltage input terminal Vin and the voltage output terminal Vout, and is configured to provide the input voltage of the voltage input terminal Vin to the voltage output terminal Vout in response to the conduction control signal.

[0038] Although the voltage generation sub-circuit 03 in this embodiment is pre-connected to the voltage input terminal Vin and the voltage output terminal Vout, since the voltage generation sub-circuit 03 is in an open circuit state, the input voltage of the voltage input terminal Vin cannot be provided to the voltage output terminal Vout through the voltage generation sub-circuit 03. That is, the voltage generation sub-circuit 03 in an open circuit state cannot output the output voltage to the outside through the voltage output terminal Vout.

[0039] During implementation, when the voltage generation sub-circuit 03 receives the conduction control signal, it turns on, that is, the voltage generation sub-circuit 03 changes from the open circuit state to the on state. The input voltage of the voltage input terminal Vin is provided to the voltage output terminal Vout through the voltage generation sub-circuit 03. In this way, the voltage output terminal Vout outputs the output voltage, which is the voltage output by the display panel after power-on and after a set delay.

[0040] Considering that the voltage required in the display panel may be positive (e.g., +12V VGH voltage) or negative (e.g., -12V VGL voltage), in one embodiment, the voltage generation circuit 00 is a positive circuit for generating a positive output voltage; in another embodiment, the voltage generation circuit 00 is a negative circuit for generating a negative voltage.

[0041] Since the power-on startup process of the display panel is the same regardless of whether a positive or negative output voltage is generated, meaning the initialization time for the same display panel is fixed, the aforementioned setting time is also fixed. Therefore, the delay sub-circuit 01 in this embodiment can be shared in both the positive and negative circuits; that is, the delay sub-circuit 01 is not differentiated between positive and negative. However, in order to generate the aforementioned positive and negative circuits, both the conduction control sub-circuit 02 and the voltage generation sub-circuit 03 need to be differentiated into positive and negative circuits.

[0042] Based on this, the voltage generation sub-circuit 03 in the embodiments of this application includes two types: positive voltage generation sub-circuit 031 and negative voltage generation sub-circuit 032. Correspondingly, the voltage input terminal Vin includes a positive voltage input terminal Vin+ and a negative voltage input terminal Vin-, and the voltage output terminal Vout includes a positive voltage output terminal Vout+ and a negative voltage output terminal Vout-.

[0043] To generate a positive output voltage, the positive voltage generation sub-circuit 031 is coupled between the positive voltage input terminal Vin+ and the positive voltage output terminal Vout+. That is, when the voltage generation sub-circuit 03 is connected between the positive voltage input terminal Vin+ and the positive voltage output terminal Vout+, this voltage generation sub-circuit 03 is the positive voltage generation sub-circuit 031.

[0044] To generate a negative voltage, the negative voltage generation sub-circuit 032 is coupled between the negative voltage input terminal Vin- and the negative voltage output terminal Vout-. That is, when the voltage generation sub-circuit 03 is connected between the negative voltage input terminal Vin- and the negative voltage output terminal Vout-, this voltage generation sub-circuit 03 is the negative voltage generation sub-circuit 032.

[0045] Given that the voltage generation sub-circuit 03 and the conduction control sub-circuit 02 are matched, when the voltage generation sub-circuit 03 is a positive voltage generation sub-circuit 031, the conduction control sub-circuit 02 is a positive conduction control sub-circuit 021. Correspondingly, when the voltage generation sub-circuit 03 is a negative voltage generation sub-circuit 032, the conduction control sub-circuit 02 is a negative conduction control sub-circuit 022.

[0046] For example, the connection relationship of the voltage generation circuit 00 that generates a positive output voltage is shown in the figure. Figure 3 As shown, the voltage generation circuit 00 includes a delay sub-circuit 01, a forward conduction control sub-circuit 021 connected to the delay sub-circuit 01, and a forward voltage generation sub-circuit 031 connected to the forward conduction control sub-circuit 021. The forward voltage generation sub-circuit 031 is connected to the forward voltage input terminal Vin+ and the forward voltage output terminal Vout+, respectively.

[0047] For example, the connection relationship of the voltage generation circuit 00 that generates a negative output voltage is shown in the figure. Figure 4 As shown, the voltage generation circuit 00 includes a delay sub-circuit 01, a negative conduction control sub-circuit 022 connected to the delay sub-circuit 01, and a negative voltage generation sub-circuit 032 connected to the negative conduction control sub-circuit 022. The negative voltage generation sub-circuit 032 is connected to the negative voltage input terminal Vin- and the negative voltage output terminal Vout-, respectively.

[0048] Considering that the delay sub-circuit 01 can be shared in the voltage generation circuit 00 that generates both positive and negative output voltages, the voltage generation circuit 00 in this application can also simultaneously include a positive voltage generation circuit 00 and a negative voltage generation circuit 00. (See reference...) Figure 5As shown, the voltage generation circuit 00 includes a delay sub-circuit 01, a forward conduction control sub-circuit 021 connected to the delay sub-circuit 01, a negative conduction control sub-circuit 022 connected to the delay sub-circuit 01, a positive voltage generation sub-circuit 031 connected to the forward conduction control sub-circuit 021, and a negative voltage generation sub-circuit 032 connected to the negative conduction control sub-circuit 022. The positive voltage generation sub-circuit 031 is connected to the positive voltage input terminal Vin+ and the positive voltage output terminal Vout+, respectively. The negative voltage generation sub-circuit 032 is connected to the negative voltage input terminal Vin- and the negative voltage output terminal Vout-, respectively.

[0049] The circuit structure of the delay sub-circuit 01, the conduction control sub-circuit 02, and the voltage generation sub-circuit 03 will be described in detail below with reference to the circuit diagram.

[0050] See Figure 6 As shown, the above-mentioned delay sub-circuit 01 includes: a first resistor R1 and a first capacitor C1.

[0051] The first end of the first resistor R1 is coupled to the initial voltage terminal Vint, the second end of the first resistor R1 is coupled to the first end of the first capacitor C1, and the second end of the first capacitor C1 is coupled to the ground terminal.

[0052] During implementation, the initial voltage terminal Vint first provides the initial voltage to the first resistor R1, which in turn charges the first capacitor C1.

[0053] In this embodiment, the first resistor R1 and the first capacitor C1 constitute an RC delay circuit. When the initial voltage Vint is input, the first capacitor C1 will be charged through the first resistor R1 under the action of the initial voltage. The voltage of the first capacitor C1 will gradually rise and discharge after reaching the threshold voltage of the first capacitor C1. The above charging and discharging process constitutes the delay process. After the charging and discharging time reaches the set time, the initial voltage will be further provided to the forward conduction control sub-circuit 021.

[0054] Similarly, see Figure 7 As shown, the above-mentioned delay sub-circuit 01 includes: a first resistor R1' and a first capacitor C1'.

[0055] The first end of the first resistor R1' is coupled to the initial voltage terminal Vint, the second end of the first resistor R1' is coupled to the first end of the first capacitor C1', and the second end of the first capacitor C1' is coupled to the ground terminal.

[0056] During implementation, the initial voltage terminal Vint first provides the initial voltage to the first resistor R1'. Under the action of the initial voltage, the first capacitor C1' is charged through the first resistor R1'. The voltage of the first capacitor C1' gradually increases, and it is discharged after reaching the threshold voltage of the first capacitor C1'. The above charging and discharging process constitutes the delay process. After the charging and discharging time reaches the set time, the initial voltage is further provided to the negative conduction control sub-circuit 022.

[0057] To ensure that the above RC delay circuit can achieve the set delay time, the following formula can be used during implementation: Vt=V0+(V1-V0) (1-e) -t / RC The resistance value of the first resistor R1' and the capacitance value of the first capacitor C1' are selected. For example, when t is 110 milliseconds, Vt is 3.3V, V0 is 0V, and V1 is also 3.3V in the above formula, the resistance value of the first resistor R1' can be selected as 4.7KΩ, and the capacitance value of the first capacitor C1' can be selected as 10uF.

[0058] See Figure 6 and Figure 8 As shown, the forward conduction control sub-circuit 021 in this embodiment includes: a first transistor Q1, a second resistor R2, and a third resistor R3.

[0059] The control terminal of the first transistor Q1 is coupled to the second terminal of the first resistor R1, the first terminal of the first transistor Q1 is coupled to the second terminal of the second resistor R2, and the second terminal of the first transistor Q1 is coupled to the ground terminal.

[0060] For example, the first transistor Q1 can be turned on under the control of an active level at the second terminal of the first resistor R1, and can be turned off under the control of an inactive level at the second terminal of the first resistor R1. For example, if the first transistor Q1 is configured as an N-type transistor, then the active level of the signal at the second terminal of the first resistor R1 is a high level, and the inactive level of the signal at the second terminal of the first resistor R1 is a low level. Alternatively, if the first transistor Q1 is configured as a P-type transistor, then the active level of the signal at the second terminal of the first resistor R1 is a low level, and the inactive level of the signal at the second terminal of the first resistor R1 is a high level.

[0061] See Figure 6 As shown, the first transistor Q1 is an N-type transistor. When the signal at the second terminal of the first resistor R1 is high, the first transistor Q1 is turned on, and the second terminal of the second resistor R2 is connected to the ground terminal through the turned-on first transistor Q1.

[0062] The first end of the second resistor R2 is coupled to the positive voltage generation sub-circuit 031. The first end of the third resistor R3 is coupled to the control terminal of the first transistor Q1, and the second end of the third resistor R3 is coupled to the ground terminal.

[0063] The second resistor R2 is set to ensure the normal operation of the first transistor Q1. The third resistor R3 serves as the discharge resistor for the first transistor Q1, which can prevent the residual charge after the initial voltage terminal Vint is disconnected from increasing the leakage current of the circuit, thereby improving the performance of the circuit.

[0064] In order to be compatible with the delay sub-circuit 01 and the voltage generation sub-circuit 03, the resistance of the second resistor R2 is 22KΩ and the resistance of the third resistor R3 is 22KΩ.

[0065] See Figure 7 and Figure 8 As shown, when the voltage generation sub-circuit 03 is a negative voltage generation sub-circuit 032, the conduction control sub-circuit 02 is also a negative conduction control sub-circuit 022. The aforementioned negative conduction control sub-circuit 022 includes: a second transistor Q2, a fourth resistor R4, and a fifth resistor R5.

[0066] The control terminal of the second transistor Q2 is coupled to the second terminal of the first capacitor C1, the first terminal of the second transistor Q2 is coupled to the second terminal of the fifth resistor R5, and the second terminal of the second transistor Q2 is coupled to the first terminal of the fourth resistor R4.

[0067] For example, the second transistor Q2 can be turned on under the control of an effective level at the second terminal of the first capacitor C1, and can be turned off under the control of an ineffective level at the second terminal of the first capacitor C1. For example, if the second transistor Q2 is configured as an N-type transistor, then the effective level of the signal at the second terminal of the first capacitor C1 is a high level, and the ineffective level of the signal at the second terminal of the first capacitor C1 is a low level. Alternatively, if the second transistor Q2 is configured as a P-type transistor, then the effective level of the signal at the second terminal of the first capacitor C1 is a low level, and the ineffective level of the signal at the second terminal of the first capacitor C1 is a high level.

[0068] See Figure 7 As shown, the second transistor Q2 is a P-type transistor. When the signal at the second terminal of the first capacitor C1 is low, the second transistor Q2 is turned on, and the second terminal of the fifth resistor R5 is connected to the first terminal of the fourth resistor R4 through the turned-on second transistor Q2.

[0069] The second end of the fourth resistor R4 is coupled to the ground terminal, and the first end of the fifth resistor R5 is coupled to the negative voltage generation sub-circuit 032.

[0070] In order to be compatible with the delay sub-circuit 01 and the voltage generation sub-circuit 03, the resistance of the fourth resistor R4 is 22KΩ and the resistance of the fifth resistor R5 is 22KΩ.

[0071] See Figure 6 and Figure 7 As shown, the polarity of the second transistor Q2 is opposite to that of the first transistor Q1. For example, Figure 6 The first transistor Q1 in the image is an NPN transistor. Figure 7 The second transistor Q2 in the transistor is a PNP transistor.

[0072] See Figure 6 As shown, the forward voltage generation sub-circuit 031 includes: a third transistor Q3, a sixth resistor R6, and a second capacitor C2.

[0073] The control terminal of the third transistor Q3 is coupled to the first terminal of the second resistor R2. The first terminal of the third transistor Q3 is coupled to the positive voltage input terminal Vin+. The second terminal of the third transistor Q3 is coupled to the positive voltage output terminal Vout+.

[0074] For example, the third transistor Q3 can be turned on under the control of the effective level of the first terminal of the second resistor R2, and can be turned off under the control of the ineffective level of the first terminal of the second resistor R2. For example, if the third transistor Q3 is set as an N-type transistor, then the effective level of the signal at the first terminal of the second resistor R2 is a high level, and the ineffective level of the signal at the first terminal of the second resistor R2 is a low level. Alternatively, if the third transistor Q3 is set as a P-type transistor, then the effective level of the signal at the first terminal of the second resistor R2 is a low level, and the ineffective level of the signal at the first terminal of the second resistor R2 is a high level.

[0075] See Figure 6 As shown, the third transistor Q3 is an N-type transistor. When the signal at the first end of the second resistor R2 is high, the third transistor Q3 is turned on. The input voltage of the positive voltage input terminal Vin+ is provided to the positive voltage output terminal Vout+ through the turned-on third transistor Q3, that is, the positive voltage is output from the positive voltage output terminal Vout+.

[0076] The first terminal of the sixth resistor R6 is coupled to the positive voltage input terminal Vin+, and the second terminal of the sixth resistor R6 is coupled to the first terminal of the second resistor R2. The first terminal of the second capacitor C2 is coupled to the positive voltage input terminal Vin+, and the second terminal of the second capacitor C2 is coupled to the first terminal of the second resistor R2.

[0077] The sixth resistor R6 and the second capacitor C2 in this embodiment can effectively control the conduction and turn-off of the third transistor Q3. The resistance value of the sixth resistor R6 can be 22KΩ, and the capacitance value of the second capacitor C2 can be 100nF.

[0078] See Figure 7 As shown, the negative voltage generation sub-circuit 032 includes: a fourth transistor Q4, a seventh resistor R7, and a third capacitor C3.

[0079] The control terminal of the fourth transistor Q4 is coupled to the first terminal of the fifth resistor R5. The first terminal of the fourth transistor Q4 is coupled to the negative voltage input terminal Vin-, and the second terminal of the fourth transistor Q4 is coupled to the negative voltage output terminal Vout-.

[0080] For example, the fourth transistor Q4 can be turned on under the control of an active level at the first terminal of the fifth resistor R5, and can be turned off under the control of an inactive level at the first terminal of the fifth resistor R5. For example, if the fourth transistor Q4 is configured as an N-type transistor, then the active level of the signal at the first terminal of the fifth resistor R5 is a high level, and the inactive level of the signal at the first terminal of the fifth resistor R5 is a low level. Alternatively, if the fourth transistor Q4 is configured as a P-type transistor, then the active level of the signal at the first terminal of the fifth resistor R5 is a low level, and the inactive level of the signal at the first terminal of the fifth resistor R5 is a high level.

[0081] See Figure 7 As shown, the fourth transistor Q4 is a P-type transistor. When the signal at the first terminal of the fifth resistor R5 is low, the fourth transistor Q4 is turned on. The input voltage of the negative voltage input terminal Vin- is provided to the negative voltage output terminal Vout- through the turned-on fourth transistor Q4, that is, the negative voltage output terminal Vout- outputs a negative voltage.

[0082] The first terminal of the seventh resistor R7 is coupled to the negative voltage input terminal Vin-, and the second terminal of the seventh resistor R7 is coupled to the first terminal of the fifth resistor R5. The first terminal of the third capacitor C3 is coupled to the negative voltage input terminal Vin-, and the second terminal of the third capacitor C3 is coupled to the first terminal of the fifth resistor R5.

[0083] The seventh resistor R7 and the third capacitor C3 in this embodiment can effectively control the conduction and turn-off of the fourth transistor Q4. The resistance value of the seventh resistor R7 can be 22KΩ, and the capacitance value of the third capacitor C3 can be 100nF.

[0084] See Figure 6 , Figure 7 and Figure 8 As shown, the polarity of the fourth transistor Q4 is opposite to that of the third transistor Q3.

[0085] For example, Figure 6 The third transistor Q3 in the image is an NPN transistor. Figure 7 The fourth transistor Q4 in the diagram is a PNP transistor. It should be noted that the third transistor Q3 and the fourth transistor Q4 can also be metal-oxide-semiconductor field-effect transistors (MOSFETs), commonly referred to as MOS transistors.

[0086] In summary, when the voltage generation circuit 00 outputs a positive output voltage (e.g., VGH), refer to... Figure 6 As shown, the circuit specifically includes a delay sub-circuit 01 composed of a first resistor R1 and a first capacitor C1, a forward conduction control sub-circuit 021 composed of a second resistor R2, a third resistor R3 and a first transistor Q1, and a forward voltage generation sub-circuit 031 composed of a sixth resistor R6, a second capacitor C2 and a third transistor Q3. During implementation, when the initial voltage Vint is received, the first capacitor C1 is first charged through the first resistor R1. The voltage of the first capacitor C1 gradually increases, and it discharges after reaching its threshold voltage. This charging and discharging process constitutes a delay. After the charging and discharging time reaches the set duration, the initial voltage, delayed by the set duration, is provided to the control terminal of the first transistor Q1. Assuming the initial voltage is 3.3V, the resistance of the first resistor R1 is 4.7KΩ, and the resistance of the third resistor R3 is 22KΩ, the voltage at the control terminal of the first transistor Q1 is the voltage value of the third resistor R3 in the circuit formed by the first resistor R1, the third resistor R3, and the ground terminal; that is, the voltage at the control terminal of the first transistor Q1 is 3.3V. (22K / (22K + 4.7K)) equals 2.72V. In this case, the first transistor Q1 is turned on. Assuming the input voltage Vin+ is +12V, the resistance of the sixth resistor R6 is 22KΩ, and the resistance of the second resistor R2 is 22KΩ, then the voltage at the control terminal of the third transistor Q3 is (+12V). (22K / (22K+22K)), which is 6V. In this case, the third transistor Q3 is turned on, and the input voltage of Vin+ is provided to Vout+ through the third transistor Q3. For example, the voltage of Vout+ is +11.8V.

[0087] Similarly, when the voltage generation circuit 00 outputs a negative output voltage (exemplarily, VGL), see [reference needed]. Figure 7As shown, the circuit specifically includes a delay sub-circuit 01 composed of a first resistor R1' and a first capacitor C1', a negative conduction control sub-circuit 022 composed of a fourth resistor R4, a fifth resistor R5, and a second transistor Q2, and a negative voltage generation sub-circuit 032 composed of a seventh resistor R7, a third capacitor C3, and a fourth transistor Q4. During implementation, when the initial voltage Vint is received, the first capacitor C1' is first charged through the first resistor R1'. The voltage of the first capacitor C1' gradually increases, and it discharges after reaching its threshold voltage. This charging and discharging process constitutes a delay. After the charging and discharging time reaches the set duration, the initial voltage, delayed by the set duration, is provided to the second terminal of the second transistor Q2. Assuming the initial voltage is 3.3V, the resistance of the first resistor R1' is 4.7KΩ, the resistance of the fourth resistor R4 is 22KΩ, and the resistance of the fifth resistor R5 is 22KΩ, the voltage at the second terminal of the second transistor Q2 is the voltage value of the fourth resistor R4 in the circuit formed by the first resistor R1', the fourth resistor R4, and the ground terminal; that is, the voltage at the second terminal of the second transistor Q2 is 3.3V. (22K / (22K + 4.7K)) equals 2.72V. In this case, the control terminal of the second transistor Q2 is connected to ground, resulting in 0V. The Vgs of the second transistor Q2 is less than 0, and the second transistor Q2 is turned on. Assuming the input voltage Vin- is -11V, the resistance of the seventh resistor R7 is 22KΩ, the resistance of the fifth resistor R5 is 22KΩ, and the resistance of the fourth resistor R4 is 22KΩ, then the voltage at the control terminal of the fourth transistor Q4 is (-11V + 2.72V). (22K / (22K+22K)), which is 4.14V. In this case, the fourth transistor Q4 is turned on, and the input voltage of Vin- is provided to Vout- through the fourth transistor Q4. For example, the voltage of Vout- is -10.8V.

[0088] See Figure 9 As shown, the voltage generation circuit 00 also includes a discharge sub-circuit 04, which is coupled between the voltage output terminal Vout and the ground terminal.

[0089] To prevent the display panel from failing to clear the charge remaining inside during an abnormal shutdown, which could cause abnormal display during the power-on process, this embodiment of the application also includes a discharge sub-circuit 04. This discharge sub-circuit 04 can introduce the charge remaining at the voltage output terminal Vout to the ground terminal, thereby completely clearing any charge that may remain inside the display panel.

[0090] See Figure 10As shown, when the voltage generation sub-circuit 03 is a positive voltage generation sub-circuit 031, the above-mentioned discharge sub-circuit 04 includes: the eighth resistor R8.

[0091] The first end of the eighth resistor R8 is coupled to the positive voltage output terminal Vout+, and the second end of the eighth resistor R8 is coupled to the ground terminal.

[0092] During implementation, if the display panel experiences an abnormal shutdown while the positive voltage generation sub-circuit 031 generates the positive output voltage, excess charge may remain in the positive voltage output terminal Vout+. To prevent more serious abnormal displays from occurring during the power-on restart process of the display panel, an eighth resistor R8 is connected to the positive voltage output terminal Vout+ in this embodiment. The eighth resistor R8 introduces the charge in the positive voltage output terminal Vout+ into the ground terminal, thereby improving the display effect of the display panel during power-on restart.

[0093] For example, the resistance of the eighth resistor R8 is 1KΩ.

[0094] Similarly, see Figure 10 As shown, when the voltage generation sub-circuit 03 is the negative voltage generation sub-circuit 032, the discharge sub-circuit 04 includes: the ninth resistor R9.

[0095] The first terminal of the ninth resistor R9 is coupled to the negative voltage output terminal Vout-, and the second terminal of the ninth resistor R9 is coupled to the ground terminal.

[0096] During implementation, if the display panel shuts down abnormally during the generation of the negative output voltage by the negative voltage generation sub-circuit 032, excess charge may remain in the negative voltage output terminal Vout-. In order to prevent more serious abnormal display during the power-on restart of the display panel, a ninth resistor R9 is connected to the negative voltage output terminal Vout- in this embodiment. The ninth resistor R9 introduces the charge in the negative voltage output terminal Vout- to the ground terminal, thereby improving the display effect of the display panel when it is powered on again.

[0097] For example, the resistance of the ninth resistor R9 is 1KΩ.

[0098] Furthermore, to better control the delay sub-circuit 01 and the discharge sub-circuit 04, the voltage generation circuit 00 in this embodiment also includes switches K1, K2, and K3. In some embodiments, switches can also be set at other nodes of the voltage generation circuit 00 to put the corresponding electronic components into a conducting or turning-off state.

[0099] For example, see Figure 10As shown, switch K1 is positioned between the initial voltage terminal Vint and the first resistor R1. When switch K1 is off, the delay sub-circuit 01 is forcibly stopped from operating. When switch K1 is on, the delay sub-circuit 01 can perform the set delay period normally. Switch K2 is positioned between the initial voltage terminal Vint and the first resistor R1. When switch K2 is off, the delay sub-circuit 01 is forcibly stopped from operating. When switch K2 is on, the delay sub-circuit 01 can perform the set delay period normally. Switch K3 is positioned between the positive voltage output terminal Vout+ and the eighth resistor R8. When switch K3 is off, the connection between the positive voltage output terminal Vout+ and the eighth resistor R8 is broken.

[0100] Based on the same inventive concept, this disclosure provides a voltage generation circuit 00, see reference. Figure 11 As shown, it includes: a microcontroller 10 coupled to the circuit and a voltage generation sub-circuit 03.

[0101] The microcontroller 10 is configured to delay the initial voltage input at the initial voltage terminal Vint for a set time, and generate a conduction control signal based on the delayed initial voltage.

[0102] Unlike the hardware delay method consisting of the delay sub-circuit 01, the conduction control sub-circuit 02, and the voltage generation sub-circuit 03, in practice, a delay of a set duration and a conduction control signal can also be generated by software delay using a microcontroller 10.

[0103] The specific software delay method in the microcontroller 10 can be flexibly set according to the display panel model and the initialization process. For example, the set duration can be achieved through delay functions such as delay. Furthermore, in order to match the operation of the display panel, the pins of the microcontroller 10 also need to be connected to the initial voltage terminal Vint and the port corresponding to the conduction control signal to facilitate signal transmission.

[0104] During implementation, after receiving the initial voltage from the initial voltage terminal Vint via a pin, i.e., upon responding to the power-on startup of the display panel, the microcontroller 10 initiates an internal software delay to set the initial voltage delay duration. Then, the microcontroller 10 generates a conduction control signal based on this initial voltage. It should be noted that the voltage magnitude of this conduction control signal is equal to that generated by the conduction control sub-circuit 02, meaning the two conduction control signals have the same function.

[0105] During implementation, after generating the conduction control signal, the microcontroller 10 will further provide the conduction control signal to the voltage generation sub-circuit 03 through its pins.

[0106] The voltage generation sub-circuit 03 described above is coupled between the voltage input terminal Vin and the voltage output terminal Vout, and is configured to provide the input voltage of the voltage input terminal Vin to the voltage output terminal Vout in response to the conduction control signal.

[0107] It should be noted that the voltage generation sub-circuit 03 connected to the microcontroller 10 and the voltage generation sub-circuit 03 connected to the conduction control sub-circuit 02 mentioned above are the same circuit. The only difference is that the voltage generation sub-circuit 03 connected to the microcontroller 10 receives the conduction control signal from the pins of the microcontroller 10, while the voltage generation sub-circuit 03 connected to the conduction control sub-circuit 02 receives the conduction control signal directly from the conduction control sub-circuit 02. Although the main body and generation method of the two conduction control signals are different, the function of the two conduction control signals is the same.

[0108] During implementation, after receiving the conduction control signal, the voltage generation sub-circuit 03 indicates that the display panel has undergone the power-on start-up process of the set duration and the display panel has completed the initialization settings. In this case, the timing of the output voltage output by the voltage generation sub-circuit 03 through the voltage output terminal Vout can match the working process of the display panel.

[0109] For example, when the voltage generation sub-circuit 03 is a positive voltage generation sub-circuit 031, since the positive voltage generation sub-circuit 031 is connected to the positive voltage input terminal Vin+ and the positive voltage output terminal Vout+ respectively, during the implementation, the voltage input by the positive voltage input terminal Vin+ (for example, a +12V input voltage signal) is converted into an output voltage (for example, a +11.8V VGH signal) after passing through the positive voltage generation sub-circuit 031, and the output voltage is output through the positive voltage output terminal Vout+.

[0110] For example, when the voltage generation sub-circuit 03 is a negative voltage generation sub-circuit 032, since the negative voltage generation sub-circuit 032 is connected to the negative voltage input terminal Vin- and the negative voltage output terminal Vout- respectively, during the implementation, the voltage input by the negative voltage input terminal Vin- (for example, an input voltage signal of -11V) is converted into an output voltage (for example, a VGL signal of -10.8V) after passing through the negative voltage generation sub-circuit 032, and the output voltage is output through the negative voltage output terminal Vout-.

[0111] Based on the same inventive concept, this disclosure provides a display device, see reference. Figure 12 As shown, it includes a voltage generation circuit 00 and a driver chip, which are any of the above.

[0112] In one embodiment, the voltage generation circuit 00 in this application embodiment can be set independently and connected to the driver chip. In this embodiment, the voltage generation circuit 00 is easy to disassemble and troubleshoot.

[0113] In another embodiment, the voltage generation circuit 00 is disposed within the driver chip. That is, the circuitry of the voltage generation circuit 00 and the circuitry included in the driver chip are disposed on the same circuit board, which facilitates wiring layout and helps to form a narrow bezel.

[0114] It should be noted that the aforementioned driver chips include display driver ICs (DDI) or touch and display driver integration chips (TDDI).

[0115] In this embodiment of the invention, the display device can be any product or component with a display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator. Other essential components of the display device are understood by those skilled in the art and will not be described in detail here, nor should they be construed as limiting the invention.

[0116] Based on the same inventive concept, this disclosure provides a driving method for a voltage generation circuit 00, see reference. Figure 13 As shown, it includes: Step 201: The delay sub-circuit 01 delays the initial voltage input at the initial voltage terminal Vint for a set time and then provides it to the conduction control sub-circuit 02.

[0117] During implementation, when the delay sub-circuit 01 receives the initial voltage input from the initial voltage terminal Vint, that is, after the delay sub-circuit 01 detects that the display panel is powered on, it delays the initial voltage for a set duration through the RC resistors and capacitors included in the sub-circuit. It should be noted that the set duration is related to the model of the display panel and the initialization process, which will not be elaborated here.

[0118] After the delay sub-circuit 01 delays the initial voltage for a set time, it outputs the initial voltage and provides it to the conduction control sub-circuit 02.

[0119] Step 202: The conduction control sub-circuit 02 generates a conduction control signal in response to the initial voltage.

[0120] During implementation, after receiving the initial voltage, the conduction control sub-circuit 02 can further generate a conduction control signal to control whether the voltage generation sub-circuit 03 generates an output voltage. In this embodiment, the conduction control sub-circuit 02 is divided into a positive conduction control sub-circuit 021 and a negative conduction control sub-circuit 022 according to the polarity of the generated output voltage, which will not be described in detail here.

[0121] Step 203: In response to the turn-on control signal, the voltage generation sub-circuit 03 provides the input voltage of the voltage input terminal Vin to the voltage output terminal Vout.

[0122] During implementation, after the voltage generation sub-circuit 03 receives the conduction control signal output by the conduction control sub-circuit 02, that is, after the voltage generation sub-circuit 03 responds to the initialization setting of the display panel after a set time, the voltage generation sub-circuit 03 is turned on, and the input voltage of the voltage input terminal Vin is provided to the voltage output terminal Vout through the turned-on voltage generation sub-circuit 03, that is, the voltage output terminal Vout provides the output voltage to the outside.

[0123] In this embodiment, the voltage generation sub-circuit 03 is divided into a positive voltage generation sub-circuit 031 and a negative voltage generation sub-circuit 032 according to the polarity of the generated output voltage, which will not be described in detail here.

[0124] Based on the same inventive concept, this disclosure provides a driving method for a voltage generation circuit 00, see reference. Figure 14 As shown, it includes: Step 301: The microcontroller 10 delays the initial voltage input at the initial voltage terminal Vint for a set duration, and generates a conduction control signal based on the delayed initial voltage.

[0125] During implementation, when the microcontroller 10 receives the initial voltage input from the initial voltage terminal Vint through the pin, that is, after the delay sub-circuit 01 detects that the display panel is powered on, it will delay for a set time through the built-in software delay method before generating the conduction control signal based on the initial voltage, and then provide the conduction control signal to the voltage generation sub-circuit 03 through the relevant pin.

[0126] It should be noted that the above-mentioned setting duration is related to the display panel model and the initialization process, which will not be elaborated here.

[0127] Step 302: In response to the turn-on control signal, the voltage generation sub-circuit 03 provides the input voltage of the voltage input terminal Vin to the voltage output terminal Vout.

[0128] During implementation, after the voltage generation sub-circuit 03 receives the conduction control signal output by the pin of the microcontroller 10, that is, after the voltage generation sub-circuit 03 responds to the initialization setting of the display panel after a set time, the voltage generation sub-circuit 03 is turned on, and the input voltage of the voltage input terminal Vin is provided to the voltage output terminal Vout through the turned-on voltage generation sub-circuit 03, that is, the voltage output terminal Vout provides the output voltage to the outside.

[0129] In this embodiment, the voltage generation sub-circuit 03 is divided into a positive voltage generation sub-circuit 031 and a negative voltage generation sub-circuit 032 according to the polarity of the generated output voltage, which will not be described in detail here.

[0130] In summary, the present disclosure provides a voltage generation circuit, a display device, and a driving method. The voltage generation circuit includes a delay sub-circuit, a conduction control sub-circuit, and a voltage generation sub-circuit. The delay sub-circuit is coupled to an initial voltage terminal and the conduction control sub-circuit. The delay sub-circuit delays the initial voltage input to the initial voltage terminal for a set time before providing it to the conduction control sub-circuit. The conduction control sub-circuit is coupled to the voltage generation sub-circuit and generates a conduction control signal in response to the initial voltage. The voltage generation sub-circuit is coupled between a voltage input terminal and a voltage output terminal. In response to the conduction control signal, the voltage generation sub-circuit provides the input voltage from the voltage input terminal to the voltage output terminal. Thus, during the power-on startup of the display panel, the aforementioned set delay time ensures that the driver chip has sufficient time for initialization settings. After the initialization settings are completed, the voltage signal used to generate the scanning signal is provided to the shift register unit, thereby ensuring that the timing of the gate line scanning matches the initialization settings and avoiding abnormal display of the display panel during the power-on startup process.

[0131] Those skilled in the art will understand that embodiments of this disclosure can be provided as methods, systems, or computer program product systems. Therefore, this disclosure can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this disclosure can take the form of a computer program product system implemented on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0132] This disclosure is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program product systems according to this disclosure. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0133] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0134] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0135] Obviously, those skilled in the art can make various modifications and variations to this disclosure without departing from its spirit and scope. Therefore, if such modifications and variations fall within the scope of the claims of this disclosure and their equivalents, this disclosure is also intended to include such modifications and variations.

Claims

1. A voltage generation circuit, characterized in that, include: Delay sub-circuit, conduction control sub-circuit, and voltage generation sub-circuit; The delay sub-circuit is coupled to the initial voltage terminal and the turn-on control sub-circuit, and is configured to delay the initial voltage input to the initial voltage terminal for a set time before providing it to the turn-on control sub-circuit. The conduction control subcircuit is coupled to the voltage generation subcircuit and is configured to generate a conduction control signal in response to the initial voltage. The voltage generation sub-circuit is coupled between the voltage input terminal and the voltage output terminal and is configured to provide the input voltage of the voltage input terminal to the voltage output terminal in response to the conduction control signal.

2. The voltage generation circuit as described in claim 1, characterized in that, The delay sub-circuit includes: a first resistor and a first capacitor; The first end of the first resistor is coupled to the initial voltage terminal, and the second end of the first resistor is coupled to the first end of the first capacitor; The second end of the first capacitor is coupled to the ground terminal.

3. The voltage generation circuit as described in claim 1, characterized in that, The voltage input terminal includes a positive voltage input terminal and a negative voltage input terminal; the voltage output terminal includes a positive voltage output terminal and a negative voltage output terminal; and the voltage generation sub-circuit includes a positive voltage generation sub-circuit and a negative voltage generation sub-circuit. The positive voltage generating sub-circuit is coupled between the positive voltage input terminal and the positive voltage output terminal; The negative voltage generating sub-circuit is coupled between the negative voltage input terminal and the negative voltage output terminal.

4. The voltage generation circuit as described in claim 3, characterized in that, The voltage generation sub-circuit is the forward voltage generation sub-circuit, and the conduction control sub-circuit includes: a forward conduction control sub-circuit; The forward conduction control sub-circuit includes: a first transistor, a second resistor, and a third resistor; The control terminal of the first transistor is coupled to the second terminal of the first resistor, the first terminal of the first transistor is coupled to the second terminal of the second resistor, and the second terminal of the first transistor is coupled to the ground terminal. The first end of the second resistor is coupled to the positive voltage generating sub-circuit; The first end of the third resistor is coupled to the control terminal of the first transistor, and the second end of the third resistor is coupled to the ground terminal.

5. The voltage generation circuit as described in claim 3, characterized in that, The voltage generation sub-circuit is the negative voltage generation sub-circuit, and the conduction control sub-circuit includes: a negative conduction control sub-circuit; The negative conduction control sub-circuit includes: a second transistor, a fourth resistor, and a fifth resistor; The control terminal of the second transistor is coupled to the second terminal of the first capacitor, the first terminal of the second transistor is coupled to the second terminal of the fifth resistor, and the second terminal of the second transistor is coupled to the first terminal of the fourth resistor. The second end of the fourth resistor is coupled to the ground terminal, and the first end of the fifth resistor is coupled to the negative voltage generating sub-circuit.

6. The voltage generation circuit as described in claim 5, characterized in that, The polarity of the second transistor is opposite to that of the first transistor.

7. The voltage generation circuit as described in claim 3, characterized in that, The positive voltage generation sub-circuit includes: a third transistor, a sixth resistor, and a second capacitor; The control terminal of the third transistor is coupled to the first terminal of the second resistor, the first terminal of the third transistor is coupled to the positive voltage input terminal, and the second terminal of the third transistor is coupled to the positive voltage output terminal. The first end of the sixth resistor is coupled to the positive voltage input terminal, and the second end of the sixth resistor is coupled to the first end of the second resistor; The first terminal of the second capacitor is coupled to the positive voltage input terminal, and the second terminal of the second capacitor is coupled to the first terminal of the second resistor.

8. The voltage generation circuit as described in claim 3, characterized in that, The negative voltage generating sub-circuit includes: a fourth transistor, a seventh resistor, and a third capacitor; The control terminal of the fourth transistor is coupled to the first terminal of the fifth resistor, the first terminal of the fourth transistor is coupled to the negative voltage input terminal, and the second terminal of the fourth transistor is coupled to the negative voltage output terminal. The first end of the seventh resistor is coupled to the negative voltage input terminal, and the second end of the seventh resistor is coupled to the first end of the fifth resistor; The first terminal of the third capacitor is coupled to the negative voltage input terminal, and the second terminal of the third capacitor is coupled to the first terminal of the fifth resistor.

9. The voltage generation circuit as described in claim 8, characterized in that, The polarity of the fourth transistor is opposite to that of the third transistor.

10. The voltage generation circuit as described in claim 3, characterized in that, It also includes a discharge sub-circuit, which is coupled between the voltage output terminal and the ground terminal.

11. The voltage generation circuit as described in claim 10, characterized in that, The voltage generation sub-circuit is the positive voltage generation sub-circuit, and the discharge sub-circuit includes: an eighth resistor; The first end of the eighth resistor is coupled to the positive voltage output terminal, and the second end of the eighth resistor is coupled to the ground terminal.

12. The voltage generation circuit as described in claim 10, characterized in that, The voltage generation sub-circuit is the negative voltage generation sub-circuit, and the discharge sub-circuit includes: a ninth resistor; The first end of the ninth resistor is coupled to the negative voltage output terminal, and the second end of the ninth resistor is coupled to the ground terminal.

13. A voltage generation circuit, characterized in that, include: A microcontroller and a voltage generation sub-circuit coupled together; The microcontroller is configured to delay the initial voltage input at the initial voltage terminal for a set time, and generate a conduction control signal based on the delayed initial voltage. The voltage generation sub-circuit is coupled between the voltage input terminal and the voltage output terminal and is configured to provide the input voltage of the voltage input terminal to the voltage output terminal in response to the conduction control signal.

14. A display device, characterized in that, include: The voltage generation circuit and driving chip as described in any one of claims 1 to 13; The voltage generation circuit is located in the driver chip.

15. A driving method applied to a voltage generation circuit as described in any one of claims 1 to 12, characterized in that, include: The delay sub-circuit delays the initial voltage input to the initial voltage terminal for a set time before providing it to the conduction control sub-circuit; The conduction control sub-circuit generates a conduction control signal in response to the initial voltage; The voltage generation sub-circuit responds to the conduction control signal by providing the input voltage at the voltage input terminal to the voltage output terminal.

16. A driving method applied to the voltage generation circuit as described in claim 13, characterized in that, include: The microcontroller delays the initial voltage input at the initial voltage terminal for a set time, and generates a conduction control signal based on the delayed initial voltage. The voltage generation sub-circuit responds to the conduction control signal by providing the input voltage at the voltage input terminal to the voltage output terminal.

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