Dynamic multiply-accumulate computing apparatus based on non-volatile memory device array

Abstract

The application discloses a dynamic multiply-accumulate computing device based on a nonvolatile memory device array, comprising: a balanced Base-n encoding base number determination module configured to determine the base number of balanced Base-n encoding through the parameters of a memory device group; an element encoding module configured to perform balanced Base-n encoding and digit decomposition on a dynamic input element through the bit width of the dynamic input element and the base number of balanced Base-n encoding, and obtain the weight bit of a plurality of digit sums; a local result computing module configured to generate a word line control vector according to the sign of the digit of each nonvolatile memory device array, and calculate a signed local result in combination with a dynamic input vector and the amplitude of the digit; and a multiply-accumulate result computing module configured to perform weighted accumulation on the signed local result and the corresponding weight bit, and obtain the multiply-accumulate result between the dynamic input element and the dynamic input vector. The application can effectively express and perform parallel computation on dynamic input without writing runtime data.

Description

Technical Field

[0001] This invention relates to the field of storage computing, and more specifically to a dynamic multiply-accumulate computing device based on a non-volatile storage device array. Background Technology

[0002] Traditional multiply-accumulate circuits based on non-volatile memory devices typically employ a Computing-in-Memory (CIM) approach. This involves pre-storing a portion of the data in non-volatile memory cells within an array of non-volatile memory devices, while another portion of the data is input from outside the array to perform multiplication and accumulation operations within the array. This approach is suitable for scenarios where at least one operand can be pre-written into the array. However, when both operands involved in the computation are data generated in real-time during runtime, the traditional pre-written CIM architecture becomes difficult to apply directly. This is because such architectures usually require at least a portion of the operands to be pre-written into non-volatile memory cells and participate in the computation as device states. However, dynamically generated data at runtime is not mapped to the array before computation. If the traditional method is used, frequent write operations are required during computation, introducing significant write latency, write power consumption, and device disturbance overhead. This makes it difficult to meet the real-time and high-efficiency requirements of dynamic computing scenarios. Furthermore, it poses a significant challenge to the cycle endurance of non-volatile memory devices (such as resistive random access memory and phase-change memory), easily leading to permanent device damage.

[0003] Especially in dynamic data computation scenarios, where both parts of data involved in multiplication and accumulation operations are generated at runtime during the computation phase, unlike static weights that can be pre-configured offline, the values ​​of this type of data are usually only determined at the current computation moment and may be frequently updated as input or intermediate computation results change. Therefore, it is difficult to pre-write and persist this data to the non-volatile memory array before computation begins. If such dynamic data is required to participate in computation by writing it to the array, repeated array write operations need to be performed during computation, resulting in significant time and energy overhead, additional control complexity, and even permanent damage to the device. In existing solutions, the mainstream approach is to use a computation core based on Static Random Access Memory (SRAM) and a computation core based on non-volatile memory devices to work together, with the SRAM side handling dynamic data-related tasks. Although this approach can avoid some online writes, it introduces additional area overhead, data transfer overhead, and heterogeneous cell collaborative control complexity, thereby weakening the potential advantages of non-volatile memory arrays in high-density parallel computing.

[0004] Therefore, how to fully leverage the potential advantages of high density, high parallelism, and high energy efficiency of non-volatile memory device arrays for dynamic data computing scenarios, and how to achieve high-efficiency multiply-accumulate calculations using pre-configured fixed templates in the array and runtime input control signals without relying on or minimizing online write operations during the computing phase, has become a key technical problem that urgently needs to be solved in the design of related computing circuits. Summary of the Invention

[0005] The purpose of this application is to provide a dynamic multiply-accumulate computing device based on a non-volatile memory device array to address the aforementioned technical problems.

[0006] In a first aspect, the present invention provides a dynamic multiply-accumulate computation device based on a non-volatile memory device array, comprising a balanced Base-n encoding radix determination module, an element encoding module, a local result calculation module, and a multiply-accumulate result calculation module. The balanced Base-n encoding radix determination module is configured to determine the maximum amplitude that a single memory device group can express through parameters of the memory device group, and determine the radix of the balanced Base-n encoding based on the maximum amplitude. The element encoding module is configured to perform multiply-accumulate operations on the dynamic input elements based on the bit width of the dynamic input elements to be multiplied and accumulated and the radix of the balanced Base-n encoding. The system balances Base-n encoding and digit decomposition to obtain multiple digits and their corresponding weights, and extracts the sign and magnitude of each digit. The local result calculation module is configured to generate a corresponding word line control vector based on the sign of the digit corresponding to each non-volatile memory device array, and calculate the signed local result output by each computing unit by combining the dynamic input vector to be multiplied and accumulated with the magnitude of the corresponding digit. The multiplication and accumulation result calculation module is configured to perform weighted accumulation on the signed local result output by each computing unit with the corresponding weight to obtain the multiplication and accumulation result between the dynamic input element and the dynamic input vector.

[0007] Preferably, a non-volatile memory device array consists of several arrayed 1T1R non-volatile memory cells, and a memory device group consists of several non-volatile memory cells corresponding to consecutive word lines on the same bit line in the non-volatile memory device array; the parameters of the memory device group include the set of effective conductance states involved in the calculation mapping in a single non-volatile memory cell, and the set of effective conductance states includes... One effective conductance state, The set of effective conduction states is represented as a number from 0 to 1. The discrete amplitude levels are defined, and the set of weights corresponding to a single row of non-volatile memory cells in the memory device group is defined as... ;

[0008] In a containing Within a group of non-volatile memory cells, the weights of each row of non-volatile memory cells are allocated according to the restricted binary extension rule, defining the first... Physical weight of row non-volatile memory cells for:

[0009] ;

[0010] in, , This indicates taking the minimum value; the physical weights of all rows of non-volatile memory cells are stored in the storage device group in the form of a fixed template;

[0011] The maximum amplitude that a single memory device bank can express is calculated based on the physical weights of all rows of non-volatile memory cells. for:

[0012] ;

[0013] Radix of a balanced Base-n code corresponding to a storage device group satisfy:

[0014] .

[0015] As a preferred option, the specific process for balancing Base-n encoding and digit decomposition is as follows:

[0016] When the bit width of the dynamic input element is The number of non-volatile memory device arrays required to complete the dynamic multiply-accumulate calculation is calculated using the following formula. :

[0017] ;

[0018] in, Indicates rounding up;

[0019] Decompose dynamic input elements into A balanced Base-n base bit, as shown in the following formula:

[0020] ;

[0021] in, Indicates a dynamically input element. Indicates the first An array of non-volatile memory devices, Indicates the first The number of bits corresponding to an array of non-volatile memory devices. Indicates the first The weight bits corresponding to the array of non-volatile memory devices; For the first A balanced Base-n base.

[0022] As a preferred method, the word line control vector is calculated as follows:

[0023] In the In an array of non-volatile memory devices, a corresponding word line control vector is generated based on the magnitude of the bits, as shown in the following formula:

[0024] ;

[0025] in, Indicates the first Word line control vectors corresponding to each non-volatile memory device array. Indicates the first The first memory device group in the corresponding memory device array of the non-volatile memory device array The conduction result of the bar lines, Indicates the first The first memory device group in the corresponding memory device array of the non-volatile memory device array The bar lines are connected. Indicates the first The first memory device group in the corresponding memory device group of the non-volatile memory device array. The bar lines are not conductive; The value is calculated using the following formula:

[0026] ;

[0027] in, Indicates the first The magnitude of the bits corresponding to an array of non-volatile memory devices.

[0028] Preferably, the dynamic input vector is input from the source line direction to each non-volatile memory device array in the form of binary bit planes, and the total number of bit planes is the bit width of the dynamic input vector.

[0029] As a preferred method, the calculation process for the signed local results is as follows:

[0030] Let the first The place value corresponding to the unit plane is Then the first The array of non-volatile memory devices in the first... In the unit plane, the vector is controlled by the word line. The corresponding fixed template, together with the binary value input in the source line direction, produces the unsigned readout result, as shown in the following formula:

[0031] ;

[0032] in, Indicates the first The array of non-volatile memory devices in the first... Unsigned readout results generated in the units plane Represents the first in the dynamic input vector The element in the first... The binary value on the units plane;

[0033] Each array of non-volatile memory devices is combined with a multi-stage sensitive amplifier, registers, local adder trees, and sign selection units to construct a computing unit;

[0034] The unsigned readout result is converted into digital code by a multi-stage sensitive amplifier and then input into the local adder tree for bit-weighted reconstruction to obtain the first bit. The unsigned local result output by the local addition tree of each computational unit is shown in the following equation:

[0035] ;

[0036] in, Indicates the first The unsigned local result output by the local addition tree of each computational unit;

[0037] The sign selection unit receives digital symbols as control signals, performs sign recovery on the unsigned local results, and obtains the signed local results output by each computation unit, as shown in the following equation:

[0038] ;

[0039] in, Indicates the first The sign of the bits corresponding to an array of non-volatile memory devices. Indicates the first The signed local results output by each computational unit.

[0040] As a preferred method, the formula for calculating the result of multiplication and accumulation is as follows:

[0041] ;

[0042] in, This represents the result of multiplication and accumulation.

[0043] Preferably, the minimum resolution stage of a multi-stage sensitive amplifier is... Satisfy the following formula:

[0044] .

[0045] As a preferred option, the total area cost function is defined as follows during the parameter optimization process:

[0046] ;

[0047] in, This represents the ratio of the area of ​​the non-volatile memory device array to the total area of ​​the multi-stage sensitive amplifier in the baseline configuration. This represents the equivalent area ratio of the fixed peripheral logic associated with each non-volatile memory device array. The function representing the area of ​​a multi-stage sensitive amplifier as a function of the resolution stage increases;

[0048] Traverse within the domain Candidate combinations, calculate the corresponding , , , and and in satisfying Under the constraints, select the one that makes Candidate combinations that reach the minimum value.

[0049] Preferably, the non-volatile memory device array includes a memristor array.

[0050] Compared with the prior art, the present invention has the following beneficial effects:

[0051] (1) The dynamic multiply-accumulate computation device based on a non-volatile memory device array proposed in this invention is designed for dynamic data computation scenarios. During the computation phase, the runtime input data is not written to the non-volatile memory device array. Instead, the non-volatile memory device array is used as a pre-configured fixed computation template. Combined with balanced Base-n encoding, memory device group structure, parallel mapping of physically independent subarrays, and a digital reconstruction mechanism, dynamic multiply-accumulate computation is achieved. The dynamic input elements... Input elements are dynamically generated from the source line (SL) in binary form. Before computation, after balanced Base-n encoding and digit decomposition, the data is not written to the non-volatile storage array. Instead, it is applied to the array from the word line (WL) direction in the form of word line control vectors. The non-volatile storage array only stores a fixed template and does not perform any write operations during the computation phase. The generation of local results and the reconstruction of the final output are completed through a hybrid computation path of simulated readout and digital reconstruction.

[0052] (2) The dynamic multiply-accumulate computing device based on non-volatile memory device array proposed in this invention designs a dynamic multiply-accumulate circuit architecture based on memory device group. The architecture uses a 1T1R non-volatile memory device array as the basic unit, and combines multiple non-volatile memory units along the bit line direction into a memory device group to represent the expressible range of a certain digit amplitude in balanced Base-n encoding; multiple non-volatile memory device arrays correspond to different digits after encoding of dynamic input element B, and each non-volatile memory device array calculates the corresponding local result in parallel. Each non-volatile memory device array is also combined with a multi-stage sense amplifier (MLSA), register (Reg), local adder tree and sign select unit (SSU) to form a computing unit, which first completes local recovery and accumulation, then completes signed conversion according to the sign of the current digit, and finally performs global accumulation by weight between different computing units.

[0053] (3) The present invention proposes a hardware resource evaluation and area optimization framework for a dynamic multiply-accumulate computing device based on a non-volatile memory device array. This framework uses the number of rows in the group, the number of non-volatile memory device arrays, and the number of available conductance states of non-volatile memory cells as core variables to establish a mapping relationship between dynamic input bit width, encoding cardinality, array size, and peripheral readout / digital logic area, thereby providing a basis for parameter combination search under the given bit width requirement to guide hardware specification configuration. Attached Figure Description

[0054] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0055] Figure 1 This is a flowchart illustrating the computation of a dynamic multiply-accumulate computational device based on a non-volatile memory device array, as an embodiment of this application.

[0056] Figure 2 The flowchart of a write-free multiply-accumulate calculation using spatial parallelism in a dynamic multiply-accumulate calculation device based on a non-volatile memory device array, which is an embodiment of this application, is shown.

[0057] Figure 3This is a circuit diagram illustrating write-free dynamic computation in a dynamic multiply-accumulate computation device based on a non-volatile memory device array, as an embodiment of this application. Detailed Implementation

[0058] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this invention, and not all of them. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this invention.

[0059] Figure 1 This application illustrates an embodiment of a dynamic multiply-accumulate computational device based on a non-volatile memory device array, comprising a balanced Base-n encoding radix determination module, an element encoding module, a local result calculation module, and a multiply-accumulate result calculation module. The balanced Base-n encoding radix determination module is configured to determine the maximum amplitude that a single memory device array can express based on parameters of the memory device array, and to determine the radix of the balanced Base-n encoding based on the maximum amplitude. The element encoding module is configured to perform multiply-accumulate operations on the dynamic input elements based on the bit width of the dynamic input elements to be multiplied and accumulated and the radix of the balanced Base-n encoding. The algorithm performs balanced Base-n encoding and digit decomposition to obtain multiple digits and their corresponding weights, and extracts the sign and magnitude of each digit. The local result calculation module is configured to generate a corresponding word line control vector based on the sign of the digit corresponding to each non-volatile memory device array, and calculate the signed local result output by each computing unit by combining the dynamic input vector to be multiplied and accumulated with the magnitude of the corresponding digit. The multiply-accumulate result calculation module is configured to perform weighted accumulation on the signed local result output by each computing unit with the corresponding weight to obtain the multiply-accumulate result between the dynamic input element and the dynamic input vector.

[0060] Specifically, the application scenarios mentioned in the embodiments of this application are all multiplication and accumulation operations, that is, the operation of multiplying any vector with any element one by one and then accumulating them together. For different specific scenarios, the source of the dynamic input element B is different. For example, for neural network model calculation, B comes from the weight vector.

[0061] The embodiments of this application uniformly adopt the following notation conventions: the dynamic input vector is denoted as... Dynamic input elements are denoted as .in, For length is A vector, where each element is a vector. -bit binary number; Given one element from another input vector, only one element is processed at a time in the current computation kernel. The current output target of the computational core is:

[0062] ;

[0063] Or equivalently written as:

[0064] ;

[0065] in, Represents the first in the dynamic input vector One element, This represents the result of multiplication and accumulation.

[0066] In other words, the current computing core implements a dynamic input element. With a dynamic input vector The process of multiplying and accumulating.

[0067] In a specific embodiment, a non-volatile memory device array is composed of a plurality of arrayed 1T1R non-volatile memory cells, and a memory device group is composed of non-volatile memory cells corresponding to a plurality of consecutive word lines on the same bit line in the non-volatile memory device array; the parameters of the memory device group include the set of effective conductance states participating in the calculation mapping in a single non-volatile memory cell, and the set of effective conductance states includes One effective conductance state, The set of effective conduction states is represented as a number from 0 to 1. The discrete amplitude levels are defined, and the set of weights corresponding to a single row of non-volatile memory cells in the memory device group is defined as... ;

[0068] In a containing Within a group of non-volatile memory cells, the weights of each row of non-volatile memory cells are allocated according to the restricted binary extension rule, defining the first... Physical weight of row non-volatile memory cells for:

[0069] ;

[0070] in, , This indicates taking the minimum value; the physical weights of all rows of non-volatile memory cells are stored in the storage device group in the form of a fixed template;

[0071] The maximum amplitude that a single memory device bank can express is calculated based on the physical weights of all rows of non-volatile memory cells. for:

[0072] ;

[0073] Radix of a balanced Base-n code corresponding to a storage device group satisfy:

[0074] .

[0075] In a specific embodiment, the non-volatile memory device array includes a memristor array.

[0076] Specifically, in the embodiments of this application, in order to effectively represent and perform parallel computation on input data with a large numerical range without writing runtime input data to the non-volatile storage device array during the computation phase, a "storage device group" is defined as the basic computational representation unit in the embodiments of this application. Unlike the traditional CIM scheme where "a single non-volatile storage unit maps to a single bit," the embodiments of this application map several lines (denoted as...) on the same bit line (BL)... Each consecutive word line (WL) is divided into a 1T1R non-volatile memory unit group to collectively represent the magnitude and sign of a single digit under balanced Base-n encoding. The purpose of this grouping structure is to achieve high cardinality digital representation capability through physical space reuse and fixed template mapping without writing runtime data.

[0077] Non-volatile memory device arrays only store a fixed template during the computation phase. This fixed template refers to the discrete conductance states pre-written into each non-volatile memory cell, and the corresponding physical weights of these conductance states within the memory device array. (Runtime dynamic input vector) and dynamic input elements Instead of writing data to non-volatile memory cells, data participates in the calculation from the SL and WL sides respectively in the form of control signals or excitation signals. Therefore, in the embodiments of this application, the non-volatile memory device array performs the function of "fixed template participating in calculation" rather than the function of "online writing of runtime data to storage".

[0078] The total number of valid conductance states that can be mapped from a non-volatile memory cell is uniformly denoted as follows in the embodiments of this application: In one preferred embodiment, if the physical minimum conductance state is difficult to satisfy the mapping linearity requirement, it can be eliminated in the mapping stage, retaining only the remaining effective conductance states; however, this process is only a preferred embodiment and does not constitute a necessary prerequisite for the establishment of the embodiments of this application.

[0079] If the set of effective conductance states involved in the mapping calculation is denoted as... Then, the range of discrete weights that a single non-volatile memory cell can provide can be determined by the set of effective conductance states; in common cases, the set of effective conductance states can be equivalently represented as a range from 0 to The discrete amplitude levels, the set of weights that can correspond to a single row of non-volatile memory cells are defined as follows: In a containing Within a group of non-volatile memory cells, the weights of each row within the group are allocated according to a restricted binary extension rule. This rule means that when... When the effective conductance state expansion capability of the non-volatile memory cell has not yet been exceeded, binary rate scaling is preferentially used within the group; when As the number of states continues to increase, the highest weight of each new row is linearly accumulated, thereby expanding the number of individual states within a finite number of elements. The range of representable amplitudes. Therefore, the maximum amplitude that a set of memory devices can represent can be given. The maximum amplitude It characterizes the upper limit of the amplitude that a single storage device group can represent under the current fixed template configuration; it determines both the single The range of values ​​for also forms an important basis for subsequently determining the radix of the balanced Base-n encoding. In other words, the definition of the storage device group is not only a description of the array organization, but also directly determines the encoding method and subsequent local computation capability of the dynamic input vector in the embodiments of this application.

[0080] In a specific implementation, the process of balancing Base-n encoding and digit decomposition is as follows:

[0081] When the bit width of the dynamic input element is The number of non-volatile memory device arrays required to complete the dynamic multiply-accumulate calculation is calculated using the following formula. :

[0082] ;

[0083] in, Indicates rounding up;

[0084] Decompose dynamic input elements into A balanced Base-n base bit, as shown in the following formula:

[0085] ;

[0086] in, Indicates a dynamically input element. Indicates the first An array of non-volatile memory devices, Indicates the first The number of bits corresponding to an array of non-volatile memory devices. Indicates the first The weight bits corresponding to the array of non-volatile memory devices; For the first A balanced Base-n base.

[0087] Specifically, the expressive power of a single memory device array is limited by a maximum value. The constraints, therefore when dynamically inputting elements When the bit width is high, a single set of structures cannot be used to represent the entire numerical range. To enable dynamic input elements to participate in multiply-accumulate calculations without being written to a non-volatile memory array, embodiments of this application first... Convert to balanced Base-n form, then decompose it into multiple signed digits. and by each number Each element participates in subsequent local calculations. Therefore, dynamically input elements... Instead of being directly fed into the non-volatile memory array as a whole numerical value, it is converted into several bits that can be processed separately by local computing channels. Amplitude-sign pair.

[0088] Because the embodiments of this application employ balanced Base-n encoding, the digital... It contains both amplitude and sign information. Therefore, the effective value range for each digit is... .

[0089] The radix selection for balanced Base-n encoding is not arbitrary, but determined by the range of positive and negative amplitude values ​​that a single group can represent: when the range of digit values ​​covers At that time, it just happened to be needed The number of discrete values ​​can be used, therefore a base number can be employed. The balanced encoding form. After this definition, each The amplitude range can correspond one-to-one with the physical weights in the fixed template of a single storage device group, thus providing a basis for subsequent... A unified interface is provided for generating control information.

[0090] When dynamically input elements The original binary bit width is At that time, the number of non-volatile memory device arrays required The information density is determined by the balanced Base-n representation. This assumes that the original input can be represented losslessly. The smallest integer whose value satisfies the following formula: Here This not only represents the number of balanced Base-n base bits, but also, in the embodiments of this application, corresponds to the number of local processing channels that subsequently participate in parallel computation. In other words, the dynamic input elements... Each of the decomposed results in Each can correspond to a physically independent array of non-volatile storage devices or an independent local computation path. Subsequently, the original i-bit dynamic input elements... Decomposed into A balanced Base-n base bit, reference Figure 2 .

[0091] In a specific embodiment, the word line control vector is calculated as follows:

[0092] In the In an array of non-volatile memory devices, a corresponding word line control vector is generated based on the magnitude of the bits, as shown in the following formula:

[0093] ;

[0094] in, Indicates the first Word line control vectors corresponding to each non-volatile memory device array. Indicates the first The first memory device group in the corresponding memory device group of the non-volatile memory device array. The conduction result of the bar lines, Indicates the first The first memory device group in the corresponding memory device group of the non-volatile memory device array. The bar lines are connected. Indicates the first The first memory device group in the corresponding memory device group of the non-volatile memory device array. The bar lines are not conductive; The value is calculated using the following formula:

[0095] ;

[0096] in, Indicates the first The magnitude of the bits corresponding to an array of non-volatile memory devices.

[0097] In a specific embodiment, the dynamic input vector is input from the source line direction to each non-volatile memory device array in the form of binary bit planes, and the total number of bit planes is the bit width of the dynamic input vector.

[0098] Specifically, dynamic input elements Rewritten as multiple signed digits with different place values For subsequent calculations, each digit... symbols Used to generate corresponding control information to determine how the fixed template participates in local computation; each digit amplitude Then it is used to control the symbolic mapping of local results; different The corresponding local results are then processed according to their respective weights. Perform a weighted summation to recover the result that is consistent with the dynamically input elements. Equivalent multiplication and summation results.

[0099] Specifically, in the In an array of non-volatile memory devices, firstly by Generate the corresponding word line control vector .in accordance with and get There are several methods, among which the most representative is the table lookup method. The table lookup method is only used for engineering implementation. Typical methods of acquisition, but not limited to these.

[0100] In a specific embodiment, the calculation process for the signed local result is as follows:

[0101] Let the first The place value corresponding to the unit plane is Then the first The array of non-volatile memory devices in the first... In the unit plane, the vector is controlled by the word line. The corresponding fixed template, together with the binary value input in the source line direction, produces the unsigned readout result, as shown in the following formula:

[0102] ;

[0103] in, Indicates the first The array of non-volatile memory devices in the first... Unsigned readout results generated in the units plane Represents the first in the dynamic input vector The element in the first... The binary value on the units plane;

[0104] Each array of non-volatile memory devices is combined with a multi-stage sensitive amplifier, registers, local adder trees, and sign selection units to construct a computing unit;

[0105] The unsigned readout result is converted into digital code by a multi-stage sensitive amplifier and then input into the local adder tree for bit-weighted reconstruction to obtain the first bit. The unsigned local result output by the local addition tree of each computational unit is shown in the following equation:

[0106] ;

[0107] in, Indicates the first The unsigned local result output by the local addition tree of each computational unit;

[0108] The sign selection unit receives digital symbols as control signals, performs sign recovery on the unsigned local results, and obtains the signed local results output by each computation unit, as shown in the following equation:

[0109] ;

[0110] in, Indicates the first The sign of the bits corresponding to an array of non-volatile memory devices. Indicates the first The signed local results output by each computational unit.

[0111] Specifically, dynamic input vector Each non-volatile memory device array is input from the source line (SL) direction in binary bit-plane form, i.e., a dynamic input vector. It is input in the form of binary values ​​on different bit planes. Let the first... The place value corresponding to the unit plane is Then the first The array of non-volatile memory devices in the first... In the bit-plane, the vector is controlled by the word line. The selected fixed template, together with the binary value input from the SL side, generates an unsigned readout result. This unsigned readout result is converted into digital code by a multi-stage sensitive amplifier (MLSA), and then fed into a local adder tree for bit-weighted reconstruction to obtain the first... The unsigned local results output by the local addition tree of each computational unit. In mathematics, Equivalent to:

[0112] .

[0113] Subsequently, the sign selection unit (SSU) receives the sign of each digit. As a control signal, for Perform symbolic recovery to obtain the first... Signed local results output by each computational unit In mathematics, Equivalent to:

[0114] .

[0115] In a specific embodiment, the formula for calculating the multiplication-accumulation result is as follows:

[0116] ;

[0117] in, This represents the result of multiplication and accumulation.

[0118] Specifically, the global accumulation unit is based on the weight of each digit. The signed local results output by each computational unit are weighted and accumulated to obtain the final multiplicative sum. .

[0119] In summary, the role of balanced Base-n encoding in the embodiments of this application is not only to complete the numerical representation conversion, but more importantly, to convert dynamically input elements... This is transformed into a control form suitable for array-distributed processing with fixed templates, thereby establishing "single-set expressive power - The one-to-one correspondence between "encoding - local computation - global reconstruction".

[0120] From a hardware perspective, refer to Figure 3 Dynamic input elements The Number of digits It will be sent as a control signal to the first A non-volatile memory device array, controlling the word line on / off combinations of corresponding memory device groups within that array. It is important to emphasize that... During computation, it only plays a control role and is not written to non-volatile memory cells; what actually remains unchanged within each non-volatile memory array is the aforementioned fixed template. In parallel, the dynamic input vector... Each element is broadcast in binary form along the source line direction to the entire non-volatile memory device array.

[0121] At the current computational granularity, the number of bits output for each non-volatile memory device array... Generate an unsigned local result; this unsigned local result is then processed by a local addition tree onto the dynamic input vector. After the binary value is recovered and accumulated, the sign selection unit then selects the sign value based on the binary value. The symbols complete the signed transformation, thus forming a signed local result. .

[0122] Finally, the signed local results output by different computational units are sorted according to their respective weights. Perform a global summation to obtain the final output result of the multiplication and summation.

[0123] From the perspective of computing circuit architecture, refer to Figure 3 The circuit architecture of the embodiments of this application is as follows: The circuit architecture consists of several physically independent computational units, a global accumulator unit, and an output register. Each computational unit includes an array of non-volatile memory devices, a multi-stage sensitive amplifier (MLSA), a register, a local adder tree, and a sign selection unit (SSU). The basic signal flow of this circuit architecture is as follows: multiple As word line control signal input to the non-volatile memory device array; dynamic input vector The source lines of each non-volatile memory device array are input in parallel; each non-volatile memory device array completes analog readout, register alignment, local addition and sign processing; finally, the output results of each computing unit are globally accumulated according to their weights and stored in the output register.

[0124] The non-volatile memory device array consists of 1T1R non-volatile memory cells. Each non-volatile memory cell in the array is pre-written with a fixed discrete conductance state before computation. Multiple non-volatile memory cells arranged along the same bit line direction constitute a memory device group. The physical weights of each row within the memory device group are predetermined, forming a fixed template for computation.

[0125] During the computation phase, the dynamic input vector Input from the source line in binary form; dynamically input elements. First, perform balanced Base-n encoding, then process each digit... As control signals, they are sent to the corresponding non-volatile memory device arrays. For the first... An array of non-volatile memory devices, corresponding to a number of bits. The amplitude is controlled by word line switching and applied to the corresponding memory device group in the non-volatile memory device array, thereby selecting a predetermined number or combination of word lines to be turned on within the memory device group. The sign bit is not implemented within the non-volatile memory array, but is reserved for processing by the subsequent sign selection unit (SSU). Throughout this process, dynamically input elements... It is not written to the non-volatile memory device array, but participates in the calculation only through port control signals.

[0126] Due to different Different word line control information needs to be input simultaneously. Therefore, the embodiments of this application use multiple non-volatile memory device arrays instead of a single large array logical partitioning structure.

[0127] Multistage sensitive amplifiers (MLSAs) are used to read out the output generated by the memory device array along the bit line (BL) direction and convert the analog amplitude into discrete levels that can be processed by subsequent digital logic. Since the sign bit is processed separately by the SSU behind the non-volatile memory device array, the MLSA is primarily responsible for amplitude discrimination; therefore, its minimum resolution only needs to cover 0 to 1. The unsigned amplitude range between these values. This design decouples the readout circuit and the sign processing circuit in terms of their responsibilities, facilitating subsequent area modeling and implementation optimization.

[0128] The local addition tree is located within each computational unit, placed after the register and before the SSU. Its function is to perform weighted local shifting and accumulation of multiple reads along the bit line (BL) to complete the dynamic input vector. Each binary component in the equation corresponds to the reconstruction and accumulation of local results, forming a result that is consistent with the current result. The magnitude corresponds to the unsigned local result.

[0129] Each computing unit is configured with a symbol selection unit (SSU). The SSU receives the corresponding... The sign bit is used as a control signal, and a signed conversion is performed on the unsigned local result output by the local addition tree. When When the sign is positive, SSU directly outputs the unsigned local result; when... When the sign of the result is negative, SSU converts the unsigned local result into two's complement form for output. After processing by SSU, the output results of different computational units can be output according to their respective weights. Enter the global accumulation path.

[0130] In a specific embodiment, the minimum resolution stage of the multi-stage sensitive amplifier Satisfy the following formula:

[0131] .

[0132] In a specific embodiment, during the parameter optimization process, the total area cost function is defined as:

[0133] ;

[0134] in, This represents the ratio of the area of ​​the non-volatile memory device array to the total area of ​​the multi-stage sensitive amplifier in the baseline configuration. This represents the equivalent area ratio of the fixed peripheral logic associated with each non-volatile memory device array. The function representing the area of ​​a multi-stage sensitive amplifier as a function of the resolution stage increases;

[0135] Traverse within the domain Candidate combinations, calculate the corresponding , , , and and in satisfying Under the constraints, select the one that makes Candidate combinations that reach the minimum value.

[0136] Specifically, to guide hardware specification design under different input bit widths, embodiments of this application further establish an array modeling and parameter optimization framework oriented towards area evaluation. The goal of this framework is: for a given dynamic input element... bit width Under the premise of satisfying encoding correctness and lossless mapping, find the row number within the storage device group. Total number of non-volatile memory device arrays and the total number of effective conduction states of non-volatile memory cells. The better combination.

[0137] Based on the aforementioned definitions, the maximum amplitude of the storage device group Depend on Together, we decide to balance the radix of Base-n encoding. Further by The minimum resolution stage of a multi-stage sensitive amplifier (MLSA) is determined. Only the range of unsigned magnitudes needs to be covered, therefore:

[0138] ;

[0139] To quantify the overall hardware overhead, a total area cost function is established. The baseline configuration in this total area cost function is... The fixed peripheral logic associated with each non-volatile memory device array mainly consists of local registers, local additions, and necessary control logic. The specific form is determined by the actual sensitive amplifier structure used. If a fully parallel (Flash) implementation is used, Typically, the resolution increases approximately linearly with the resolution level; however, if a successive approximation (SAR) implementation is used, This is closer to logarithmic growth. Since the embodiments of this application treat the size of the addition tree as fixed, the optimization variables mainly focus on... , On both parameters.

[0140] Therefore, the area optimization process can be described as: traversing within the feasible domain. Candidate combinations, calculate the corresponding , , , and and in satisfying Under the constraints, select the one that makes The parameter combination that achieves the minimum value.

[0141] Through the above modeling, the embodiments of this application achieve a unified mapping from "input bit width requirements" to "memory device group structure, non-volatile memory device array size, and readout circuit size". This framework is not an abstract algorithm independent of hardware implementation, but directly serves the determination of circuit specifications for write-free dynamic multiply-accumulate computation cores, and therefore constitutes an important part of the embodiments of this application.

[0142] To facilitate understanding of the computational flow of the embodiments of this application, a specific numerical example is provided below, using a memristor as a representative of non-volatile memory, to illustrate the encoding decomposition of the second dynamic input, the generation of local results, and the reconstruction of the final result. It should be noted that the following example is only used to explain the working principle of the embodiments of this application and does not constitute a limitation on the scope of protection of the embodiments of this application.

[0143] Assume the first dynamic input vector is The second dynamic input is And the maximum representable amplitude of a single storage device group under the current fixed template configuration is This allows us to determine the radix of the balanced Base-n encoding. Therefore, a single The valid range of values ​​is Further assuming a second dynamic input Then it can be expressed as:

[0144] ;

[0145] This results in two balanced Base-5 digits, respectively. and During the computation phase, the first dynamic input vector Each element is input in parallel to all physically independent subarrays, while the two These correspond to the local computation processes of the two subarrays, respectively. The amplitude portion is used to generate corresponding control information to determine the participation mode of the fixed template in the relevant storage device group; The symbolic part is used to control the symbolic mapping of local results. Because of the two in this example... All values ​​are positive, so no sign conversion is needed for the corresponding local results.

[0146] Suppose and and The corresponding local results are as follows and The final output can be represented as:

[0147] ;

[0148] in, and These represent the first dynamic input vector. With each The corresponding amplitude is the result of local multiplication and accumulation. After weighted accumulation, the result can be recovered to be the same as the original input. The final result directly participates in the multiplication-accumulation equivalence. Therefore, it can be seen that the embodiments of this application can achieve this without requiring runtime input. Under the condition of writing to the array, multiply-accumulate calculations for dynamic data can be achieved using only pre-configured fixed templates and runtime control signals.

[0149] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A dynamic multiply-accumulate computing device based on a non-volatile memory device array, characterized in that, It includes a balanced Base-n encoding radix determination module, an element encoding module, a local result calculation module, and a multiply-accumulate result calculation module. The balanced Base-n encoding radix determination module is configured to determine the maximum amplitude that a single storage device group can express through the parameters of the storage device group, and determine the radix of the balanced Base-n encoding based on the maximum amplitude. The element encoding module is configured to perform balanced Base-n encoding and digit decomposition on the dynamic input element based on the bit width of the dynamic input element to be multiplied and accumulated and the radix of the balanced Base-n encoding, to obtain multiple digits and their corresponding weights, and to extract the sign and magnitude of each digit. The local result calculation module is configured to generate a corresponding word line control vector based on the sign of the bits corresponding to each non-volatile memory device array, and calculate the signed local result output by each computing unit by combining the dynamic input vector to be multiplied and accumulated with the magnitude of the corresponding bits. The multiply-accumulate result calculation module is configured to perform weighted accumulation on the signed local result output by each computing unit with the corresponding weight bits to obtain the multiply-accumulate result between the dynamic input element and the dynamic input vector.

2. The dynamic multiply-accumulate computing device based on a non-volatile memory device array according to claim 1, characterized in that, A non-volatile memory device array consists of several arrayed 1T1R non-volatile memory cells, and a memory device group consists of several non-volatile memory cells corresponding to consecutive word lines on the same bit line in the non-volatile memory device array; the parameters of the memory device group include the set of effective conductance states involved in the calculation mapping in a single non-volatile memory cell, and the set of effective conductance states includes... One effective conductance state, The total number of effective conduction states is represented by the set of effective conduction states from 0 to... The discrete amplitude levels are defined, and the set of weights corresponding to a single row of non-volatile memory cells in the memory device group is defined as... ; In a containing Within a group of non-volatile memory cells, the weights of each row of non-volatile memory cells are allocated according to the restricted binary extension rule, defining the first... Physical weight of row non-volatile memory cells for: ； in, , This indicates taking the minimum value; the physical weights of all rows of non-volatile memory cells are stored in the memory device group in the form of a fixed template; The maximum amplitude that a single memory device bank can express is calculated based on the physical weights of all rows of non-volatile memory cells. for: ； Radix of a balanced Base-n code corresponding to a storage device group satisfy: 。 3. The dynamic multiply-accumulate computing device based on a non-volatile memory device array according to claim 2, characterized in that, The specific process of balancing Base-n encoding and digit decomposition is as follows: When the bit width of the dynamic input element is The number of non-volatile memory device arrays required to complete the dynamic multiply-accumulate calculation is calculated using the following formula. : ； in, Indicates rounding up; Decompose the dynamic input element into A balanced Base-n base bit, as shown in the following formula: ； in, Indicates a dynamically input element. Indicates the first An array of non-volatile memory devices, Indicates the first The number of bits corresponding to an array of non-volatile memory devices. Indicates the first The weight bits corresponding to the array of non-volatile memory devices; For the first A balanced Base-n base.

4. The dynamic multiply-accumulate computing device based on a non-volatile memory device array according to claim 3, characterized in that, The calculation process for the word line control vector is as follows: In the In a non-volatile memory device array, a corresponding word line control vector is generated based on the magnitude of the bits, as shown in the following formula: ； in, Indicates the first Word line control vectors corresponding to each non-volatile memory device array. Indicates the first The first memory device group in the corresponding memory device group of the non-volatile memory device array. The conduction result of the bar lines, Indicates the first The first memory device group in the corresponding memory device group of the non-volatile memory device array. The bar lines are connected. Indicates the first The first memory device group in the corresponding memory device group of the non-volatile memory device array. The bar lines are not conductive; The value is calculated using the following formula: ； in, Indicates the first The magnitude of the bits corresponding to an array of non-volatile memory devices.

5. The dynamic multiply-accumulate computing device based on a non-volatile memory device array according to claim 4, characterized in that, The dynamic input vector is input from the source line direction to each non-volatile memory device array in the form of binary bit planes, and the total number of bit planes is the bit width of the dynamic input vector.

6. The dynamic multiply-accumulate computing device based on a non-volatile memory device array according to claim 5, characterized in that, The calculation process for the signed local result is as follows: Let the first The place value corresponding to the unit plane is Then the first The array of non-volatile memory devices in the first... In the unit plane, the vector is controlled by the word line. The corresponding fixed template, together with the binary value input in the source line direction, produces the unsigned readout result, as shown in the following formula: ； in, Indicates the first The array of non-volatile memory devices in the first... Unsigned readout results generated in the units plane Represents the first in the dynamic input vector The element in the first... The binary value on the units plane; Each array of non-volatile memory devices is combined with a multi-stage sensitive amplifier, registers, local adder trees, and sign selection units to construct a computing unit; The unsigned readout result is converted into digital code by a multi-stage sensitive amplifier and then input into a local adder tree for bit-weighted reconstruction to obtain the first bit. The unsigned local result output by the local addition tree of each computational unit is shown in the following equation: ； in, Indicates the first The unsigned local results output by the local addition tree of each computational unit; The sign of the digits is received by the sign selection unit and used as a control signal to perform sign recovery on the unsigned local result, resulting in the signed local result output by each computing unit, as shown in the following formula: ； in, Indicates the first The sign of the bits corresponding to an array of non-volatile memory devices. Indicates the first The signed local results output by each computational unit.

7. The dynamic multiply-accumulate computing device based on a non-volatile memory device array according to claim 6, characterized in that, The formula for calculating the result of the multiplication and accumulation is as follows: ； in, This represents the result of multiplication and accumulation.

8. The dynamic multiply-accumulate computing device based on a non-volatile memory device array according to claim 6, characterized in that, Minimum resolution stage of a multi-stage sensitive amplifier Satisfy the following formula: 。 9. The dynamic multiply-accumulate computing device based on a non-volatile memory device array according to claim 8, characterized in that, During parameter optimization, the total area cost function is defined as follows: ； in, This represents the ratio of the area of ​​the non-volatile memory device array to the total area of ​​the multi-stage sensitive amplifier in the baseline configuration. This represents the equivalent area ratio of the fixed peripheral logic associated with each non-volatile memory device array. The function representing the area of ​​a multi-stage sensitive amplifier as a function of the resolution stage increases; Traverse within the domain Candidate combinations, calculate the corresponding , , , and and in satisfying Under the constraints, select the one that makes Candidate combinations that reach the minimum value.

10. The dynamic multiply-accumulate computing device based on a non-volatile memory device array according to claim 1, characterized in that, The non-volatile memory device array includes a memristor array.

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