Three-dimensional integrated memory device and data error correction processing method

Abstract

The application provides a three-dimensional integrated storage device and a data error correction processing method, and relates to the technical field of semiconductors. The device comprises: a first wafer, the first wafer being integrated with NAND flash memory cells and a control unit, the NAND flash memory cells being used for storing a check matrix, and the control unit comprising an error correction controller and a buffer; and a second wafer, the second wafer being integrated with NAND flash memory cells. The first wafer and the second wafer are vertically stacked and electrically connected through a bonding interface. The error correction controller is configured to: perform error detection on original data read by the control unit from the NAND flash memory cells into the buffer through the bonding interface; if an error is detected, read the check matrix from the NAND flash memory cells, and perform error correction on the original data by using the read check matrix to obtain error-corrected data. The technical scheme can realize the configurability and upgradability of the check matrix simply and efficiently under the premise of ensuring error correction capability, and meanwhile, the occupation of on-chip buffer resources is reduced.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically, to a three-dimensional integrated storage device and a data error correction processing method. Background Technology

[0002] Memory devices are one of the core components of modern electronic systems. NAND flash memory is widely used in large-capacity data storage scenarios due to its high storage density and low cost. To ensure the reliability of data reading from NAND flash memory, error correction technology is widely used, among which error correction codes based on parity-check matrices have become the mainstream choice in high-end storage systems due to their excellent error correction performance.

[0003] In practical applications, the aforementioned error correction techniques are typically executed by an error correction controller, which needs to store a large parity check matrix to support data error correction during the decoding process. In existing technologies, the parity check matrix is ​​stored in read-only memory (ROM) within the error correction controller. After the memory device is powered on, the error correction controller loads the entire parity check matrix into the on-chip cache and keeps it resident to meet high-speed random access requirements. However, this approach has the following problems: First, the parity check matrix stored in ROM cannot or is difficult to replace or upgrade according to different lifecycle stages of the non-flash memory cells, leading to a rigid error correction strategy; second, keeping the entire parity check matrix resident consumes a large amount of expensive on-chip cache resources, thereby increasing the area and cost of the memory chip.

[0004] Therefore, how to achieve simple and efficient configurability and upgradeability of the parity check matrix while ensuring error correction capability, and at the same time reduce the occupation of on-chip cache resources, has become a technical problem that urgently needs to be solved in this field. Summary of the Invention

[0005] The purpose of this application is to provide a three-dimensional integrated storage device and a data error correction processing method, which can simply and efficiently realize the configurability and upgradeability of the parity check matrix while ensuring error correction capability, and at the same time reduce the occupation of on-chip cache resources.

[0006] This application is implemented as follows: In a first aspect, this application provides a three-dimensional integrated storage device, comprising: a first wafer integrating NOR flash memory cells and a control unit, wherein the NOR flash memory cells are used to store a parity check matrix, and the control unit includes an error correction controller and a buffer; and a second wafer integrating NAND flash memory cells. The first and second wafers are vertically stacked and electrically connected via a bonding interface. The error correction controller is configured to: perform error detection on raw data read into the buffer from the NAND flash memory cells by the control unit via the bonding interface; if an error is detected, read the parity check matrix from the NOR flash memory cells and use the read parity check matrix to correct the original data, obtaining error-corrected data.

[0007] In some implementations, when the error correction controller reads the parity matrix from the NOR flash memory cell, it is configured to read portions of the parity matrix from the NOR flash memory cell as needed and in blocks, based on the current decoding progress.

[0008] In some implementations, the OR non-flash cell is also used to store at least two sets of parity check matrices with different error correction intensities, which correspond to different lifecycle stages of the OR non-flash cell. When the error correction controller reads the parity check matrix from the OR non-flash cell, it is configured to: identify the current lifecycle stage of the OR non-flash cell, and select the parity check matrix with the corresponding error correction intensity from the OR non-flash cell according to the identified lifecycle stage.

[0009] In some implementations, the lifecycle phase includes the new disk phase or the end of the lifecycle; in this case, the error correction controller selects to read the parity check matrix with a higher error correction strength at the end of the lifecycle than when selecting to read the parity check matrix at the new disk phase.

[0010] In some implementations, the NOR / Non-flash cells are also used to store at least two sets of parity check matrices with different bit rates. When the error correction controller reads the parity check matrix from the NOR / Non-flash cells, it is configured to: identify the current bit error rate state of the NOR / Non-flash cells, and select the parity check matrix from the NOR / Non-flash cells that matches the bit error rate state.

[0011] In some implementations, non-flash cells are also used to update the parity matrix they store via firmware upgrades.

[0012] In some implementations, the bonding interface includes a data bus, a control bus, and a clock signal line.

[0013] In some implementations, the parity check matrix is ​​the parity check matrix of the LDPC code, and the error correction controller is an LDPC decoder.

[0014] In some implementations, a first substrate is provided on the side of the first wafer away from the second wafer, and a second substrate is provided on the side of the second wafer away from the first wafer.

[0015] In some implementations, the bonding interface is a hybrid bonding interface.

[0016] In a second aspect, this application provides a data error correction processing method, applied to a three-dimensional integrated storage device in any implementation of the first aspect, the data error correction processing method including a data reading operation process and / or a data writing operation process.

[0017] The data reading operation process includes: the control unit reads the raw data from the NAND flash memory cell through the bonding interface and stores the raw data in the buffer; the control unit controls the error correction controller to check the raw data in the buffer for errors; if an error is detected, the control unit controls the error correction controller to read the parity matrix from the NAND flash memory cell and controls the error correction controller to use the read parity matrix to correct the raw data to obtain the corrected data.

[0018] The data writing operation process includes: the control unit receives the data to be written and stores it in the buffer; the control unit allocates the storage address of the data to be written in the NAND flash memory cell; the control unit controls the error correction controller to read the parity matrix from the NAND flash memory cell and controls the error correction controller to generate a check code for the data to be written using the read parity matrix; the control unit sends the data to be written and the check code in the buffer to the NAND flash memory cell for storage through the bonding interface.

[0019] Compared with the prior art, this application has at least the following advantages or beneficial effects: This application re-architects the data error correction mechanism by storing the parity check matrix in a non-flash memory cell of the first wafer and adopting a structure in which the first wafer and the second wafer are vertically stacked. This allows for the simple and efficient implementation of configurable and upgradeable parity check matrices while ensuring error correction capabilities, and at the same time reducing the occupation of on-chip cache resources.

[0020] Specifically, this application moves the parity check matrix from inside the error correction controller to the storage of a non-flash memory cell on the first wafer. This allows the parity check matrix to be upgraded or replaced with firmware based on different lifecycle stages of the non-flash memory cell, avoiding the problem of rigid error correction strategies that cannot adapt to different usage stages. Furthermore, the error correction controller in this application only reads the parity check matrix from the non-flash memory cell when an error is detected, eliminating the need to keep the entire parity check matrix resident in the cache. This significantly reduces the peak usage of cache resources within the control unit, thereby reducing the storage chip area and hardware cost.

[0021] Furthermore, to further optimize the overall performance of the storage device, this application also divides the storage device into a first wafer and a second wafer, which are vertically stacked through a bonding interface, integrating NOR flash memory cells and NAND flash memory cells into one unit. This simultaneously achieves the advantages of fast read parity matrix access and high-density data storage. Moreover, this allows for a larger capacity cache on the first wafer to improve data processing efficiency without increasing the projected area of ​​the storage chip, while enabling the second wafer to focus on high-density data storage, thereby reducing system-level access latency, printed circuit board area, and interconnect power consumption. Attached Figure Description

[0022] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0023] Figure 1 This is a structural block diagram of an embodiment of a three-dimensional integrated storage device according to this application; Figure 2 This is a structural block diagram of another embodiment of a three-dimensional integrated storage device according to this application; Figure 3 This is a flowchart illustrating the data reading operation process. Figure 4 A flowchart illustrating the data writing operation process.

[0024] Icons: 100, first wafer; 200, second wafer; 300, bonding interface; 400, first substrate; 500, second substrate. Detailed Implementation

[0025] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. It should be understood that this application is not limited to the exemplary embodiments described herein.

[0026] In this document, relational terms such as first and second are used only to distinguish one entity or operation from another entity or operation, without necessarily requiring or implying any such actual relationship or order between these entities or operations.

[0027] To facilitate understanding of the technical solutions provided in this application, some concepts will be introduced below.

[0028] 1. Or non-flash memory Also known as NOR Flash, it is a type of non-volatile memory that reads data randomly in bytes or words (similar to SRAM, Static Random Access Memory). It is characterized by fast read speeds, slow write speeds, slow erase speeds, and relatively small capacities (commonly 1Mb to 1Gb).

[0029] 2. Unlike non-flash memory Also known as NAND Flash, it is a type of non-volatile memory that reads and writes pages and erases blocks. It features high density, low cost, and fast write / erase, but reads are not random (requiring whole pages). It's important to note that NAND Flash memory's physical structure naturally generates bit errors when subjected to write / erase operations, charge leakage, and inter-cell interference, resulting in a relatively high raw bit error rate. Therefore, error correction controllers are almost essential mechanisms to ensure the integrity of data in NAND Flash memory cells.

[0030] 3. Key interface 300 The bonding interface 300 refers to the contact surface after two wafers are bonded. Typically, the bonding interface 300 is implemented using methods such as hybrid bonding, direct bonding (e.g., silicon fusion bonding, anodic bonding), metal hot pressing bonding, eutectic bonding, glass paste bonding, and adhesive bonding. In this application, the bonding interface 300 is an electrical connection layer formed between the first wafer 100 and the second wafer 200 using bonding technology, enabling data, control, and clock signal transmission between the two wafers. Vertical stacking is a structural method in which the first wafer 100 and the second wafer 200 are aligned vertically and bonded together, resulting in a physical stacked relationship between the two wafers.

[0031] In existing NAND flash memory cells, error correction techniques based on parity-check matrices are typically used to ensure data reliability. In practice, this error correction function is performed by a dedicated error correction controller. To decode and correct data read from the NAND flash memory cell, this controller needs to store a large parity-check matrix.

[0032] In existing implementations, this parity check matrix is ​​not generated temporarily, but is embedded in a dedicated read-only memory (ROM) within the error correction controller during the chip manufacturing process. When the memory chip powers on and begins operation, to meet the requirements of high-speed, low-latency random access, the error correction controller loads the entire parity check matrix embedded in the ROM into a high-speed on-chip buffer, also located within the controller, and keeps it resident there throughout the entire operation to respond to data calls during the decoding process.

[0033] It's important to note that in existing error correction controller architectures, read-only memory (ROM) is physically an integral part of the controller and possesses non-volatility. However, its contents cannot or are difficult to modify after manufacturing because conventional ROMs are unwriteable once completed, and the parity check matrix is ​​defined as a fixed hardware parameter area, deeply coupled with the decoding logic of the error correction controller. Its address mapping and read timing are essentially fixed and hard-coded. Although some ROMs (such as EPROMs) are now physically erasable and rewritable with technological advancements, erasing and rewriting these limited-write-capability ROMs requires specific command sequences and high voltages. Power outages during this process can lead to data corruption, posing a significant risk and making the process inconvenient. Therefore, even when using ROMs with limited write capabilities to store the parity check matrix in existing error correction controller architectures, replacing or upgrading the parity check matrix still requires modifying the hardware circuitry or using a dedicated programmer. This is not only cumbersome but also prone to damaging the parity check matrix. If the parity check matrix is ​​damaged, the error correction controller will be unable to perform effective error correction. Therefore, virtually no manufacturer is willing to take this risk. Consequently, even if read-only memory with limited write capabilities is used to store the parity check matrix, no interface or mechanism for online upgrades will be reserved. In other words, in existing solutions, the read-only memory is physically part of the error correction controller, and the contents of the parity check matrix stored on it cannot or are difficult to change after it leaves the factory.

[0034] Therefore, based on the above analysis, it can be seen that because the read-only memory of existing error correction controllers is physically unwritable or difficult to rewrite, the parity check matrix is ​​essentially fixed from the moment the memory chip leaves the factory. However, the physical characteristics of NAND flash cells change significantly with increasing lifespan; for example, the bit error rate rises sharply after more erase / write cycles. A fixed, non-upgradeable parity check matrix cannot switch different error correction strategies based on whether the NAND flash cells are in the early or late stages of their lifespan, resulting in a mismatch between error correction performance and the actual needs of flash memory—the so-called rigid error correction strategy. Furthermore, permanently occupying valuable static random access memory resources with the entire parity check matrix proportionally and drastically increases the memory chip area and manufacturing cost. In area- and power-sensitive embedded applications, this resource occupation may even become unacceptable.

[0035] To address the aforementioned technical problems, this application provides a three-dimensional integrated storage device and a data error correction processing method. By physically separating the parity check matrix from the error correction controller and storing them in a non-flash memory cell, the device can undergo firmware upgrades based on the lifecycle of the non-flash memory cell, avoiding a rigid error correction strategy. Simultaneously, the parity check matrix is ​​only read when error correction is needed and no longer resides in the cache, thereby reducing cache resource consumption and decreasing the area and cost of the chip constituting the three-dimensional integrated storage device. Furthermore, the first wafer 100 and the second wafer 200 are vertically stacked through a bonding interface 300, thus combining the advantages of fast parity check matrix reading and high-density data storage, while reducing access latency and interconnect power consumption.

[0036] After introducing the basic principles of this application, various non-limiting embodiments of this application will be described in detail below with reference to the accompanying drawings. Unless otherwise specified, the various embodiments and features described below can be combined with each other.

[0037] Please see Figure 1 The three-dimensional integrated storage device includes: a first wafer 100, which integrates NAND flash memory cells and a control unit; the NAND flash memory cells are used to store a parity check matrix, and the control unit includes an error correction controller and a buffer; and a second wafer 200, which integrates NAND flash memory cells. The first wafer 100 and the second wafer 200 are vertically stacked and electrically connected via a bonding interface 300. The error correction controller is configured to: perform error detection on the raw data read into the buffer from the NAND flash memory cells by the control unit via the bonding interface 300; if an error is detected, read the parity check matrix from the NAND flash memory cells and use the read parity check matrix to correct the original data, obtaining corrected data.

[0038] It should be noted that during the data reading process of this 3D integrated storage device, the control unit first reads the raw data from the NAND flash memory cell of the second wafer 200 through the bonding interface 300 and stores the raw data in the buffer inside the control unit. Subsequently, the error correction controller checks the raw data in the buffer for errors. If the error detection result shows that the raw data contains errors, the error correction controller will read the pre-stored check matrix from the NOR flash memory cell of the first wafer 100 and use the check matrix to correct the raw data, finally obtaining the corrected data. If the error detection result shows that the raw data does not contain errors, no error correction operation is required, and the raw data can be directly used as the output result.

[0039] To enable those skilled in the art to better understand this application, the principles of each unit in this three-dimensional integrated storage device will be explained below: First, the second wafer 200 is the data storage core of this three-dimensional integrated storage device. It is manufactured using optimized storage technology, resulting in higher storage density and lower unit bit cost for its NAND flash memory cells, thus enabling large-capacity data storage. During read operations, the raw data stored in the NAND flash memory cells is transferred to the control unit of the first wafer 100 via the bonding interface 300.

[0040] Next, the bonding interface 300 provides an electrical connection channel between the first wafer 100 and the second wafer 200. The control unit reads raw data from the NAND flash memory cells of the second wafer 200 through the bonding interface 300; the error-corrected data obtained by the error correction controller can also be written back to the NAND flash memory cells through the bonding interface 300. By vertically stacking the bonding interfaces 300, the physical distance between the first wafer 100 and the second wafer 200 is greatly reduced, significantly lowering data transmission latency and power consumption. Simultaneously, the vertical stacking structure improves integration and reduces package area.

[0041] For example, the bonding interface 300 can be implemented using a hybrid bonding process, i.e., the bonding interface 300 is a hybrid bonding interface. The bonding interface 300 of the hybrid bonding process includes metal-metal connection (electrical path) and dielectric-dielectric bonding (mechanical strength / insulation). It should be noted that the hybrid bonding interface can realize high-density, short-pitch vertical interconnection between the first wafer 100 and the second wafer 200, thereby effectively reducing data transmission latency and interconnect power consumption, while eliminating the need for underfill or bump processes, which is beneficial for reducing the overall package thickness and improving integration. The implementation of the hybrid bonding interface may specifically include: firstly, preparing a dielectric layer (such as silicon dioxide) and copper metal pads on the surfaces of the first wafer 100 and the second wafer 200 respectively, making the surfaces extremely flat through chemical mechanical polishing, then aligning and bonding the two wafers, pre-bonding at room temperature, and then annealing at a higher temperature to melt-bond the dielectric layers and interdiffusion-connect the copper pads, forming a vertical interconnection interface that is both insulating and conductive.

[0042] Finally, the first wafer 100 is the core of the control and parameter storage of this three-dimensional integrated storage device, and it is also an important feature that distinguishes this application from existing solutions. The first wafer 100 provides non-volatile storage of the parity check matrix through NOR flash memory cells, and implements data reading, error detection, and error correction operations on the second wafer 200 through the control unit. As an independent physical layer, the first wafer 100 can be manufactured using optimized logic processes, enabling its control unit to have higher operating efficiency and lower power consumption. Simultaneously, the NOR flash memory cells provide fast random access capabilities, ensuring the reading speed of the parity check matrix.

[0043] Specifically, the OR / NOR flash memory cells integrated on the first wafer 100 are used to store the parity check matrix. The parity check matrix is ​​the set of parameters required for error correction decoding and is invoked by the error correction controller during data error correction. The OR / NOR flash memory cells are non-volatile and have fast random access capabilities, allowing the parity check matrix to be stored long-term and quickly accessed when needed. It also supports updates via firmware upgrades, thus enabling configurability of the error correction strategy. Since the parity check matrix is ​​relatively fixed configuration data with an extremely low update frequency, storing it in OR / NOR flash memory cells eliminates the need for frequent erasure and rewriting, thereby avoiding the erasure and wear issues that might arise from storing such data in AND / NOR flash memory cells.

[0044] It should be noted that during error correction, the parity check matrix needs to be accessed frequently and randomly. This is why, in existing technologies, the parity check matrix is ​​stored in read-only memory (ROM) within the error correction controller. After the memory device is powered on, the error correction controller loads the entire parity check matrix into the on-chip buffer and keeps it resident to meet the high-speed random access requirements. Typically, the parity check matrix stored within existing error correction controllers cannot support data updates and requires hardware modifications. While some types of ROM support limited write capabilities, they are significantly limited compared to NOR flash memory in terms of update convenience, write cycles, and online upgrade support. This application chooses NOR flash memory to store the parity check matrix. On the one hand, it utilizes the nanosecond-level random access capability of NOR flash memory to ensure that the error correction controller can quickly obtain the parity check matrix data when needed; on the other hand, it utilizes the more convenient online update capability of NOR flash memory to provide flexible support for firmware upgrades of the parity check matrix.

[0045] The first wafer 100 also integrates a control unit, which specifically includes two components: an error correction controller and a buffer. The control unit is mainly responsible for managing the data flow and error correction process, specifically including reading raw data from the NAND flash memory cells of the second wafer 200 through the bonding interface 300, storing the raw data into the buffer, and starting the error correction controller to perform error detection and correction operations.

[0046] The error correction controller is primarily responsible for the following operations: detecting errors in the raw data read from the NAND flash memory cells by the control unit via the bonding interface 300, determining if bit errors exist in the raw data; if errors are found, the error correction controller reads the parity check matrix from the NAND flash memory cells and uses the read parity check matrix to correct the raw data, obtaining the corrected data. Since the parity check matrix is ​​stored in the erasable NAND flash memory cells, the error correction controller can call parity check matrices with different correction strengths according to different lifecycle stages of the NAND flash memory cells, achieving an adaptive error correction strategy. Furthermore, because the parity check matrix is ​​only read when errors are detected, it does not need to reside in the cache, thus reducing cache resource consumption.

[0047] The buffer is used to temporarily store the raw data read by the control unit from the NAND flash memory cells of the second wafer 200 through the bonding interface 300, for access by the error correction controller during error detection and correction operations. It should be noted that, unlike existing technologies where the entire parity check matrix resides in the buffer, the buffer in this application only needs to store the currently processed raw data and parity check matrix fragments loaded on demand during error correction, significantly reducing the peak resource consumption of the buffer.

[0048] In summary, based on the principles of each unit of the aforementioned three-dimensional integrated storage device, a complete data reading process is as follows: First, the control unit initiates a read operation, sending a read command to the NAND flash memory cell of the second wafer 200 via the bonding interface 300. Next, the NAND flash memory cell responds to the read command, transmitting its stored raw data to the control unit of the first wafer 100 via the bonding interface 300. Then, the control unit stores the received raw data in a buffer and activates the error correction controller, which checks the raw data in the buffer for errors. If the raw data is error-free, the error correction controller directly outputs the raw data as the corrected data; if the raw data contains errors, it enters the error correction process. The error correction process refers to the error correction controller first reading the parity check matrix from the NAND flash memory cell of the first wafer 100, then using the read parity check matrix to correct the raw data in the buffer, obtaining the corrected data. Finally, this corrected data can be output to an external device or written back to the NAND flash memory cell of the second wafer 200 via the bonding interface 300. Therefore, a complete data reading process has ended.

[0049] In summary, this application addresses the issues of non-upgradable parity check (JCD) matrices and on-chip cache resource consumption in existing technologies by moving the JCD matrix from within the error correction controller to a separate or non-flash memory cell and splitting the storage and processing units onto two vertically stacked wafers. Specifically, the JCD matrix is ​​stored in an erasable or non-flash memory cell, making it possible to upgrade or replace the JCD matrix based on the lifespan of the cell, thus resolving the rigidity of error correction strategies in existing solutions. Furthermore, since the entire JCD matrix no longer needs to reside permanently in the control unit's cache as in existing technologies, but is only read on demand when an error is detected, valuable on-chip cache resources are significantly freed up, effectively reducing the memory chip area and cost.

[0050] Based on the aforementioned scheme, in some implementations of this application, when the error correction controller reads the parity matrix from the NOR flash memory cell, it is configured to read partial data of the parity matrix from the NOR flash memory cell on demand and in blocks according to the current decoding progress.

[0051] Understandably, unlike existing technologies that resident the parity check matrix in the on-chip cache, this application reads the parity check matrix from the NOR flash memory cell only when an error is detected. Furthermore, this implementation reads the parity check matrix in blocks as needed, avoiding loading the entire parity check matrix into the cache at once. Thus, the cache only needs to hold the currently processed block, rather than the entire parity check matrix, significantly reducing the cache resource capacity requirements in the control unit. Compared to existing solutions that resident the entire parity check matrix in the cache, this implementation significantly reduces peak cache resource usage while ensuring error correction capabilities, thereby reducing memory chip area and cost.

[0052] It should be noted that in existing methods, the parity check matrix is ​​embedded within the error correction controller, resulting in extremely low read latency. Therefore, current designs tend to load the entire parity check matrix into the cache at once for simplicity. This implementation, however, moves the parity check matrix to a NOR flash memory cell on the first wafer 100. This NOR flash memory cell supports byte-level random addressing, allowing for on-demand reading of any segment. Since the NOR flash memory cell itself has nanosecond-level random read speeds, and block reading is only performed after an error is detected, the additional latency introduced by on-demand, block reading is extremely low, and its impact on overall read performance is negligible.

[0053] Based on the aforementioned scheme, in some implementations of this application, the non-flash memory cell is further used to store at least two sets of parity check matrices with different error correction intensities, and the at least two sets of parity check matrices with different error correction intensities correspond to different lifecycle stages of the non-flash memory cell. When the error correction controller reads the parity check matrix from the non-flash memory cell, it is configured to: identify the current lifecycle stage of the non-flash memory cell, and select the parity check matrix with the corresponding error correction intensity from the non-flash memory cell according to the identified lifecycle stage.

[0054] Understandably, this implementation pre-stores multiple sets of parity-check matrices with different error correction intensities and dynamically selects which to use based on the lifecycle stage of the non-flash memory cells, thereby matching the error correction capability with the actual state of the non-flash memory cells. This approach enables dynamic adaptation of the error correction strategy to the actual state of the non-flash memory cells while ensuring data integrity, thus optimizing the performance and power consumption of the storage device throughout its entire lifecycle.

[0055] For example, in some implementations of this application, the lifecycle phase includes a new disk phase or a lifecycle end phase; wherein, the error correction intensity of the parity check matrix selected for reading by the error correction controller at the lifecycle end phase is higher than the error correction intensity of the parity check matrix selected for reading at the new disk phase.

[0056] Understandably, the "new disk lifespan" refers to the initial stage of use for non-flash memory cells, during which fewer erase / write cycles occur and the bit error rate is low. Therefore, a lower-strength parity check matrix can be selected during this period to reduce computational overhead and power consumption. Conversely, the "end-of-life" stage refers to the stage nearing the end of the non-flash memory cell's lifespan, during which more erase / write cycles occur and the bit error rate increases significantly. Therefore, a higher-strength parity check matrix can be selected during the end-of-life stage to ensure effective data error correction even with the increased bit error rate.

[0057] Based on the aforementioned scheme, in some implementations of this application, the OR non-flash memory cell is also used to store at least two sets of parity check matrices with different bit rates. When the error correction controller reads the parity check matrix from the OR non-flash memory cell, it is configured to: identify the current bit error rate state of the OR non-flash memory cell, and select the parity check matrix from the OR non-flash memory cell that matches the bit error rate state.

[0058] Here, the bit rate refers to the ratio of valid data bits to total bits in the parity check matrix (PCM). PCMs with different bit rates have different error correction capabilities and redundant data overhead. In actual operation, the error correction controller first identifies the current bit error rate (BER) state of the NOR / NAND flash memory cells, such as a low BER or a high BER. Then, based on the identification result, the error correction controller selects a PCM from the NOR / NAND flash memory cells that matches the current BER state and uses this PCM to correct the original data. When the BER of the NOR / NAND flash memory cells is low, a PCM with a higher bit rate and less redundancy can be selected, thereby reducing the storage space and read bandwidth occupied by the PCM. When the BER of the NOR / NAND flash memory cells is high, a PCM with a lower bit rate and more redundancy can be selected to provide stronger error correction capabilities. Thus, this implementation can optimize the resource utilization efficiency of the storage device under different operating states while ensuring data reliability.

[0059] Based on the aforementioned scheme, in some implementations of this application, the non-flash cell may also be used to update the parity matrix it stores through firmware upgrades.

[0060] First, it should be noted that, as mentioned above, the read-only memory in the existing solution is physically part of the error correction controller, and the contents of the verification matrix stored on it are difficult or inconvenient to change after leaving the factory.

[0061] In this application, the parity check matrix is ​​stored in a NOR (non-flash memory) cell of the first wafer 100. This NOR cell is designed as an independent, configurable storage area, rather than a fixed hardware parameter area deeply coupled with the error correction controller logic. Its address mapping and read timing are uniformly managed by the control unit and do not depend on the fixed logic inside the error correction controller. Therefore, during an upgrade, only the new parity check matrix needs to be written to the designated area of ​​the NOR cell via a firmware package. The control unit will automatically call the error correction controller to read the new parity check matrix from the updated address during subsequent reads. The entire process does not require modification of the hardware circuitry or the use of a dedicated programmer; it can be completed through a conventional firmware upgrade process, making the operation convenient and the risks controllable.

[0062] In other words, since NOR flash cells support electrical erase and write operations, when it is necessary to optimize error correction performance or adapt to different types of NOR flash cells, a new parity matrix can be written to the NOR flash cells through a firmware upgrade, replacing the original parity matrix. This allows the parity matrix to be updated without modifying the hardware design, making it easy for the storage device to continuously optimize its error correction strategy during use.

[0063] Based on the aforementioned scheme, in some implementations of this application, the bonding interface 300 includes a data bus, a control bus, and a clock signal line.

[0064] The data bus is used to transmit raw data and error-corrected data between the first wafer 100 and the second wafer 200. The control bus is used to transmit read commands, write commands, and address information issued by the control unit to the non-flash memory cells. The clock signal line is used to provide a synchronization clock, ensuring that the transmission of data and control signals between the first wafer 100 and the second wafer 200 is performed in a unified timing sequence, avoiding data errors caused by timing deviations. This separate design of the data bus, control bus, and clock signal line avoids mutual interference between signals, ensuring the reliability and efficiency of communication between the two wafers.

[0065] Based on the aforementioned scheme, in some implementations of this application, the parity check matrix is ​​the parity check matrix of the LDPC code, and the error correction controller is an LDPC decoder.

[0066] LDPC codes (Low Density Parity Check Codes) are linear block codes based on sparse parity-check matrices. Their decoding algorithm approximates maximum likelihood decoding performance by iteratively propagating confidence information. LDPC codes offer error correction performance close to the Shannon limit, making them particularly suitable for high error rate scenarios. Especially at the end of the lifespan of non-flash memory cells and when the bit error rate increases significantly, LDPC codes provide stronger error correction capabilities than traditional error-correcting codes.

[0067] Based on the aforementioned scheme, in some implementations of this application, substrates are further disposed on the outer sides of the first wafer 100 and the second wafer 200 to provide mechanical support for the vertically stacked structure. Specifically, as... Figure 2 As shown, a first substrate 400 is provided on the side of the first wafer 100 away from the second wafer 200, and a second substrate 500 is provided on the side of the second wafer 200 away from the first wafer 100. The two substrates are located on the outermost side of the stacked structure, and each provides physical support and protection for its respective wafer.

[0068] This dual-substrate design allows the two wafers to maintain structural stability during bonding and subsequent packaging, reducing wafer warpage or bonding interface damage caused by stress, which helps improve manufacturing yield and long-term reliability.

[0069] This application also provides a data error correction processing method, applied to the three-dimensional integrated storage device in any of the foregoing implementations. The data error correction processing method includes a data reading operation process and / or a data writing operation process.

[0070] Among them, such as Figure 3As shown, the data reading operation process includes: Step S101: The control unit reads the raw data from the NAND flash memory unit through the bonding interface 300 and stores the raw data in the buffer; Step S102: The control unit controls the error correction controller to check the raw data in the buffer for errors; Step S103: If an error is detected, the control unit controls the error correction controller to read the parity matrix from the NAND flash memory unit and controls the error correction controller to use the read parity matrix to correct the raw data, thereby obtaining the corrected data.

[0071] like Figure 4 As shown, the data writing operation process includes: Step S201: The control unit receives the data to be written and stores the data to be written in the buffer; Step S202: The control unit allocates the storage address of the data to be written in the NAND flash memory cell; Step S203: The control unit controls the error correction controller to read the parity matrix from the NAND flash memory cell and controls the error correction controller to generate a check code for the data to be written using the read parity matrix; Step S204: The control unit sends the data to be written and the check code in the buffer to the NAND flash memory cell for storage through the bonding interface 300.

[0072] It is understandable that this implementation can solve the problems of the check matrix not being able to be upgraded and the excessive consumption of cache resources in the existing solution by storing the check matrix in a non-flash memory unit and using the control unit to uniformly schedule data transfer and error correction operations.

[0073] Specifically, in the data reading operation process, the control unit first reads raw data from the NAND flash memory cell via the bonding interface 300 and stores it in the buffer. Then, the control unit controls the error correction controller to check the raw data in the buffer for errors. If an error is found, the control unit further controls the error correction controller to read the parity check matrix from the NAND flash memory cell and uses this matrix to correct the raw data, thus obtaining the corrected data. If the error detection result shows that the raw data has no errors, no error correction operation is required, and the raw data can be directly used as the output result.

[0074] In addition, during the data writing operation process, the control unit first receives the data to be written, stores it in the buffer, and allocates a storage address. Then, it controls the error correction controller to read the parity matrix from the NOR flash memory cell to generate a check code. Finally, it sends the data to be written and the check code to the NOR flash memory cell for storage.

[0075] In summary, this application achieves flexible configuration and firmware upgrades of the check matrix by moving the check matrix out of the read-only memory inside the error correction controller. At the same time, since the check matrix is ​​called on demand during reading instead of being in a resident cache, the on-chip cache resource occupation can be significantly reduced, thereby effectively reducing chip area and cost.

[0076] It will be apparent to those skilled in the art that this application is not limited to the details of the exemplary embodiments described above, and that this application can be implemented in other specific forms without departing from the spirit or essential characteristics of this application. Therefore, the embodiments should be considered illustrative and non-limiting in all respects, and the scope of this application is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within this application. No reference numerals in the claims should be construed as limiting the scope of the claims.

Claims

1. A three-dimensional integrated storage device, characterized in that, include: A first wafer, the first wafer integrating a NOR flash memory cell and a control unit, the NOR flash memory cell being used to store a parity matrix, the control unit including an error correction controller and a buffer; The second wafer integrates NAND flash memory cells; The first wafer and the second wafer are vertically stacked and electrically connected via a bonding interface; the error correction controller is configured to perform error detection on the raw data read into the cache from the NAND flash memory cell by the control unit via the bonding interface; If an error is detected, the parity check matrix is ​​read from the non-flash memory cell, and the read parity check matrix is ​​used to correct the original data to obtain the corrected data.

2. The three-dimensional integrated storage device according to claim 1, characterized in that, When the error correction controller reads the parity check matrix from the NOR flash memory unit, it is configured to read partial data of the parity check matrix from the NOR flash memory unit on demand and in blocks, according to the current decoding progress.

3. The three-dimensional integrated storage device according to claim 1, characterized in that, The non-flash memory cell is also used to store at least two sets of check matrices with different error correction intensities, the at least two sets of check matrices with different error correction intensities corresponding to different lifecycle stages of the non-flash memory cell; When the error correction controller reads the parity check matrix from the NOR flash memory cell, it is configured to: identify the current lifecycle stage of the NOR flash memory cell, and select the NOR flash memory cell to read the parity check matrix with the corresponding error correction intensity according to the identified lifecycle stage.

4. The three-dimensional integrated storage device according to claim 3, characterized in that, The life cycle phases include the new disk phase or the end of the life cycle; The error correction intensity of the parity check matrix selected for reading at the end of the disk's lifespan by the error correction controller is higher than the error correction intensity of the parity check matrix selected for reading during the new disk period.

5. The three-dimensional integrated storage device according to claim 1, characterized in that, The non-flash memory unit is also used to store at least two sets of parity check matrices with different code rates; When the error correction controller reads the parity check matrix from the NOR flash memory cell, it is configured to: identify the current bit error rate state of the NOR flash memory cell, and select a parity check matrix from the NOR flash memory cell that matches the bit error rate state.

6. The three-dimensional integrated storage device according to claim 1, characterized in that, The non-flash memory unit is also used to update the parity matrix it stores via firmware upgrades.

7. The three-dimensional integrated storage device according to claim 1, characterized in that, The bonding interface includes a data bus, a control bus, and a clock signal line.

8. The three-dimensional integrated storage device according to claim 1, characterized in that, The parity check matrix is ​​an LDPC code parity check matrix, and the error correction controller is an LDPC decoder.

9. The three-dimensional integrated storage device according to claim 1, characterized in that, The first wafer has a first substrate on the side away from the second wafer, and the second wafer has a second substrate on the side away from the first wafer.

10. A data error correction processing method, characterized in that, The data error correction processing method, applied to any one of the three-dimensional integrated storage devices according to claims 1-9, includes a data reading operation process and / or a data writing operation process. The data reading operation process includes: the control unit reads raw data from the NAND flash memory cell through the bonding interface and stores the raw data in the buffer; the control unit controls the error correction controller to check the raw data in the buffer for errors; if an error is detected, the control unit controls the error correction controller to read the parity check matrix from the NOR flash memory cell and controls the error correction controller to use the read parity check matrix to correct the raw data to obtain the corrected data; The data writing operation process includes: the control unit receiving the data to be written and storing the data to be written in the buffer; the control unit allocating a storage address for the data to be written in the NAND flash memory cell; the control unit controlling the error correction controller to read the parity matrix from the NOR flash memory cell and controlling the error correction controller to generate a checksum for the data to be written using the read parity matrix; and the control unit sending the data to be written and the checksum from the buffer to the NAND flash memory cell for storage through the bonding interface.

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