Solid state drive testing method, system, testing device, and program product

Abstract

This application discloses a solid-state drive (SSD) testing method, system, testing equipment, and program product, relating to the field of storage testing technology. The method includes: injecting a controllable error mode into the flash memory physical address of the SSD according to test configuration parameters; wherein the test configuration parameters include error injection parameters; the controllable error mode is used to trigger error correction logic that can correct errors according to the error injection parameters; initiating a read operation to the flash memory physical address, so that the SSD triggers error correction and garbage collection operations in the controllable error mode, simulating a high-stress scenario of data retention effect, and performing performance testing on the SSD. By replacing physical aging with controllable error injection, the high-stress scenario of data retention effect at the end of the SSD's lifespan can be quickly and accurately simulated, without relying on dedicated aging equipment or high-temperature environments, and can ensure stable reproduction of high-stress scenarios to achieve efficient performance testing, which is beneficial to meeting the industrialization needs of rapid iteration of SSDs.

Description

Technical Field

[0001] This application relates to the field of data storage technology, and in particular to a solid-state drive testing method, system, testing equipment, and program product. Background Technology

[0002] Reliability verification of solid-state storage devices (SSDs) is a core aspect of ensuring their stable operation throughout their entire lifecycle. Among these aspects, the evaluation of the data retention effect of NAND flash memory is particularly critical. The data retention effect refers to the gradual leakage of charge within the storage cells over time or due to ambient temperature, leading to increased bit flipping and ECC error correction frequency. This forces the controller to frequently perform garbage collection (GC) operations to move valid data and erase dirty blocks, resulting in significant performance degradation.

[0003] Currently, verification of data retention capabilities mainly relies on multi-dimensional physical aging methods, such as high-temperature accelerated aging tests (placing SSDs in a high-temperature environment for weeks to months to accelerate charge leakage), long-term power-off data retention tests (power-off storage for months after data writing, with periodic power-on verification), or read interference tests combined with different write / erase (P / E) cycles. While this method can partially reflect the degradation trend of storage units, it has significant limitations and is difficult to efficiently verify the performance of solid-state storage devices under high-pressure scenarios at the end of data retention: On the one hand, the test cycle is extremely long and resource-intensive. The physical aging process requires dedicated equipment such as high-temperature test chambers and aging boards, taking anywhere from weeks to months. This not only causes an exponential increase in power, equipment, and maintenance costs but also severely restricts the efficiency of product development iteration, mass production reliability screening, and firmware GC algorithm robustness verification. On the other hand, error distribution is uncontrollable and scenario reproduction is difficult. Traditional testing methods rely on the natural degradation of storage units, which cannot accurately control the density, distribution, and address range of ECC errors within a limited time. This makes it difficult to stably reproduce the complex state of high GC pressure caused by the accumulation of a large number of ECC errors, and thus cannot stably reproduce the actual situation where GC threads are frequently awakened and effective data movement and erasure operations continuously occupy the front-end I / O bandwidth.

[0004] The above content is only used to help understand the technical solution of this application and does not represent an admission that the above content is prior art. Summary of the Invention

[0005] The main purpose of this application is to provide a solid-state drive (SSD) testing method, system, testing equipment, and program product, aiming to solve the technical problems of existing methods that rely on physical aging processes to simulate data retention effects for SSD testing, which have long testing cycles, high resource consumption, uncontrollable error distribution, and difficulty in reproducing high-stress scenarios.

[0006] To achieve the above objectives, this application proposes a solid-state drive (SSD) testing method, comprising: According to the test configuration parameters of the hard drive under test, a controllable error mode is injected into the flash memory physical address of the hard drive under test; wherein, the test configuration parameters include error injection parameters; the controllable error mode is used to trigger error correction logic that can correct errors according to the error injection parameters; A read operation is initiated to the physical address of the flash memory, so that the hard disk under test triggers error correction and garbage collection operations in the controlled error mode to simulate the high-pressure scenario of data retention effect. The performance of the hard drive under test is performed under the high-pressure scenario.

[0007] In one embodiment, the step of injecting a controllable error mode into the flash memory physical address region of the hard disk under test according to the test configuration parameters of the hard disk under test includes: Based on the error injection parameters in the test configuration parameters, the flash physical address of the hard drive under test that needs to be injected with errors is dynamically selected; the error injection parameters include at least one of error quantity, error density distribution, and expected performance degradation threshold. An error injection instruction is generated based on the selected flash memory physical address, and the error injection instruction is sent to the hard disk under test to inject a controllable error mode into the physical address in batches; the error injection instruction is used to instruct the hard disk under test to trigger and execute error correction logic that can correct errors when reading data in the flash memory physical address.

[0008] In one embodiment, the test configuration parameters further include the address range of logical addresses for error injection; the step of injecting a controllable error mode into the flash physical address of the hard disk under test according to the test configuration parameters includes: Obtain the mapping relationship between the physical address and logical address of the flash memory of the hard drive under test; Based on the mapping relationship, determine the flash physical address corresponding to the address range of error injection in the test configuration parameters; Based on the error injection parameters in the test configuration parameters and the flash memory physical address, an error injection instruction is generated; the error injection instruction is used to instruct the hard disk under test to trigger and execute error correction logic that can correct errors when reading data in the flash memory physical address. The error injection command is sent to the hard disk under test to inject a controllable error mode into the flash memory physical address of the hard disk under test.

[0009] In one embodiment, the step of obtaining the mapping relationship between the physical address and logical address of the flash memory of the hard disk under test includes: Send an address query command to the hard drive under test; The system receives the mapping relationship between the physical address and logical address of the flash memory sent by the hard disk under test; the mapping relationship is returned by the hard disk under test in response to the address query command.

[0010] In one embodiment, the step of injecting a controllable error mode into the flash memory physical address of the hard disk under test according to the test configuration parameters of the hard disk under test includes: Based on the test configuration parameters of the hard drive under test, determine the target flash memory physical address that needs error correction; The physical address of the target flash memory is recorded in the static random access memory of the hard disk under test; After the step of initiating a read operation to the physical address of the flash memory, the method further includes: When the flash controller of the hard drive under test reads the target flash physical address, it marks the command status of the entry corresponding to the target flash physical address as failed in the read command completion queue to trigger error correction logic that can correct errors.

[0011] In one embodiment, before the step of injecting a controllable error mode into the flash memory physical address of the hard disk under test according to the test configuration parameters of the hard disk under test, the method further includes: Write all data to the hard drive under test; Based on the full disk data, a test command is sent to the hard drive under test to perform a performance test on the hard drive under test, and the test result is used as a baseline performance indicator.

[0012] In one embodiment, after the step of performing performance testing on the hard drive under the high-pressure scenario, the method further includes: The target performance indicators of the hard drive under test are determined based on the test results under the high-pressure scenario. The performance degradation ratio of the target performance index relative to the baseline performance index is calculated and used as the basis for evaluating the reliability of the hard drive under test.

[0013] Furthermore, to achieve the above objectives, this application also proposes a solid-state drive (SSD) testing system, including a test host and a SSD to be tested, wherein the test host is communicatively connected to the SSD, and the test host includes: An error injection module is used to inject a controllable error mode into the flash memory physical address of the hard drive under test according to the test configuration parameters; wherein, the test configuration parameters include error injection parameters; the controllable error mode is used to trigger error correction logic that can correct errors according to the error injection parameters; The high-pressure simulation module is used to initiate a read operation to the physical address of the flash memory, so that the hard disk under test can trigger error correction and garbage collection operations in the controlled error mode to simulate the high-pressure scenario of data retention effect; The performance testing module is used to perform performance testing on the hard drive under test under the high-pressure scenario.

[0014] In addition, to achieve the above objectives, this application also proposes a testing device, which includes a memory and a controller. The memory stores a computer program, which, when executed by the controller, implements the steps of any of the solid-state drive testing methods described above.

[0015] In addition, to achieve the above objectives, this application also proposes a computer program product, which includes a computer program that, when executed by a processor, implements the steps of any of the solid-state drive testing methods described above.

[0016] In addition, to achieve the above objectives, this application also proposes a computer-readable storage medium storing a computer program that, when executed by a processor, implements the steps of any of the solid-state drive testing methods described above.

[0017] One or more technical solutions proposed in this application have at least the following technical effects: By injecting controllable error modes into the hard drive under test, error correction and garbage collection operations are triggered during read operations, simulating the high-stress scenario of data retention effect. This replaces the lengthy process relying on physical aging, eliminating the need for dedicated aging equipment such as high-temperature test chambers, significantly shortening the test cycle and reducing resource consumption. Simultaneously, controllable error triggering is achieved through test configuration parameters. The controllable error modes injected into the flash memory physical address can precisely trigger error correction logic that can correct errors. Combined with read operations initiated at the corresponding flash memory physical address, this can stably reproduce the high-stress composite state of garbage collection caused by the accumulation of numerous errors during the data retention effect at the end of the solid-state drive's lifespan. This ensures that the high-stress scenario can be stably reproduced based on the test configuration parameters, enabling performance testing of solid-state drives under high-stress conditions. It efficiently verifies the scheduling strategies and performance of solid-state drives at the end of their lifespan, which is beneficial for meeting the industrialization needs of rapid iteration in solid-state drives. Attached Figure Description

[0018] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0019] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 This is one of the schematic diagrams of a solid-state drive testing process provided in the embodiments of this application; Figure 2 A flowchart illustrating the solid-state drive testing method provided in this application embodiment; Figure 3 This is the second schematic diagram of the solid-state drive testing process provided in the embodiments of this application; Figure 4 This is a schematic diagram of the system structure of the solid-state drive testing system provided in the embodiments of this application; Figure 5 This is a schematic diagram of the test equipment involved in the solid-state drive test method in the embodiments of this application.

[0021] The purpose, features, and advantages of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0022] It should be understood that the specific embodiments described herein are merely illustrative of the technical solutions of this application and are not intended to limit this application.

[0023] To better understand the technical solution of this application, a detailed description will be provided below in conjunction with the accompanying drawings and specific implementation methods.

[0024] In performance testing of solid-state drives (SSDs) (or solid-state storage devices), simulating the combined state of high GC pressure caused by a large number of CEE errors during the data retention effect at the end of an SSD's lifespan requires relying on the physical aging process of specific aging devices. This approach suffers from drawbacks such as long testing cycles, high resource consumption, controllable error distribution, and difficulty in reproducing high-pressure scenarios. This limitation makes it difficult to fully verify the scheduling strategies, read / write latency limits, and power consumption performance of SSDs under extreme GC pressure, becoming a bottleneck restricting the improvement of the performance consistency prediction capability throughout the entire lifecycle of storage devices.

[0025] Therefore, this application provides a solid-state drive (SSD) testing method that can break through traditional time and equipment constraints in SSD performance testing. It can efficiently trigger high-pressure scenarios caused by GC pressure surge after a large number of ECC errors, and can reproduce the performance degradation characteristics at the end of the SSD's lifespan in a short period of time, better meeting the industrialization needs of rapid iteration of next-generation high-density storage technology.

[0026] The main technical solution of this application is as follows: By controlling error injection and address locking, error modes that can trigger ECC error correction are injected in batches into preset flash memory addresses. When a read operation is performed on the address region with injected errors, the ECC error correction logic can be systematically activated, thereby simulating the high-pressure scenario caused by garbage collection operation after a large number of errors have accumulated. This breaks through the timing limitations of traditional testing methods and can complete the equivalent simulation of long-term aging effects under normal scenarios in a short time, without relying on specific aging equipment or high-temperature environments, thus building an accelerated aging test system for reliability verification of solid-state storage devices.

[0027] It should be noted that the executing entity in this embodiment can be a computing service device with data processing, network communication, and program execution functions, such as a memory, computer, mobile phone, etc., or an electronic device capable of performing the above functions. In this embodiment, a test host is used as an example, which can be a computer or a mobile phone.

[0028] Specifically, refer to Figure 1 , Figure 1 This paper illustrates a flowchart of a solid-state drive (SSD) testing method provided in an embodiment of this application. In this embodiment, the SSD testing method is applied to a test host. The SSD to be tested is either built into the test host or external to the test host and is communicatively connected to the test host.

[0029] The testing process for solid-state drives is encapsulated as an executable script, which is configured with an input interface. The test host is configured with a graphical user interface, and the input interface of the executable script is set in the graphical user interface of the test host, which is the same as configuring test configuration parameters.

[0030] In actual testing, a private instruction set is constructed using command-line parameters, and the encapsulated execution script is called to execute the corresponding test process. In this embodiment, the test process specifically includes steps S10 to S30: Step S10: According to the test configuration parameters of the hard disk under test, inject a controllable error mode into the flash memory physical address of the hard disk under test; wherein, the test configuration parameters include error injection parameters; the controllable error mode is used to trigger error correction logic that can correct errors according to the error injection parameters; Step S20: Initiate a read operation to the physical address of the flash memory so that the hard disk under test can trigger error correction and garbage collection operations in the controlled error mode to simulate the high-pressure scenario of data retention effect; Step S30: Under the high-pressure scenario, perform a performance test on the hard drive under test.

[0031] First, based on the test configuration parameters of the hard drive under test, a controllable error mode is injected into the flash physical address of the hard drive under test. The test configuration parameters include error injection parameters. Based on the error injection parameters in the test configuration parameters, a controllable error mode is injected into the flash physical address of the solid-state drive. This controllable error mode is used to trigger error correction logic that can correct errors according to the error injection parameters.

[0032] As an example, the error injection parameters include at least the number of errors, which is the number of errors that need to be triggered for ECC correction. The controllability of the number of ECC corrections can be achieved through configurable error injection parameters.

[0033] Then, a read operation is initiated to the physical address of the flash memory of the hard drive under test, causing the hard drive to trigger error correction and garbage collection operations in a controlled error mode, simulating the high-stress scenario of data retention effect of solid-state drives. Finally, under the simulated high-stress scenario, the performance of the hard drive under test is tested to verify its reliability at the end of its lifespan.

[0034] It should be noted that the test configuration parameters can be manually configured or automatically generated. These parameters are used to control the scale of error injection and performance targets. The controllable error mode can be a manually constructed bit error mode that can trigger ECC error correction, such as modifying the ECC checksum or adjusting the threshold voltage distribution. The error correction logic that can correct errors can be the algorithm flow used in ECC verification to detect and repair bit errors, such as the error correction process of BCH code and LDPC code.

[0035] The hard drive under test contains a flash memory controller responsible for flash memory management, ECC error correction, and garbage collection. Its flash memory physical address can be the actual storage cell address in the NAND flash memory of the solid-state drive, such as block number, page number, plane, and channel.

[0036] Furthermore, garbage collection is the process in flash memory where valid data is moved from a block containing invalid data to a new block, and then the original block is erased to free up space. Data retention effect is the process by which charge leakage in flash memory cells over time or due to temperature changes leads to data errors, mostly occurring towards the end of a solid-state drive's lifespan. High-stress scenarios are a complex state where the drive under test experiences frequent GC operations due to numerous ECC errors caused by the data retention effect, resulting in a significant decrease in front-end I / O performance.

[0037] By actively injecting controllable error modes to replace physical aging, the high-stress scenario of solid-state drives' data retention effect at the end of their lifespan can be simulated in a short time, without the need for high-temperature equipment or long waiting times, significantly improving testing efficiency.

[0038] Furthermore, by using configurable error injection parameters, the performance of the hard drive under test can be verified under different error scales, which helps to improve the comprehensiveness of performance testing.

[0039] In this embodiment, by injecting a controllable error mode into the hard drive under test, error correction and garbage collection operations are triggered during read operations, thereby simulating the high-stress scenario of the data retention effect. This replaces the lengthy process relying on physical aging, eliminates the need for dedicated aging equipment such as high-temperature test chambers, significantly shortens the test cycle, and reduces resource consumption. Simultaneously, controllable error triggering is achieved through test configuration parameters. The controllable error mode injected into the flash memory physical address can accurately trigger the error correction logic that can correct errors. Combined with initiating read operations to the corresponding logical address, it can stably reproduce the high-stress composite scenario of error correction and garbage collection caused by the accumulation of a large number of errors in the data retention effect at the end of the solid-state drive's lifespan. This ensures that the high-stress scenario can be stably reproduced based on the test configuration parameters, thereby enabling performance testing of the solid-state drive under high-stress scenarios. It can efficiently verify the scheduling strategy and performance of the solid-state drive at the end of its lifespan, which is beneficial to meeting the industrialization needs of rapid iteration of solid-state drives.

[0040] As an example, the controllable error mode includes at least one of modifying the error correction verification information associated with the data page, marking the degraded state in the page state table of the hard disk under test, and adjusting the threshold voltage distribution of the storage unit, so that the read operation of the hard disk under test triggers error correction and garbage collection operations without generating uncorrectable errors.

[0041] Modifying the error correction verification information associated with data pages includes, but is not limited to, tampering with ECC checksums so that the ECC decoder detects errors during read operations; marking a degraded status in the page status table can be done by the hard drive under test marking the corresponding page as "retry required" or "low reliability," triggering the ECC error correction process; adjusting the threshold voltage distribution of storage cells can be done by changing the threshold voltage of flash memory cells, causing their read values ​​to deviate from normal values, triggering ECC error correction; uncorrectable errors refer to errors that ECC cannot repair, which will lead to data read failure.

[0042] In one embodiment, the controllable error mode can be implemented as follows: Selectively modify the error correction and verification information associated with the data page, for example, change the ECC checksum of a certain page from 0x1234 to 0x5678. When reading the page, the ECC decoder detects the error and starts the error correction process; at the same time, the page is marked as "degraded" in the page status table of the solid-state drive. After the hard drive under test identifies the page, the block in which it is located is marked as pending reclamation, triggering the GC operation.

[0043] In one embodiment, the controllable error mode is implemented at the protocol layer by modifying the command status in the read command completion queue. Based on this, step S10 may include steps S101~S102: Step S101: Determine the target flash memory physical address that needs error correction based on the test configuration parameters of the hard drive under test; Step S102: Record the physical address of the target flash memory into the static random access memory of the hard disk under test; After the step of initiating a read operation to the physical address of the flash memory, the method further includes: When the flash memory controller of the hard drive under test reads the target flash memory physical address, it marks the command status of the entry corresponding to the target flash memory physical address as failed in the read command completion queue to trigger error correction logic that can correct errors.

[0044] In the specific implementation of injecting a controllable error mode into the flash physical address of the hard drive under test, firstly, the target flash physical address that needs to be corrected is determined according to the test configuration parameters. Then, the target flash physical address is recorded in the static random access memory (SRAM) of the hard drive under test and marked as the flash physical address that needs to be corrected.

[0045] After initiating a read operation to the physical address of the flash memory of the hard drive under test, the flash memory controller of the hard drive under test matches the read physical address of the flash memory with the target physical address of the flash memory recorded in the static random access memory. When the target physical address of the flash memory that needs to be corrected is read from the static random access memory, the command status of the entry corresponding to the target physical address of the flash memory that needs to be corrected is modified or marked as failed in the read command completion queue, thereby triggering the firmware of the hard drive under test to enter the error correction process, execute the error correction logic that can correct the error, and then trigger the garbage collection operation of the hard drive under test in the controllable error mode, forming a high-pressure GC scenario that can simulate the data preservation effect.

[0046] By modifying the execution result state of the flash physical address read operation command through the link interception mechanism at the protocol layer, on the one hand, it does not require substantial rewriting of the flash physical medium, reducing the wear and tear of the storage unit and ensuring the repeatability and non-destructive nature of the test process; on the other hand, it can stably trigger the firmware's error correction logic, ensuring stable reproduction of high-stress scenarios.

[0047] It should be noted that the target flash memory physical address for error correction can be configured or dynamically selected. Specifically, if the test configuration parameters of the hard drive under test do not include an address range, the target flash memory physical address for error correction can be dynamically selected based on the error injection parameters in the test configuration parameters; if the test configuration parameters of the hard drive under test include an address range, the target flash memory physical address for error correction can be determined based on the configured address range.

[0048] Based on this, in one feasible implementation, the test configuration parameters for the solid-state drive include error injection parameters that need to be injected into the drive under test. These error injection parameters include at least one of the following: error quantity, error density distribution, and expected performance degradation threshold. Therefore, step S10 may include steps S11-S12: Step S11: Dynamically select the flash memory physical address of the hard disk under test that needs to be injected with errors according to the error injection parameters in the test configuration parameters; the error injection parameters include at least one of error quantity, error density distribution and expected performance reduction threshold; Step S12: Generate an error injection instruction based on the selected flash memory physical address, and send the error injection instruction to the hard disk under test to inject a controllable error mode into the physical address in batches; the error injection instruction is used to instruct the hard disk under test to trigger and execute error correction logic that can correct errors when reading data in the flash memory physical address.

[0049] Based on the error injection parameters in the test configuration parameters of the hard drive under test, the flash physical address of the hard drive under test that needs to be injected with errors is dynamically selected. The error injection parameters include at least one of the number of errors, error density distribution, and expected performance reduction threshold. That is, based on at least one of the number of errors, error density distribution, and expected performance reduction threshold of the hard drive under test that needs to be injected with errors, the error injection scale and / or expected performance reduction threshold are determined, and the flash physical address of the hard drive under test that needs to be injected with errors is dynamically selected.

[0050] Furthermore, based on the error injection parameters and the dynamically selected flash memory physical addresses of the hard drive under test that need to be injected with errors, an error injection instruction is generated and sent to the hard drive under test to inject controllable error modes into the selected flash memory physical addresses of the hard drive under test in batches.

[0051] It should be noted that the number of errors, i.e. the number of ECC errors, is the total number of ECC errors that can be triggered by the error modes that need to be injected; the error density distribution can be the distribution of error modes in the physical address of flash memory, such as uniform distribution, concentrated distribution, or alternating distribution by block; the expected performance degradation threshold can be the minimum acceptable proportion of performance degradation.

[0052] It's also important to note that the test host accesses the SSD using logical addresses, which are virtual addresses, such as Logical Block Addresses (LABs). These virtual addresses have a mapping relationship with the physical address regions of the SSD. The selection of flash memory physical addresses can be achieved by selecting logical addresses. For example, a target logical address can be dynamically selected, and an error injection command can be generated based on the selected target logical address and error injection parameters. Alternatively, a target logical address can be dynamically selected, the corresponding flash memory physical address can be determined, and an error injection command can be generated based on the selected target logical address and error injection parameters. The generated error injection command is then sent to the SSD under test to inject a controllable error mode into the flash memory physical address corresponding to the selected target logical address. The target logical address can be a set or list of LBA addresses to be injected with errors.

[0053] By dynamically selecting flash memory physical addresses and injecting errors in batches, the density and distribution of injected errors can be adjusted according to testing needs, simulating the degradation characteristics of data retention at different stages.

[0054] As an example, the physical address of the flash memory where the error is injected can be dynamically selected or configured, while the injection of a controllable error mode is achieved through logical addresses. Based on this, if the test configuration parameters include the address range of logical addresses to be injected with errors, step S10 may further include steps S13-S16: Step S13: Obtain the mapping relationship between the physical address region and the logical address of the hard disk under test; Step S14: Based on the mapping relationship, determine the flash physical address corresponding to the address range of error injection in the test configuration parameters; Step S15: Generate an error injection instruction based on the error injection parameters in the test configuration parameters and the flash memory physical address; the error injection instruction is used to instruct the hard disk under test to trigger and execute error correction logic that can correct errors when reading data in the flash memory physical address; Step S16: Send the error injection instruction to the hard disk under test to inject a controllable error mode into the flash memory physical address of the hard disk under test.

[0055] The mapping relationship between the physical address and logical address of the flash memory of the hard drive under test is obtained. Based on the mapping relationship, the physical address of the flash memory corresponding to the address range of the logical address in the test configuration parameters is determined. Then, an error injection instruction is generated based on the physical address of the flash memory and the error injection parameters. The error injection instruction is used to instruct the hard drive under test to trigger and execute error correction logic when reading data within the physical address of the flash memory corresponding to the configured address range, thereby triggering the execution of the error correction logic during the read operation.

[0056] Furthermore, based on the mapping relationship between flash physical addresses and logical addresses, the generated error injection instructions are sent to the hard drive under test, thereby injecting controllable error modes into the flash physical addresses corresponding to the configured address range in batches.

[0057] The address range configured in the test configuration parameters is the range of physical flash memory addresses that need to be injected with errors, such as block 0 to block 100. This address range is represented by logical addresses. The error injection instruction is used to trigger and execute error correction logic that can correct errors when the hard drive under test reads data in the physical flash memory address that needs error correction.

[0058] It is understandable that a read operation to a flash physical address can also be initiated based on the mapping relationship between logical addresses and flash physical addresses, by using the target logical address to initiate a read operation to the corresponding flash physical address.

[0059] In one embodiment, the test configuration parameters include at least one of error injection parameters and error injection address ranges. Based on this, step S10 may include the following steps: The target logical address is dynamically selected based on the test configuration parameters, or the target logical address is determined based on the address range in the configuration parameters. Obtain the mapping relationship between the physical address region and the logical address of the hard disk under test, and determine the flash memory physical address corresponding to the target logical address based on the mapping relationship; Based on the flash memory physical address and the error injection parameters, an error injection instruction is generated; The error injection instruction is sent to the hard disk under test to inject a controllable error mode into the flash physical address corresponding to the target logical address in batches; the error injection instruction is used to instruct the hard disk under test to trigger error correction logic that can correct errors when reading data in the flash physical address corresponding to the target logical address.

[0060] In one embodiment, the generated error injection instruction is used to instruct the flash memory controller of the hard disk under test to record the target flash physical address that needs to be corrected into the static random access memory of the hard disk under test, and when the target flash physical address is read, modify or mark the command status of the entry corresponding to the target flash physical address as failed in the read command completion queue, so as to trigger the error correction logic that can correct errors.

[0061] The specific triggering method for the error correction logic is as follows: A read command is issued to the physical address of the flash memory of the hard drive under test. Upon receiving the read command, the flash memory controller of the hard drive under test performs the read operation on the physical address. When the target physical address requiring error correction is encountered, the command status of the entry corresponding to the target physical address in the read command completion queue (CQ) is modified or marked as failed. When the flash memory controller firmware queries the CQ and finds the failed read entry, it determines that a data read anomaly has occurred at the corresponding target physical address, thus triggering the ECC error correction process to attempt data repair.

[0062] By combining error injection instructions with mapping relationships, precise access to flash memory physical addresses is achieved, ensuring that errors are injected into designated storage areas. This allows control over the scale and distribution of error triggers, enabling accurate simulation and stable reproduction of high-stress scenarios.

[0063] In one embodiment, the mapping relationship between the physical address and logical address of the flash memory of the hard disk under test is obtained by querying the address query instruction. Therefore, step S13 may also include steps S131 to S132: Step S131: Send an address query command to the hard drive under test; Step S132: Receive the mapping relationship between the physical address and logical address of the flash memory sent by the hard disk under test; the mapping relationship is returned by the hard disk under test in response to the address query instruction.

[0064] The system sends an address query command to the hard drive under test and receives the mapping relationship between the flash memory physical address and logical address from the hard drive under test. This mapping relationship is returned by the hard drive under test in response to the address query command from the test host. The address query command may contain a list of logical addresses that the test host requests to query.

[0065] It should be noted that the address lookup instruction can be the Get_lba_to_faa command in the private instruction set. The mapping relationship is the correspondence between the logical address LBA and the flash physical address FAA. For example, LBA 0x1000 corresponds to FAA0x00001234.

[0066] For example, the address lookup command sent by the test host to the hard drive under test is the Get_lba_to_faa command. This command contains a list of LBAs for the target logical address (e.g., 0x1000, 0x2000, 0x3000). After receiving the command, the hard drive under test queries the mapping table in the FTL (Flash Translation Layer) and returns the corresponding list of FAAs for the flash physical addresses (e.g., 0x00001234, 0x00005678, 0x00009ABC). The test host receives and stores the mapping relationship between the LBA list and the FAA list for subsequent error injection.

[0067] In one embodiment, before injecting a controllable error mode into the hard drive under test, a performance test is performed on the hard drive under test as a baseline performance indicator. Therefore, steps S01-S02 may be included before step S10: Step S01: Write all data to the hard drive under test; Step S02: Based on the full disk data, send a test command to the hard drive under test to perform a performance test on the hard drive under test, and obtain the test result as a baseline performance indicator.

[0068] Write all data to the hard drive under test. Based on the written data, send test commands to the hard drive under test to perform performance testing. The test results are used as baseline performance indicators.

[0069] The full disk data can be test data that fills all available space on the solid-state storage device, such as data in all 0, all 1, or random mode. The baseline performance metric is the normal performance value of the solid-state storage device before the error injection.

[0070] For example, write all zeros to the hard drive under test to ensure that the flash memory space of the hard drive under test is fully occupied; then perform a random read test on the hard drive under test and record the performance index of the hard drive under test at this time as the baseline performance index.

[0071] Accordingly, after performing performance tests on the hard drive under high-pressure scenarios, the target performance indicators of the hard drive under test under high-pressure scenarios are determined based on the test results, thereby obtaining the basis for reliability assessment of the hard drive under test. Following step S30, steps S301-S302 may also be included: Step S301: Determine the target performance index of the hard drive under test based on the test results under the high-pressure scenario; Step S302: Calculate the performance degradation ratio of the target performance index relative to the baseline performance index, as the basis for evaluating the reliability of the hard drive under test.

[0072] Based on the test results under high-stress scenarios, the target performance index of the hard drive under test is determined, and the performance degradation ratio of the target performance index relative to the baseline performance index is calculated as the basis for evaluating the reliability of the hard drive under test.

[0073] For example, the performance degradation ratio of the target performance index relative to the baseline performance index is obtained by calculating (baseline performance index - target performance index) / baseline performance index × 100%.

[0074] Reliability assessment can be done by comparing the performance degradation rate with the expected performance reduction threshold to determine whether the reliability of the hard drive under test meets the requirements. For example, if the target performance metric under high stress is 35,000 IOPS (baseline is 50,000 IOPS), the performance degradation rate is calculated as (50,000-35,000) / 50,000×100%=30%. If the expected performance reduction threshold is 30%, the hard drive under test is deemed to meet the reliability requirements, and the test passes.

[0075] In one embodiment, reference is made to Figure 3 The solid-state drive (SSD) testing process, as shown, begins by initializing the state of the SSD under test after the test starts. All data is written to the disk, and the initial FIO read performance is used as a baseline performance indicator to record the performance benchmark of the SSD under normal, stress-free conditions. Subsequently, a private instruction set is generated based on the user-input configuration parameters to obtain the physical address regions corresponding to the logical addresses. After determining the physical address regions where errors need to be injected, error modes that can trigger error correction are injected into each flash memory physical address region.

[0076] Next, a read operation is initiated into the physical address region to read data from the flash memory's physical address region. This triggers the error correction process of the hard drive under test, induces the ECC error correction mechanism of the solid-state storage device, and prompts it to perform garbage collection (GC) operations, thereby constructing a high-pressure operating scenario simulating the end of the data retention effect in a short period of time. By obtaining the flash memory address FAA and private instruction set corresponding to multiple logical address LBAs, ECC errors are injected into each logical address FAA. ECC error correction is triggered by reading the corresponding logical address LBA, and then the FIO read performance under high GC pressure is tested.

[0077] Finally, the target performance metrics under high-stress scenarios are tested and compared with the previously recorded baseline metrics. If the target performance metric is greater than or equal to the baseline performance metric, the reliability test of the hard drive under test is considered passed, indicating that the firmware under test can still maintain sufficient performance stability under high-stress scenarios; otherwise, the test is considered a failure and the test is completed.

[0078] It should be noted that FIO read performance refers to key metrics of a solid-state drive under read load, measured through specific testing tools and other methods, such as IOPS (read operations per second), bandwidth (MiB / s), and latency.

[0079] By calculating the performance degradation ratio, the test results are transformed into quantifiable reliability metrics, making it easier to compare the GC performance of different firmware versions.

[0080] Understandably, the testing process for solid-state drives (SSDs) is encapsulated as an executable script. This script has standardized input and output interfaces. The input interface is used to configure test parameters, while the output interface is used to output test results. Specifically, based on the test configuration parameters, the executable script is invoked via command-line arguments, specifying the number and distribution density of ECC errors to be triggered. The script then executes the corresponding test logic based on these parameters. During test execution, test logs are generated in real time and synchronously output through the output interface, enabling visual monitoring of the testing process. After the test is completed, the test results are analyzed based on the test logs, and a structured test report is generated and output through the output interface.

[0081] In this embodiment, error correction is triggered by actively injecting controllable error modes, simulating high-stress scenarios of data retention effect. This replaces traditional physical aging, compressing the data retention effect test, which originally required weeks to months, into a short period. This enables rapid simulation and immediate testing of high-stress GC conditions at the end of device lifespan, eliminating the need for high-temperature equipment or long waiting times, thus improving testing efficiency and reducing costs. Furthermore, configurable parameters allow for parameterized control of the number, density, and distribution of triggered errors, achieving accurate reproduction of high-stress scenarios and eliminating the randomness of physical aging. The same test scenario can be repeated an unlimited number of times, providing a standardized testing platform for firmware GC algorithm optimization and wear leveling strategy improvement for SSDs. This significantly improves the R&D iteration efficiency of storage devices and meets the needs of rapid verification for next-generation high-density storage technologies.

[0082] Furthermore, by dynamically adjusting the number, density, and distribution of errors based on user configuration parameters, it can efficiently test whether GC performance meets requirements under high-pressure scenarios. Users can set the number, density distribution, and address range of errors as needed, enabling flexible selection of test modes and effectively improving the maintainability and execution efficiency of solid-state storage device testing. Moreover, it can directly construct extreme working conditions (such as concentrated errors at specific addresses) that are difficult to achieve with traditional testing methods, systematically verifying the robustness of firmware under extreme conditions.

[0083] It should be noted that the above examples are only for understanding this application and do not constitute a limitation on the solid-state drive testing method of this application. Any simple modifications based on this technical concept are within the protection scope of this application.

[0084] This application also provides a solid-state drive testing system, for reference... Figure 4The system includes a test host and at least one hard drive under test (SDV). The SDV is a solid-state drive (SSD) or a solid-state storage device. The SDV is either built into the test host or external to it. The test host is communicatively connected to the SDV and interacts with its controller to implement the SSD testing methods described in the above embodiments. Figure 4 As shown, the test host includes: Error injection module 10 is used to inject a controllable error mode into the flash physical address of the hard disk under test according to the test configuration parameters of the hard disk under test; wherein, the test configuration parameters include error injection parameters; the controllable error mode is used to trigger error correction logic that can correct errors according to the error injection parameters; High-pressure simulation module 20 is used to initiate a read operation to the physical address of the flash memory, so that the hard disk under test can trigger error correction and garbage collection operations in the controlled error mode to simulate the high-pressure scenario of data retention effect; The performance testing module 30 is used to perform performance testing on the hard drive under test under the high-pressure scenario.

[0085] In one embodiment, the error injection module 10 is further configured to: Based on the error injection parameters in the test configuration parameters, the flash physical address of the hard drive under test that needs to be injected with errors is dynamically selected; the error injection parameters include at least one of error quantity, error density distribution, and expected performance degradation threshold. An error injection instruction is generated based on the selected flash memory physical address, and the error injection instruction is sent to the hard disk under test to inject a controllable error mode into the physical address in batches; the error injection instruction is used to instruct the hard disk under test to trigger and execute error correction logic that can correct errors when reading data in the flash memory physical address.

[0086] In one embodiment, the test configuration parameters further include the address range of the logical address for error injection; the error injection module 10 is further configured to: Obtain the mapping relationship between the physical address and logical address of the flash memory of the hard drive under test; Based on the mapping relationship, determine the flash physical address corresponding to the address range of error injection in the test configuration parameters; Based on the error injection parameters in the test configuration parameters and the flash memory physical address, an error injection instruction is generated; the error injection instruction is used to instruct the hard disk under test to trigger and execute error correction logic that can correct errors when reading data in the flash memory physical address. The error injection command is sent to the hard disk under test to inject a controllable error mode into the flash memory physical address of the hard disk under test.

[0087] In one embodiment, the error injection module 10 is further configured to: Send an address query command to the hard drive under test; The system receives the mapping relationship between physical address regions and logical addresses sent by the hard disk under test; the mapping relationship is returned by the hard disk under test in response to the address query command.

[0088] In one embodiment, the error injection module 10 is further configured to: Based on the test configuration parameters of the hard drive under test, determine the target flash memory physical address that needs error correction; The physical address of the target flash memory is recorded in the static random access memory of the hard disk under test; After the step of initiating a read operation to the physical address of the flash memory, the method further includes: When the flash memory controller of the hard drive under test reads the target flash memory physical address, it marks the command status of the entry corresponding to the target flash memory physical address as failed in the read command completion queue to trigger error correction logic that can correct errors.

[0089] In one embodiment, the test host further includes an initial test module, used for: Write all data to the hard drive under test; Based on the full disk data, a test command is sent to the hard drive under test to perform a performance test on the hard drive under test, and the test result is used as a baseline performance indicator.

[0090] In one embodiment, the test host further includes a performance evaluation module for: The target performance indicators of the hard drive under test are determined based on the test results under the high-pressure scenario. The performance degradation ratio of the target performance index relative to the baseline performance index is calculated and used as the basis for evaluating the reliability of the hard drive under test.

[0091] The solid-state drive (SSD) testing system provided in this application can implement the SSD testing method in the above embodiments. It solves the technical problems of existing methods that rely on physical aging processes to simulate data retention effects for SSD testing, which suffer from long testing cycles, high resource consumption, uncontrollable error distribution, and difficulty in reproducing high-stress scenarios. Compared with the prior art, the beneficial effects of the SSD testing system provided in this application are the same as those of the SSD testing method provided in the above embodiments, and other technical features of the SSD testing system are the same as those disclosed in the methods of the above embodiments, and will not be repeated here.

[0092] The following is for reference. Figure 5This is a schematic diagram of a test device 500 provided in an embodiment of this application. The test device 500 includes a controller 510 and a memory 520. The controller 510 and the memory 520 are electrically connected directly or indirectly to realize data transmission or interaction. For example, these components can be electrically connected to each other through one or more communication buses or signal lines.

[0093] The memory 520 stores a computer program that can be executed by the controller 510. The controller is used to read / write the data or computer program stored in the memory 520 and perform corresponding functions. For example, when the computer program stored in the memory 520 is executed by the controller 510, the solid-state drive testing method disclosed in the above embodiments can be implemented.

[0094] It should be understood that, Figure 5 The structure shown is only a schematic diagram of the test equipment 500. The test equipment 500 may also include a ratio Figure 5 The more or fewer components shown, or having the same Figure 5 The different configurations shown. Figure 5 The components shown can be implemented using hardware, software, or a combination thereof.

[0095] This application provides a computer-readable storage medium having computer-readable program instructions (i.e., a computer program) stored thereon, which are used to execute the solid-state drive testing method in the above embodiments.

[0096] The computer-readable storage medium provided in this application may be, for example, a USB flash drive, but is not limited to, electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices, or any combination thereof. More specific examples of computer-readable storage media may include, but are not limited to: electrical connections with one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof. In this embodiment, the computer-readable storage medium may be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, system, or device. The program code contained on the computer-readable storage medium may be transmitted using any suitable medium, including but not limited to: wires, optical cables, RF (Radio Frequency), etc., or any suitable combination thereof.

[0097] The aforementioned computer-readable storage medium may be contained within a memory or may exist independently without being assembled into a memory.

[0098] The aforementioned computer-readable storage medium carries one or more programs, which, when executed by the memory, cause the test device to: According to the test configuration parameters of the hard drive under test, a controllable error mode is injected into the flash memory physical address of the hard drive under test; wherein, the test configuration parameters include error injection parameters; the controllable error mode is used to trigger error correction logic that can correct errors according to the error injection parameters; A read operation is initiated to the physical address of the flash memory, so that the hard disk under test triggers error correction and garbage collection operations in the controlled error mode to simulate the high-pressure scenario of data retention effect. The performance of the hard drive under test is performed under the high-pressure scenario.

[0099] Computer program code for performing the operations of this application can be written in one or more programming languages ​​or a combination thereof, including object-oriented programming languages ​​such as Java, Smalltalk, and C++, and conventional procedural programming languages ​​such as the "C" language or similar programming languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving remote computers, the remote computer can be connected to the user's computer via any type of network—including a Local Area Network (LAN) or a Wide Area Network (WAN)—or can be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0100] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0101] The modules described in the embodiments of this application can be implemented in software or hardware. The names of the modules do not necessarily limit the functionality of the unit itself.

[0102] The readable storage medium provided in this application is a computer-readable storage medium that stores computer-readable program instructions (i.e., a computer program) for executing the above-described solid-state drive testing method. This solves the technical problem that the error correction capability of error correction schemes based on static retry tables is insufficient in extreme error scenarios. Compared with the prior art, the beneficial effects of the computer-readable storage medium provided in this application are the same as those of the solid-state drive testing method provided in the above embodiments, and will not be repeated here.

[0103] This application also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of the solid-state drive testing method described above.

[0104] The computer program product provided in this application can solve the technical problem that the error correction capability of the static retry table-based error correction scheme is insufficient under extreme error scenarios. Compared with the prior art, the beneficial effects of the computer program product provided in this application are the same as those of the solid-state drive testing method provided in the above embodiments, and will not be repeated here.

[0105] The above are only some embodiments of this application and do not limit the patent scope of this application. All equivalent structural transformations made under the technical concept of this application and using the contents of the specification and drawings of this application, or direct / indirect applications in other related technical fields, are included in the patent protection scope of this application.

Claims

1. A solid-state drive testing method, characterized in that, The testing method includes: According to the test configuration parameters of the hard drive under test, a controllable error mode is injected into the flash memory physical address of the hard drive under test; wherein, the test configuration parameters include error injection parameters; the controllable error mode is used to trigger error correction logic that can correct errors according to the error injection parameters; A read operation is initiated to the physical address of the flash memory, so that the hard disk under test triggers error correction and garbage collection operations in the controlled error mode to simulate the high-pressure scenario of data retention effect. The performance of the hard drive under test is performed under the high-pressure scenario.

2. The solid-state drive testing method as described in claim 1, characterized in that, The step of injecting a controllable error mode into the flash memory physical address region of the hard drive under test according to the test configuration parameters of the hard drive under test includes: Based on the error injection parameters in the test configuration parameters, the flash physical address of the hard drive under test that needs to be injected with errors is dynamically selected; the error injection parameters include at least one of error quantity, error density distribution, and expected performance degradation threshold. An error injection instruction is generated based on the selected flash memory physical address, and the error injection instruction is sent to the hard disk under test to inject a controllable error mode into the physical address in batches; the error injection instruction is used to instruct the hard disk under test to trigger and execute error correction logic that can correct errors when reading data in the flash memory physical address.

3. The solid-state drive testing method as described in claim 1, characterized in that, The test configuration parameters also include the address range of logical addresses for error injection; the step of injecting a controllable error mode into the flash physical address of the hard disk under test according to the test configuration parameters includes: Obtain the mapping relationship between the physical address and logical address of the flash memory of the hard drive under test; Based on the mapping relationship, determine the flash physical address corresponding to the address range of error injection in the test configuration parameters; Based on the error injection parameters in the test configuration parameters and the flash memory physical address, an error injection instruction is generated; the error injection instruction is used to instruct the hard disk under test to trigger and execute error correction logic that can correct errors when reading data in the flash memory physical address. The error injection command is sent to the hard disk under test to inject a controllable error mode into the flash memory physical address of the hard disk under test.

4. The solid-state drive testing method as described in claim 3, characterized in that, The step of obtaining the mapping relationship between the physical address and logical address of the flash memory of the hard disk under test includes: Send an address query command to the hard drive under test; The system receives the mapping relationship between the physical address and logical address of the flash memory sent by the hard disk under test; the mapping relationship is returned by the hard disk under test in response to the address query command.

5. The solid-state drive testing method as described in claim 1, characterized in that, The step of injecting a controllable error mode into the flash memory physical address of the hard drive under test according to the test configuration parameters of the hard drive under test includes: Based on the test configuration parameters of the hard drive under test, determine the target flash memory physical address that needs error correction; The physical address of the target flash memory is recorded in the static random access memory of the hard disk under test; After the step of initiating a read operation to the physical address of the flash memory, the method further includes: When the flash controller of the hard drive under test reads the target flash physical address, it marks the command status of the entry corresponding to the target flash physical address as failed in the read command completion queue to trigger error correction logic that can correct errors.

6. The solid-state drive testing method as described in claim 1, characterized in that, Before the step of injecting a controllable error mode into the flash memory physical address of the hard drive under test according to the test configuration parameters, the method further includes: Write all data to the hard drive under test; Based on the full disk data, a test command is sent to the hard drive under test to perform a performance test on the hard drive under test, and the test result is used as a baseline performance indicator.

7. The solid-state drive testing method as described in claim 6, characterized in that, Following the step of performing performance testing on the hard drive under the high-pressure scenario, the method further includes: The target performance indicators of the hard drive under test are determined based on the test results under the high-pressure scenario. The performance degradation ratio of the target performance index relative to the baseline performance index is calculated and used as the basis for evaluating the reliability of the hard drive under test.

8. A solid-state drive testing system, characterized in that, The test host includes a test host and a solid-state drive (SSD) to be tested, wherein the test host is communicatively connected to the SSD, and the test host includes: An error injection module is used to inject a controllable error mode into the flash memory physical address of the hard drive under test according to the test configuration parameters; wherein, the test configuration parameters include error injection parameters; the controllable error mode is used to trigger error correction logic that can correct errors according to the error injection parameters; The high-pressure simulation module is used to initiate a read operation to the physical address of the flash memory, so that the hard disk under test can trigger error correction and garbage collection operations in the controlled error mode to simulate the high-pressure scenario of data retention effect; The performance testing module is used to perform performance testing on the hard drive under test under the high-pressure scenario.

9. A testing device, characterized in that, The testing device includes a memory and a controller. The memory stores a computer program, which, when executed by the controller, implements the steps of the solid-state drive testing method according to any one of claims 1 to 7.

10. A computer program product, characterized in that, The computer program product includes a computer program that, when executed by a processor, implements the steps of the solid-state drive testing method as described in any one of claims 1 to 7.

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