Laser chip, method for manufacturing laser chip, and optical module

Abstract

The laser chip, its fabrication method, and optical module disclosed herein relate to the field of optical element technology and facilitate the quality assurance of the connection between the emitting region and the modulation region. The laser chip includes an emitting region and a modulation region, with the modulation region located at the light-emitting end of the emitting region. The fabrication method of the laser chip includes: dry etching of the laser chip epitaxial layer based on a dielectric film to remove the laser chip epitaxial layer within the modulation region, with the dry etching stopping at the first active layer or the first buffer layer; oxidizing the side surface of the dry-etched laser chip epitaxial layer using oxygen-containing plasma, and oxidizing the side surface of the electron blocking layer using oxygen-containing plasma to form an aluminum oxide layer on the side surface of the electron blocking layer; etching the first active layer or the first buffer layer exposed in the modulation region using an etchant, wherein the etching rate of the etchant on the aluminum oxide layer is less than the etching rate of the etchant on the first active layer and the first buffer layer; and forming a modulation epitaxial layer above the first buffer layer or substrate within the modulation region.

Description

Technical Field

[0001] This disclosure relates to the field of optical fiber communication technology, and in particular to a laser chip, a method for fabricating the laser chip, and an optical module. Background Technology

[0002] With the development of new business and application models such as cloud computing, mobile internet, and video, advancements in optical communication technology have become increasingly important. In optical communication technology, the optical module, as one of the key components in optical communication equipment, enables photoelectric signal conversion; and in the development of optical communication technology, the data transmission rate of optical modules is required to continuously improve.

[0003] Laser chips are one of the core components of optical modules for generating optical signals. Laser chips can be made from electro-absorption modulated lasers (EMLs), etc. Summary of the Invention

[0004] Some embodiments provide a laser chip, a method for fabricating the laser chip, and an optical module, which facilitates ensuring the docking quality between the light-emitting region and the modulation region.

[0005] Some embodiments provide a method for fabricating a laser chip, the laser chip including a light-emitting region and a modulation region, the modulation region being located at the light-emitting end of the light-emitting region; the method includes: A laser chip epitaxial layer is grown on a substrate. The laser chip epitaxial layer includes a first buffer layer, a first active layer and an electron blocking layer from bottom to top. The electron blocking layer is an InAlAs layer. An initial dielectric film is deposited above the epitaxial layer of the laser chip; The initial dielectric film is patterned to form a dielectric film that covers the light-emitting area and exposes the modulation area. Based on the dielectric film, the epitaxial layer of the laser chip is dry-etched to remove the epitaxial layer of the laser chip in the modulation region. The dry etching stops at the first active layer or the first buffer layer. The side surface of the laser chip epitaxial layer is oxidized by dry etching using oxygen-containing plasma, and the side edge of the electron blocking layer is oxidized by oxygen-containing plasma to form an aluminum oxide layer on the side surface of the electron blocking layer. The first active layer or the first buffer layer exposed by the modulation region is etched with an etchant to remove the first active layer or the first buffer layer, wherein the etching rate of the etchant on the alumina layer is less than the etching rate of the etchant on the first active layer and the first buffer layer. A modulation epitaxial layer is formed above the first buffer layer or substrate within the modulation region; Remove the dielectric film and grow a waveguide layer over the light-emitting region and the modulation region.

[0006] One of the above technical solutions has the following advantages or beneficial effects: An electron blocking layer is set above the first active layer. During the operation of the laser chip, electrons move upward from the substrate to the first active layer. If too many electrons are injected into the first active layer, the excess electrons will continue to move upward, resulting in electron waste. The electron blocking layer can block the electrons, keeping them in the first active layer for light emission, thus ensuring the optical power of the light-emitting area of ​​the laser chip. After dry etching and before wet etching, oxygen-containing plasma is used to oxidize the side of the epitaxial layer of the laser chip after dry etching. The aluminum in the electron blocking layer is oxidized, forming a dense aluminum oxide layer on the surface of the sidewall of the electron blocking layer. The aluminum oxide layer has excellent chemical stability, and the etching rate of the etching solution on the aluminum oxide layer is slow, which can effectively resist the erosion of the wet etching solution. It can protect the side of the electron blocking layer from excessive corrosion during the wet etching process, thereby significantly reducing the risk of drilling and ensuring the docking quality between the light-emitting area and the modulation area.

[0007] In some embodiments, a method for fabricating a laser chip is provided in which, when dry etching stops at the first active layer, the remaining thickness of the first active layer is less than 50% of the thickness of the first active layer before dry etching. When dry etching stops at the first buffer layer, the remaining thickness of the first buffer layer is less than 50% of the thickness of the first buffer layer before dry etching.

[0008] Another technical solution in the above-mentioned technical solution has the following advantages or beneficial effects: Dry etching to the first active layer makes the remaining thickness of the first active layer less than 50% of the thickness of the first active layer before dry etching, which facilitates shortening the time required for wet etching of the first active layer. Since the alumina layer on the sidewall surface of the electron blocking layer has a limited time to resist the etchant, by controlling the thickness of the remaining first active layer, the time required for wet etching of the first active layer can be adapted to the time required for the alumina layer on the sidewall surface of the electron blocking layer to resist the etchant, thus facilitating the alumina layer on the sidewall surface of the electron blocking layer to resist the etchant during wet etching. Correspondingly, dry etching to the first buffer layer makes the remaining thickness of the first buffer layer less than 50% of the thickness of the first buffer layer before dry etching, which facilitates shortening the time required for wet etching of the first buffer layer. Since the aluminum oxide layer on the sidewall surface of the electron blocking layer has a limited time to resist the etchant, by controlling the thickness of the remaining first buffer layer, the time taken for wet etching of the first buffer layer can be adapted to the time taken for the aluminum oxide layer on the sidewall surface of the electron blocking layer to resist the etchant, so that the aluminum oxide layer on the sidewall surface of the electron blocking layer can resist the etchant during the wet etching process.

[0009] In some embodiments, a method for fabricating a laser chip includes using an etchant to etch the first active layer or the first buffer layer exposed in the modulation region to remove the first active layer or the first buffer layer, comprising: After etching the first active layer exposed by the modulation region with an etchant for a first preset time, the etching of the first active layer with the etchant is stopped, and the first preset time is less than the time required for the alumina layer to be completely etched. The side surface of the laser chip epitaxial layer is oxidized again using oxygen-containing plasma, thereby oxidizing the side edge of the electron blocking layer again with oxygen-containing plasma. The first active layer exposed by the modulation region is etched again using an etchant to remove the first active layer.

[0010] Another technical solution mentioned above has the following advantages or beneficial effects: By using a stepwise wet etching process for the first active layer, and controlling the etching time of the first active layer in a single step to not exceed the time required for complete etching of the alumina layer, it can be ensured that the sidewalls of the electron blocking layer are always protected by the alumina layer throughout the entire wet etching process. This prevents the etchant from prematurely eroding the electron blocking layer, thereby avoiding damage to the structural performance of the laser chip. Furthermore, by re-oxidizing the sides of the epitaxial layer of the laser chip, especially the sides of the electron blocking layer, with oxygen-containing plasma, the alumina layer consumed in the first etching step can be replenished, providing sufficient protection for subsequent second etching. This ensures that the first active layer can be completely removed while maintaining the protective effect of the alumina layer. Ultimately, while meeting the etching requirements, the stability of the laser chip structure and device performance are guaranteed, and the fabrication yield is improved.

[0011] In some embodiments, a method for fabricating a laser chip includes using an etchant to etch the first active layer or the first buffer layer exposed in the modulation region to remove the first active layer or the first buffer layer, comprising: After a second preset time for etching the first buffer layer exposed by the etchant in the modulation area, the etching of the first buffer layer with the etchant is stopped. The second preset time is less than the time required for the alumina layer to be completely etched. The side surface of the laser chip epitaxial layer is oxidized again using oxygen-containing plasma, thereby oxidizing the side edge of the electron blocking layer again with oxygen-containing plasma. The first buffer layer exposed by the modulation region is etched again using an etchant to remove the first buffer layer.

[0012] Another technical solution mentioned above has the following advantages or beneficial effects: By using a stepwise wet etching process to etch the first buffer layer, and controlling the etching time of the first buffer layer in a single step to be within the time required for the complete etching of the alumina layer, it is ensured that the alumina layer always retains sufficient thickness to protect the sidewalls of the electron blocking layer during the etching process. This prevents the etchant from prematurely penetrating the alumina layer and eroding the electron blocking layer, thus preventing damage to the structure and performance of the laser chip. Furthermore, by re-oxidizing the sides of the epitaxial layer of the laser chip, especially the electron blocking layer, with oxygen-containing plasma, the alumina layer consumed in the first etching step can be replenished, providing sufficient protection for subsequent etching. This ensures that the first buffer layer can be completely removed while maintaining the protective effect of the alumina on the electron blocking layer. Ultimately, while meeting the process requirements for removing the first buffer layer, the stability of the overall structure of the laser chip and the performance of the final device are guaranteed, improving the fabrication yield.

[0013] In some embodiments, a method for fabricating a laser chip is provided, in which the dry etching stops at the first active layer, the etching solution is sulfuric acid-hydrogen peroxide-aqueous solution, phosphoric acid-hydrogen peroxide-aqueous solution, or citric acid-hydrogen peroxide-aqueous solution; When dry etching stops at the first buffer layer, the etching solution is a mixture of phosphoric acid and hydrochloric acid, a mixture of phosphoric acid and hydrobromic acid, an aqueous solution of hydrochloric acid, or an aqueous solution of hydrobromic acid.

[0014] Another technical solution mentioned above has the following advantages or beneficial effects: the etching solution can be selected from sulfuric acid-hydrogen peroxide-aqueous solution, phosphoric acid-hydrogen peroxide-aqueous solution, citric acid-hydrogen peroxide-aqueous solution, phosphoric acid-hydrochloric acid mixture, phosphoric acid-hydrobromic acid mixture, hydrochloric acid aqueous solution, or hydrobromic acid aqueous solution. By matching the corresponding components of the etching solution to different etching stop positions, different etching depth requirements can be specifically adapted. While ensuring the efficiency of wet etching in removing the target material, it avoids erroneous etching of non-target layer structures. This ensures the cleanliness of the removed target material, meets the precision requirements of the process preparation, and further reduces the risk of damage to the core functional layer of the laser chip. It adapts to the fabrication process requirements of laser chips with different structures, improving process adaptability and fabrication yield. It facilitates controllable etching rates for the first active layer and the first buffer layer during wet etching, avoids excessive consumption of the alumina layer while etching the first active layer and the first buffer layer, stably maintains the protective effect of the alumina layer on the electron blocking layer, reduces the impact of process parameter fluctuations on the fabrication effect, and further ensures the stability of the etching process and the yield of the finished device.

[0015] In some embodiments, a method for fabricating a laser chip is provided in which, when dry etching stops at the first active layer, the remaining thickness of the first active layer is less than or equal to 30% of the thickness of the first active layer before dry etching. When dry etching stops at the first buffer layer, the remaining thickness of the first buffer layer is less than or equal to 30% of the thickness of the first buffer layer before dry etching.

[0016] Another technical solution mentioned above has the following advantages or beneficial effects: By controlling the thickness of the remaining layer to be etched to no more than 30% of the original thickness, it is easier to shorten the time used for wet etching of the first active layer, and the process load of dry etching and subsequent wet etching can be balanced. Since the alumina layer on the sidewall surface of the electron blocking layer has a limited time to resist the etchant, by controlling the thickness of the remaining first active layer and the first buffer layer, the time used for wet etching of the first active layer can be adapted to the time for the alumina layer on the sidewall surface of the electron blocking layer to resist the etchant, so that the alumina layer on the sidewall surface of the electron blocking layer can resist the etchant during the wet etching process.

[0017] In some embodiments, a method for fabricating a laser chip is provided, wherein a modulation epitaxial layer is formed above a first buffer layer or substrate within the modulation region, comprising: A second buffer layer, a second active layer, and a P-InP layer are sequentially formed above the first buffer layer or substrate within the modulation region. The bottom of the second active layer is lower than the bottom of the first active layer, and the top of the second active layer is higher than the top of the first active layer.

[0018] Another technical solution mentioned above has the following advantages or beneficial effects: by controlling the bottom of the second active layer to be lower than the bottom of the first active layer and the top of the second active layer to be higher than the top of the first active layer, the overlap between the optical field and the active layer in the modulation region can be increased, thereby improving the modulation efficiency of the laser chip. At the same time, the optical field distribution between the gain region and the modulation region can be reasonably allocated, balancing the gain and modulation performance, reducing optical field crosstalk between different functional regions, and helping to improve the overall output performance and working stability of the laser chip.

[0019] In some embodiments, a method for fabricating a laser chip is provided in which the electron blocking layer is not doped with N-type impurities.

[0020] Another technical solution mentioned above has the following advantages or beneficial effects: the electron blocking layer is not doped with N-type impurities, which can prevent the mutual diffusion of N-type impurities and P-type impurities, prevent the material properties of the quantum well active layer from being destroyed, and thus ensure the radiative recombination efficiency of the active layer. This can improve the output optical power of the laser chip, extend the working life of the device, and at the same time reduce the series resistance of the device, reduce the heat generation during operation, and further improve the overall working stability and reliability of the laser chip.

[0021] In some embodiments, a laser chip is provided, wherein the laser chip is prepared by the method provided in the above embodiments.

[0022] Another technical solution described above has the following advantages or beneficial effects: The laser chip prepared by the method provided in the above embodiments ensures that the side of the electron blocking layer is flush with the side of the first active layer, thus facilitating the connection quality between the light-emitting region and the modulation region. During the operation of the laser chip, electrons move upwards from the substrate to the first active layer. If too many electrons are injected into the first active layer, the excess electrons will continue to move upwards, leading to electron waste. The electron blocking layer can block the electrons, keeping them in the first active layer for light emission, thus ensuring the optical power of the light-emitting region of the laser chip.

[0023] In some embodiments, an optical module is provided, including a laser chip, wherein the laser chip is the laser chip provided in the above embodiments.

[0024] Another technical solution in the above technical solution has the following advantages or beneficial effects: the laser chip in the optical module is the laser chip provided in the above embodiment. Since the side of the electron blocking layer of the laser chip is flush with the side of the first active layer, the docking quality between the light-emitting area and the modulation area is guaranteed. The electron blocking layer can also effectively block excess electrons from overflowing and confine the electrons in the first active layer for light emission, thereby ensuring the output light power of the light-emitting area and thus ensuring the stable light output performance of the entire optical module. Attached Figure Description

[0025] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly introduced below. Obviously, the drawings described below are only drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual flow of the method, the actual timing of the signals, etc. involved in the embodiments of this disclosure.

[0026] Figure 1 This is a schematic diagram of the structure of an optical module access switch according to some embodiments; Figure 2 This is a partial structural diagram of a switch according to some embodiments; Figure 3 This is a structural diagram of an optical module according to some embodiments; Figure 4 An exploded view of an optical module according to some embodiments; Figure 5 This is a partial schematic diagram of a light emitting component according to some embodiments; Figure 6 This is a structural diagram of a laser assembly according to some embodiments; Figure 7This is a structural diagram of a laser chip according to some embodiments; Figure 8A This is a cross-sectional view of a laser chip according to some embodiments; Figure 8B This is a cross-sectional view of another laser chip according to some embodiments; Figure 9A The flowchart of a first laser chip fabrication method according to some embodiments Figure 1 ; Figure 9B The flowchart of a first laser chip fabrication method according to some embodiments Figure 2 ; Figure 10A The flowchart of a second laser chip fabrication method according to some embodiments Figure 1 ; Figure 10B The flowchart of a second laser chip fabrication method according to some embodiments Figure 2 ; Figure 11 A flowchart illustrating a third method for fabricating a laser chip according to some embodiments; Figure 12 This is a flowchart of a fourth method for fabricating a laser chip according to some embodiments.

[0027] Among them, 100-switch, 101-fiber optic cable, 102-PCB circuit board, 103-cage, 104-heat sink, 200-optical module, 201-upper housing, 2011-cover plate, 202-lower housing, 2021-base plate, 2022-lower side plate, 203-electrical interface, 204-optical interface, 300-circuit board, 301-gold fingers, 302-mounting hole, 303-DSP chip, 400-optical emitting component, 400a-laser assembly, 400b-carrier, 40 0c - Laser chip, 410 - Light-emitting region, 420 - Modulation region, 411 - Light-emitting electrode, 421 - Modulation electrode, 401 - Substrate, 402 - First buffer layer, 403 - First active layer, 404 - Electron blocking layer, 405 - Grating layer, 406 - Second buffer layer, 407 - Second active layer, 408 - P-InP layer, 409 - Waveguide layer, 412a - Initial dielectric film, 412 - Dielectric film, 500 - Light receiving component, 600 - Unlocking component, 700 - Light transmission component. Detailed Implementation

[0028] The embodiments of this disclosure will now be described clearly and in detail with reference to the accompanying drawings. However, the described embodiments are merely some, and not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.

[0029] Unless the context otherwise requires, throughout this specification, the term "comprising" is interpreted as open and inclusive, meaning "including, but not limited to"; the terms "first" and "second" should not be construed as indicating or implying relative importance or an upper limit on the number; the term "multiple" means two or more; the term "connection" should be interpreted broadly, for example, "connection" can be a fixed connection, a detachable connection, or an integral part, and can be a direct connection or an indirect connection through an intermediate medium; the use of the terms "applies to" or "is configured to" implies open and inclusive language, which does not exclude the applicability to or configuration of devices to perform additional tasks or steps; descriptions such as "parallel," "perpendicular," "identical," "consistent," and "aligned" are not limited to absolute mathematical theoretical relationships, but also include acceptable error ranges arising in practice, and differences based on the same design concept but due to manufacturing reasons.

[0030] In optical communication technology, information is loaded onto light to generate optical signals, which are then used to transmit information between information processing devices. Connections are established between these devices via optical transmission equipment. Optical power loss is minimal during transmission through this equipment, allowing for long-distance transmission with relatively low power loss. Light boasts extremely high transmission speeds, and the cost of optical transmission equipment, such as fiber optic cables, is lower than that of electrical transmission equipment like copper wires. Using optical signals to transmit information offers advantages such as long-distance transmission, high speed, and low cost.

[0031] Information processing equipment typically includes switches, servers, optical network units (ONUs), optical distribution networks (ODNs), optical line terminals (OLTs), gateways, routers, mobile phones, computers, tablets, televisions, etc.; optical transmission equipment typically includes optical fibers and optical waveguides. Information processing equipment can recognize and process electrical signals, while optical transmission equipment can transmit optical signals. Therefore, optical modules are needed between the optical transmission equipment and the information processing equipment to perform the conversion between optical and electrical signals.

[0032] In some embodiments, the optical signal input and / or optical signal output of the optical module are connected to an optical fiber, and the electrical signal input and / or electrical signal output of the optical module are connected to a switch; a first optical signal from the optical fiber is transmitted to the optical module, the optical module converts the first optical signal into a first electrical signal, and transmits the first electrical signal to the switch; a second electrical signal from the switch is transmitted to the optical module, the optical module converts the second electrical signal into a second optical signal, and transmits the second optical signal to the optical fiber.

[0033] Information processing equipment connected to optical modules can also be referred to as the host computer for optical modules. In access network transmission scenarios, the host computer for optical modules is usually an ONU, ODN, or OLT; in data center transmission scenarios, the host computer for optical modules is usually a Switch or Server.

[0034] Figure 1 This is a schematic diagram of the structure of an optical module access switch according to some embodiments. For example... Figure 1 As shown, switch 100 has multiple optical module interfaces. Multiple optical modules are inserted into the switch through these interfaces, establishing electrical signal communication between the optical modules and the switch. Optical fiber 101 is connected to the optical modules, establishing optical signal communication between the optical fiber and the optical modules. One end of optical fiber 101 is connected to the optical module, and the other end of optical fiber 101 (…) Figure 1 (not shown in the image) connects to another optical module ( Figure 1 (not shown in the image), another optical module accesses the server ( Figure 1 (not shown in the image) or another switch ( Figure 1 (Not shown in the image).

[0035] In some embodiments, the optical fiber 101 and the optical module 200 are detachably connected; in other embodiments, the optical fiber 101 and the optical module 200 are non-detachably connected.

[0036] The switch 100 is configured to provide data electrical signals to the optical module 200, or receive data electrical signals from the optical module 200, or monitor or control the operating status of the optical module 200.

[0037] In some embodiments, the optical module is a tool for converting optical signals to electrical signals. During the conversion process, the information does not change, but the encoding or decoding method of the information changes.

[0038] Figure 2 This is a partial structural diagram of a switch according to some embodiments. To clearly show the connection relationship between the optical module 200 and the switch 100, Figure 2 Only the structures related to the switch 100 and the optical module 200 are shown. (For example...) Figure 2As shown, in some embodiments, the switch 100 further includes a PCB circuit board 102 disposed in the receiving cavity, and a cage 103 disposed on the surface of the PCB circuit board 102; the optical module 200 is inserted into the cage 103 and fixed by the cage 103.

[0039] In some embodiments, a heat sink 104 is provided on the cage 103 to dissipate heat for the optical module; in some embodiments, the heat sink 104 has protruding structures such as fins to increase the heat dissipation area.

[0040] In some embodiments, an electrical connector is provided inside the cage 103, which is configured to access the electrical interface of the optical module 200.

[0041] In some embodiments, the optical module 200 is inserted into the cage 103 of the switch 100, and the cage 103 fixes the optical module 200. The heat generated by the optical module 200 is conducted to the cage 103 and then diffused through the heat sink 104.

[0042] In some embodiments, the optical module 200 is inserted into the cage 103 of the switch 100, and the electrical interface of the optical module 200 is connected to the electrical connector inside the cage 103, thereby establishing an electrical signal connection between the optical module 200 and the switch 100.

[0043] In some embodiments, the optical interface of the optical module 200 is connected to the optical fiber 101, thereby enabling the optical module 200 to establish an optical signal connection with the optical fiber 101.

[0044] Figure 3 This is a structural diagram of an optical module according to some embodiments. Figure 4 This is an exploded view of an optical module according to some embodiments. Figure 3 and Figure 4 As shown, in some embodiments, the optical module 200 includes a housing. The housing may include an upper housing 201 and a lower housing 202. The upper housing 201 covers the lower housing 202, forming two openings, one of which is an electrical interface and the other is an optical interface. In some embodiments, the housing forms an opening that serves as both an electrical interface and an optical interface.

[0045] In some embodiments, the upper housing 201 and the lower housing 202 are made of metal materials, which is beneficial for achieving electromagnetic shielding and heat dissipation.

[0046] The assembly method of combining the upper housing 201 and the lower housing 202 facilitates the installation of circuit boards 300 and other components into the housing. The upper housing 201 and the lower housing 202 can encapsulate and protect the aforementioned devices.

[0047] In some embodiments, the direction of the connection between the electrical interface 203 and the optical interface 204 may be consistent with or inconsistent with the length direction of the optical module 200. For example, the electrical interface 203 is located at the end of the optical module 200. Figure 3 (At the right end), the optical interface 204 is also located at the end of the optical module 200. Figure 3 (The left end). Of course, the electrical interface 203 is located at the end of the optical module 200, while the optical interface 204 is located on the side of the optical module 200.

[0048] In some embodiments, the lower housing 202 includes a base plate 2021 and two lower side plates 2022 located on both sides of the base plate 2021 and perpendicular to the base plate 2021; the upper housing 201 includes a cover plate 2011, which covers the two lower side plates 2022 of the lower housing 202 to form the aforementioned housing.

[0049] In some embodiments, the lower housing 202 includes a base plate 2021 and two lower side plates 2022 located on both sides of the base plate 2021 and perpendicular to the base plate 2021; the upper housing 201 includes a cover plate 2011 and two upper side plates located on both sides of the cover plate 2011 and perpendicular to the cover plate 2011. The two upper side plates and the two lower side plates 2022 are combined to realize that the upper housing 201 covers the lower housing 202.

[0050] like Figure 3 and Figure 4 As shown, in some embodiments, the optical module includes a circuit board 300 disposed within a housing. The circuit board 300 includes circuit traces, electronic components, and chips, etc. The electronic components and chips are connected according to the circuit design through the circuit traces to realize functions such as power supply, electrical signal transmission, and grounding. Electronic components may include, for example, capacitors, resistors, transistors, and metal-oxide-semiconductor field-effect transistors (MOSFETs). Chips may include microcontroller units (MCUs), laser driver chips, transimpedance amplifiers (TIAs), limiting amplifiers (LAs), clock and data recovery chips (CDRs), or power management chips, etc.

[0051] In some embodiments, the circuit board includes a rigid circuit board, which, due to its relatively rigid material, can also serve a load-bearing function, such as being able to stably support the aforementioned electronic components and chips; the rigid circuit board can also be inserted into an electrical connector in the cage 103 of the switch 100.

[0052] In some embodiments, the circuit board may also include a flexible circuit board, which can be used independently or in conjunction with a rigid circuit board.

[0053] In some embodiments, the circuit board further includes gold fingers 301 formed on its end surface, the gold fingers 301 being composed of a plurality of independent pins.

[0054] In some embodiments, the gold fingers 301 are disposed on a surface on one side of the circuit board 300 (e.g., Figure 4 (as shown on the upper surface); In some embodiments, the gold fingers 301 are disposed on the upper and lower surfaces of the circuit board 300 to provide a greater number of pins, thereby adapting to applications with high pin count requirements.

[0055] In some embodiments, the gold fingers 301 of the circuit board 300 extend from the electrical interface and are inserted into the electrical connector of the switch 100; the circuit board is inserted into the cage 103, and the gold fingers are connected to the electrical connector inside the cage 103. The gold fingers 301 are configured to establish an electrical connection with the switch, enabling electrical connection functions such as power supply, grounding, two-wire synchronous serial (Inter-Integrated Circuit, I2C) signal transmission, and data signal transmission.

[0056] In some embodiments, the optical module 200 further includes an unlocking component 600 located outside its housing. The unlocking component 600 is configured to establish a fixed connection between the optical module 200 and the switch, or to release the fixed connection between the optical module 200 and the switch.

[0057] For example, the unlocking component 600 is located on the outside of the two lower side plates 2022 of the lower housing 202, and includes a locking component that matches the cage 103 of the switch 100. When the optical module 200 is inserted into the cage 103, the locking component of the unlocking component 600 fixes the optical module 200 in the cage 103; when the unlocking component 600 is pulled, the locking component of the unlocking component 600 moves accordingly, thereby changing the connection relationship between the locking component and the switch, so as to release the fixation between the optical module 200 and the switch, thereby allowing the optical module 200 to be pulled out of the cage 103.

[0058] In some embodiments, the optical module includes a light emitting component 400. In some embodiments, the optical module includes a light receiving component 500.

[0059] In some embodiments, at least one of the light emitting component 400 or the light receiving component 500 is located on the side of the circuit board 300 away from the gold fingers.

[0060] In some embodiments, the light emitting component 400 and the light receiving component 500 are physically separated from the circuit board 300, and then electrically connected to the circuit board 300 through corresponding flexible circuit boards or electrical connectors.

[0061] In some embodiments, at least one of the light emitting component or the light receiving component may be directly disposed on the circuit board 300. For example, at least one of the light emitting component or the light receiving component may be disposed on the surface of the circuit board 300 or the side of the circuit board 300.

[0062] In some embodiments, the optical module 200 further includes an optical transmission component 700 disposed within the housing. The optical transmission component 700 is used to connect to an external optical fiber 101 (hereinafter referred to as the external optical fiber) to establish an optical connection between the optical emitting component 400, the optical receiving component 500 and the external optical fiber, so that the optical signal generated by the optical emitting component 400 can be coupled to the external optical fiber, and the optical signal input from the external optical fiber can be coupled to the optical receiving component.

[0063] In some embodiments, the optical transmission component 700 includes an optical fiber adapter and an optical fiber, which may also be referred to as an internal optical fiber relative to an external optical fiber. One end of the optical fiber is connected to the optical fiber adapter, and the other end is connected to the optical transmitting component 400 or the optical receiving component 500. Exemplarily, the optical transmission component 700 includes multiple optical fiber adapters and multiple optical fibers. The optical transmitting component 400 can be connected to one or more optical fiber adapters via multiple optical fibers, and the optical receiving component 500 can be connected to multiple optical fiber adapters via multiple optical fibers. Of course, in this embodiment, the structure of the optical fiber adapter is not limited to one type; it can also be an LC connector, where the optical fiber adapter connects to one optical fiber.

[0064] In some embodiments, the optical transmission component 700 may include two optical fiber adapters and multiple optical fibers, each optical fiber adapter being connected to the optical transmitting component 400 and the optical receiving component 500 via the multiple optical fibers.

[0065] In some embodiments, a mounting hole 302 is provided on the circuit board 300, and the light emitting component 400 is assembled and connected to the mounting hole 302. For example, the light emitting component 400 is embedded in the mounting hole 302.

[0066] In some embodiments, the mounting hole 302 can be a through hole, such that the top of the light emitting component 400 is above the mounting hole 302 and the bottom of the light emitting component 400 is below the mounting hole 302.

[0067] In some embodiments, a DSP chip 303 may be disposed on the front side of the circuit board 300; the DSP chip 303 is used to transmit high-frequency signals to the light emitting component 400, etc. The light emitting component 400 receives the high-frequency signals transmitted by the DSP chip 303 to generate light signals. Two opposing surfaces on the circuit board 300 are the main bearing surfaces of the circuit board 300; one of these surfaces is called the front surface of the circuit board 300, facing the cover plate 2011; the other surface is the back surface of the circuit board 300, facing the base plate 2021. The front and back surfaces of the circuit board 300 are opposing surfaces.

[0068] In some embodiments, the light receiving component 500 is disposed on the back side of the circuit board 300. Of course, in this embodiment, the light receiving component 500 is not limited to being disposed on the back side of the circuit board 300, but may also be disposed on the front side of the circuit board 300.

[0069] In some embodiments, the optical transmission component 700 may include a fiber optic adapter and multiple optical fibers. The optical transmitting component 400 can be optically connected to the fiber optic adapter through a portion of the multiple optical fibers, and the optical receiving component 500 can be optically connected to the fiber optic adapter through a portion of the multiple optical fibers.

[0070] Figure 5 This is a partial schematic diagram of a light emitting component according to some embodiments. Figure 5 The present invention illustrates the structure of a light emitting component, but the structure of the light emitting component in this embodiment is not limited to that described above. Figure 5 The structure shown. (As shown) Figure 5 As shown, in some embodiments, the optical emitting component 400 includes a laser component 400a, which generates an optical signal. The optical signal output by the laser component 400a can be coupled to an optical fiber after passing through a lens or other device, and then transmitted to an optical fiber adapter via the optical fiber.

[0071] In some embodiments, the light emitting component 400 may include a plurality of laser components 400a arranged side by side. Exemplarily, four, eight, or sixteen laser components 400a may be arranged side by side on the emitting base.

[0072] In some embodiments, a lens, such as a collimating lens or a converging lens, may be provided in the output direction of the laser component 400a to converge the optical signal, so as to facilitate the coupling of the optical signal generated by the laser component 400a into the optical fiber.

[0073] Figure 6 This is a structural diagram of a laser assembly according to some embodiments. Figure 6As shown, in some embodiments, the laser assembly 400a includes a carrier 400b and a laser chip 400c. A circuit pattern is formed on the carrier 400b, and the laser chip 400c is disposed on the carrier 400b. The laser chip 400c can be electrically connected to the circuit pattern on the carrier 400b. The circuit pattern on the carrier 400b can be electrically connected to a circuit board 300, so that the laser chip 400c can be electrically connected to the circuit board 300 through the circuit pattern on the carrier 400b. The laser chip 400c is used to generate optical signals. Matching resistors or matching capacitors, etc., can be disposed on the carrier 400b.

[0074] In some embodiments, the laser chip 400c can be a distributed feedback laser (DFB). DFB uses direct modulation to load the signal, which is simple in structure, low in cost, and low in power consumption.

[0075] In some embodiments, the laser chip 400c can employ an EML. The EML is monolithically integrated with a DFB and an electroabsorption modulator. Its bandwidth is primarily limited by its parasitic parameters, rather than its relaxation resonant frequency; therefore, the bandwidth of an EML can be relatively high. In recent years, with the rapid growth of data volume and the increasing demand for network speed upgrades, EMLs have become increasingly popular.

[0076] Figure 7 This is a structural diagram of a laser chip according to some embodiments. Figure 7 A basic EML structure is shown, with the direction of arrow X indicating the optical field transmission direction. (See diagram.) Figure 7 As shown, in some embodiments, the laser chip 400c includes a light-emitting region 410 and a modulation region 420. One end of the light-emitting region 410 is connected to the modulation region 420, and the other end of the light-emitting region 410 is away from the modulation region 420. The modulation region 420 is located at the light-emitting end of the light-emitting region 410. The light-emitting region 410 generates light without carrying a signal, and the modulation region 420 can modulate the light emitted by the light-emitting region 410 to generate an optical signal.

[0077] A light-emitting electrode 411 may be disposed on the top of the light-emitting region 410. The light-emitting electrode 411 is used to load a bias current, thereby providing charge carriers to the first active layer of the light-emitting region 410, so that the light-emitting region 410 generates light. A modulation electrode 421 is disposed on the top of the modulation region 420. The modulation electrode 421 is used to load a modulation signal, thereby providing a modulation current to the modulation region 420, so that the modulation region 420 modulates the light generated by the light-emitting region 410.

[0078] Figure 8A This is a cross-sectional view of a laser chip according to some embodiments. Figure 8B This is a cross-sectional view of another laser chip according to some embodiments. Figure 8A and Figure 8BThe cross-sectional structures of the laser chip along the optical field propagation direction are shown respectively. For example... Figure 8A and Figure 8B As shown, in some embodiments, the laser chip 400c may include a substrate 401. The substrate 401 spans the light-emitting region 410 and the modulation region 420. The substrate 401 may be made of InP material.

[0079] In some embodiments, an N-InGaAsP layer may be disposed between the first buffer layer 402 and the substrate 401. The N-InGaAsP layer can be wet-etched for positioning.

[0080] In some embodiments, the laser chip 400c may include a first buffer layer 402 located above the substrate 401. The first buffer layer 402 may be located in the light-emitting region 410, and the length of the first buffer layer 402 is less than the length of the substrate 401; alternatively, the first buffer layer 402 may span the light-emitting region 410 and the modulation region 420, and the length of the first buffer layer 402 is equal to the length of the substrate 401. The first buffer layer 402 may be an N-InP layer.

[0081] In some embodiments, the laser chip 400c may include a first active layer 403, which is located above the first buffer layer 402. The first active layer 403 may be located in the light-emitting region 410. The first active layer 403 may be made of AlInGaAs or InGaAsP, etc. The first active layer 403 may include a quantum barrier, a quantum well, a quantum barrier, a quantum well, and a quantum barrier stacked sequentially.

[0082] In some embodiments, the laser chip 400c may include an electron blocking layer 404. The electron blocking layer 404 is located in the light-emitting region 410 and is situated above the first active layer 403. The electron blocking layer 404 blocks electrons, causing them to remain in the first active layer 403. During the operation of the laser chip 400c, electrons move upwards from the substrate 401 to the first active layer 403. If too many electrons are injected into the first active layer 403, the excess electrons will continue to move upwards, resulting in electron waste. The electron blocking layer 404 can block the electrons, causing them to remain in the first active layer 403 for light emission. The electron blocking layer 404 may be made of InAlAs. InAlAs is not doped with N-type impurities such as Si.

[0083] In some embodiments, the laser chip 400c may include a grating layer 405. The grating layer 405 is located in the light-emitting region 410 and is situated above the first active layer 403. A P-InGaAsP layer may be formed above the electron blocking layer 404, and the grating layer 405 may be formed using electron beam lithography or holographic lithography of the P-InGaAsP layer.

[0084] In some embodiments, the laser chip 400c may include a second buffer layer 406. The second buffer layer 406 is located in the modulation region 420. The second buffer layer 406 may be disposed above the first buffer layer 402, with its bottom connected to the first buffer layer 402; alternatively, the second buffer layer 406 may be disposed on the side of the first buffer layer 402, with its bottom connected to the substrate 401. The second buffer layer 406 may be an N-InP layer.

[0085] In some embodiments, the laser chip 400c may include a second active layer 407. The second active layer 407 is located in the modulation region 420 and is situated above the second buffer layer 406. The second active layer 407 may be made of AlInGaAs or InGaAsP, etc. The second active layer 407 may include sequentially stacked quantum barriers, quantum wells, quantum barriers, quantum wells, and quantum barriers. Exemplarily, the top of the second active layer 407 is higher than the top of the first active layer 403.

[0086] In some embodiments, the bottom of the second active layer 407 is lower than the bottom of the first active layer 403, and the top of the second active layer 407 is higher than the top of the first active layer 403. This facilitates the high-efficiency coupling of light generated by the first active layer 403 to the second active layer 407.

[0087] In some embodiments, the laser chip 400c may include a P-InP layer 408. The P-InP layer is located in the modulation region 420 and above the second active layer 407.

[0088] In some embodiments, the laser chip 400c may include a waveguide layer 409. The waveguide layer 409 is located above the P-InP layer 408 and the grating layer 405, and may span the light-emitting region 410 and the modulation region 420. The waveguide layer 409 may be formed using P-InP.

[0089] Based on the laser chip of the above embodiments, this disclosure also provides a method for preparing the laser chip provided in the above embodiments. Figure 9A The flowchart of a first laser chip fabrication method according to some embodiments Figure 1 , Figure 9B The flowchart of a first laser chip fabrication method according to some embodiments Figure 2 , Figure 10A The flowchart of a second laser chip fabrication method according to some embodiments Figure 1 , Figure 10B The flowchart of a second laser chip fabrication method according to some embodiments Figure 2 ; Figure 9A and Figure 9BThe image shows a cross-sectional structure corresponding to each step in the fabrication of a laser chip. Figure 10A and Figure 10B The image shows another cross-sectional structure corresponding to each step in the fabrication of a laser chip. For example... Figures 9A-10B As shown in the embodiment of this disclosure, a method for fabricating a laser chip includes: S100: A laser chip epitaxial layer is grown on a substrate. The laser chip epitaxial layer includes a first buffer layer, a first active layer, and an electron blocking layer. The first buffer layer is located below the first active layer, and the first active layer is located below the electron blocking layer.

[0090] In some embodiments, a first buffer layer 402, a first active layer 403, and an electron blocking layer 404 are sequentially grown on a substrate 401. Exemplarily, the first buffer layer 402, the first active layer 403, and the electron blocking layer 404 can be grown on the substrate 401 using metal-organic chemical vapor deposition (MOCVD). A P-InP layer and a P-InGaAsP layer are grown on the electron blocking layer 404, and the P-InGaAsP layer is photolithographically etched to form a grating layer 405.

[0091] In some embodiments, a P-InP layer may be grown above the grating layer 405. This P-InP layer can protect the grating layer 405.

[0092] S200: Deposit an initial dielectric film on top of the epitaxial layer of the laser chip.

[0093] In some embodiments, an initial dielectric film 412a is deposited on the P-InP layer above the grating layer 405, such that the initial dielectric film 412a covers the epitaxial layer of the laser chip. The initial dielectric film 412a may be made of SiO2 or SiN. x It can be formed by deposition of materials such as SiON. The initial dielectric film 412a can protect the epitaxial layer of the laser chip. The thickness of the initial dielectric film 412a can be 50-500 nm, such as 250-500 nm.

[0094] S300: The initial dielectric film is patterned to form a dielectric film that covers the light-emitting area and exposes the modulation area.

[0095] In some embodiments, a dielectric film 412 can be formed by photolithography of an initial dielectric film 412a. The dielectric film 412 covers the top of the light-emitting region 410 to assist in the formation of the epitaxial layer of the light-emitting region 410. Exemplarily, photoresist is coated on the dielectric film 412, exposed and developed, and then the initial dielectric film 412a is etched using the photoresist as a mask to remove the initial dielectric film 412a above the modulation region 420, while retaining the initial dielectric film 412a above the light-emitting region 410, thus forming the dielectric film 412.

[0096] S400: Based on the dielectric film, the epitaxial layer of the laser chip is dry-etched to remove the epitaxial layer of the laser chip in the modulation region. The dry etching stops at the first active layer or the first buffer layer.

[0097] In some embodiments, using the dielectric film 412 as a mask, the epitaxial layer of the laser chip within the modulation region 420 is removed by inductively coupled plasma (ICP) etching. Dry etching can be stopped at the first active layer 403 or the first buffer layer 402. During dry etching, a mixed gas such as Cl2, CH4, and H2 can be used as the etching gas. By precisely controlling the gas flow rate, RF power, and cavity pressure, precise control of the etching depth can be achieved, ensuring that the epitaxial layer of the modulation region 420 is completely removed while protecting the epitaxial layer of the light-emitting region 410 from damage. After dry etching, the modulation region 420 exposes the surface of the first active layer 403 or the first buffer layer 402, making the first active layer 403 or the first buffer layer 402 step-shaped.

[0098] S500: The first active layer or first buffer layer exposed by etching the modulation region using an etchant.

[0099] In some embodiments, the etchant used in wet etching can be a selective etchant, such as sulfuric acid-hydrogen peroxide-aqueous solution, phosphoric acid-hydrogen peroxide-aqueous solution, citric acid-hydrogen peroxide-aqueous solution, phosphoric acid-hydrogen acid mixture, phosphoric acid-hydrobromic acid mixture, hydrochloric acid aqueous solution, or hydrobromic acid aqueous solution. Wet etching exposes the first active layer 403 or the first buffer layer 402 in the modulation region to remove the exposed first active layer 403 or the first buffer layer 402, thereby eliminating the stepped structure of the first active layer 403 or the first buffer layer 402. For example, when dry etching stops at the first active layer 403, the etchant can be a sulfuric acid-hydrogen peroxide-aqueous solution, a phosphoric acid-hydrogen peroxide-aqueous solution, or a citric acid-hydrogen peroxide-aqueous solution, etc., to facilitate selective etching of the first active layer 403; when dry etching stops at the first buffer layer 402, the etchant can be a phosphoric acid-hydrochloric acid mixture, a phosphoric acid-hydrobromic acid mixture, a hydrochloric acid aqueous solution, or a hydrobromic acid aqueous solution, etc., to facilitate selective etching of the first buffer layer 402. By matching the etchant with the corresponding components for different etching stop positions, different etching depth requirements can be specifically adapted. While ensuring the efficiency of wet etching in removing the target material, it avoids erroneous etching of non-target layer structures. This ensures the cleanliness of the removed target material, meets the precision requirements of the process fabrication, and further reduces the risk of damage to the core functional layers of the laser chip. It adapts to the fabrication process requirements of laser chips with different structures, improving process adaptability and fabrication yield.

[0100] In some embodiments, when dry etching stops at the first buffer layer 402, the first buffer layer 402 exposed in the modulation region 420 is removed by wet etching, thereby exposing the surface of the substrate 401 of the modulation region 420. Wet etching has a high selectivity and can precisely remove the first buffer layer 402 exposed in the modulation region 420 without damaging the underlying structure.

[0101] In some embodiments, when dry etching stops at the first active layer 403, wet etching removes the first active layer 403 exposed in the modulation region 420, exposing the surface of the first buffer layer 402 of the modulation region 420. Wet etching has a high selectivity and can precisely remove the first active layer 403 exposed in the modulation region 420 without damaging the underlying first buffer layer 402.

[0102] S600: A modulation epitaxial layer is formed above the first buffer layer or substrate in the modulation region. The modulation epitaxial layer includes a second buffer layer, a second active layer and a P-InP layer. The second buffer layer is located above the first buffer layer or substrate, the second active layer is located above the second buffer layer, and the P-InP layer is located above the second active layer.

[0103] After wet etching removes the first active layer 403 or the first buffer layer 402 exposed within the modulation region 420, the area can be cleaned first, and then a modulation epitaxial layer can be formed above the first buffer layer 402 or the substrate 401. The sides of the modulation epitaxial layer are connected to the sides of the first active layer 403, the electron blocking layer 404, and the grating layer 405 to complete the docking of the light-emitting region 410 and the modulation region 420. A modulation epitaxial layer can be formed above the first buffer layer 402 or the substrate 401 of the modulation region 420 using a selective epitaxial growth process. For example, above the first buffer layer 402 or the substrate 401, a second buffer layer 406, a second active layer 407, and a P-InP layer 408 are sequentially epitaxially grown using MOCVD. The bottom of the second buffer layer 406 is connected to the first buffer layer 402 or the substrate 401, the bottom of the second active layer 407 is connected to the top of the second buffer layer 406, and the bottom of the P-InP layer 408 is connected to the top of the second active layer 407.

[0104] During selective epitaxial growth, parameters such as growth temperature, reaction gas flow rate, and pressure can be controlled to ensure that the modulated epitaxial layer grows only on the exposed modulation region 420 surface, while the dielectric film 412 above the light-emitting region 410 effectively prevents material deposition, thereby achieving regional selective growth.

[0105] S700: Remove the dielectric film above the light-emitting region and grow a waveguide layer above the light-emitting region and the modulation region.

[0106] After the modulation epitaxial layer is grown, the dielectric film 412 above the light-emitting region 410 can be removed using a wet or dry etching process, exposing the surfaces of both the light-emitting region 410 and the modulation region 420. Subsequently, a waveguide layer 409 is epitaxially grown above the light-emitting region 410 and the modulation region 420. The waveguide layer 409 can cover the grating layer 405 and the P-InP layer 408. The waveguide layer 409 can be a P-InP layer.

[0107] When the first active layer 403 or the first buffer layer 402 exposed in the modulation region 420 is removed by wet etching, the etchant also erodes the sides of the electron blocking layer 404 and the grating layer 405. The etchant has a lower etching rate on the grating layer 405, resulting in less lateral damage. However, the etchant has a relatively high etching rate on the electron blocking layer 404, which easily leads to drilling and inward shrinkage of the electron blocking layer 404's edges, forming a stepped sidewall structure. This deteriorates the interface morphology between the light-emitting region 410 and the modulation region 420, thus worsening the performance of the laser chip 400c. Therefore, an etchant formulation with a lower etching rate on the electron blocking layer 404 is typically selected during wet etching. However, etchant formulations with a lower etching rate on the electron blocking layer 404 are relatively complex, time-consuming to prepare, and highly sensitive to process windows, making them unsuitable for large-scale mass production.

[0108] To address the aforementioned issues, before wet etching removes the first active layer or the first buffer layer, the laser chip fabrication method provided in this embodiment further includes: using oxygen-containing plasma to perform surface treatment on the laser chip epitaxial layer after dry etching; the oxygen-containing plasma oxidizes the side surface of the electron blocking layer, and the oxidized side surface of the electron blocking layer blocks the lateral erosion of the electron blocking layer by the etching solution.

[0109] Figure 11 This is a flowchart illustrating a third method for fabricating a laser chip according to some embodiments. Figure 12 This is a flowchart illustrating a fourth method for fabricating a laser chip according to some embodiments. Figure 11 and Figure 12 As shown, between steps S400 and S500, the laser chip fabrication method provided in this embodiment of the disclosure further includes: S450: The side surface of the laser chip epitaxial layer is oxidized by oxygen-containing plasma after dry etching, and the side surface of the electron blocking layer is oxidized by oxygen-containing plasma to form an aluminum oxide layer on the side surface of the electron blocking layer.

[0110] In some embodiments, when the side surfaces of the laser chip epitaxial layer are oxidized by dry etching using oxygen-containing plasma, the oxygen-containing plasma oxidizes the surface of the laser chip epitaxial layer, including the side surfaces of the laser chip epitaxial layer and the surface of the first active layer 403 or the first buffer layer 402 exposed within the modulation region 420. Oxidation of the laser chip epitaxial layer surface by oxygen-containing plasma can generate a series of oxides, which can be etched by a wet etching solution, but at different rates. In this embodiment, the different etching rates of the oxides generated by oxygen-containing plasma oxidation of the laser chip epitaxial layer surface reduce the risk of the etchant penetrating the electron blocking layer 404.

[0111] In some embodiments, oxygen-containing plasma treatment can be performed after dry etching and before wet etching. By controlling the plasma power, oxygen flow rate, and treatment time, the oxygen-containing plasma can oxidize the sidewalls of the light-emitting region 410 after dry etching, forming a dense oxide layer on the sidewalls of the electron blocking layer 404. The etching rate of the etchant on this oxide layer is relatively slow, thus the oxide layer can effectively inhibit the lateral penetration of the etchant along the sidewalls of the electron blocking layer 404 during wet etching, thereby reducing the occurrence of the etchant drilling into the electron blocking layer 404, and thus improving the docking morphology between the light-emitting region 410 and the modulation region 420. For example, under the conditions of a power of 100-300W, an oxygen flow rate of 50-200sccm, and a treatment time of 30-120 seconds, the thickness of the formed oxide layer is about 5-20nm, which is sufficient to block the lateral erosion of the subsequent wet etchant and can be removed simultaneously during the wet etching process, without remaining in the device structure and without affecting subsequent epitaxial growth and device performance.

[0112] In some embodiments, a dense alumina layer is formed on the sidewalls of the electron blocking layer 404. This alumina layer has excellent chemical stability, and the corrosion rate of the etchant on the alumina layer is slow, effectively resisting the erosion of wet etchants. This significantly reduces the risk of erosion and ensures the docking morphology between the luminescent region 410 and the modulation region 420. The formation process of the alumina layer is highly controllable, and its thickness and density can be precisely controlled by adjusting the plasma processing parameters.

[0113] In some embodiments, dry etching removes the epitaxial layer of the laser chip within the modulation region. Dry etching stops at the first active layer or the first buffer layer, including: dry etching stopping within the first active layer, where the remaining thickness of the first active layer is less than 50% of the thickness of the first active layer before dry etching; or dry etching stopping within the first buffer layer, where the remaining thickness of the first buffer layer is less than 50% of the thickness of the first buffer layer before dry etching. Controlling the endpoint of dry etching within the first active layer, and ensuring the remaining thickness of the first active layer is less than 50% of the thickness of the first active layer before dry etching, facilitates reducing the etching time of the first active layer during wet etching. This, in turn, reduces the etching time of the oxide layer on the electron blocking layer 404 during wet etching, effectively avoiding the risk that the etching solution will continue to etch the electron blocking layer 404 after the oxide layer has been completely etched due to excessive etching time. Correspondingly, controlling the dry etching endpoint within the first buffer layer, and ensuring the remaining thickness of the first buffer layer is less than 50% of its initial thickness before dry etching, can also shorten the wet etching time. This reduces the etching time of the oxide layer on the electron blocking layer 404, effectively avoiding the risk that the etching solution will continue to etch the electron blocking layer 404 after the oxide layer has been completely etched due to excessive etching time. For example, when dry etching stops within the first active layer, the remaining thickness of the first active layer can be 10-50 nm; when dry etching stops within the first buffer layer, the remaining thickness of the first buffer layer can also be 10-50 nm.

[0114] In some embodiments, dry etching stops at the first active layer, including: dry etching stops within the first active layer, and the remaining thickness of the first active layer can be 30% of the thickness of the first active layer before dry etching. By controlling the remaining thickness of the first active layer to 30%, the wet etching time can be further shortened, the corrosion pressure on the alumina layer can be reduced, and the wet etching efficiency and the effect of protecting the electron blocking layer 404 can be simultaneously achieved.

[0115] In some embodiments, dry etching stops at the first buffer layer, including: dry etching stops within the first buffer layer, and the remaining thickness of the first buffer layer can be 30% of the thickness of the first buffer layer before dry etching. By controlling the remaining thickness of the first buffer layer to 30%, the wet etching time can be further shortened, the corrosion pressure on the alumina layer can be reduced, and the wet etching efficiency and the effect of protecting the electron blocking layer 404 can be simultaneously achieved.

[0116] In some embodiments, wet etching to remove the first active layer exposed in the modulation region includes: wet etching the first active layer exposed in the modulation region for a first preset time; surface treating the sidewalls after wet etching with oxygen-containing plasma; re-oxidizing the sidewalls of the electron blocking layer with oxygen-containing plasma; the first preset time being less than or equal to the time required for the oxide layer on the sidewalls of the electron blocking layer to be completely etched before wet etching; and wet etching again to remove the first active layer exposed in the modulation region. The first preset time can be obtained through experimental testing. During the wet etching process to remove the first active layer exposed in the modulation region, by etching the first active layer in segments and re-oxidizing the sidewalls of the light-emitting region 410 with oxygen-containing plasma during the intervals of wet etching, the risk of the electron blocking layer 404 being drilled through during wet etching can be further reduced.

[0117] In some embodiments, wet etching to remove the first buffer layer exposed in the modulation region includes: setting the time for the first wet etching of the first buffer layer to a second preset time, wet etching the first buffer layer for the second preset time, surface treating the sidewalls after wet etching with oxygen-containing plasma, and re-oxidizing the sidewalls of the electron blocking layer with oxygen-containing plasma, wherein the second preset time is less than or equal to the time required for the oxide layer on the sidewalls of the electron blocking layer to be completely etched before wet etching; and wet etching again to remove the first buffer layer exposed in the modulation region. The second preset time can be obtained through experimental testing. During the wet etching process to remove the first buffer layer exposed in the modulation region, by etching the first buffer layer in segments and re-oxidizing the sidewalls of the light-emitting region 410 with oxygen-containing plasma during the intervals of wet etching, the risk of the electron blocking layer 404 being drilled through during wet etching can be further reduced.

[0118] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this disclosure, and are not intended to limit them. Although this disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this disclosure.

Claims

1. A method for fabricating a laser chip, characterized in that, The laser chip includes a light-emitting region and a modulation region, wherein the modulation region is located at the light-emitting end of the light-emitting region; the method includes: A laser chip epitaxial layer is grown on a substrate. The laser chip epitaxial layer includes a first buffer layer, a first active layer and an electron blocking layer from bottom to top. The electron blocking layer is an InAlAs layer. An initial dielectric film is deposited above the epitaxial layer of the laser chip; The initial dielectric film is patterned to form a dielectric film that covers the light-emitting area and exposes the modulation area. Based on the dielectric film, the epitaxial layer of the laser chip is dry-etched to remove the epitaxial layer of the laser chip in the modulation region. The dry etching stops at the first active layer or the first buffer layer. The side surface of the laser chip epitaxial layer is oxidized by dry etching using oxygen-containing plasma, and the side edge of the electron blocking layer is oxidized by oxygen-containing plasma to form an aluminum oxide layer on the side surface of the electron blocking layer. The first active layer or the first buffer layer exposed by the modulation region is etched with an etchant to remove the first active layer or the first buffer layer, wherein the etching rate of the etchant on the alumina layer is less than the etching rate of the etchant on the first active layer and the first buffer layer. A modulation epitaxial layer is formed above the first buffer layer or substrate within the modulation region; Remove the dielectric film and grow a waveguide layer over the light-emitting region and the modulation region.

2. The method according to claim 1, characterized in that, When dry etching stops at the first active layer, the remaining thickness of the first active layer is less than 50% of the thickness of the first active layer before dry etching; When dry etching stops at the first buffer layer, the remaining thickness of the first buffer layer is less than 50% of the thickness of the first buffer layer before dry etching.

3. The method according to claim 1, characterized in that, The process of removing the first active layer or the first buffer layer by etching the modulation region with an etchant includes: After etching the first active layer exposed by the modulation region with an etchant for a first preset time, the etching of the first active layer with the etchant is stopped, and the first preset time is less than the time required for the alumina layer to be completely etched. The side surface of the laser chip epitaxial layer is oxidized again using oxygen-containing plasma, thereby oxidizing the side edge of the electron blocking layer again with oxygen-containing plasma. The first active layer exposed by the modulation region is etched again using an etchant to remove the first active layer.

4. The method according to claim 1, characterized in that, The process of removing the first active layer or the first buffer layer by etching the modulation region with an etchant includes: After a second preset time for etching the first buffer layer exposed by the etchant in the modulation area, the etching of the first buffer layer with the etchant is stopped. The second preset time is less than the time required for the alumina layer to be completely etched. The side surface of the laser chip epitaxial layer is oxidized again using oxygen-containing plasma, thereby oxidizing the side edge of the electron blocking layer again with oxygen-containing plasma. The first buffer layer exposed by the modulation region is etched again using an etchant to remove the first buffer layer.

5. The method according to claim 1, characterized in that, When dry etching stops at the first active layer, the etching solution is sulfuric acid-hydrogen peroxide-aqueous solution, phosphoric acid-hydrogen peroxide-aqueous solution, or citric acid-hydrogen peroxide-aqueous solution; When dry etching stops at the first buffer layer, the etching solution is a mixture of phosphoric acid and hydrochloric acid, a mixture of phosphoric acid and hydrobromic acid, an aqueous solution of hydrochloric acid, or an aqueous solution of hydrobromic acid.

6. The method according to claim 1, characterized in that, When dry etching stops at the first active layer, the remaining thickness of the first active layer is less than or equal to 30% of the thickness of the first active layer before dry etching; When dry etching stops at the first buffer layer, the remaining thickness of the first buffer layer is less than or equal to 30% of the thickness of the first buffer layer before dry etching.

7. The method according to claim 1, characterized in that, A modulation epitaxial layer is formed above the first buffer layer or substrate within the modulation region, comprising: A second buffer layer, a second active layer, and a P-InP layer are sequentially formed above the first buffer layer or substrate within the modulation region. The bottom of the second active layer is lower than the bottom of the first active layer, and the top of the second active layer is higher than the top of the first active layer.

8. The method according to claim 1, characterized in that, The electron blocking layer is not doped with N-type impurities.

9. A laser chip, characterized in that, The laser chip is a laser chip prepared by the method described in any one of claims 1-8.

10. An optical module, characterized in that, It includes a laser chip, wherein the laser chip is the laser chip described in claim 9 above.

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