A method for manufacturing a laser chip and a laser chip

Abstract

The application discloses a preparation method of a laser chip and the laser chip, and relates to the technical field of optical fiber communication. The first photoresist and other photoresists are coated on the passivation layer, the support part and the second contact layer in sequence; after exposure and development, the first photoresist in the support part, the second contact layer and the grooves on both sides of the second contact layer is exposed; the first metal layer is grown on the other photoresists, the second contact layer, the support part and the first photoresist; the photoresist is removed to form the second positive electrode and the second pad. The electric connection bridge is grown on the top of the second positive electrode and the top of the second pad. The undercut structure is formed after the other photoresist is developed, and the thickness of the first metal layer is smaller than the thickness of the undercut structure. According to the application, the electric connection bridge is grown on the top of the second positive electrode and the top of the second pad to ensure the high-frequency performance of the modulation area; the undercut structure is formed after the other photoresist is developed, and the thickness of the first metal layer is smaller than the thickness of the undercut structure, so that the photoresist removal is smoothly completed.

Description

Technical Field

[0001] This disclosure relates to the field of optical fiber communication technology, and in particular to a method for fabricating a laser chip and the laser chip itself. Background Technology

[0002] With the development of new business and application models such as cloud computing, mobile internet, and video, advancements in optical communication technology have become increasingly important. In optical communication technology, the optical module, as one of the key components in optical communication equipment, enables photoelectric signal conversion; and in the development of optical communication technology, the data transmission rate of optical modules is required to continuously improve.

[0003] The optical module includes a laser chip, which includes a modulation region. The modulation region includes a positive electrode and a pad. The positive electrode and the pad are connected by an electrical connection. The electrical connection is located in a trench on one side of the positive electrode, which cannot meet the high-frequency performance requirements of the modulation region. Summary of the Invention

[0004] This disclosure provides a method for fabricating a laser chip and a laser chip to ensure the high-frequency performance of the modulation region.

[0005] In some embodiments, a method for fabricating a laser chip is provided, comprising: A first active layer and a second active layer are grown above an N-type InP layer; A P-type InP layer and a contact layer are sequentially grown above both the first and second active layers; The contact layer is etched down to the P-type InP layer in the middle to divide the contact layer into a first contact layer and a second contact layer that are not connected. Multiple trenches are formed by etching downwards to the N-type InP layer between the first and second contact layers. A passivation layer is grown above multiple trenches and the platforms on both sides of the trenches to form a support portion in a trench corresponding to the second contact layer. Etch downwards through the middle of the passivation layer to the first contact layer and the second contact layer; A first positive electrode is grown above the first contact layer, a second positive electrode is grown above the second contact layer, a first pad and an electrical connection portion are grown above the passivation layer on one side of the first contact layer, and a second pad is grown above the support portion. An electrical connection bridge is grown above the second positive electrode and above the second pad; A negative electrode is grown on the lower surface of an N-type InP layer; Specifically, a second positive electrode is grown above the second contact layer, and a second pad is grown above the support portion, including: A first photoresist and other photoresists are sequentially coated on top of the passivation layer, the support portion, and the second contact layer. After exposure, a developing solution is used to develop the substrate so that the support portion, the second contact layer, and the first photoresist in the trenches on both sides of the second contact layer are all exposed. A first metal layer is grown on top of the other photoresist, the second contact layer, the support, and the first photoresist; Remove the first photoresist and other photoresist to remove the first metal layer above the photoresist, so that a second positive electrode is formed above the second contact layer and a second pad is formed above the support portion; The second positive electrode is a titanium-platinum layer, and the electrical connection bridge is a pure gold layer; other photoresists form an undercut structure after development, including a fourth photoresist, or a second and third photoresist arranged sequentially from bottom to top; the exposed areas of the first and third photoresists are soluble in the developer, while the non-exposed areas are insoluble in the developer; both the exposed and non-exposed areas of the second photoresist are soluble in the developer, while the exposed area of ​​the fourth photoresist is insoluble in the developer, and the non-exposed area is soluble in the developer; the thickness of the first metal layer is less than the thickness of the second photoresist and less than the thickness of the undercut structure.

[0006] The above technical solution has the following beneficial effects: This disclosure provides a method for fabricating a laser chip. A first active layer and a second active layer are grown above an N-type InP layer. A P-type InP layer and a contact layer are sequentially grown above both the first and second active layers. The contact layer is etched downwards to the P-type InP layer in the middle to divide the contact layer into a non-connected first contact layer and a second contact layer. The first and second contact layers are not connected. The positive potential received by the first and second contact layers is respectively input to the first and second active layers, enabling the first and second active layers to perform their respective functions. Multiple trenches are formed by etching downwards to the N-type InP layer between the first and second contact layers. A passivation layer is grown above the multiple trenches and the mesa on both sides of the trenches, which provides insulation protection. Simultaneously, a support portion is formed in a trench corresponding to the second contact layer, providing a growth support foundation for the second pad. Next, the passivation layer is etched downwards to the first and second contact layers. A first positive electrode, a second positive electrode, a first pad, an electrical connection, and a second pad are then grown sequentially. An electrical connection bridge connecting the second positive electrode and the second pad is then grown. Finally, a negative electrode is grown on the lower surface of the N-type InP layer, completing the chip fabrication. The modulation region is composed of the negative electrode, N-type InP layer, first active layer, P-type InP layer, second contact layer, and the electrode layer containing the second positive electrode, arranged from bottom to top. The electrode layer containing the second positive electrode includes the second positive electrode, the second pad, and the electrical connection bridge above the second positive electrode and above the second pad. Growing the electrical connection bridge above the second positive electrode and above the second pad increases the distance between the negative electrode and the electrode layer containing the second positive electrode, reducing the capacitance formed by the two electrode layers, lowering the charging and discharging delay, and ensuring the high-frequency performance of the modulation region. A second positive electrode is grown above the second contact layer, and a second pad is grown above the support portion. First, a first photoresist and other photoresists are sequentially coated above the passivation layer, the support portion, and the second contact layer. Then, the photoresists are exposed, followed by development with a developer to expose the support portion, the second contact layer, and the first photoresist within the trenches on both sides of the second contact layer. Next, a first metal layer is grown above the other photoresists, the second contact layer, the support portion, and the first photoresist. Finally, the first and other photoresists are removed to remove the first metal layer adhering to the photoresist, thus forming the second positive electrode above the second contact layer and the second pad above the support portion. The second positive electrode is a titanium-platinum layer, and the electrical connection bridge is a pure gold layer to prevent oxidation of the metal in the electrical connection bridge, thereby avoiding affecting the electrical performance of the second positive electrode and ensuring the stability of the electrode structure. After other photoresists are developed, an undercut structure is formed. The thickness of the first metal layer is less than the thickness of the undercut structure. This prevents the first metal layer from covering the exposed first photoresist and the adjacent photoresist layer. As a result, the resist remover cannot come into contact with the first photoresist and the adjacent photoresist layer, and the resist removal cannot be completed smoothly.Other photoresists include a second photoresist and a third photoresist arranged sequentially from bottom to top. The exposed area of ​​the third photoresist is soluble in the developer, while the non-exposed area is insoluble. Both the exposed and non-exposed areas of the second photoresist are soluble in the developer, so that the second and third photoresists form an undercut structure after development. Other photoresists include a fourth photoresist, whose exposed area is insoluble in the developer, while the non-exposed area is soluble, so that the fourth photoresist forms an undercut structure after development. The exposed area of ​​the first photoresist is soluble in the developer, while the non-exposed area is insoluble, so that the first photoresist within the trenches on both sides of the second contact layer, the support portion, and the second contact layer can be exposed. The exposed areas of the third photoresist are soluble in the developer, while the unexposed areas are insoluble. After development, the third photoresist on both sides of the second contact layer forms a trapezoidal shape. When the first metal layer is grown above the third photoresist, the first metal layer is also grown on the side of the third photoresist. The thickness of the first metal layer is less than the thickness of the second photoresist to prevent the first metal layer from covering the exposed first and second photoresist. The resist remover cannot contact the first and second photoresist, resulting in the resist removal not being completed smoothly, and thus the photoresist and the first metal layer above the photoresist cannot be removed. In this disclosure, an electrical connection bridge is grown above the second positive electrode and above the second pad, increasing the distance between the electrode layers containing the negative electrode and the second positive electrode. This reduces the capacitance formed by the electrode layers containing the negative electrode and the second positive electrode, lowering the charging and discharging delay and ensuring the high-frequency performance of the modulation region. The second positive electrode is a titanium-platinum layer, and the electrical connection bridge is a pure gold layer, preventing the metal in the electrical connection bridge from being oxidized, thereby avoiding affecting the electrical performance of the second positive electrode. After the other photoresist is developed, an undercut structure is formed. The thickness of the first metal layer is less than the thickness of the undercut structure, preventing the first metal layer from covering the exposed first photoresist and the adjacent photoresist layer. This allows the resist remover to contact the first photoresist and the adjacent photoresist layer, ensuring successful resist removal.

[0007] In some embodiments, a method for fabricating a laser chip is provided, wherein growing an electrical connection bridge above the second positive electrode and above the second pad includes: A fifth photoresist is coated on top of the passivation layer, the second positive electrode, the support portion, and the second pad; After exposure, a developing solution is used to develop the second positive electrode, the second pad, the fifth photoresist between the second positive electrode and the second pad, the fifth photoresist in the trench on the left side of the second positive electrode, the passivation layer on the left mesa of the trench on the left side of the second positive electrode, and the passivation layer on the right side of the second pad. The fifth photoresist is hardened by heating with a hot plate, so that the fifth photoresist between the second pad and the second positive electrode forms an arch shape. A sixth photoresist is coated on top of the passivation layer, the fifth photoresist, the second positive electrode, and the second pad; The second positive electrode, the second pad, the fifth photoresist in the trench on the left side of the second positive electrode, and the fifth photoresist between the second pad and the second positive electrode are exposed. A second metal layer is grown above the sixth photoresist, the second positive electrode, and the second pad; Remove the fifth and sixth photoresists to remove the second metal layer on the photoresists, so that an electrical connection bridge is formed above the second positive electrode and above the second pad. The fifth photoresist's exposed area dissolves in the developer, while its unexposed area does not; the sixth photoresist's exposed area does not dissolve in the developer, while its unexposed area dissolves in the developer; after development, the top of the fifth photoresist between the second positive electrode and the second pad protrudes beyond the top of the second positive electrode and the top of the second pad.

[0008] The above technical solution has the following beneficial effects: An electrical connection bridge is grown above the second positive electrode and the second pad, including: coating a fifth photoresist above the passivation layer, the second contact layer, the support portion, and the second pad; after exposure, developing with a developer to expose the second positive electrode, the second pad, the fifth photoresist between the second positive electrode and the second pad, the fifth photoresist in the trench on the left side of the second positive electrode, the passivation layer on the left mesa of the trench on the left side of the second positive electrode, and the passivation layer on the right side of the second pad; and using a hot plate for heating to harden the fifth photoresist, making the fifth photoresist between the second pad and the second positive electrode arched, providing support for the electrical connection bridge without additional processing, allowing the electrical connection bridge to be suspended between the second positive electrode and the second pad, avoiding direct contact between the electrical connection bridge and the underlying passivation layer. Next, a sixth photoresist is coated over the passivation layer, the fifth photoresist, the second positive electrode, and the second pad. After exposure, development is performed using a developer to expose the fifth photoresist in the second positive electrode, the second pad, the trench to the left of the second positive electrode, and the area between the second pad and the second positive electrode. A second metal layer is grown over the sixth photoresist, the second positive electrode, and the second pad. The fifth and sixth photoresists are then removed to remove the second metal layer on the photoresist, forming an electrical connection bridge above the second positive electrode and the second pad. After removing the fifth and sixth photoresists, the second metal layer at the arched position is retained, directly forming a suspended pure gold electrical connection bridge. The exposed area of ​​the fifth photoresist dissolves in the developer, while the unexposed area does not, thus exposing the fifth photoresist on the second positive electrode, the second pad, one side of the second contact layer, and the area between the second pad and the second positive electrode. The exposed area of ​​the sixth photoresist is insoluble in the developer, while the unexposed area is soluble. This ensures that the sixth photoresist forms an undercut structure after development. The thickness of the second metal layer is less than the thickness of the undercut structure, i.e., the thickness of the sixth photoresist. This prevents the second metal layer from encapsulating the exposed fifth photoresist and its adjacent layer, thus preventing the resist remover from contacting them and hindering the removal process. After development, the top of the fifth photoresist between the second positive electrode and the second pad protrudes beyond the top of the second positive electrode and the second pad. This causes the electrical connection bridge formed above the fifth photoresist to protrude above the second positive electrode and the second pad, ensuring that the electrical connection bridge is suspended between the second positive electrode and the second pad. This further increases the distance between the electrical connection bridge and the lower negative electrode, reducing the inter-electrode capacitance and ensuring the high-frequency performance of the modulation region.

[0009] In some embodiments, a method for fabricating a laser chip is provided, wherein other photoresists include a second photoresist and a third photoresist disposed sequentially from bottom to top, and the first photoresist, the second photoresist, and the third photoresist are sequentially coated above the passivation layer, the support portion, and the second contact layer, comprising: A first photoresist is coated over the passivation layer, the support portion, and the second contact layer; A second photoresist is coated on top of the first photoresist; A third photoresist is coated on top of the second photoresist; Other photoresists include a fourth photoresist, which is applied sequentially over the passivation layer, the support layer, and the second contact layer, including: A first photoresist is coated over the passivation layer, the support portion, and the second contact layer; A fourth photoresist is coated on top of the first photoresist.

[0010] The above technical solution has the following beneficial effects: Other photoresists include a second photoresist and a third photoresist arranged sequentially from bottom to top. A first photoresist, a second photoresist, and a third photoresist are sequentially coated above the passivation layer, the support portion, and the second contact layer. This includes: firstly, coating the first photoresist above the passivation layer, the support portion, and the second contact layer; secondly, coating the second photoresist above the first photoresist; and thirdly, coating the third photoresist above the second photoresist, so that the first photoresist, the second photoresist, and the third photoresist are arranged sequentially from bottom to top. Other photoresists include a fourth photoresist. The first and fourth photoresists are sequentially coated on top of the passivation layer, the support portion, and the second contact layer. This includes: firstly, coating the first photoresist on top of the passivation layer, the support portion, and the second contact layer; secondly, coating the fourth photoresist on top of the first photoresist, so that the first and fourth photoresists are arranged sequentially from bottom to top. This facilitates the formation of corresponding undercut structures after sequential exposure and development according to the different characteristics of the photoresists, ensuring that the photoresist removal process can be completed smoothly.

[0011] In some embodiments, a method for fabricating a laser chip is provided, wherein other photoresists include a second photoresist and a third photoresist arranged sequentially from bottom to top, wherein the thickness of the first photoresist is 2.3 μm to 3.0 μm, the thickness of the second photoresist is 1.0 μm to 2.0 μm, and the thickness of the third photoresist is 1.0 μm to 2.0 μm.

[0012] Other photoresists include a fourth photoresist, wherein the thickness of the first photoresist is 2.3 μm to 3.0 μm, and the thickness of the fourth photoresist is 2.0 μm to 4.0 μm.

[0013] The above technical solution has the following beneficial effects: Other photoresists include a second photoresist and a third photoresist arranged sequentially from bottom to top. The thickness of the first photoresist is 2.3µm to 3.0µm to prevent it from being completely developed during exposure and development, thus preventing the first metal layer from being directly deposited on the N-type InP layer. This ensures the first metal layer can be directly deposited on the first photoresist, facilitating the removal of the first metal layer on the first photoresist when using a photoresist remover. The thickness of the second photoresist is 1.0µm to 2.0µm to prevent the first metal layer from completely encapsulating the exposed second photoresist, preventing the photoresist remover from contacting the second photoresist and hindering the removal process. Consequently, the photoresist and the first metal layer above it cannot be removed. The third photoresist has a thickness of 1.0µm to 2.0µm. This not only ensures that light can pass through smoothly during exposure, resulting in a photolithographic pattern with the required precision, but also protects the second photoresist, preventing it from being exposed before development and thus avoiding complete dissolution by the developer. Other photoresists include a fourth photoresist. The first photoresist has a thickness of 2.3µm to 3.0µm to prevent it from being completely developed during exposure, thus preventing the first metal layer from being directly deposited on the N-type InP layer. This ensures the first metal layer can be directly deposited on the first photoresist, facilitating the removal of the first metal layer from the first photoresist using a photoresist remover. The fourth photoresist has a thickness of 2.0µm to 4.0µm. This not only ensures that light can pass through smoothly during exposure, resulting in a photolithographic pattern with the required precision, but also allows the fourth photoresist to form a sufficiently large undercut structure after development, preventing the first metal layer from completely covering the exposed sides of the first photoresist and ensuring that the photoresist remover can easily contact the photoresist.

[0014] In some embodiments, a method for fabricating a laser chip is provided, wherein the thickness of the fifth photoresist is 3.0 μm to 3.6 μm, and the thickness of the sixth photoresist is 2.0 μm to 4.0 μm.

[0015] The above technical solution has the following beneficial effects: The thickness of the fifth photoresist is 3.0um~3.6um, which avoids completely developing the fifth photoresist during exposure and development, thereby preventing the second metal layer from being directly deposited on the N-type InP layer. This ensures that the second metal layer can be directly deposited on the fifth photoresist, facilitating the removal of the second metal layer on the fifth photoresist when the photoresist is removed using a resist remover. The thickness of the sixth photoresist is 2.0um~4.0um, which not only ensures that light can pass through smoothly during exposure to obtain a photolithographic pattern with the required precision, but also allows the sixth photoresist to form a sufficiently large undercut structure after development, preventing the first metal layer from completely encasing the exposed fifth and sixth photoresists, and ensuring that the resist remover can smoothly contact the photoresist.

[0016] In some embodiments, a method for fabricating a laser chip is provided, wherein a first photoresist is coated over a passivation layer, a support portion, and a second contact layer, comprising: Apply a base coat over the passivation layer, the support layer, and the second contact layer using an oven. A first photoresist is applied on top of the base adhesive using a spin coater; Heat drying is performed using a hot plate.

[0017] The above technical solution has the following beneficial effects: A first photoresist is coated on top of the passivation layer, the support portion, and the second contact layer, including: First, using an oven to coat a base coat on top of the passivation layer, the support portion, and the second contact layer. The base coat ensures good adhesion between the passivation layer, the support portion, the second contact layer, and the first photoresist, preventing the first photoresist from detaching from these layers. Second, a spin coater is used to coat the first photoresist on top of the base coat. Third, a hot plate is used for baking to remove excess solvent from the first photoresist and improve its adhesion.

[0018] In some embodiments, a method for fabricating a laser chip is provided, which uses a hot plate to heat-bake the fifth photoresist to harden it. The heat-bake conditions are 140°C to 160°C for 1 min to 3 min.

[0019] The above technical solution has the following beneficial effects: using a hot plate for hot baking to harden the fifth photoresist, with the baking conditions being 140℃~160℃ for 1min~3min, allows the fifth photoresist to fully harden and set in a short time, ensuring the stability of the arched structure and meeting the support requirements for the suspended electrical connection bridge, while preventing excessive carbonization of the fifth photoresist due to excessively high temperature or heating time, which would affect the smooth progress of subsequent photoresist removal processes and ensure the yield of the arched suspended electrical connection bridge.

[0020] In some embodiments, a method for fabricating a laser chip is provided, comprising removing a first photoresist and other photoresists, including: Use a resist remover to remove the main resist from the first photoresist and other photoresists; Plasma removes residual photoresist from the first photoresist and other photoresists.

[0021] The above technical solution has the following beneficial effects: Removing the first photoresist and other photoresists includes: firstly, using a resist remover to remove the main resist of the first photoresist and other photoresists; secondly, using plasma to remove the residual resist of the first photoresist and other photoresists, removing the photoresist and the first metal layer above the photoresist, retaining only the first metal layer above the second contact layer and the support portion, thus obtaining the formed second positive electrode and second pad. This two-step process of removing the main resist first and then the residual resist ensures thorough photoresist removal, preventing residual photoresist from adhering to the chip surface and affecting the electrical performance of the second positive electrode and the second pad, while also preventing damage to other structures of the chip, ensuring the stable and reliable performance of the fabricated laser chip.

[0022] In some embodiments, a method for fabricating a laser chip is provided, wherein the second positive electrode includes: A titanium layer is located above the second contact layer and is connected to the second contact layer; A platinum layer is located above and connected to the titanium layer; A gold layer is located above and connected to the platinum layer.

[0023] The above technical solution has the following beneficial effects: The second positive electrode includes a titanium layer, a platinum layer, and a gold layer. The titanium layer is located above the second contact layer and is connected to the second contact layer. The platinum layer is located above the titanium layer and is connected to the titanium layer. The gold layer is located above the platinum layer and is connected to the platinum layer. This avoids the titanium layer from contacting air, prevents the titanium layer from oxidizing, ensures that the second positive electrode has stable and low-resistance ohmic contact performance, avoids the degradation of the electrical performance of the second positive electrode, and thus ensures the photoelectric conversion efficiency and service life of the laser chip during operation.

[0024] In some embodiments, a laser chip is provided, which is a laser chip prepared by the above-described preparation method.

[0025] The above technical solution has the following beneficial effects: This disclosure provides a laser chip, which is a laser chip fabricated using a laser chip fabrication method. The laser chip has a suspended electrical connection bridge, which can avoid contact with the underlying passivation layer, reduce the shading of the electrical connection bridge on the chip's functional areas, and reduce the loss during beam transmission. Attached Figure Description

[0026] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0027] Figure 1This is a partial structural diagram of an optical communication system according to some embodiments; Figure 2 This is a partial structural diagram of a host computer according to some embodiments; Figure 3 This is a structural diagram of an optical module according to some embodiments; Figure 4 An exploded view of an optical module according to some embodiments; Figure 5 This is an assembly diagram of an optical transceiver and an optical fiber adapter according to some embodiments; Figure 6 This is a structural diagram of a light-emitting component according to some embodiments; Figure 7 This is a cross-sectional view of a light-emitting component provided according to some embodiments; Figure 8 This is a structural diagram of a laser chip according to some embodiments; Figure 9 This is a flowchart illustrating a method for fabricating a laser chip according to some embodiments; Figure 10 This is a partial flow chart of a laser chip fabrication method according to some embodiments. Figure 1 ; Figure 11 This is a partial flow chart of a laser chip fabrication method according to some embodiments. Figure 2 ; Figure 12a This is a partial flowchart illustrating a method for fabricating a laser chip according to some embodiments. Figure 1 ; Figure 12b This is a partial flowchart illustrating a method for fabricating a laser chip according to some embodiments. Figure 2 ; Figure 13a This is a partial schematic diagram of a laser chip fabrication method according to some embodiments. Figure 3 ; Figure 13b This is a partial schematic diagram of a laser chip fabrication method according to some embodiments. Figure 4 ; Figure 14 This is a partial schematic diagram of a laser chip fabrication method according to some embodiments. Figure 5 . Detailed Implementation

[0028] The embodiments of this disclosure will now be described clearly and in detail with reference to the accompanying drawings. However, the described embodiments are merely some, and not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.

[0029] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as open and inclusive, meaning "including, but not limited to"; the terms "first" and "second" should not be construed as indicating or implying relative importance or indicating an upper limit on the number; the term "multiple" means two or more; the term "connection" should be interpreted broadly, for example, "connection" can be a fixed connection, a detachable connection, or an integral part, and can be a direct connection or an indirect connection through an intermediate medium; the use of the terms "applicable to" or "configured to" implies open and inclusive language, which does not exclude applicability to or configuration to devices performing additional tasks or steps; descriptions such as "parallel," "perpendicular," "identical," "consistent," and "aligned" are not limited to absolute mathematical theoretical relationships, but also include acceptable error ranges arising in practice, and differences based on the same design concept but due to manufacturing reasons.

[0030] In optical communication technology, information is loaded onto light to generate optical signals, which are then used to transmit information between information processing devices. Connections are established between these devices via optical transmission equipment. Optical power loss is minimal during transmission through this equipment, allowing for long-distance transmission with relatively low power loss. Light boasts extremely high transmission speeds, and the cost of optical transmission equipment, such as fiber optic cables, is lower than that of electrical transmission equipment like copper wires. Using optical signals to transmit information offers advantages such as long-distance transmission, high speed, and low cost.

[0031] Information processing equipment typically includes switches, servers, optical network units (ONUs), optical distribution networks (ODNs), optical line terminals (OLTs), gateways, routers, mobile phones, computers, tablets, televisions, etc.; optical transmission equipment typically includes optical fibers and optical waveguides. Information processing equipment can recognize and process electrical signals, while optical transmission equipment can transmit optical signals. Therefore, optical modules are needed between the optical transmission equipment and the information processing equipment to perform the conversion between optical and electrical signals.

[0032] In some embodiments, the optical signal input and / or optical signal output of the optical module are connected to an optical fiber, and the electrical signal input and / or electrical signal output of the optical module are connected to a switch; a first optical signal from the optical fiber is transmitted to the optical module, the optical module converts the first optical signal into a first electrical signal, and transmits the first electrical signal to the switch; a second electrical signal from the switch is transmitted to the optical module, the optical module converts the second electrical signal into a second optical signal, and transmits the second optical signal to the optical fiber.

[0033] Information processing equipment connected to optical modules is also known as the host computer for optical modules. In access network transmission scenarios, the host computer for optical modules is usually an ONU, ODN, or OLT; in data center transmission scenarios, the host computer for optical modules is usually a Switch or Server.

[0034] Figure 1 This is a schematic diagram of the structure of an optical module access switch according to some embodiments. Figure 1 As shown, switch 100 has multiple optical module interfaces. Multiple optical modules are inserted into the switch through these interfaces, establishing electrical signal communication between the optical modules and the switch. Optical fiber 101 is connected to the optical modules, establishing optical signal communication between the optical fiber and the optical modules. One end of optical fiber 101 is connected to the optical module, and the other end of optical fiber 101 (…) Figure 1 (not shown in the image) connects to another optical module ( Figure 1 (Not shown in the image), another optical module accesses the server ( Figure 1 (not shown in the image) or another switch ( Figure 1 (Not shown in the image).

[0035] In some embodiments, the optical fiber 101 and the optical module 200 are detachably connected; in other embodiments, the optical fiber 101 and the optical module 200 are non-detachably connected.

[0036] The switch 100 is configured to provide data electrical signals to the optical module 200, or receive data electrical signals from the optical module 200, or monitor or control the operating status of the optical module 200.

[0037] In some embodiments, the optical module is a tool for converting optical signals to electrical signals. During the conversion process, the information does not change, but the encoding or decoding method of the information changes.

[0038] Figure 2 This is a partial structural diagram of a switch according to some embodiments. To clearly show the connection relationship between the optical module 200 and the switch 100, Figure 2 Only the structures related to the switch 100 and the optical module 200 are shown. (For example...) Figure 2As shown, in some embodiments, the switch 100 further includes a PCB circuit board 102 disposed in the receiving cavity, and a cage 103 disposed on the surface of the PCB circuit board 102; the optical module 200 is inserted into the cage 103 and fixed by the cage 103.

[0039] In some embodiments, a heat sink 104 is provided on the cage 103 to dissipate heat for the optical module; in some embodiments, the heat sink 104 has protruding structures such as fins to increase the heat dissipation area.

[0040] In some embodiments, an electrical connector is provided inside the cage 103, which is configured to access the electrical interface of the optical module 200.

[0041] In some embodiments, the optical module 200 is inserted into the cage 103 of the switch 100, and the cage 103 fixes the optical module 200. The heat generated by the optical module 200 is conducted to the cage 103 and then diffused through the heat sink 104.

[0042] In some embodiments, the optical module 200 is inserted into the cage 103 of the switch 100, and the electrical interface of the optical module 200 is connected to the electrical connector inside the cage 103, thereby establishing an electrical signal connection between the optical module 200 and the switch 100.

[0043] In some embodiments, the optical interface of the optical module 200 is connected to the optical fiber 101, thereby enabling the optical module 200 to establish an optical signal connection with the optical fiber 101.

[0044] Figure 3 This is a structural diagram of an optical module according to some embodiments. Figure 4 This is an exploded view of an optical module according to some embodiments. Figure 3 and Figure 4 As shown, in some embodiments, the optical module 200 includes a shell, which includes an upper shell 201 and a lower shell 202. The upper shell 201 covers the lower shell 202, forming a first opening 204 and a second opening 205, wherein the first opening 204 is an electrical interface and the second opening 205 is an optical interface.

[0045] In some embodiments, the upper housing 201 and the lower housing 202 are made of metal materials, which facilitates electromagnetic shielding and heat dissipation.

[0046] The assembly method of combining the upper housing 201 and the lower housing 202 facilitates the installation of circuit boards 300 and other components into the housing. The upper housing 201 and the lower housing 202 can encapsulate and protect the aforementioned devices.

[0047] The direction of the line connecting the first opening 204 and the second opening 205 can be consistent with or inconsistent with the length direction of the optical module 200. For example, the first opening 204 is located at the end of the optical module 200. Figure 3 The second opening 205 is also located at the end of the optical module 200 (left end). Figure 3 (The right end). Alternatively, the first opening 204 is located at the end of the optical module 200, while the second opening 205 is located on the side of the optical module 200.

[0048] In some embodiments, the lower housing 202 includes a base plate 2021 and two lower side plates 2022 located on both sides of the base plate 2021 and perpendicular to the base plate 2021; the upper housing 201 includes a cover plate 2011, which covers the two lower side plates 2022 of the lower housing 202 to form the aforementioned housing.

[0049] In some embodiments, the lower housing 202 includes a base plate 2021 and two lower side plates 2022 located on both sides of the base plate 2021 and perpendicular to the base plate 2021; the upper housing 201 includes a cover plate 2011 and two upper side plates located on both sides of the cover plate 2011 and perpendicular to the cover plate 2011. The two upper side plates and the two lower side plates 2022 are combined to realize that the upper housing 201 covers the lower housing 202.

[0050] In some embodiments, the optical module 200 further includes an unlocking component 600 located outside its housing. The unlocking component 600 is configured to establish a fixed connection between the optical module 200 and the host computer, or to release the fixed connection between the optical module 200 and the host computer.

[0051] For example, the unlocking component 600 is located on the outside of the two lower side plates 2022 of the lower housing 202, and includes a locking component that matches the cage 103 of the switch 100. When the optical module 200 is inserted into the cage 103, the locking component of the unlocking component 600 fixes the optical module 200 in the cage 103; when the unlocking component 600 is pulled, the locking component of the unlocking component 600 moves accordingly, thereby changing the connection relationship between the locking component and the host computer, so as to release the fixation between the optical module 200 and the host computer, thereby allowing the optical module 200 to be pulled out of the cage 103.

[0052] like Figure 3 and Figure 4As shown, in some embodiments, the optical module includes a circuit board 300 disposed within a housing. The circuit board 300 includes circuit traces, electronic components, and chips, etc. The electronic components and chips are connected according to the circuit design through the circuit traces to realize functions such as power supply, electrical signal transmission, and grounding. Electronic components may include, for example, capacitors, resistors, transistors, and metal-oxide-semiconductor field-effect transistors (MOSFETs). Chips may include microcontroller units (MCUs), laser driver chips, transimpedance amplifiers (TIAs), limiting amplifiers (LAs), clock and data recovery chips (CDRs), power management chips, and digital signal processing (DSP) chips.

[0053] In some embodiments, the circuit board includes a rigid circuit board, which, due to its relatively rigid material, can also serve a load-bearing function, such as being able to stably support the aforementioned electronic components and chips; the rigid circuit board can also be inserted into the electrical connector in the cage 103 of the switch 100.

[0054] In some embodiments, the circuit board further includes a flexible circuit board, which can be used independently or in conjunction with a rigid circuit board.

[0055] In some embodiments, the circuit board further includes gold fingers formed on its end surface, the gold fingers consisting of a plurality of independent pins.

[0056] In some implementations, the gold fingers are located on one side of the surface of the circuit board 300. Figure 4 (as shown on the upper surface); In some implementations, the gold fingers are located on the upper and lower surfaces of the circuit board 300 to provide a greater number of pins, thus adapting to applications with high pin count requirements.

[0057] In some implementations, the gold fingers of the circuit board extend from the electrical interface and are inserted into the electrical connector of the switch 100; the circuit board is inserted into the cage 103, and the gold fingers are connected to the electrical connector inside the cage 103. The gold fingers are configured to establish an electrical connection with the host computer, enabling electrical connection functions such as power supply, grounding, two-wire synchronous serial (Inter-Integrated Circuit, I2C) signal transmission, and data signal transmission.

[0058] In some embodiments, the optical module includes a light emitting component 400, such as... Figure 3 and Figure 4 As shown. The light emitting component 400 is used to emit a second light signal.

[0059] In some embodiments, the optical module includes an optical receiving component 500, such as... Figure 3 and Figure 4 As shown, the optical receiving unit 500 is used to receive the first optical signal and convert the first optical signal into an electrical signal.

[0060] In some embodiments, at least one of the light emitting component 400 or the light receiving component 500 is located on the side of the circuit board 300 away from the gold fingers.

[0061] In some embodiments, the light emitting component 400 and the light receiving component 500 are physically separated from the circuit board 300, and then electrically connected to the circuit board 300 through corresponding flexible circuit boards or electrical connectors.

[0062] In some embodiments, at least one of the light emitting component or the light receiving component may be directly disposed on the circuit board 300. For example, at least one of the light emitting component or the light receiving component may be disposed on the surface of the circuit board 300 or the side of the circuit board 300.

[0063] Figure 5 This is an internal structural diagram of an optical module according to some embodiments. Figure 5 As shown, in some embodiments, the first end of the light receiving component 500 may be connected to the light emitting component 400 so that the light receiving component 500 can receive the second light signal emitted by the light emitting component 400.

[0064] In some embodiments, an optical fiber adapter 700 may be disposed within the housing of the optical module 200. The optical fiber adapter 700 may be connected to the second end of the optical receiving component 500 so that an externally input first optical signal is input to the optical receiving component 500 through the optical fiber adapter 700.

[0065] The first end of the optical receiver 500 can be connected to the optical transmitter 400, and the second end of the optical receiver 500 can be connected to the fiber optic adapter 700. The light output direction of the optical transmitter 400 faces the fiber optic adapter 700, so that the transmitted optical signal emitted by the optical transmitter 400 is first transmitted to the optical receiver 500, then transmitted through the optical receiver 500 to the fiber optic adapter 700, and finally output through the fiber optic adapter 700. The optical receiver 500 and the optical transmitter 400 share the fiber optic adapter 700, and thus the uplink and downlink optical signals of the optical module share the same optical fiber 101.

[0066] In some embodiments, the optical receiving component 500 may include an optical receiving assembly 520. The optical receiving assembly 520 may be connected to the first cavity 510 so that an externally input first optical signal is input to the first cavity 510 via the fiber optic adapter 700, and then transmitted to the optical receiving assembly 520 via the first cavity 510.

[0067] In some embodiments, the optical receiving component 500 may include a first cavity 510. The first cavity 510 has a first light-transmitting aperture. An optical fiber adapter 700 may be connected to the first light-transmitting aperture to connect the optical fiber adapter 700 to the first cavity 510. The first cavity 510 has a second light-transmitting aperture. An optical receiving component 520 may be connected to the second light-transmitting aperture to connect the optical receiving component 520 to the first cavity 510. The first cavity 510 has a third light-transmitting aperture. An optical emitting component 400 may be connected to the third light-transmitting aperture to connect the optical emitting component 400 to the first cavity 510.

[0068] Figure 6 This is a structural diagram of a light emitting component according to some embodiments. Figure 7 This is a cross-sectional view of a light-emitting component according to some embodiments. Figure 6 and Figure 7 As shown, in some embodiments, the light emitting component 400 may include a socket 410. A laser chip 450 is disposed on the top surface of the socket 410, and the laser chip 450 emits light signals.

[0069] In some embodiments, the light emitting component 400 may include a cap 420. The cap 420 covers the base 410.

[0070] In some embodiments, the light emitting component 400 may include a lens 440. The lens 440 is used to collimate the light signal emitted by the laser chip 450, so that the light signal is collimated from divergent light to parallel light, thereby reducing transmission loss.

[0071] In some embodiments, the light emitting component 400 may include a pin 430. The pin 430 extends upward from the bottom of the socket 410 until it extends beyond the top of the socket 410. One end of the pin 430 is connected to the circuit board 300 via a flexible circuit board to achieve an electrical connection between the pin 430 and the circuit board 300. The other end of the pin 430 extends beyond the top of the socket 410 and is wire-connected to the pad where the laser chip 450 is located to achieve an electrical connection between the pin and the laser chip 450, thereby transmitting electrical signals from the circuit board 300 to the pad where the laser chip 450 is located via the pin 430.

[0072] Figure 8 This is a structural diagram of a laser chip according to some embodiments. Figure 8As shown, in some embodiments, the laser chip 450 may include a light-emitting region 451, which may emit light without carrying data.

[0073] In some embodiments, the laser chip 450 may include a modulation region 452, one end of which may be connected to the light-emitting region 451, so that the modulation region 452 can receive light without data emitted from the light-emitting region 451. The modulation region 452 may absorb the light without data and modulate the absorbed light according to an electrical signal, so that the output light carries the data to be transmitted.

[0074] In some embodiments, both the light-emitting region 451 and the modulation region 452 may include an N-type InP layer 453, and a negative electrode may be disposed on the lower surface of the N-type InP layer 453. The negative electrode is an N-face electrode, which is used to receive a negative potential (ground or negative voltage).

[0075] In some embodiments, a first active layer 4511 may be disposed above and connected to the N-type InP layer 453. The first active layer 4511 can emit light of a specific wavelength. The first active layer 4511 has a relatively small number of freely moving charge carriers, and is non-conductive in the absence of an electric field. Under the influence of an electric field, the first active layer 4511 undergoes population inversion, thereby generating stimulated emission.

[0076] The first active layer 4511 may include a first quantum well layer. The first quantum well layer may be disposed above and connected to the N-type InP layer 453. The first quantum well layer is generally made of InGaAsP or InAlGaAs multilayer quantum well material to enable it to emit light.

[0077] The first active layer 4511 may include a grating layer. The grating layer may be disposed above and connected to the first quantum well layer. The grating layer is used to select light of a specific wavelength from the light emitted from the first quantum well layer. The grating layer may be a Bragg grating. By changing the current injected into the grating layer, the effective refractive index of the grating layer can be changed, thereby changing the resonant lasing wavelength of the grating layer, thus achieving the selection of a specific wavelength.

[0078] In some embodiments, a second active layer 4521 may be disposed above and connected to the N-type InP layer 453. The second active layer 4521 can absorb light. The second active layer 4521 can be a second quantum well layer. The second quantum well layer is generally made of InGaAsP or InAlGaAs multilayer quantum well material to achieve light absorption and modulation.

[0079] The second active layer 4521 has a relatively small number of freely movable charge carriers, and it is non-conductive in the absence of an electric field. Under the influence of an electric field, the second active layer 4521 absorbs light of a specific wavelength. By changing the current injected into the second active layer 4521, the absorption intensity of the light by the second active layer 4521 can be adjusted, thereby achieving modulation of the emitted light power.

[0080] The first active layer 4511 and the second active layer 4521 can be arranged side by side above the N-type InP layer 453, realizing monolithic integration of the light source and the modulator without additional coupling, reducing packaging difficulty and transmission loss.

[0081] In some embodiments, the light-emitting region 451 may include a first P-type InP layer 4512, which may be located above the first active layer 4511 and connected to the first active layer 4511.

[0082] In some embodiments, the light-emitting area 451 may include a first contact layer 4513, which may be located above and connected to the first P-type InP layer 4512.

[0083] In some embodiments, the light-emitting area 451 may include a first positive electrode 4553, which may be connected to the first contact layer 4513.

[0084] In some embodiments, the light-emitting region 451 may include a first trench 4514. The first trench 4514 may extend from the top of the first contact layer 4513 to the N-type InP layer 453. A passivation layer 454 may be disposed on the first trench 4514 and on one side of the first trench 4514. A first positive electrode 4553 may be disposed on the other side of the first trench 4514. The first positive electrode 4553 is a P-side electrode, which is used to receive a positive potential.

[0085] In some embodiments, the light-emitting area 451 may include a second trench 4515. The second trench 4515 may extend from the top of the first contact layer 4513 to the N-type InP layer 453. One side of the second trench 4515 is also the other side of the first trench 4514, and a first positive electrode 4553 may be disposed on one side of the second trench 4515. A passivation layer 454 may be disposed on the second trench 4515 and the other side of the second trench 4515. A first pad 4554 may be disposed above the passivation layer 454 above the other side of the second trench 4515. An electrical connection portion 4555 may be disposed above the passivation layer 454 above the second trench 4515. One end of the electrical connection portion 4555 may be electrically connected to the first positive electrode 4553, and the other end of the electrical connection portion 4555 may be electrically connected to the first pad 4554, so that the first positive electrode 4553 is electrically connected to the first pad 4554.

[0086] The N-type InP layer 453 and the first P-type InP layer 4512 are doped with different impurity elements to form a PN junction. During PN junction formation, the concentration difference of charge carriers induces diffusion. The result of this diffusion is that the first P-type InP layer 4512 contains holes and negative ions, while the N-type InP layer 453 contains electrons and positive ions. Based on the principle of charge, holes are driven downwards into the first quantum well layer, and electrons are driven upwards into the first quantum well layer. Within the first quantum well layer, stimulated emission causes the discrete electron-hole pairs to recombine, generating photons. This effectively converts electrically injected charge carriers into photons and produces gain light. The photons generated by recombination within the first quantum well layer are reflected by the resonant cavity or distributed feedback grating to form positive feedback, thereby generating lasing light.

[0087] In some embodiments, the modulation region 452 may include a second P-type InP layer 4522, which may be located above and connected to the second active layer 4521.

[0088] In some embodiments, the modulation region 452 may include a second contact layer 4523, which may be located above and connected to the second P-type InP layer 4522.

[0089] In some embodiments, the modulation region 452 may include a second positive electrode 4551, which may be connected to the second contact layer 4523.

[0090] In some embodiments, the modulation region 452 may include a third trench 4524. The third trench 4524 may extend from the top of the second contact layer 4523 to the N-type InP layer 453. A passivation layer 454 may be disposed on one side of the third trench 4524 and on the other side of the third trench 4524. A second positive electrode 4551 may be disposed on the other side of the third trench 4524. The second positive electrode 4551 is a P-side electrode, which is used to receive a positive potential.

[0091] In some embodiments, the modulation region 452 may include a fourth trench 4525. The fourth trench 4525 may extend from the top of the second contact layer 4523 to the N-type InP layer 453. One side of the fourth trench 4525 is also the other side of the third trench 4524, and a second positive electrode 4551 may be disposed on one side of the fourth trench 4525. A passivation layer 454 may be disposed on the fourth trench 4525 and the other side of the fourth trench 4525. A support portion 4541 may be disposed on the passivation layer 454 above the bottom of the fourth trench 4525. A second pad 4452 may be disposed on the support portion 4541.

[0092] In some embodiments, the support portion 4541 may be made of the same material as the passivation layer 454.

[0093] In some embodiments, the support portion 4541 may be made of a material that is not passivated.

[0094] In some embodiments, a second pad 4552 may be provided on the passivation layer 454 on the other side of the fourth trench 4525.

[0095] The light-emitting region 451 only needs to emit light upon receiving an electrical signal, without requiring consideration of high-frequency performance. The modulation region 452, however, requires high-frequency performance. In some embodiments, the modulation region 452 may include an electrical connection bridge 4561. One end of the electrical connection bridge 4561 can be connected to the second positive electrode 4551, and the other end can be connected to the second pad 4552, thus electrically connecting the second positive electrode 4551 to the second pad 4552. The electrical connection bridge 4561 can be suspended above the fourth trench 4525, shortening the electrical connection path and increasing the distance between it and the negative electrode on the lower surface of the N-type InP layer 453, reducing the capacitance between the electrodes, lowering the charging and discharging delay, and ensuring the high-frequency performance of the modulation region.

[0096] In addition to providing a laser chip, this disclosure also provides a method for fabricating the laser chip. Figure 9 This is a flowchart of a method for fabricating a laser chip according to some embodiments. Figure 10 This is a partial flow chart of a laser chip fabrication method according to some embodiments. Figure 1 .like Figure 9 and Figure 10As shown, a method for fabricating a laser chip includes: S100: A first active layer and a second active layer are grown above an N-type InP layer.

[0097] S110: The first active layer is grown above the N-type InP layer.

[0098] The first active layer includes a first quantum well layer and a grating layer, with the grating layer located above and connected to the first quantum well layer. The grating layer has a grating pattern.

[0099] (1) A first quantum well layer and a grating layer are grown on top of an N-type InP layer using MOCVD (metal-organic chemical vapor deposition) epitaxial growth technology. At this time, the grating layer does not have a grating pattern.

[0100] The first quantum well layer and grating layer were grown on top of the N-type InP layer using an epitaxial device and MOCVD (metal-organic chemical vapor deposition) epitaxial growth technology.

[0101] (2) A protective layer is uniformly coated on the grating layer. A grating pattern is made on the protective layer by holographic exposure. The grating pattern on the protective layer is transferred to the grating layer by wet etching or dry etching process. The protective layer on the surface of the substrate wafer is then removed to form a grating layer with a grating pattern.

[0102] The first position of the raster layer has a raster pattern, while the area outside the first position does not have a raster pattern. The area outside the first position may include a second position and a third position, where one end of the second position may be connected to the first position, and the other end of the second position may be connected to the third position.

[0103] Since the first position of the grating layer has a grating pattern, and the area outside the first position of the grating layer does not have a grating pattern, in order not to damage the grating pattern, the area outside the first position of the grating layer can be etched down to the second N-type InP layer.

[0104] S120: Etch down to the N-type InP layer in the region outside the first position of the first active layer.

[0105] Since the first active layer includes a first quantum well layer and a grating layer, with the grating layer located above the first quantum well layer, the region outside the first position of the grating layer is etched downwards to the N-type InP layer, that is, the region outside the first position of the first active layer is etched downwards to the N-type InP layer.

[0106] The region outside the first position of the first active layer is etched down to the N-type InP layer using a wet etching process.

[0107] S130: A second active layer is grown above an N-type InP layer.

[0108] A second active layer is grown above an N-type InP layer using an epitaxial device via MOCVD (metal-organic chemical vapor deposition) epitaxial growth technology, such that the end faces of the first and second active layers are in contact. The second active layer may include a second quantum well layer.

[0109] S200: A P-type InP layer and a contact layer are sequentially grown above both the first active layer and the second active layer.

[0110] A P-type InP layer and a contact layer are sequentially grown above the first and second active layers using MOCVD (metal-organic chemical vapor deposition) epitaxial growth technology with an epitaxial device.

[0111] S300: Etch down to the P-type InP layer in the middle of the contact layer to divide the contact layer into a first contact layer and a second contact layer that are not connected.

[0112] The second position of the contact layer corresponds to the second position of the first active layer, meaning that the projected area of ​​the second position of the contact layer is located outside the area of ​​the first active layer. The projected area of ​​the second position of the contact layer can cover the mating surface of the first and second active layers. The first and second contact layers are electrically isolated from each other, allowing for independent current injection into the first and second active layers respectively, thus avoiding current crosstalk.

[0113] The contact layer is divided into a first contact layer and a second contact layer that are not connected by photolithography and etching processes, by etching downwards to the P-type InP layer at the second position of the contact layer.

[0114] S400: The first and second contact layers are both etched downwards to the N-type InP layer to form multiple trenches.

[0115] (1) The first trench and the second trench are formed by etching down to the N-type InP layer through photolithography and etching processes in the middle of the first contact layer.

[0116] (2) The second contact layer is etched downward to the N-type InP layer through photolithography and etching processes to form the third and fourth trenches.

[0117] S500: A passivation layer is grown above multiple trenches and the platforms on both sides of the trenches to form a support portion in a trench corresponding to the second contact layer.

[0118] A passivation layer is grown above multiple trenches and the terraces on both sides of the trenches using a thin-film deposition process to form a support portion in a trench corresponding to the second contact layer. For example, a passivation layer is grown above the first trench and its two terraces, the second trench and its two terraces, the third trench and its two terraces, and the fourth trench and its two terraces using a thin-film deposition process to form a support portion in the fourth trench.

[0119] S600: Etch downwards through the middle of the passivation layer to the first contact layer and the second contact layer.

[0120] (1) Etch down to the first contact layer at the position corresponding to the first contact layer in the middle of the passivation layer.

[0121] The passivation layer is etched downwards to the first contact layer at the position corresponding to the first contact layer in the middle through photolithography and etching processes, so that the first contact layer in the middle of the laser chip is exposed, which facilitates the growth of the first positive electrode above the first contact layer.

[0122] (2) Etch downwards to the second contact layer at the position corresponding to the second contact layer in the middle of the passivation layer.

[0123] The passivation layer is etched downwards to the second contact layer at the position corresponding to the second contact layer in the middle through photolithography and etching processes, so that the second contact layer in the middle of the laser chip is exposed, which facilitates the growth of the second positive electrode above the second contact layer.

[0124] S700: A first positive electrode is grown above the first contact layer, a second positive electrode is grown above the second contact layer, a first pad and an electrical connection portion are grown above the passivation layer on one side of the first contact layer, and a second pad is grown above the support portion.

[0125] (1) A first positive electrode is grown above the first contact layer, and a first pad and electrical connection are grown above the passivation layer on one side of the first contact layer.

[0126] A first metal layer is grown above the first contact layer and above the passivation layer on one side of the first contact layer by vapor deposition / sputtering, so that a first positive electrode is grown above the first contact layer, and a first pad and electrical connection are grown above the passivation layer on one side of the first contact layer.

[0127] (2) A second positive electrode is grown above the second contact layer, and a second pad is grown above the support.

[0128] A first metal layer is grown above the second contact layer and above the support by vapor deposition / sputtering, so that a second positive electrode is grown above the second contact layer and a second pad is grown above the support.

[0129] In some embodiments, both the second positive electrode and the second pad are titanium-platinum layers.

[0130] S800: An electrical connection bridge is grown above the second positive electrode and above the second pad.

[0131] In some embodiments, the electrical connection bridge is a pure gold layer.

[0132] The second positive electrode is a titanium-platinum layer, and the electrical connection bridge is a pure gold layer. This prevents the metal in the electrical connection bridge from being oxidized, thereby avoiding affecting the electrical performance of the second positive electrode and ensuring the stability of the electrode structure.

[0133] S900: A negative electrode is grown on the lower surface of an N-type InP layer.

[0134] Figure 11 This is a partial flow chart of a laser chip fabrication method according to some embodiments. Figure 2 .like Figure 11 As shown, the growth process of a second positive electrode and a second pad includes: S610: A first photoresist and other photoresists are sequentially coated on top of the passivation layer, the support portion, and the second contact layer.

[0135] Other photoresists can form undercut structures after development.

[0136] S620: After exposure, develop with a developer to expose the support, the second contact layer, and the first photoresist in the trenches on both sides of the second contact layer.

[0137] The first photoresist is dissolved in the developer in the exposed area and insoluble in the developer in the non-exposed area, so that after exposure and development with the developer, the first photoresist in the support, the second contact layer and the trenches on both sides of the second contact layer are exposed.

[0138] (1) Use an ultraviolet exposure machine to expose the pattern on the first mask and transfer it to the topmost photoresist of other photoresists.

[0139] The purpose of exposure is to precisely transfer the circuit pattern on the mask (photomask) onto the photoresist coated on the wafer surface using a specific light source.

[0140] Exposure involves the interaction of a light source of a specific wavelength (such as ultraviolet light) with the photoresist, triggering chemical changes in the photosensitive material. In a positive photoresist, the photoacid generator in the exposed area decomposes, generating substances soluble in the developer. In a negative photoresist, the photoinitiator in the exposed area triggers a cross-linking reaction, forming an insoluble polymer network. Exposure only creates a chemical latent image in the photoresist (i.e., the physical structure is not actually formed).

[0141] Excessive exposure time leads to linewidth expansion, pattern distortion, and microbridge defects, reducing circuit performance and reliability. Insufficient exposure time results in residual colloid, linewidth reduction, and random line breaks, directly causing functional failure. This disclosure uses a UV exposure machine with the following exposure conditions: power 600±20mW, time 230ms~270s. For example, the exposure conditions are: power 600mW, time 260ms.

[0142] Exposure only alters the chemical properties of the photoresist (such as solubility), but does not directly form a pattern. To convert the chemical latent image into a usable physical structure, development is required after exposure. Development transforms the chemical latent image into a usable physical structure through the difference in dissolution / retention.

[0143] (2) Develop using developer to expose the support, the second contact layer and the first photoresist in the trenches on both sides of the second contact layer.

[0144] The purpose of development is to selectively dissolve specific areas of the photoresist using a chemical solution (developer), thereby transferring the pattern on the first mask (photomask) to the photoresist layer.

[0145] The developer (such as an organic solvent) selectively dissolves specific areas of the photoresist based on its chemical state. If the photoresist is positive, the developer dissolves the exposed areas, leaving the unexposed portions intact. If the photoresist is negative, the developer dissolves the unexposed areas, leaving the cross-linked exposed portions intact. After development, a physical texture (such as lines or holes) forms on the photoresist surface.

[0146] Excessive development time leads to oversized critical dimensions and linewidth expansion, directly causing short circuits or functional failures. Insufficient development time results in pattern erosion, linewidth loss, and structural collapse, reducing device reliability and yield. The recommended development time is 20-30 seconds. For example, a development time of 30 seconds is recommended.

[0147] After development, dry oxygen plasma is used to remove the photoresist film from the exposed and developed areas, ensuring the cleanliness of the exposed areas and preventing residual impurities from affecting the adhesion and conductivity of subsequent metal layer deposition. This also prevents problems such as electrode detachment and excessive contact resistance. The photoresist film in the exposed and developed areas refers to the photoresist that remains in these otherwise unrepelled opening areas after development.

[0148] S630: A first metal layer is grown on top of other photoresists, the second contact layer, the support, and the first photoresist.

[0149] A first metal layer is grown on top of other photoresists, a second contact layer, a support, and a first photoresist using an electron beam evaporation apparatus.

[0150] The first metal layer can be a titanium-platinum metal layer, so that both the second positive electrode and the second pad are titanium-platinum layers.

[0151] In some embodiments, the thickness of the first metal layer is less than the thickness of the undercut structure to prevent the first metal layer from covering the exposed first photoresist and the adjacent photoresist layer, thus preventing the resist remover from contacting the first photoresist and the adjacent photoresist layer and causing the resist remover to fail to complete smoothly.

[0152] S640: Remove the first photoresist and other photoresist to remove the first metal layer above the photoresist, so that a second positive electrode is formed above the second contact layer and a second pad is formed above the support.

[0153] Remove the first photoresist and other photoresists to remove the first metal layer above the photoresist, so that a second positive electrode is formed above the second contact layer and a second pad is formed above the support.

[0154] (1) Use a resist remover to remove the main resist of the first photoresist and other photoresists.

[0155] Adhesive remover can be an organic solvent or an alkaline solution. An organic solvent could be acetone, and an alkaline solution could be tetramethylammonium hydroxide.

[0156] (2) Plasma removes the residue of the first photoresist and other photoresists so that a second positive electrode is formed above the second contact layer and a second pad is formed above the support.

[0157] In some embodiments, other photoresists may include a second photoresist and a third photoresist from bottom to top. Both the exposed and unexposed areas of the second photoresist are soluble in the developer, while the exposed areas of the third photoresist are soluble in the developer, and the unexposed areas are insoluble. The width of the unexposed area of ​​the second photoresist is smaller than the width of the unexposed area of ​​the third photoresist, so that the second and third photoresists form an undercut structure after development.

[0158] Both the first and third photoresists are soluble in the developer in the exposed areas and insoluble in the developer in the non-exposed areas. This allows the first photoresist in the support, the second contact layer, and the trenches on both sides of the second contact layer to be exposed, ensuring that the support, the second contact layer, and the trenches on both sides are fully exposed, providing a clear opening outline for the subsequent deposition of the first metal layer.

[0159] In some embodiments, other photoresists may include a fourth photoresist, wherein the exposed areas of the fourth photoresist are insoluble in the developer, while the unexposed areas are soluble in the developer, so that the fourth photoresist forms an inverted trapezoid after development, i.e., the fourth photoresist forms an undercut structure after development.

[0160] The exposed area of ​​the fourth photoresist is insoluble in the developer, while the unexposed area is soluble in the developer. In contrast, the exposed area of ​​the first photoresist is soluble in the developer, while the unexposed area is insoluble in the developer. The solvent of the fourth photoresist above the second contact layer and the subsequent developer swell / dissolve the surface layer of the first photoresist that is not fully cured. Due to poor interfacial adhesion, the surface layer is washed away during development, allowing the first photoresist in the support portion, the second contact layer, and the trenches on both sides of the second contact layer to be exposed. This ensures that the support portion, the second contact layer, and the trenches on both sides are fully exposed, providing a clear opening outline for the subsequent deposition of the first metal layer.

[0161] Figure 12a This is a partial flowchart illustrating a method for fabricating a laser chip according to some embodiments. Figure 1 . Figure 12b This is a partial flowchart illustrating a method for fabricating a laser chip according to some embodiments. Figure 2 . Figure 12a Growth process for the second positive electrode and the second pad Figure 1 . Figure 12b For the first photoresist and other photoresist coating processes Figure 1 . Figure 12a and Figure 12b These are partial process diagrams of other photoresists, including the second and third photoresists from bottom to top. For example... Figure 12a and Figure 12b As shown, a growth process for a second electrode and a second pad includes: S611: A first photoresist, a second photoresist, and a third photoresist are sequentially coated on top of the passivation layer, the support portion, and the second contact layer.

[0162] S621: After exposure, develop with a developer to expose the support, the second contact layer, and the first photoresist in the trenches on both sides of the second contact layer.

[0163] (1) Using an ultraviolet exposure machine, the pattern on the first mask is transferred to the third photoresist 462.

[0164] (2) Develop using developer to expose the support 4541, the second contact layer 4523 and the first photoresist 460 in the trenches on both sides of the second contact layer 4523.

[0165] In some embodiments, the exposure area of ​​the first mask may correspond to the second contact layer and both sides of the second contact layer, so as to expose the first photoresist in the trenches on both sides of the second contact layer.

[0166] In some embodiments, the exposure area of ​​the first mask may correspond to a portion of the support portion, so that the support portion is partially exposed.

[0167] In some embodiments, the exposure area of ​​the first mask can correspond to the entire support portion, so that the entire support portion is exposed.

[0168] In some embodiments, the exposure area of ​​the first mask may correspond to the support portion and both sides of the support portion, so as to expose the first photoresist on both sides of the support portion.

[0169] The exposure area of ​​the first photomask corresponds to the second contact layer and both sides of the second contact layer. The exposure area of ​​the third photoresist is dissolved in the developer, while the non-exposure area is not dissolved in the developer. Both the exposure area and the non-exposure area of ​​the second photoresist are dissolved in the developer. The first, second, and third photoresists are arranged sequentially from bottom to top. The developer can dissolve the second and second photoresists in the two trenches of the second contact layer, so that the first photoresist in the trenches on both sides of the second contact layer can be exposed.

[0170] S631: A first metal layer is grown on top of the third photoresist, the second contact layer, the support portion, and the first photoresist.

[0171] A first metal layer 455 is grown on top of the third photoresist 462, the second contact layer 4523, the support portion 4541, and the first photoresist 460 using an electron beam evaporation apparatus.

[0172] S641: Remove the first photoresist, the second photoresist and the third photoresist to remove the first metal layer above the photoresist, so that a second positive electrode is formed above the second contact layer and a second pad is formed above the support portion.

[0173] (1) Use a resist remover to remove the main resists of the first photoresist 460, the second photoresist 461 and the third photoresist 462.

[0174] (2) Plasma removes the residue of the first photoresist 460, the second photoresist 461 and the third photoresist 462 to remove the first metal layer 455 above the photoresist, so that the second positive electrode 4551 is formed above the second contact layer 4523 and the second pad 4552 is formed above the support portion 4541.

[0175] The process of sequentially coating the first photoresist, the second photoresist, and the third photoresist above the passivation layer, the support layer, and the second contact layer is as follows: S6111: A first photoresist is coated on top of the passivation layer, the support portion, and the second contact layer.

[0176] (1) Apply a base coat to the passivation layer 454, the support 4541 and the second contact layer 4523 using an oven.

[0177] The base adhesive can ensure good adhesion between the passivation layer, the support portion, and the second contact layer and the first photoresist, preventing the first photoresist from falling off from the passivation layer, the support portion, and the second contact layer.

[0178] The base adhesive can be hexamethylsilylamine.

[0179] The steam coating temperature of the oven is 110℃~150℃. For example, the steam coating temperature of the oven is 120℃.

[0180] (2) Apply the first photoresist 460 on top of the base coat using a spin coater.

[0181] The first photoresist is a positive photoresist, meaning that the exposed areas of the first photoresist are soluble in the developer, while the unexposed areas are insoluble in the developer.

[0182] (3) Use a hot plate for heating.

[0183] A hot plate is used for baking to remove excess solvent from the first photoresist and improve its adhesion. The baking conditions are 90°C to 110°C for 2 to 3 minutes. For example, the baking conditions are 90°C for 2 minutes.

[0184] S6112: Coat a second photoresist on top of the first photoresist.

[0185] A second photoresist 461 is coated on top of the first photoresist 460 using a spin coater. Both the exposed and unexposed areas of the second photoresist are dissolved in the developer.

[0186] After coating the second photoresist, it is heated using a hot plate to remove excess solvent and improve its adhesion. The heating conditions are 150°C to 200°C for 5 to 10 minutes. For example, the heating conditions are 150°C for 5 minutes.

[0187] S6113: Coat the third photoresist on top of the second photoresist.

[0188] A third photoresist 462 is coated on top of the second photoresist 461 using a spin coater. The third photoresist is a positive photoresist, meaning that the exposed areas of the third photoresist are soluble in the developer, while the unexposed areas are insoluble in the developer.

[0189] After coating the third photoresist, it is heated using a hot plate to remove excess solvent and improve its adhesion. The heating conditions are 90°C to 110°C for 2 to 3 minutes. For example, the heating conditions are 90°C for 2 minutes.

[0190] In some embodiments, the thickness d1 of the first photoresist can be set to 2.3µm~3.0µm to avoid completely removing the first photoresist during exposure and development, thereby preventing the first metal layer from being directly deposited on the N-type InP layer. This ensures that the first metal layer can be directly deposited on the first photoresist, facilitating the removal of the first metal layer on the first photoresist when the photoresist is subsequently removed using a photoresist remover. For example, the thickness d1 of the first photoresist can be set to 2.6µm.

[0191] like Figure 12a As shown, the second photoresist 461 and the third photoresist 462 form an undercut structure after development.

[0192] The exposed areas of the third photoresist dissolve in the developer, while the unexposed areas do not. After development, the third photoresist on both sides of the second contact layer forms a trapezoidal shape. Therefore, when the first metal layer grows on top of the third photoresist after development, the first metal layer also grows on the sides of the third photoresist. In some embodiments, the thickness of the first metal layer is less than the thickness of the second photoresist to prevent the first metal layer from covering the exposed first and second photoresists. This would prevent the resist remover from contacting the first and second photoresists, resulting in unsuccessful resist removal and thus preventing the removal of the photoresist and the first metal layer above it.

[0193] In some embodiments, the thickness d2 of the second photoresist can be set to 1.0µm to 2.0µm to prevent the first metal layer from covering the exposed second photoresist, thus preventing the resist remover from contacting the second photoresist and hindering the removal process. Consequently, the photoresist and the first metal layer above it cannot be removed. For example, the thickness d2 of the second photoresist can be set to 1µm.

[0194] In some embodiments, the thickness d3 of the third photoresist can be set to 1.0µm to 2.0µm. This not only ensures that light can pass through smoothly during exposure to obtain a photolithographic pattern with the required precision, but also protects the second photoresist, preventing it from being exposed before development and thus avoiding complete dissolution of the second photoresist in the developer during development. For example, the thickness d3 of the third photoresist can be set to 1.3µm.

[0195] Among them, the thickness d1 of the first photoresist, the thickness d2 of the second photoresist, and the thickness d3 of the third photoresist are all as follows: Figure 12b As shown 。

[0196] Figure 13a This is a partial schematic diagram of a laser chip fabrication method according to some embodiments. Figure 3 . Figure 13b This is a partial schematic diagram of a laser chip fabrication method according to some embodiments. Figure 4 . Figure 13a Growth process for the second positive electrode and the second pad Figure 2 . Figure 13b For the first photoresist and other photoresist coating processes Figure 2 . Figure 13a and Figure 13b These are partial process diagrams for other photoresists, including the fourth photoresist. For example... Figure 13a and Figure 13b As shown, this disclosure provides another growth process for the second electrode and the second pad. The other growth process for the second electrode and the second pad includes: S612: A first photoresist and a fourth photoresist are sequentially coated on top of the passivation layer, the support portion, and the second contact layer.

[0197] S622: After exposure, develop with a developer to expose the support, the second contact layer, and the first photoresist in the trenches on both sides of the second contact layer.

[0198] (1) Using an ultraviolet exposure machine, the pattern on the second mask is transferred to the fourth photoresist 463.

[0199] (2) Develop using developer to expose the support 4541, the second contact layer 4523 and the first photoresist 460 in the trenches on both sides of the second contact layer 4523.

[0200] In some embodiments, the non-exposed area of ​​the second mask may correspond to the second contact layer and both sides of the second contact layer, so as to expose the first photoresist in the trenches on both sides of the second contact layer.

[0201] In some embodiments, the unexposed area of ​​the second mask may correspond to a portion of the support portion, thereby exposing a portion of the support portion.

[0202] In some embodiments, the unexposed area of ​​the second mask can correspond to the entire support portion, so that the entire support portion is exposed.

[0203] In some embodiments, the non-exposed area of ​​the second mask may correspond to the support portion and both sides of the support portion, so as to expose the first photoresist on both sides of the support portion.

[0204] S632: A first metal layer is grown on top of the fourth photoresist, the second contact layer, the support portion, and the first photoresist.

[0205] A first metal layer 455 is grown on top of the fourth photoresist 463, the second contact layer 4523, the support portion 4541, and the first photoresist 460 using an electron beam evaporation apparatus.

[0206] S642: Remove the first photoresist and the fourth photoresist to remove the first metal layer above the photoresist, so that a second positive electrode is formed above the second contact layer and a second pad is formed above the support.

[0207] (1) Use a resist remover to remove the main resists of the first photoresist 460 and the fourth photoresist 463.

[0208] (2) Plasma removes the residual photoresist 460 and 463 so that a second positive electrode 4551 is formed above the second contact layer 4523 and a second pad 4552 is formed above the support portion 4541.

[0209] The process of sequentially coating the first photoresist, the second photoresist, and the third photoresist above the passivation layer, the support layer, and the second contact layer is as follows: S6121: A first photoresist is coated on top of the passivation layer, the support portion, and the second contact layer.

[0210] (1) Apply a base coat to the passivation layer 454, the support 4541 and the second contact layer 4523 using an oven.

[0211] The base adhesive can ensure good adhesion between the passivation layer, the support, and the second contact layer and the first photoresist, preventing the first photoresist from falling off from the passivation layer, the support, and the second contact layer.

[0212] The base adhesive can be hexamethylsilylamine.

[0213] The steam coating temperature of the oven is 100℃~150℃. For example, the steam coating temperature of the oven is 120℃.

[0214] (2) Apply the first photoresist 460 on top of the base coat using a spin coater.

[0215] The first photoresist is a positive photoresist, meaning that the exposed areas of the first photoresist are soluble in the developer, while the unexposed areas are insoluble in the developer.

[0216] (3) Use a hot plate for heating.

[0217] A hot plate is used for baking to remove excess solvent from the first photoresist and improve its adhesion. The baking conditions are 90°C to 110°C for 2 to 3 minutes. For example, the baking conditions are 90°C for 2 minutes.

[0218] S6122: A fourth photoresist is coated on top of the first photoresist.

[0219] A fourth photoresist 463 is coated on top of the first photoresist 460 using a spin coater. The exposed areas of the fourth photoresist are insoluble in the developer, while the unexposed areas are soluble in the developer.

[0220] After coating the fourth photoresist on top of the first photoresist, it is heated using a hot plate to remove excess solvent from the fourth photoresist and improve its adhesion. The heating conditions are 130°C to 150°C for 1 to 2 minutes. For example, the heating conditions are 150°C for 1 minute.

[0221] like Figure 13a As shown, the fourth photoresist 463 forms an undercut structure after development.

[0222] After the fourth photoresist is developed, an undercut structure is formed. When the first metal layer is grown on top of the fourth photoresist after development, the first metal layer is not grown on the side of the fourth photoresist. In some embodiments, the thickness of the first metal layer is smaller than the thickness of the fourth photoresist to prevent the first metal layer from covering the exposed first and fourth photoresists, thus preventing the resist remover from contacting the first and fourth photoresists and causing the resist remover to fail to complete smoothly.

[0223] In some embodiments, the thickness d4 of the fourth photoresist can be set to 2.0µm to 4.0µm. This not only ensures that light can pass through smoothly during exposure to obtain a photolithographic pattern with the required precision, but also allows the fourth photoresist to form a sufficiently large undercut structure after development, preventing the first metal layer from completely covering the exposed sides of the first photoresist and ensuring that the resist remover can smoothly contact the photoresist. For example, the thickness d4 of the fourth photoresist can be set to 2.3µm.

[0224] Among them, the photoresist thickness d4 of the fourth photoresist is as follows Figure 13b As shown 。

[0225] Figure 14 This is a partial schematic diagram of a laser chip fabrication method according to some embodiments. Figure 5 .like Figure 14 As shown, this disclosure provides a growth process for an electrical connection bridge. The growth process for an electrical connection bridge includes: S810: A fifth photoresist is coated on top of the passivation layer, the second positive electrode, the support portion, and the second pad.

[0226] (1) Apply a layer of primer to the passivation layer 454, the second positive electrode 4551, the support portion 4541 and the second pad 4552 using an oven.

[0227] The base adhesive ensures good adhesion between the passivation layer, the support, the second positive electrode, and the second pad and the fifth photoresist, preventing the fifth photoresist from detaching from the passivation layer, the support, the second contact layer, and the second pad.

[0228] The base adhesive can be hexamethylsilylamine.

[0229] The steam coating temperature of the oven is 110℃~150℃. For example, the steam coating temperature of the oven is 120℃.

[0230] (2) Use a spin coater to coat the fifth photoresist 464 on top of the base coat.

[0231] The fifth photoresist is a positive photoresist, meaning that the exposed areas of the fifth photoresist are soluble in the developer, while the unexposed areas are insoluble in the developer.

[0232] (3) Use a hot plate for heating.

[0233] A hot plate is used for baking to remove excess solvent from the fifth photoresist and improve its adhesion. The baking conditions are 90°C to 110°C for 2 to 3 minutes. For example, the baking conditions are 90°C for 2 minutes.

[0234] S820: After exposure, a developing solution is used to develop the second positive electrode, the second pad, the fifth photoresist between the second positive electrode and the second pad, the fifth photoresist in the trench on the left side of the second positive electrode, the passivation layer on the left mesa of the trench on the left side of the second positive electrode, and the passivation layer on the right side of the second pad.

[0235] (1) Use an ultraviolet exposure machine to expose the pattern on the third mask and transfer it onto the fifth photoresist 464.

[0236] The exposure conditions were: power 600±20mW, time 800ms.

[0237] (2) Develop using developer to expose the second positive electrode 4551, the second pad 4552, the fifth photoresist 464 between the second positive electrode 4551 and the second pad 4552, the fifth photoresist 464 in the trench on the left side of the second positive electrode 4551, the passivation layer 454 on the left mesa of the trench on the left side of the second positive electrode 4551, and the passivation layer 454 on the right side of the second pad 4552.

[0238] The development conditions are a development time of 120s to 130s. For example, the development conditions are a development time of 125s.

[0239] In some embodiments, the non-exposed area of ​​the third mask is the entire modulation area, so that the second positive electrode, the second pad, the fifth photoresist between the second positive electrode and the second pad, the fifth photoresist in the trench on the left side of the second positive electrode, the passivation layer on the left mesa of the trench on the left side of the second positive electrode, and the passivation layer on the right side of the second pad are exposed.

[0240] In some embodiments, the fifth photoresist is exposed in the trench on the left side of the second positive electrode 4551, which facilitates the growth of the second metal layer on the fifth photoresist and avoids the second metal layer growing directly on the passivation layer. This makes it easier to remove the excess second metal layer along with the photoresist when removing the second metal layer later, ensuring that the electrical connection bridge is only retained between the second positive electrode and the second pad that need to be connected and in the preset exposed area, without leaving any excess metal structure that would affect the chip performance.

[0241] S830: The fifth photoresist is hardened by heating with a hot plate, so that the fifth photoresist between the second pad and the second positive electrode forms an arch shape.

[0242] The baking conditions are 140℃~160℃ for 1min~3min. For example, the baking conditions are 150℃ for 2min.

[0243] S840: A sixth photoresist is coated on top of the passivation layer, the fifth photoresist, the second positive electrode, and the second pad.

[0244] A sixth photoresist 465 is coated on top of the passivation layer 454, the fifth photoresist 464, the second positive electrode 4551, and the second pad 4552 using a spin coater. The sixth photoresist is a negative photoresist, meaning that the exposed areas of the sixth photoresist are insoluble in the developer, while the unexposed areas are soluble in the developer.

[0245] After coating the sixth photoresist, it is heated using a hot plate to remove excess solvent and improve its adhesion. The heating conditions are 90°C to 110°C for 2 to 3 minutes. For example, the heating conditions are 90°C for 2 minutes.

[0246] S850: After exposure, a developing solution is used to expose the second positive electrode, the second pad, the fifth photoresist in the trench on the left side of the second positive electrode, and the fifth photoresist between the second pad and the second positive electrode.

[0247] (1) Using an ultraviolet exposure machine, the pattern on the fourth mask is transferred to the fifth photoresist 464.

[0248] The exposure conditions were: power 600±20mW, time 500ms.

[0249] (2) Develop using developer to expose the second positive electrode 4551, the second pad 4552, the fifth photoresist 464 in the trench on the left side of the second positive electrode 4551, and the fifth photoresist 464 between the second pad 4552 and the second positive electrode 4551.

[0250] In some embodiments, the exposure area of ​​the fourth mask is the second positive electrode, both sides of the second positive electrode and the second pad, so as to expose the second positive electrode, the second pad, the fifth photoresist in the trench on the left side of the second positive electrode and the fifth photoresist between the second pad and the second positive electrode.

[0251] The development conditions are a development time of 40s to 60s. For example, the development conditions are a development time of 50s.

[0252] S860: A second metal layer is grown above the sixth photoresist, the second positive electrode, and the second pad.

[0253] A second metal layer 456 is grown above the sixth photoresist 465, the second positive electrode 4551, and the second pad 4552 using an electron beam evaporation apparatus.

[0254] The second metal layer can be a pure gold metal layer.

[0255] S870: Remove the fifth and sixth photoresists to remove the second metal layer on the photoresists, so that an electrical connection bridge is formed above the second positive electrode and above the second pad.

[0256] (1) Use a resist remover to remove the main resists of the fifth photoresist 464 and the sixth photoresist 465.

[0257] Adhesive remover can be an organic solvent or an alkaline solution. An organic solvent could be acetone, and an alkaline solution could be tetramethylammonium hydroxide.

[0258] (2) Plasma removes the residual photoresist 464 and 465 to form an electrical connection bridge above the second positive electrode 4551 and above the second pad 4552.

[0259] In some embodiments, the thickness d5 of the fifth photoresist can be set to 3.0µm~3.6µm to avoid completely developing away the fifth photoresist during exposure and development, thereby preventing the second metal layer from being directly deposited on the N-type InP layer. This ensures that the second metal layer can be directly deposited on the fifth photoresist, facilitating the removal of the second metal layer on the fifth photoresist when the photoresist is subsequently removed using a photoresist remover. For example, the thickness d5 of the fifth photoresist can be set to 3.5µm.

[0260] In some embodiments, the thickness d6 of the sixth photoresist can be set to 2.0µm~4.0µm. This not only ensures that light can pass through smoothly during exposure to obtain a photolithographic pattern with the required precision, but also allows the sixth photoresist to form a sufficiently large undercut structure after development, preventing the second metal layer from completely covering the exposed sides of the fifth photoresist and ensuring that the resist remover can smoothly contact the photoresist. For example, the thickness d6 of the sixth photoresist can be set to 2.3µm.

[0261] Among them, the thickness d5 of the fifth photoresist and the thickness d6 of the sixth photoresist are both as follows: Figure 14 As shown 。

[0262] In some embodiments, after development, the top of the fifth photoresist between the second positive electrode and the second pad protrudes beyond the top of the second positive electrode and the top of the second pad, such that the electrical connection bridge formed above the fifth photoresist protrudes above the second positive electrode and the second pad, ensuring that the electrical connection bridge is suspended between the second positive electrode and the second pad, further increasing the distance between the electrical connection bridge and the lower negative electrode, reducing the inter-electrode capacitance, and ensuring the high-frequency performance of the modulation region.

[0263] In some embodiments, the second positive electrode includes a titanium layer, a platinum layer, and a gold layer. The titanium layer is located above and connected to the second contact layer, the platinum layer is located above and connected to the titanium layer, and the gold layer is located above and connected to the platinum layer. This prevents the titanium layer from contacting air, prevents oxidation of the titanium layer, ensures that the second positive electrode has stable and low-resistance ohmic contact performance, avoids the degradation of the electrical performance of the second positive electrode, and thus ensures the photoelectric conversion efficiency and lifespan of the laser chip during operation.

[0264] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this disclosure, and are not intended to limit them. Although this disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this disclosure.

Claims

1. A method for fabricating a laser chip, characterized in that, include: A first active layer and a second active layer are grown above an N-type InP layer; A P-type InP layer and a contact layer are sequentially grown above both the first and second active layers; The contact layer is etched down to the P-type InP layer in the middle to divide the contact layer into a first contact layer and a second contact layer that are not connected. Multiple trenches are formed by etching downwards to the N-type InP layer between the first and second contact layers. A passivation layer is grown above multiple trenches and the platforms on both sides of the trenches to form a support portion in a trench corresponding to the second contact layer. Etch downwards through the middle of the passivation layer to the first contact layer and the second contact layer; A first positive electrode is grown above the first contact layer, a second positive electrode is grown above the second contact layer, a first pad and an electrical connection portion are grown above the passivation layer on one side of the first contact layer, and a second pad is grown above the support portion. An electrical connection bridge is grown above the second positive electrode and above the second pad; A negative electrode is grown on the lower surface of an N-type InP layer; Specifically, a second positive electrode is grown above the second contact layer, and a second pad is grown above the support portion, including: A first photoresist and other photoresists are sequentially coated on top of the passivation layer, the support portion, and the second contact layer. After exposure, a developing solution is used to develop the substrate so that the support portion, the second contact layer, and the first photoresist in the trenches on both sides of the second contact layer are all exposed. A first metal layer is grown on top of the other photoresist, the second contact layer, the support, and the first photoresist; Remove the first photoresist and other photoresist to remove the first metal layer above the photoresist, so that a second positive electrode is formed above the second contact layer and a second pad is formed above the support portion; The second positive electrode is a titanium-platinum layer, and the electrical connection bridge is a pure gold layer; other photoresists form an undercut structure after development, including a fourth photoresist, or a second and third photoresist arranged sequentially from bottom to top; the exposed areas of the first and third photoresists are soluble in the developer, while the non-exposed areas are insoluble in the developer; both the exposed and non-exposed areas of the second photoresist are soluble in the developer, while the exposed area of ​​the fourth photoresist is insoluble in the developer, and the non-exposed area is soluble in the developer; the thickness of the first metal layer is less than the thickness of the second photoresist and less than the thickness of the undercut structure.

2. The method for fabricating a laser chip according to claim 1, characterized in that, The growth of an electrical connection bridge above the second positive electrode and above the second pad includes: A fifth photoresist is coated on top of the passivation layer, the second positive electrode, the support portion, and the second pad; After exposure, a developing solution is used to develop the second positive electrode, the second pad, the fifth photoresist between the second positive electrode and the second pad, the fifth photoresist in the trench on the left side of the second positive electrode, the passivation layer on the left mesa of the trench on the left side of the second positive electrode, and the passivation layer on the right side of the second pad. The fifth photoresist is hardened by heating with a hot plate, so that the fifth photoresist between the second pad and the second positive electrode forms an arch shape. A sixth photoresist is coated on top of the passivation layer, the fifth photoresist, the second positive electrode, and the second pad; The second positive electrode, the second pad, the fifth photoresist in the trench on the left side of the second positive electrode, and the fifth photoresist between the second pad and the second positive electrode are exposed. A second metal layer is grown above the sixth photoresist, the second positive electrode, and the second pad; Remove the fifth and sixth photoresists to remove the second metal layer on the photoresists, so that an electrical connection bridge is formed above the second positive electrode and above the second pad. The fifth photoresist's exposed area dissolves in the developer, while the unexposed area does not; the sixth photoresist's exposed area does not dissolve in the developer, while the unexposed area dissolves; the thickness of the second metal layer is less than the thickness of the sixth photoresist; after development, the top of the fifth photoresist between the second positive electrode and the second pad protrudes beyond the top of the second positive electrode and the top of the second pad.

3. The method for fabricating a laser chip according to claim 1, characterized in that, Other photoresists include a second photoresist and a third photoresist arranged sequentially from bottom to top. The first photoresist, the second photoresist, and the third photoresist are sequentially coated above the passivation layer, the support portion, and the second contact layer, including: A first photoresist is coated over the passivation layer, the support portion, and the second contact layer; A second photoresist is coated on top of the first photoresist; A third photoresist is coated on top of the second photoresist; Other photoresists include a fourth photoresist, which is applied sequentially over the passivation layer, the support layer, and the second contact layer, including: A first photoresist is coated over the passivation layer, the support portion, and the second contact layer; A fourth photoresist is coated on top of the first photoresist.

4. The method for fabricating a laser chip according to claim 1, characterized in that, Other photoresists include a second photoresist and a third photoresist arranged sequentially from bottom to top. The thickness of the first photoresist is 2.3 μm to 3.0 μm, the thickness of the second photoresist is 1.0 μm to 2.0 μm, and the thickness of the third photoresist is 1.0 μm to 2.0 μm. Other photoresists include a fourth photoresist, wherein the thickness of the first photoresist is 2.3 μm to 3.0 μm, and the thickness of the fourth photoresist is 2.0 μm to 4.0 μm.

5. The method for fabricating a laser chip according to claim 2, characterized in that, The thickness of the fifth photoresist is 3.0um to 3.6um, and the thickness of the sixth photoresist is 2.0um to 4.0um.

6. The method for fabricating a laser chip according to claim 3, characterized in that, A first photoresist is coated over the passivation layer, the support portion, and the second contact layer, including: Apply a base coat over the passivation layer, the support layer, and the second contact layer using an oven. A first photoresist is applied on top of the base adhesive using a spin coater; Heat drying is performed using a hot plate.

7. The method for fabricating a laser chip according to claim 2, characterized in that, The fifth photoresist is hardened by heating with a hot plate at 140℃~160℃ for 1min~3min.

8. The method for fabricating a laser chip according to claim 1, characterized in that, Removal of the first photoresist and other photoresists, including: Use a resist remover to remove the main resist from the first photoresist and other photoresists; Plasma removes residual photoresist from the first photoresist and other photoresists.

9. The method for fabricating a laser chip according to claim 1, characterized in that, The second positive electrode includes: A titanium layer is located above the second contact layer and is connected to the second contact layer; A platinum layer is located above and connected to the titanium layer; A gold layer is located above and connected to the platinum layer.

10. A laser chip, characterized in that, The laser chip is used to generate optical signals and is prepared by the method described in any one of claims 1-9.

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