A relay protection device data preprocessing and cooperative control system and method
Patent Information
- Application Number
- CN202610730554.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-05-26
- Publication Date
- 2026-08-21
AI Technical Summary
[0002]当前继电保护装置核心数据处理单元主流采用CPU+MCU、CPU+FPGA两种架构，其中，CPU+MCU架构中，MCU辅助CPU完成基础数据处理，但两者协同时延较高，且MCU自身数据处理能力有限，无法承担复杂的数据处理任务；CPU+FPGA架构应用最为广泛，虽能承担模拟量采集、高速信号滤波等功能，但随着电力行业对装置实时性、可靠性、低功耗及运维便捷性要求的不断提升，其资源浪费、功耗偏高、开发维护繁琐的缺陷日益凸显
[0024]本发明提供一种继电保护装置数据预处理及协同控制系统及方法，通过定制化ASIC硬件模块实现核心数据处理与接口扩展功能，结合逻辑芯片的协同调度，构建完整的“采集-预处理-计算-控制-交互”闭环体系，提升继电保护装置的实时性、可靠性与环境适应性。本发明通过ASIC模块中的硬件化数据采集模块大幅降低数据处理时延，结合CPU模块高效的保护计算与逻辑判断能力，可满足高压智能变电站的速动性要求。相较于同功能的FPGA和MCU，本发明通过ASIC 具备低功耗特性，有效降低装置散热压力，解决现有架构发热较为严重、影响整装置运行寿命的问题。本发明通过ASIC模块无需固件升级，仅需CPU模块配置参数，现场运维人员无需掌握FPGA开发技术、MCU调试技巧，且ASIC模块预先烧写逻辑，无需生产时单独烧录，大幅简化生产与运维流程，降低维护难度。
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Figure CN122620366A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of power system relay protection technology, specifically relating to a data preprocessing and collaborative control system and method for relay protection devices. It is applicable to protection, measurement and control, and stability control devices in smart substations and conventional substations, realizing high-speed preprocessing of power data, real-time protection logic operation, and reliable control output. Background Technology
[0002] Currently, the core data processing units of relay protection devices mainly adopt two architectures: CPU+MCU and CPU+FPGA. In the CPU+MCU architecture, the MCU assists the CPU in completing basic data processing, but the collaboration latency between the two is relatively high, and the MCU's own data processing capability is limited, making it unable to handle complex data processing tasks. The CPU+FPGA architecture is the most widely used. Although it can handle functions such as analog signal acquisition and high-speed signal filtering, its shortcomings of resource waste, high power consumption, and cumbersome development and maintenance are becoming increasingly prominent as the power industry continues to increase its requirements for the real-time performance, reliability, low power consumption, and ease of operation and maintenance of devices.
[0003] Application-specific integrated circuits (ASICs) offer advantages such as customized hardware logic, high integration, low power consumption, and ease of maintenance, effectively addressing the inherent shortcomings of the aforementioned two architectures. This invention uses an ASIC as the data acquisition and control core and a general-purpose CPU processor as the main control core to construct a "CPU+ASIC" heterogeneous collaborative architecture. This solves key issues in the design of dedicated ASIC hardware modules and their efficient collaboration with the CPU, overcoming the limitations of existing technologies. Summary of the Invention
[0004] The purpose of this invention is to provide a data preprocessing and collaborative control system and method for relay protection devices. By implementing core data processing and interface expansion functions through customized ASIC hardware modules, and combining the collaborative scheduling of logic chips, a complete closed-loop system of "acquisition-preprocessing-computation-control-interaction" is constructed to improve the real-time performance, reliability and environmental adaptability of relay protection devices.
[0005] On one hand, the present invention provides a data preprocessing and collaborative control system for a relay protection device, including a CPU module, an ASIC module, and a logic chip module. The CPU module, ASIC module, and logic chip module establish a bidirectional communication connection. The logic chip module is electrically connected to the CPU module and ASIC module respectively to realize signal transfer and timing coordination between modules. The CPU module is used to perform relay protection management scheduling, data operation, and instruction issuance. The ASIC module is used to perform core logic operation and fast signal processing of the relay protection. The CPU module, ASIC module, and logic chip module collaboratively constitute the hardware processing architecture of the relay protection device.
[0006] This invention significantly reduces data processing latency by using a hardware-based data acquisition module in the ASIC module, and combined with the CPU module's efficient protection calculation and logic judgment capabilities, it can meet the speed requirements of high-voltage intelligent substations.
[0007] In the aforementioned relay protection device data preprocessing and collaborative control system, the CPU module and ASIC module establish a direct communication link through a dedicated data bus to achieve high-speed interaction between control commands and computational data.
[0008] The aforementioned relay protection device data preprocessing and collaborative control system uses a dedicated data bus that combines parallel and serial transmission to adapt to the transmission requirements of different types of data.
[0009] In the aforementioned relay protection device data preprocessing and collaborative control system, the logic chip module has a built-in timing control unit that synchronously matches the working clocks of the CPU module and the ASIC module to ensure consistent data transmission timing.
[0010] In the aforementioned relay protection device data preprocessing and collaborative control system, the ASIC module is equipped with a dedicated relay protection calculation circuit, which is used to quickly calculate current and voltage electrical quantities and identify faults.
[0011] In the aforementioned relay protection device data preprocessing and collaborative control system, the CPU module is equipped with a storage unit for storing relay protection settings, operating parameters, and fault data.
[0012] This invention eliminates the need for firmware upgrades by using an ASIC module, requiring only CPU module configuration parameters. On-site maintenance personnel do not need FPGA development skills or MCU debugging techniques. Furthermore, the ASIC module has its logic pre-programmed, eliminating the need for separate programming during production, significantly simplifying production and maintenance processes and reducing maintenance difficulty.
[0013] In the aforementioned relay protection device data preprocessing and collaborative control system, the CPU module, ASIC module, and logic chip module adopt a modular integrated layout, and the modules are detachably connected through standardized interfaces.
[0014] Secondly, the present invention provides a method for data preprocessing and coordinated control of a relay protection device, comprising:
[0015] The CPU module sends control instructions and computational tasks to the logic chip module;
[0016] After the logic chip module completes instruction verification and task parsing, it distributes the corresponding instructions and tasks to the ASIC module.
[0017] The ASIC module performs core logic operations and sends the results back to the logic chip module.
[0018] After verifying the calculation results, the logic chip module transmits them to the CPU module for subsequent processing, realizing the whole-process collaborative control of data interaction, task scheduling and instruction verification.
[0019] In the aforementioned relay protection device data preprocessing and collaborative control method, during the instruction issuance and data feedback process, the logic chip module simultaneously completes instruction validity verification, data integrity verification, and timing calibration operations.
[0020] The aforementioned data preprocessing and collaborative control method for relay protection devices also includes: establishing a hierarchical scheduling mechanism for real-time protection tasks and non-real-time management tasks;
[0021] When the ASIC module detects an anomaly and triggers an interrupt, the CUP module suspends non-real-time tasks and prioritizes the execution of real-time tasks such as protection calculations and logic judgments to ensure rapid fault response and handling.
[0022] When there is no fault, the CPU module is mainly used to perform non-real-time management tasks such as event logging, waveform storage, human-machine interaction, and remote communication. The CPU module reads the sampled data cached by the ASIC module and the inter-board interaction data through the high-speed data bus, and allocates resources reasonably to ensure the priority execution of real-time protection tasks.
[0023] Compared with the prior art, the beneficial effects of the present invention are as follows:
[0024] This invention provides a data preprocessing and collaborative control system and method for relay protection devices. It utilizes a customized ASIC hardware module to implement core data processing and interface expansion functions. Combined with the collaborative scheduling of logic chips, it constructs a complete closed-loop system of "acquisition-preprocessing-calculation-control-interaction," improving the real-time performance, reliability, and environmental adaptability of the relay protection device. This invention significantly reduces data processing latency through a hardware-based data acquisition module within the ASIC module. Combined with the efficient protection calculation and logic judgment capabilities of the CPU module, it meets the speed requirements of high-voltage smart substations. Compared to FPGAs and MCUs with similar functions, this invention, through the low-power characteristics of the ASIC, effectively reduces the heat dissipation pressure of the device, solving the problem of severe heat generation in existing architectures that affects the overall lifespan of the device. This invention eliminates the need for firmware upgrades through the ASIC module; only CPU module configuration parameters are required. On-site maintenance personnel do not need to master FPGA development technology or MCU debugging skills. Furthermore, the ASIC module has pre-programmed logic, eliminating the need for separate programming during production, greatly simplifying production and maintenance processes and reducing maintenance difficulty. Attached Figure Description
[0025] Figure 1 This is a schematic diagram of the hardware framework of a data preprocessing and collaborative control system for a relay protection device in Embodiment 1 of the present invention. Detailed Implementation
[0026] The technical solution of the present invention will be described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the embodiments of the present invention and the specific features in the embodiments are detailed descriptions of the technical solution of the present invention, rather than limitations thereof. In the absence of conflict, the embodiments of the present invention and the technical features in the embodiments can be combined with each other.
[0027] The term "and / or" simply describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone. Additionally, the character " / " generally indicates that the preceding and following related objects have an "or" relationship.
[0028] Example 1:
[0029] like Figure 1 As shown, this embodiment provides a data preprocessing and collaborative control system for a relay protection device, including: a CPU module, an ASIC module, and a logic chip module. A bidirectional communication connection is established between the CPU module, the ASIC module, and the logic chip module. The logic chip module is electrically connected to both the CPU module and the ASIC module to achieve signal transfer and timing coordination between modules. The CPU module is used to perform relay protection management scheduling, data computation, and instruction issuance. The ASIC module is used to perform core logic computation and rapid signal processing for relay protection. The CPU module, ASIC module, and logic chip module collaboratively constitute the hardware processing architecture of the relay protection device.
[0030] Specifically, this includes hardware implementation and software implementation, wherein the hardware implementation includes:
[0031] ASIC selection: It integrates 16KB on-chip RAM, serial interface, 2 ST optical ports, 2 FC optical ports, 4 LC 100M optical Ethernet ports, and PCIe, RGMII, and SPI interaction interfaces. It is designed with 2 groups of ADCs, with 3 chips in each group, and supports a maximum of 48 channels of sampling.
[0032] CPU Selection: Adopts a high-performance ARM architecture processor with a main frequency of ≥1.5GHz, configured with 12GB DDR4 memory and 16GB eMMC flash memory, running an RTOS operating system, specifically responsible for protection calculation, logic judgment, event logging, waveform recording and storage, and supports working in conjunction with ASIC's PCIe, RGMII and SPI interfaces.
[0033] The software implementation includes:
[0034] CPU Driver: Develop ASIC-specific drivers that adapt to the PCIe, RGMII, and SPI interfaces between general-purpose CPU processors and ASICs, enabling data transmission and reception, interrupt handling, and parameter configuration. The driver code is compatible with Linux / RTOS operating systems, ensuring conflict-free collaboration between multiple interfaces.
[0035] Protection algorithm program: The protection calculation and logic judgment program is developed based on the CPU processor. It is adapted to the AD sampling data uploaded by ASIC and converted by the synchronous analog-to-digital converter chip to realize distance protection, differential protection, zero sequence protection and other algorithms. The algorithm execution delay is ≤1ms.
[0036] Data management program: Based on the CPU processor, it implements event logging, waveform recording and storage, remote communication, and human-computer interaction functions. It reads the sampled data from the ASIC cache through the SPI interface to complete data storage and reporting.
[0037] ASIC configuration program: It issues configuration commands through the CPU processor's PCIe interface to configure various ASIC interface functions, calibrate sampling parameters, set interface priorities, etc., to ensure adaptability to different application scenarios.
[0038] The ASIC employs customized hardware modules, specifically including:
[0039] Analog Input Module: The backplane receives 48 analog inputs. These inputs pass through a low-pass filter circuit and are then fed into a synchronous analog-to-digital converter (ADC). The ADC transmits the converted data to the ASIC via a serial interface. The ASIC is designed with two sets of ADCs, each containing three ADCs, supporting a maximum of 48 channels. The sampled data converted by the ADCs is transmitted to the ASIC in real-time via the serial interface, buffered in the ASIC's on-chip RAM, and then synchronously transmitted to the general-purpose CPU processor via the SPI interface, ensuring the real-time performance and integrity of the sampled data. Simultaneously, a sampling calibration unit and an anomaly detection unit are integrated. Built-in hardware calibration logic allows the general-purpose CPU processor to issue calibration commands via the SPI interface, enabling dynamic calibration of sampling accuracy and preventing sampling deviations caused by long-term operation. An integrated sampling anomaly detection unit immediately sends an alarm signal to the general-purpose CPU processor via the PCIe interface if the sampled data exceeds a preset range, and simultaneously activates a backup sampling channel to ensure continuous sampling.
[0040] Extended communication interface module: ASIC serves as the core implementation carrier of the extended communication interface. In addition to meeting the multi-interface interaction with the general-purpose CPU processor, it focuses on implementing the following extended interface functions: (1) 2-channel ST optical port: One channel is an optional function that can be configured as optical serial port output or input according to the actual scenario. It supports RS232 / RS485 protocols and is compatible with the access and data transmission of various optical serial port devices on site. The other channel has a fixed function and is only used for optical serial port input. It is specifically used to receive control commands or status signals sent by external devices to ensure the specificity and reliability of the input signal. (2) 2-channel FC optical longitudinal interface: It integrates the FC optical longitudinal interface hard core, supports optical fiber longitudinal protection communication, transmission rate ≥100Mbps, and transmission distance ≥20km. It meets the requirements of long-distance relay protection signal transmission; it has built-in optical signal detection and redundancy switching logic, and automatically switches to another channel when the signal of one interface is abnormal, so as to ensure the continuous communication of longitudinal protection; (3) 4-channel LC 100M optical Ethernet interface: supports 100M speed transmission, adapts to the Ethernet networking of smart substations, and can realize high-speed data interaction with merging units, smart terminals and other devices; the 4 interfaces work independently and do not interfere with each other, support priority configuration, and can set the protection data transmission interface to the highest priority through the general CPU processor to ensure that data is transmitted first when there is a fault; it has a built-in Ethernet link detection unit to monitor the link status in real time, and immediately feeds back alarm information to the general CPU processor through the RGMII interface when the link is interrupted, which is convenient for operation and maintenance to troubleshoot.
[0041] High-speed interface adapter module: Specifically adapted to the PCIe, RGMII and SPI interfaces for data interaction between general-purpose CPU processors and ASICs. Specifically implemented: (1) PCIe interface unit: Supports PCIe 3.0 protocol, transmission rate ≥1Gbps, mainly used for high-speed data interaction to ensure fast transmission of large data volumes; built-in CRC32 check logic to ensure data transmission is error-free and avoid data loss or bit errors; (2) RGMII interface unit: Supports 1000Mbps high-speed Ethernet transmission, mainly used for ASIC to transmit batch sampling data and interface status information to general-purpose CPU processors, and works in conjunction with 4-channel LC 100Mbps optical Ethernet interfaces; built-in bus arbitration logic, with a priority lower than the PCIe interface to avoid data transmission conflicts; (3) SPI interface unit: Supports SPI 4.0 protocol, transmission rate ≥50Mbps, mainly used for general-purpose CPU processors to read cached sampling data in the ASIC's on-chip RAM for event recording and waveform storage; adopts master-slave mode, with the general-purpose CPU processor as the master device initiating the read command to ensure active and reliable data reading.
[0042] Power module: It adopts a DC-DC chip to realize power timing control of ASIC and general CPU processor, adapt to the low power consumption characteristics of ASIC, and ensure stable power supply for various interfaces and modules;
[0043] Interface module: It is equipped with ST, FC and LC optical connectors. The small panel side integrates 4 LC 100M optical Ethernet ports, 2 ST optical ports, 2 FC optical longitudinal interfaces and 1 RJ45 debugging network port. The back panel side supports multiple function buses to adapt to the networking requirements of smart substations.
[0044] Auxiliary module: Configures fault alarm indicator lights, driven by ASIC, to display the operating status in real time; backup power module, which supplies power to the ASIC's on-chip RAM when power is lost, ensuring that fault data is not lost.
[0045] Example 2:
[0046] Based on the relay protection device data preprocessing and collaborative control system provided in Embodiment 1, this embodiment provides a relay protection device data preprocessing and collaborative control method, including: the CPU module sending control instructions and calculation tasks to the logic chip module;
[0047] After the logic chip module completes instruction verification and task parsing, it distributes the corresponding instructions and tasks to the ASIC module.
[0048] The ASIC module performs core logic operations and sends the results back to the logic chip module.
[0049] After verifying the calculation results, the logic chip module transmits them to the CPU module for subsequent processing, realizing the whole-process collaborative control of data interaction, task scheduling and instruction verification.
[0050] During the instruction issuance and data feedback process, the logic chip module simultaneously completes instruction validity verification, data integrity verification, and timing calibration operations.
[0051] The relay protection device data preprocessing and collaborative control method also includes: establishing a hierarchical scheduling mechanism for real-time protection tasks and non-real-time management tasks;
[0052] When the ASIC module detects an anomaly and triggers an interrupt, the CUP module suspends non-real-time tasks and prioritizes the execution of real-time tasks such as protection calculations and logic judgments to ensure rapid fault response and handling.
[0053] When there is no fault, the CPU module is mainly used to perform non-real-time management tasks such as event logging, waveform storage, human-machine interaction, and remote communication. The CPU module reads the sampled data cached by the ASIC module and the inter-board interaction data through the high-speed data bus, and allocates resources reasonably to ensure the priority execution of real-time protection tasks.
[0054] The embodiments of the present invention have been described above with reference to the accompanying drawings. However, the present invention is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of the present invention without departing from the spirit and scope of the claims. All of these forms are within the protection scope of the present invention.
Claims
1. A data preprocessing and collaborative control system for a relay protection device, comprising a CPU module, an ASIC module, and a logic chip module, characterized in that, A bidirectional communication connection is established between the CPU module, the ASIC module, and the logic chip module. The logic chip module is electrically connected to the CPU module and the ASIC module respectively to realize signal transfer and timing coordination between modules. The CPU module is used to perform relay protection management scheduling, data operation and instruction issuance. The ASIC module is used to perform relay protection core logic operation and fast signal processing. The CPU module, ASIC module and logic chip module work together to form the hardware processing architecture of the relay protection device.
2. The data preprocessing and collaborative control system for relay protection devices according to claim 1, characterized in that, The CPU module and the ASIC module establish a direct communication link through a dedicated data bus to enable high-speed interaction between control instructions and computational data.
3. The relay protection device data preprocessing and collaborative control system according to claim 2, characterized in that, The dedicated data bus adopts a communication mode that combines parallel and serial transmission to adapt to the transmission needs of different types of data.
4. The data preprocessing and collaborative control system for relay protection devices according to claim 1, characterized in that, The logic chip module has a built-in timing control unit that synchronizes and matches the operating clocks of the CPU module and the ASIC module to ensure consistent data transmission timing.
5. The data preprocessing and collaborative control system for relay protection devices according to claim 1, characterized in that, The ASIC module is equipped with a dedicated relay protection calculation circuit, which is used to quickly calculate current and voltage electrical quantities and identify faults.
6. The data preprocessing and collaborative control system for relay protection devices according to claim 1, characterized in that, The CPU module is equipped with a storage unit for storing relay protection settings, operating parameters, and fault data.
7. The data preprocessing and collaborative control system for relay protection devices according to claim 1, characterized in that, The CPU module, ASIC module, and logic chip module adopt a modular integrated layout, and the modules are detachably connected through standardized interfaces.
8. A method for data preprocessing and collaborative control of a relay protection device, applied to the data preprocessing and collaborative control system of the relay protection device as described in any one of claims 1-7, characterized in that, include: The CPU module sends control instructions and computational tasks to the logic chip module; After the logic chip module completes instruction verification and task parsing, it distributes the corresponding instructions and tasks to the ASIC module. The ASIC module performs core logic operations and sends the results back to the logic chip module. After verifying the calculation results, the logic chip module transmits them to the CPU module for subsequent processing, realizing the whole-process collaborative control of data interaction, task scheduling and instruction verification.
9. The data preprocessing and collaborative control method for relay protection devices according to claim 8, characterized in that, During the instruction issuance and data feedback process, the logic chip module simultaneously completes instruction validity verification, data integrity verification, and timing calibration operations.
10. The data preprocessing and collaborative control method for relay protection devices according to claim 8, characterized in that, This also includes: establishing a hierarchical scheduling mechanism for real-time protection tasks and non-real-time management tasks; When the ASIC module detects an anomaly and triggers an interrupt, the CUP module suspends non-real-time tasks and prioritizes the execution of real-time tasks such as protection calculations and logic judgments to ensure rapid fault response and handling. When there is no fault, the CPU module is mainly used to perform non-real-time management tasks such as event logging, waveform storage, human-machine interaction, and remote communication. The CPU module reads the sampled data cached by the ASIC module and the inter-board interaction data through the high-speed data bus, and allocates resources reasonably to ensure the priority execution of real-time protection tasks.