An under-voltage lockout circuit and an IGBT drive circuit

Abstract

The application provides an under-voltage locking circuit and an IGBT driving circuit. The under-voltage locking circuit comprises a signal generation module, a driving module and a gate detection module. The signal generation module is connected with the driving module through a voltage stabilizing module. The voltage stabilizing module generates a reference voltage from an input power supply and transmits the reference voltage to the signal generation module, the driving module and the gate detection module. The signal generation module detects a system supply voltage based on the reference voltage and outputs an under-voltage locking control signal. The driving module outputs an IGBT driving voltage according to the locking control signal. The gate detection module collects the IGBT gate side driving voltage in real time with the reference voltage. The system supply voltage, the IGBT driving voltage and the gate voltage can be monitored in real time, the limitation of traditional circuit sampling of a single power supply is broken, and any abnormal voltage can be captured and controlled by the circuit to drive the output. The IGBT overheat, damage and failure hidden danger caused by the abnormal voltage of multiple paths can be avoided.

Description

Technical Field

[0001] This application relates to the field of IGBT drive circuit technology, and in particular to an undervoltage lockout circuit and an IGBT drive circuit. Background Technology

[0002] Undervoltage lockout circuits are key modules in IGBT drive and protection systems. They are used to monitor the system supply voltage, IGBT drive voltage, and gate voltage status to prevent IGBT conduction losses from increasing, overheating, operating in the amplification region, or even device burnout due to insufficient voltage. They are widely used in power electronic systems such as photovoltaic inverters, new energy vehicles, industrial converters, and rail transportation.

[0003] Traditional undervoltage lockout circuits only monitor a single power supply and cannot simultaneously achieve comprehensive real-time monitoring of IGBT drive voltage, gate voltage, and system power supply voltage, making it difficult to fully avoid the risk of IGBT failure caused by multiple voltage anomalies. Summary of the Invention

[0004] The technical problem this application aims to solve is that traditional undervoltage lockout circuits only monitor a single power supply, making it impossible to simultaneously achieve comprehensive real-time monitoring of IGBT drive voltage, gate voltage, and system power supply voltage, and thus making it difficult to fully avoid the risk of IGBT failure caused by multiple voltage anomalies.

[0005] To address the aforementioned issues, this application provides an undervoltage lockout circuit and an IGBT drive circuit.

[0006] In a first aspect, the present invention discloses an undervoltage lockout circuit, which includes a voltage regulator module, a signal generation module, a driving module and a gate detection module. The voltage regulator module is connected to the signal generation module and the driving module respectively, and the driving module is connected to the gate detection module. The voltage regulator module acquires the power supply voltage, generates a reference voltage, and transmits it to the signal generation module, the drive module, and the gate detection module. The signal generation module detects the power supply voltage based on the reference voltage and generates a lockout control signal. The drive module outputs a drive voltage based on the control signal, and the gate detection module detects the drive voltage based on the reference voltage.

[0007] Preferably, the signal generation module includes a voltage detection unit, a comparator unit, and a logic conversion unit. The voltage regulation module is connected to the comparator unit and the logic conversion unit respectively. The voltage detection unit is connected to the comparator unit, and the comparator unit is connected to the logic conversion unit. The voltage detection unit acquires the power supply voltage and outputs a sampled voltage. The comparator unit acquires the reference voltage generated by the voltage regulator module and compares it with the sampled voltage output by the voltage detection unit, outputting a comparison signal. The logic conversion unit generates a lockout control signal based on the comparison signal.

[0008] Preferably, it includes a time delay condition recovery module, which is connected to the signal generation module. The lock control signal is transmitted to the time delay condition recovery module to generate a reset signal.

[0009] Preferably, the driving module includes a driving control unit and a gate driving unit. The driving control unit is connected to the gate driving unit, the gate driving unit is connected to the gate detection module, and the driving control unit is connected to the delay condition recovery module and the logic conversion unit, respectively.

[0010] Preferably, the gate drive unit includes a high-speed comparator and a non-inverting amplifier, the high-speed comparator is connected to the through amplifier, and the high-speed comparator is connected to a three-input AND gate and a voltage regulator module respectively.

[0011] Preferably, the drive control unit includes an RS latch and a three-input AND gate. The RS latch is connected to the three-input AND gate. The RS latch receives a reset signal and a lock control signal, and outputs a latch signal. The three-input AND gate acquires the external control signal, the latch signal output by the RS latch, and the lock control signal.

[0012] Preferably, the voltage detection unit includes a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a first resistor, and a second resistor. The first PMOS transistor is connected to the second PMOS transistor, the first NMOS transistor is connected to the first PMOS transistor and the third NMOS transistor, the third NMOS transistor is connected to the second NMOS transistor and the fourth NMOS transistor, one end of the first resistor is connected to the power supply voltage, the other end of the first resistor is connected to one end of the second resistor and the gate of the third NMOS transistor, and the other end of the second resistor is grounded.

[0013] Preferably, the gate detection module includes a detection comparator and a detection tube, the detection tube being connected to the output terminal of the gate driving unit, and the detection comparator acquiring the driving voltage and the reference voltage respectively.

[0014] Preferably, the voltage regulator module includes a common source cascode bandgap reference subunit and an error amplifier subunit, which are connected together.

[0015] Secondly, the present invention discloses an IGBT driving circuit, which includes the undervoltage lockout circuit described above.

[0016] The technical solution provided in this application has the following advantages compared with the prior art: This application provides an undervoltage lockout circuit and an IGBT drive circuit. The undervoltage lockout circuit mentions that a voltage regulator module is connected to both a signal generation module and a drive module, and the drive module is connected to a gate detection module. The voltage regulator module generates a reference voltage from the input power supply and sends it to the signal generation module, drive module, and gate detection module. The signal generation module uses the reference voltage to detect the system power supply voltage and outputs an undervoltage lockout control signal. The drive module outputs the IGBT drive voltage based on the lockout control signal. The gate detection module uses the reference voltage to acquire the IGBT gate-side drive voltage in real time. This allows for simultaneous real-time monitoring of the system power supply voltage, IGBT drive voltage, and gate voltage, breaking the limitation of traditional circuits that only sample a single power supply. Any voltage anomaly can be detected by the circuit and the drive output can be controlled accordingly, comprehensively avoiding the potential for IGBT overheating and damage caused by multiple voltage anomalies.

[0017] The IGBT driver circuit mentions that it integrates the aforementioned undervoltage lockout circuit. Relying on the all-dimensional voltage monitoring capability of the undervoltage lockout circuit, it improves the protection architecture of the IGBT driver system. In various fault scenarios such as power supply undervoltage, drive abnormality, and gate open circuit, it promptly locks out the IGBT drive, thereby improving the operational stability and fault protection capability of the entire IGBT driver circuit. Attached Figure Description

[0018] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention.

[0019] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, those skilled in the art can obtain other drawings based on these drawings without creative effort.

[0020] Figure 1 A structural block diagram of an undervoltage lockout circuit provided in this application; Figure 2 A circuit diagram of an undervoltage lockout circuit provided in this application; Figure 3 A circuit diagram of a voltage regulator module for an undervoltage lockout circuit provided in this application; Figure 4 A block diagram of a signal generation module for an undervoltage lockout circuit provided in this application; Figure 5 A circuit diagram of a voltage detection unit for an undervoltage lockout circuit provided in this application; Figure 6 The response diagram of the power supply voltage VDD of the voltage detection unit of the undervoltage lockout circuit provided in this application; Figure 7 A schematic diagram comparing the response of a high-speed comparator and a conventional comparator in an undervoltage lockout circuit provided in this application; Figure 8 A circuit diagram of the logic conversion unit of an undervoltage lockout circuit provided in this application; Figure 9 A flowchart of an algorithm for a delay condition recovery module of an undervoltage lockout circuit provided in this application; Figure 10 A schematic diagram of the connection structure of the drive control unit, gate drive unit and gate detection module of an undervoltage lockout circuit provided in this application; Figure 11 A circuit diagram of a drive control unit for an undervoltage lockout circuit provided in this application; Figure 12 A circuit diagram of the gate drive unit of an undervoltage lockout circuit provided in this application; Figure 13 A comparison diagram of the gate voltage response of the gate detection module of the undervoltage lockout circuit provided in this application to the gate voltage of the IGBT and the response of the key signal following VDD; Figure 14 A circuit diagram of a gate detection module for an undervoltage lockout circuit provided in this application.

[0021] Explanation of reference numerals in the attached figures: 1. Undervoltage lockout circuit; 11. Voltage regulator module; 111. Common source cascode bandgap reference subunit; 112. Error amplifier subunit; 12. Signal generation module; 121. Voltage detection unit; 122. Comparator unit; 123. Logic conversion unit; 13. Driver module; 131. Drive control unit; 1311. RS latch; 1312. Three-input AND gate; 132, Gate drive unit; 1321, High-speed comparator; 1322, Non-inverting amplifier; 14. Gate detection module; 141. Detection comparator; 142. Detection tube; 15. Delay condition recovery module. Detailed Implementation

[0022] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0023] Firstly, see Figures 1-14 This invention discloses an undervoltage lockout circuit 1, which includes a voltage regulator module 11, a signal generation module 12, a driving module 13, and a gate detection module 14. The voltage regulator module 11 is connected to the signal generation module 12 and the driving module 13, and the driving module 13 is connected to the gate detection module 14. The voltage regulator module 11 acquires the power supply voltage, generates a reference voltage, and transmits it to the signal generation module 12, the driving module 13, and the gate detection module 14. The signal generation module 12 detects the power supply voltage based on the reference voltage and generates a lockout control signal UVLO_Ctrl. The driving module 13 outputs a driving voltage based on the control signal, and the gate detection module 14 detects the driving voltage based on the reference voltage.

[0024] Specifically, the voltage regulator module 11 is connected to the signal generation module 12 and the drive module 13, respectively. The drive module 13 is connected to the gate detection module 14. The voltage regulator module 11 generates a reference voltage from the input power supply and sends it to the signal generation module 12, the drive module 13, and the gate detection module 14. The signal generation module 12 uses the reference voltage to detect the system power supply voltage and outputs an undervoltage lockout control signal. The drive module 13 outputs the IGBT drive voltage according to the lockout control signal. The gate detection module 14 uses the reference voltage to collect the IGBT gate-side drive voltage in real time. It can simultaneously perform real-time monitoring of the system power supply voltage, IGBT drive voltage, and gate voltage, breaking the limitation of traditional circuits that only sample a single power supply. Any abnormal voltage can be captured by the circuit and the drive output can be controlled in conjunction, comprehensively avoiding the risk of IGBT overheating and damage caused by multiple abnormal voltages.

[0025] Furthermore, in addition to providing a reference voltage, the voltage regulator module 11 also provides a regulated power supply VLDO to provide a stable power supply for the signal generation module 12.

[0026] The voltage regulator module 11 includes a common-source cascode bandgap reference subunit 111 and an error amplifier subunit 112, which are connected together. Specifically, the voltage regulator module 11 can be divided into two parts: a common-source cascode bandgap reference and an error amplifier. To obtain a stable power supply voltage, the PSRR, PPM, and noise of the voltage regulator module 11 cannot be ignored. For the LDO voltage regulator module 11 system, bandgap reference voltage noise is one of the main sources of noise in the LDO voltage regulator module 11 system. High noise in the output voltage of the voltage regulator module 11 will further severely affect other systems using the voltage regulator module 11 as a power supply, such as high-precision sensors. Therefore, obtaining a low-noise output reference voltage, and thus a low-noise voltage regulator module 11, is essential. Noise generated by devices in a circuit is generally mainly flicker noise and thermal noise, with flicker noise having a dominant effect at low frequencies. Therefore, to reduce circuit noise, flicker noise and thermal noise in the circuit should be minimized as much as possible. Generally, the noise level of a transistor is lower than that of a MOSFET. Therefore, to reduce operational amplifier noise, a feasible approach is to use transistors as the input pair of the op-amp. To accommodate the voltage of the current branch generating IPTAT in the bandgap reference and the voltage value input from the bandgap output to the error amplifier, PNP and NPN type BJTs are used as the operational amplifiers in the illustrated voltage regulator module 11, respectively. This structure, which uses BJTs as the input pair of the op-amps in the bandgap reference circuit with integrated op-amps and the error amplifier of the voltage regulator module 11, significantly reduces the noise generated by these two circuits, thereby improving the noise immunity of the voltage regulator module 11 and resulting in a cleaner output voltage. The output of the voltage regulator module 11 supplies power to the anti-chain circuit and obtains the VREF required by the comparator through a voltage divider network.

[0027] according to Figure 3 The working principle of the low-noise voltage regulator module 11 shown is as follows: its output bandgap reference voltage and the output voltage of the voltage regulator module 11 are: ; .

[0028] The signal generation module 12 includes a voltage detection unit 121, a comparator unit 122, and a logic conversion unit 123. The voltage regulation module 11 is connected to the comparator unit 122 and the logic conversion unit 123 respectively. The voltage detection unit 121 is connected to the comparator unit 122, and the comparator unit 122 is connected to the logic conversion unit 123. The voltage detection unit 121 acquires the power supply voltage and outputs a sampled voltage V1. The comparator unit 122 acquires the reference voltage generated by the voltage regulation module 11 and compares it with the sampled voltage output by the voltage detection unit 121, and outputs a comparison signal. The logic conversion unit 123 generates a lockout control signal based on the comparison signal.

[0029] Specifically, the voltage detection unit 121 includes a first PMOS transistor PM1, a second PMOS transistor PM2, a first NMOS transistor NM1, a second NMOS transistor NM2, a third NMOS transistor NM3, a fourth NMOS transistor NM4, a first resistor R1, and a second resistor R2. The first PMOS transistor is connected to the second PMOS transistor, the first NMOS transistor is connected to the first PMOS transistor and the third NMOS transistor, the third NMOS transistor is connected to the second NMOS transistor and the fourth NMOS transistor, one end of the first resistor is connected to the power supply voltage, the other end of the first resistor is connected to one end of the second resistor and the gate of the third NMOS transistor, and the other end of the second resistor is grounded.

[0030] like Figure 5 As shown, when the power supply voltage VDD is in a normal state, under normal operating conditions, the voltage across the second resistor is higher than the threshold voltage of the third NMOS transistor, therefore the third NMOS transistor is turned on. At this time, the current I2 in the first NMOS transistor branch is mirrored through the first and second PMOS transistors. Since the size of the second NMOS transistor is m times that of the first NMOS transistor, therefore... The first and fourth NMOS transistors have the same dimensions, therefore I4 = I1, and the first and second PMOS transistors have the same dimensions. Under normal conditions, the third NMOS transistor operates in the saturation region, I3 = I2. Since I3 > I4, the current in the second PMOS transistor branch is determined by the current I4 of the fourth NMOS transistor. Therefore, the second PMOS transistor enters the linear region, and the voltage at point A is pulled high.

[0031] As the power supply voltage VDD changes from high to low, the detection voltage across the second resistor gradually decreases. With the voltage drop across the second resistor, the third NMOS transistor's operating state transitions from the saturation region to the linear region and even the sub-saturation region. The current I3 flowing through the third NMOS transistor also decreases, making it the current-determining device for its branch. In this circuit, the branch currents of the second NMOS transistor, third NMOS transistor, and second PMOS transistor are equal. When I3 decreases to less than I4, the fourth NMOS transistor is pulled into the linear region, and the voltage at point A flips from high to low. At this point, the output state of the UVLO circuit reverses, controlling the subsequent circuit to turn off and achieving undervoltage protection. That is, under normal power supply voltage conditions, the second PMOS transistor operates in the linear region, and vice versa. The corresponding operating state of the fourth NMOS transistor is the opposite.

[0032] The switching of the operating state of such transistors, especially the third NMOS transistor, will inevitably cause internal voltage instability. When the third NMOS transistor is in the linear region, the current is small and it turns off at a lower voltage. When the third NMOS transistor enters the saturation region, it requires a higher voltage to conduct. The unequal voltage creates a hysteresis window.

[0033] according to Figure 5 The voltage detection unit 121 of the current-mode method shown herein and the principle of its hysteresis loop generation are illustrated, and the hysteresis window is as follows: ; ; In the formula, This represents the gate voltage of the three bottom NMOS transistors (the second, third, and fourth NMOS transistors). This is the gate voltage of the third NMOS transistor.

[0034] ; In the formula, yes The combination It is the threshold voltage of the second NMOS transistor. It is the sum of the resistance values ​​of the first resistor and the second resistor. The sampling voltage V1 output by the voltage detection unit 121 will rise rapidly after the power supply voltage reaches near the threshold. However, it is still observed that it does not immediately rise to a high voltage, but rather there is a buffer zone. This buffer zone is dangerous because when in this intermediate buffer zone, the device cannot clearly indicate whether it is a high voltage or low voltage state, making it difficult for the system to distinguish the current operating state. Furthermore, before actually reaching the normal power supply voltage, it is actually in an undervoltage state, which is unacceptable. To ensure the stable and reliable IGBT gate drive, the logic conversion unit 123 needs to complete the signal conversion and undervoltage control signal output to avoid device damage or circuit malfunction caused by abnormal power supply voltage. The hysteretic analog signal output by the voltage detection unit 121 needs to be converted into a logic signal that meets the requirements of the subsequent stage.

[0035] The core of the logic conversion unit 123 consists of a high-speed comparator 1321 and an inverting logic chain, which work together to complete signal conversion and undervoltage control signal output. The reference terminal of the high-speed comparator 1321 is connected to a stable reference voltage VREF generated by a voltage divider network to ensure accurate threshold judgment. The other input terminal is connected to the analog signal V1 from the previous stage voltage detection circuit, i.e., the sampling voltage, whose amplitude fluctuates with the IGBT drive supply voltage VDD, directly reflecting the power supply status. Compared to conventional cross-pair comparators, the high-speed comparator 1321 proposed in this invention adds two resistors, a first sampling resistor and a second sampling resistor, which can improve the response speed and thus obtain better output switching. When the sampling voltage V1 transitions from low to high, the voltage divider clamping effect of the second sampling resistor rapidly pulls down the gate potentials of PM3 and PM6. After an RC delay, they return to a steady state. The transient large current rapidly charges and discharges the internal parasitic capacitance, shortening the delay and preventing incomplete switching. When the sampling voltage V1 transitions from high to low, an additional resistor adjusts the gate potential of the NMOS transistor, and the capacitor is charged and discharged through the transient current, ensuring rapid reverse switching of the output. The core function of the high-speed comparator 1321 is to compare the sampling voltage V1 with the reference voltage VREF in real time: when the sampling voltage V1 is higher than the reference voltage VREF, the output is high, corresponding to a normal power supply voltage VDD, and the IGBT gate drive can work normally. When the sampling voltage V1 is lower than the reference voltage VREF, the output is low, corresponding to an undervoltage power supply voltage VDD. Subsequent logic is needed to implement IGBT undervoltage lockout to prevent device damage. This method can synchronously track the dynamic changes of VDD / DVDD and promptly capture undervoltage anomalies. Meanwhile, by adjusting the aspect ratio or the number of cross-pairs, ensuring that the aspect ratio of each cross-pair is larger than that of its individual pairs, a hysteresis window can be formed based on the positive feedback principle. The larger this aspect ratio, the larger the hysteresis window. Due to the hysteresis window, an adaptive threshold window is formed. This window ensures that the comparator confirms the voltage has not bounced back after a rise before flipping again, preventing the input detection voltage from repeatedly outputting high and low levels due to frequent transitions, which could interfere with the system's judgment or even damage the system.

[0036] Figure 7The response comparison between the high-speed comparator 1321 and a conventional comparator is shown. It can be seen that both cross-pair comparators have a certain hysteresis window, and neither flips the level at the same threshold point. When processing higher frequency signals, the high-speed comparator 1321 has a slightly faster response speed than the conventional comparator, allowing for faster waveform processing. Furthermore, the output waveform is more regular than that of the conventional comparator; under a standard mid-to-high frequency sine wave input, the high and low levels are closer in time. This demonstrates that the high-speed comparator 1321 can process signals faster; otherwise, the output wouldn't have time to drop to a low level before the next input signal threshold point that would cause the comparator to output a high level arrives. Since the phase and level of the comparator's output signal may not be compatible with subsequent circuits, inverters need to be cascaded at its output to form an inverting logic chain. Inverters not only invert logic signals but also shape and filter out noise and glitches, improving signal stability. By appropriately increasing the number of inverter stages, a UVLO output signal and its inverted signal that match the timing requirements of subsequent stages can be obtained, avoiding control logic disorder. Finally, the latching control signal UVLO_Ctrl, after being processed by the inverting logic chain, is transmitted to the subsequent drive control unit. When the latching control signal UVLO_Ctrl is high, the power supply is normal, which means that one of the conditions for the drive circuit to work is met. When the latching control signal is low, undervoltage lockout is triggered, the IGBT gate drive signal is cut off, and the IGBT is turned off, realizing undervoltage protection for the device and the system and ensuring long-term stable operation of the system.

[0037] The undervoltage lockout circuit 1 includes a time-delay condition recovery module 15, which is connected to the signal generation module 12. The lockout control signal is transmitted to the time-delay condition recovery module 15 to generate a reset signal. Specifically, the time-delay condition recovery module 15 takes the lockout control signal UVLO_Ctrl as input and outputs a corresponding level of reset signal according to the changes in the lockout control signal. When the lockout control signal is high, the time-delay condition recovery module 15 outputs a low level. Once a low level is detected in the lockout control signal, it outputs a high level until the next high level arrives, at which point a timer starts, and then it outputs a low level again. If a low level is detected in the lockout control signal later, it outputs a high level again. This allows the circuit to conduct when the power supply voltage VDD is normal, lock the circuit when VDD is abnormal, and resume conduction only after a delay after the lockout control signal returns to normal and the lockout control signal is confirmed to be no longer abnormal. This protects the IGBT gate from repeated conduction due to frequent voltage changes.

[0038] Depend on Figure 9It can be seen that the delay condition recovery module 15 receives the lock control signal output from the signal generation module 12. After the module is powered on, it first performs an initialization operation, clears the timing parameter t_rise to zero, assigns the working state state to 0, and sets the default output level Vout to low level Vlow. During the power-on operation phase, it first determines whether the system running time t is less than the power-on start-up time TSTARTUP. If t < TSTARTUP, the module continuously maintains Vout at a low level, thereby forcibly shielding the drive output during the power-on phase and avoiding IGBT erroneous turn-on caused by voltage instability at the moment of power-on. When the system running time exceeds TSTARTUP, it exits the power-on shielding logic and enters the UVLO level discrimination step, which collects the UVLO_Ctrl voltage in real time and compares it with the undervoltage threshold VTH. If V(UVLO) < VTH is detected, the power supply is determined to be in an undervoltage fault state. The module marks the undervoltage flag, and regardless of whether the internal delay timer reaches the set delay parameter TDELAY, the output Vout remains at a low level, continuously cooperating with the downstream SR latch to block the IGBT drive path. If V(UVLO) ≥ VTH, it means that the power supply voltage has returned to normal. The module clears the timer t_rise and the state bit, and directly sets the output Vout to a high level. The high-level signal is connected to the reset terminal R of the internal SR latch of the drive control module to complete the fault unlocking. Although this module sets the timing logic after the voltage recovery for status recording, the actual output level is not constrained by the timing duration. It only relies on the UVLO_Ctrl level change to switch the output high and low levels. Finally, the output signal is sent to the downstream drive control module after level conversion.

[0039] Figure 9 The parameters in the table are as follows: t represents the system real-time running time; TSTARTUP represents the power-on shielding time threshold, a fixed duration for forced latching of the output during the initial power-on phase; V(UVLO) represents the module input voltage, i.e., the latching control signal; VTH represents the undervoltage judgment threshold voltage, used to distinguish between undervoltage and normal operating conditions; t_rise represents the voltage recovery start time, recording the system time for UVLO to jump from undervoltage to normal voltage; state represents the module status flag, where state=0 is the standby latching state and state=1 is the timing recording state; TDELAY represents the fault recovery delay threshold, a preset voltage recovery waiting time, used only for internal timing statistics and not involved in output level control; Vout represents the output level of the delay module, sent to the SR latch R reset terminal; Vlow is low (reset invalid, latching remains), Vhigh is high (reset valid, fault latch released); and abstime represents the system absolute clock, the global reference time, used to calculate the interval duration after voltage recovery.

[0040] The drive module 13 includes a drive control unit 131 and a gate drive unit 132. The drive control unit 131 is connected to the gate drive unit 132, and the gate drive unit 132 is connected to the gate detection module 14. The drive control unit 131 is connected to the delay condition recovery module 15 and the logic conversion unit 123 respectively.

[0041] Specifically, the drive control unit 131, as the core control unit of the IGBT gate drive system, outputs drive control signals to drive the IGBT to operate normally, achieving precise control over the IGBT drive state, abnormal locking, and reset recovery, ensuring the safe and stable operation of the entire drive system. The gate drive unit 132 utilizes the drive control signals output by the drive control unit 131, converting them into power signals with sufficient drive capability, thereby achieving precise and stable drive of the IGBT device to turn on and off. At the same time, it adapts to the characteristics of the IGBT itself, outputting a sufficiently large drive voltage to avoid damage to the device due to insufficient drive or signal distortion.

[0042] The drive control unit 131 includes an RS latch 1311 and a three-input AND gate 1312. The RS latch 1311 and the three-input AND gate 1312 are connected. The RS latch receives a reset signal and a lock control signal, and outputs a latch signal. The three-input AND gate 1312 acquires the external control signal, the latch signal output by the RS latch 1311, and the lock control signal.

[0043] Specifically, the core of the drive control unit 131 consists of a cascaded SR latch and a three-input AND gate 1312, ensuring the accuracy and reliability of the circuit response. The SR latch is composed of two cross-coupled NAND gates, and its core characteristic is that it is active low. That is, both the set (S) and reset (R) control terminals must be low to trigger the corresponding action, and illegal operations where S=R=0 must be strictly avoided. In this state, the latch output will be unpredictable, leading to drive control logic disorder, which in turn can cause IGBT device malfunction or damage. Therefore, this condition must be strictly avoided in circuit design and actual operation. Based on the low-level active characteristic of the SR latch, its set terminal S is specifically used for the low-level state of the latch control signal output by the logic conversion unit 123 of the previous stage. As can be seen from the previous principle, when the latch control signal is low, the corresponding IGBT drive supply voltage VDD is in an undervoltage state. At this time, the low-level signal input to the S terminal of the SR latch triggers the latch set action, locking the drive control unit in the undervoltage protection state. This latching function effectively prevents frequent fluctuations in VDD voltage between undervoltage and normal states, avoiding repeated switching of the IGBT gate drive signal due to minor fluctuations in VDD. This protects the IGBT device from transient voltage surges and reduces the risk of device damage. Simultaneously, the latched state remains active until a valid low-level reset signal is received at the R terminal, ensuring the continuity and reliability of undervoltage protection. The reset terminal R of the SR latch is specifically used to receive an external reset signal, undertaking the reset and recovery function after the system undervoltage fault is resolved. When the power supply voltage undervoltage fault is resolved and power supply returns to normal, an external reset signal is input low to the R terminal, triggering the SR latch to reset, releasing the latch from its latched state and restoring normal operation. The entire drive control unit re-enters the VDD voltage detection and drive control mode, continuously tracking real-time changes in VDD to ensure the system can promptly return to normal operation, balancing the reliability of undervoltage protection with the continuity of system operation. Due to its low-level triggering characteristic, the output terminal Q' of the SR latch in this example represents the enable drive signal terminal. Its output state directly determines whether the subsequent three-input AND gate 1312 is turned on or off. Therefore, Q' is connected to one of the input terminals of the next-stage three-input AND gate 1312 as one of the core control signals for drive enable. Simultaneously, the other two input terminals of the three-input AND gate 1312 are connected to the latch control signal and the external control signal, respectively. These three signals work together to form the logical judgment condition for the drive control signal, achieving comprehensive control of multiple signals. Based on the operating characteristics of this NAND gate SR latch, we know that when the R terminal is low, the SR latch will reset, and the Q' terminal will output a high level. That is, when the R terminal is low, the output of the SR latch will be considered valid by the next-stage three-input AND gate 1312.The three-input AND gate 1312 operates only when all three inputs are high. It conducts only when all three input signals are simultaneously high, outputting a high-level drive control signal. This high-level signal is transmitted to the subsequent IGBT gate drive module, indicating that the power supply voltage is normal, the system has no undervoltage abnormality, and the external control command allows drive. In this case, the IGBT gate drive circuit operates normally, driving the IGBT device to run according to the command. Conversely, if any input signal is low, the three-input AND gate 1312 is cut off, outputting a low-level control signal to cut off the IGBT gate drive signal, turning off the IGBT device and achieving comprehensive drive protection, further ensuring the safety of the system and the device.

[0044] The gate drive unit 132 includes a high-speed comparator 1321 and a non-inverting amplifier 1322. The high-speed comparator 1321 is connected to the through amplifier and is connected to a three-input AND gate 1312 and a voltage regulator module 11.

[0045] Specifically, the gate drive unit 132, as the final execution unit of the entire IGBT drive system, consists of a high-speed comparator 1321 and a non-inverting amplifier 1322 in its core architecture. The circuit connection of the high-speed comparator 1321 is basically the same as that used in the logic conversion unit 123 described earlier. This design not only maintains the universality and consistency of the entire system circuit design and reduces the difficulty of circuit integration and debugging, but also continues the advantages of the high-speed comparator 1321, such as fast response speed and strong anti-interference capability. It can quickly capture changes in the input signal level, ensuring timely response to drive commands. Furthermore, the left input terminal of the high-speed comparator 1321 in the gate drive unit 132 is connected to a reference voltage VREF, precisely output by the voltage regulator unit through a voltage divider network. Since the output of the previous stage drive control unit 131 is only high and low levels, this reference voltage VREF should be set to a stable value slightly higher than the system's low level. Its stability directly determines the accuracy of the comparator's level judgment, effectively avoiding erroneous output of the drive signal due to fluctuations in the reference voltage. The right input of the high-speed comparator 1321 is specifically connected to the output signal of the previous stage drive control unit. When the drive control unit outputs a low level, the signal voltage is lower than the reference voltage VREF, and the comparator outputs a low level. When the drive control unit outputs a high level, the signal voltage is higher than VREF, and the comparator synchronously outputs a high level, completing the level judgment and shaping of the control signal. Since the equivalent circuit of the IGBT device itself is a cascaded structure of a MOS transistor and a PNP transistor, its gate has typical capacitive load characteristics, resulting in a relatively large equivalent gate-emitter capacitance Cge. Due to the characteristics of the capacitive load, the driving capability of ordinary logic signals is insufficient to quickly complete the charging and discharging of Cge. This not only makes it difficult to drive the IGBT to conduct and turn off normally, but may also lead to insufficient IGBT conduction and delayed turn-off, causing device heating and increased losses. Therefore, this circuit connects the output of the high-speed comparator 1321 to the non-inverting input of the operational amplifier, and the output of the operational amplifier is directly connected to the gate of the IGBT. Simultaneously, it connects back to the inverting input of the operational amplifier through a resistor feedback network, forming a stable negative feedback drive loop. The operational amplifier primarily plays a core role in providing high gain and strong driving capability, amplifying the logic signal output from the high-speed comparator 1321 to provide sufficient drive current to the IGBT gate, quickly completing the charging and discharging process of the equivalent capacitance Cge, ensuring that the IGBT can quickly and reliably turn on and off. At the same time, the resistor feedback network at the inverting input stabilizes the output voltage and current of the operational amplifier, suppressing signal distortion and external interference, making the output drive signal more stable, further ensuring the operational stability of the IGBT, extending the device's lifespan, and ensuring the reliable operation of the entire drive system.

[0046] The gate detection module 14 includes a detection comparator 141 and a detection tube 142. The detection tube 142 is connected to the output terminal of the gate driving unit 132. The detection comparator 141 acquires the driving voltage and the reference voltage respectively.

[0047] Specifically, the gate detection module 14, as one of the monitoring units of the entire undervoltage lockout protection system, mainly functions to cooperate with the front-end circuit to detect the voltage status of the IGBT gate drive node in real time, quickly identify abnormal conditions such as gate open circuit, drive disconnection, and drive failure, and convert the presence or absence of gate voltage into a stable logic monitoring signal. The gate detection module 14 consists of a sampling resistor, an inverter, an NMOS detection transistor 142, and a detection comparator 141. It can directly monitor the voltage of the IGBT gate node and has the characteristics of rapid response, simple structure, and strong anti-interference capability. A resistor series branch is connected at the IGBT gate node VG and connected to the drain of the NMOS transistor to realize real-time detection of the gate voltage. At the same time, the gate node VG is directly connected to the input terminal of the inverter, the output terminal of the inverter is connected to the gate of the NMOS transistor, and the source of the NMOS transistor is directly grounded, forming a complete status detection and level biasing path. Since the front-end circuit ensures that the power supply voltage VDD is normal, the gate control signal will only be output when VDD is normal. That is to say, the gate drive voltage will only appear when VDD is normal; otherwise, the gate drive voltage is 0. Therefore, detecting the gate drive voltage only requires checking its presence. If it exists, it indicates a normal state; if it does not exist, the IGBT gate must have encountered a major problem, such as an open circuit. This architecture achieves state judgment through level switching and switch control, eliminating the need for additional bias circuitry and reliably distinguishing between normal and abnormal gate drive conditions. When the IGBT gate node VG has a normal drive waveform and the drive voltage is valid, the inverter input is high and the output is low. The NMOS transistor gate is pulled low and remains off, while the NMOS drain node remains high, indicating normal gate drive. When the gate loses its drive voltage due to abnormal reasons such as a drive disconnection or signal loss, and VG becomes low, the inverter input becomes low and the output flips to high, turning on the NMOS transistor and quickly pulling the drain node low, indicating gate drive failure.

[0048] When a normal drive waveform is present in VG, the detection comparator 141 outputs a high level, indicating normal drive; when VG loses its drive signal, the detection comparator 141 outputs a low level, indicating a gate abnormality. Through this mechanism, this circuit can provide real-time and accurate feedback on the IGBT gate drive status, working in conjunction with the UVLO system to provide reliable abnormality monitoring, improving the overall protection's comprehensiveness and response speed, and ensuring the stable and safe operation of the IGBT under complex operating conditions. Figure 13The waveforms showing the response of the IGBT gate voltage and key internal control signals to changes in the power supply voltage VDD are illustrated, intuitively reflecting the overall working effect and protection performance of the undervoltage lockout protection system described in this invention. The waveforms demonstrate that the protection system proposed in this invention can achieve real-time coordinated monitoring of the power supply voltage and the IGBT gate drive state: when the power supply voltage VDD is within the normal operating range, the system outputs a gate drive voltage that meets the IGBT's safe turn-on requirements, ensuring that the IGBT operates in a saturated conduction state. This avoids the problem of the IGBT entering the linear amplification region due to insufficient drive voltage or low gate voltage, which would lead to a sharp increase in conduction losses, excessive device heating, and ultimately IGBT damage or even failure of the entire power electronic system. The V_Ctrl waveform at the bottom of the figure clearly illustrates the internal logic and timing relationship of the undervoltage protection system of this invention, intuitively demonstrating the strict correspondence between the IGBT gate voltage VG and each stage of control signals. Figure 13 The timing response shown clearly demonstrates that this invention employs multi-level logic and a latching mechanism to achieve reliable protection. The effective output of the drive control signal requires that the latch signal, external input enable signal, and UVLO control signal (equivalent to Q') all be simultaneously high. Only when all conditions are met will the drive path open, allowing the gate drive signal to be output normally. Simultaneously, the R-terminal reset signal and the UVLO control signal maintain a largely inverted logical correspondence, with only a forced low timing difference during the initial power-on phase. This achieves orderly unlocking after power-on reset, fault locking, and voltage recovery.

[0049] Secondly, this invention discloses an IGBT driving circuit, which includes the aforementioned undervoltage lockout circuit 1. Specifically, the IGBT driving circuit integrates the aforementioned undervoltage lockout circuit 1, and relies on the all-dimensional voltage monitoring capability of the undervoltage lockout circuit 1 to improve the protection architecture of the IGBT driving system. In various fault scenarios such as power supply undervoltage, driving abnormality, and gate open circuit, the IGBT drive is promptly locked, thereby improving the operational stability and fault protection capability of the entire IGBT driving circuit.

[0050] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0051] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," and "counterclockwise," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0052] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0053] In this invention, unless otherwise explicitly specified and limited, the terms "installation," "connection," "linking," and "fixing," etc., should be interpreted broadly. For example, they can refer to a connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0054] In this invention, unless otherwise explicitly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0055] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. The illustrative expressions of the above terms in this specification should not be construed as necessarily referring to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. In addition, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.

[0056] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Since these modifications and variations fall within the scope of the claims and their equivalents, this invention also intends to include these modifications and variations.

[0057] The above description describes specific embodiments of the present invention, but the scope of protection of the present invention is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in the present invention, and these modifications or substitutions should all be covered within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. An undervoltage lockout circuit, characterized in that, It includes a time delay condition recovery module, a voltage regulator module, a signal generation module, a drive module, and a gate detection module. The voltage regulator module is electrically connected to the signal generation module, the drive module, and the gate detection module. The drive module is electrically connected to the gate detection module, and the time delay condition recovery module is electrically connected to the signal generation module. The voltage regulator module is configured to receive the power supply voltage and generate a reference voltage, and synchronously transmit the reference voltage to the signal generation module, the driving module, and the gate detection module. The signal generation module is configured to detect the power supply voltage of the system based on the reference voltage and generate an undervoltage lockout control signal according to the system power supply voltage status. Specifically, when the sampling system power supply voltage is higher than the reference voltage, the undervoltage lockout control signal outputs a high level, and when the sampling system power supply voltage is lower than the reference voltage, the undervoltage lockout control signal outputs a low level. The logic conversion unit generates a lockout control signal based on the received undervoltage lockout control signal. A high level lockout control signal indicates that the power supply voltage is normal, and a low level lockout control signal indicates that the power supply is undervoltage. The lockout control signal is transmitted to the delay condition recovery module, which generates a reset signal and transmits it to the drive module. The gate detection module is configured to acquire the IGBT drive voltage in real time based on the reference voltage, compare the acquired IGBT drive voltage with the reference voltage, and output a gate fault judgment signal; wherein, when the IGBT gate drive voltage is lower than the reference voltage, the gate detection module outputs a low level, and when the IGBT gate drive voltage is higher than the reference voltage, the gate detection module outputs a high level. The drive module includes a drive control unit and a gate drive unit. The drive control unit has an RS latch and a three-input AND gate. The RS latch receives the latch control signal and the reset signal output by the delay condition recovery module, and outputs a latch signal. The three-input AND gate is simultaneously connected to the latch signal, the latch control signal, and the external control signal. The three-input AND gate outputs an effective drive control level to the gate drive unit only when all three inputs are high. If the latch control signal is low and / or the gate fault judgment signal is low, the gate drive unit blocks the IGBT drive voltage output.

2. The undervoltage lockout circuit according to claim 1, characterized in that, The signal generation module includes a voltage detection unit, a comparator unit, and a logic conversion unit. The voltage regulation module is connected to the comparator unit and the logic conversion unit respectively. The voltage detection unit is connected to the comparator unit, and the comparator unit is connected to the logic conversion unit. The voltage detection unit acquires the power supply voltage and outputs a sampled voltage. The comparator unit acquires the reference voltage generated by the voltage regulator module and compares it with the sampled voltage output by the voltage detection unit, outputting a comparison signal. The logic conversion unit generates a lockout control signal based on the comparison signal.

3. The undervoltage lockout circuit according to claim 1, characterized in that, The drive control unit is connected to the gate drive unit, the gate drive unit is connected to the gate detection module, and the drive control unit is connected to the delay condition recovery module and the logic conversion unit respectively.

4. The undervoltage lockout circuit according to claim 3, characterized in that, The gate drive unit includes a high-speed comparator and a non-inverting amplifier. The high-speed comparator is connected to the non-inverting amplifier, and the high-speed comparator is connected to a three-input AND gate and a voltage regulator module.

5. The undervoltage lockout circuit according to claim 1, characterized in that, The voltage detection unit includes a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a first resistor, and a second resistor. The first PMOS transistor is connected to the second PMOS transistor, the first NMOS transistor is connected to the first PMOS transistor and the third NMOS transistor, the third NMOS transistor is connected to the second NMOS transistor and the fourth NMOS transistor, one end of the first resistor is connected to the power supply voltage, the other end of the first resistor is connected to one end of the second resistor and the gate of the third NMOS transistor, and the other end of the second resistor is grounded.

6. The undervoltage lockout circuit according to claim 1, characterized in that, The gate detection module includes a detection comparator and a detection tube. The detection tube is connected to the output terminal of the gate driving unit, and the detection comparator acquires the driving voltage and the reference voltage respectively.

7. The undervoltage lockout circuit according to claim 1, characterized in that, The voltage regulator module includes a common source cascode bandgap reference subunit and an error amplifier subunit, which are connected together.

8. An IGBT driving circuit, characterized in that, Includes the undervoltage lockout circuit described in any one of claims 1-7.

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