A method and system for discharge boosting control of a shunt parallel circuit

Abstract

The application discloses a discharge efficiency control method and system of an interleaved parallel circuit, relates to the field of battery discharge control, and comprises the following steps: when the port voltage enters a preset low voltage interval, the power phases are controlled to enter a discontinuous conduction mode, so that a discontinuous idle interval in which the inductor current is zero appears in each switching cycle; the observation shots are selected according to a preset observation period, and the conduction starting time of each power phase is rearranged, so that the discontinuous idle intervals overlap with each other at the tail section of the observation shots, and a full-phase zero-current observation window in which the inductor currents of the power phases are all zero is formed; the port voltage is collected in the full-phase zero-current observation window to obtain zero-current voltage sample values, the zero-current voltage sample values of multiple observation shots constitute a zero-current voltage sequence, and the zero-current voltage sequence is compared with a discharge-to-position template library to generate a discharge-to-position judgment result; after the observation shots are ended, the interleaved phase difference is restored, and the discharge is controlled to continue or stop conduction according to the judgment result. The application solves the problems that the port voltage at the end section of the discharge is polluted by the loop voltage drop and the discharge-to-position is difficult to accurately judge.

Description

Technical Field

[0001] This application relates to the field of battery discharge control technology, and more specifically, to a discharge efficiency enhancement control method and system for interleaved parallel circuits. Background Technology

[0002] In battery production and testing, discharging is a fundamental process as important as charging. Before lithium batteries leave the factory, the formation and capacity testing of the cells requires a complete discharge process according to the process specifications to determine capacity. The screening for reuse of retired batteries and the periodic capacity verification of energy storage power stations also rely on standardized discharge testing. In these scenarios, the discharge current is large and the number of channels is high. The discharge circuit generally adopts a structure with multiple power branches connected in parallel, and the switching actions of each branch are staggered according to phase to smooth the bus current ripple and distribute the stress on the components. As battery production capacity and testing scale expand, the degree of automation and accuracy of the discharge process directly affects production cycle time and battery quality.

[0003] In the prior art, various solutions have emerged for controlling the battery discharge process. For example, patent CN102651560A discloses a solution where, when the battery pack is nearing the end of its discharge and the remaining charge has dropped to a certain percentage, the voltage across the battery pack is reduced and applied to a small number of low-voltage individual cells to replenish their charge, thus slowing down the discharge rate of the low-voltage batteries and allowing all individual cells to discharge almost simultaneously, thereby extending the discharge time. Another example is patent CN101728839A, which discloses a solution for collecting battery operating parameters such as voltage, controlling the battery to discharge according to set conditions, and ending the discharge when termination conditions are met.

[0004] However, existing discharge control schemes typically determine whether discharge is complete by directly using the port voltage collected in the discharge circuit to reach a set threshold, without considering the variation in circuit voltage drop that varies with channel and operating conditions. At the end of the discharge process, the battery voltage is low, but the discharge current continues to flow. This current flowing through the cables, connectors, and clamp contact points generates a voltage drop. The collected port voltage equals the sum of the battery's actual voltage and the circuit voltage drop. Because the cable lengths, clamp condition, and contact tightness vary across channels, the voltage drop component mixed into the port voltage also differs for each channel. Since the threshold is uniformly set, this can lead to some channels prematurely terminating discharge before the battery has truly discharged to its full extent, while others continue to over-discharge. This results in deviations in capacity measurement results, inconsistent depth of discharge, and in severe cases, damage to the battery and affect the accuracy of capacity grading.

[0005] Furthermore, existing solutions all come at a significant cost. The method of stopping the discharge and allowing it to stand still before retesting requires interrupting the discharge and waiting for the voltage to stabilize. While the readings are clean, this disrupts the continuity of the discharge process and significantly lengthens the cycle time, making it unacceptable for streamlined formation and capacity testing lines. The method of actively changing the discharge current to identify the loop resistance and then compensating requires establishing and calibrating the resistance model for each channel, and the identification process itself repeatedly disturbs the process current. Adding a four-wire sampling method to each channel requires laying double the leads and a dedicated probe for each channel, increasing the cost exponentially with the number of channels. Moreover, this method only eliminates the voltage drop across lines other than the sampling leads, not the influence of the internal ohmic voltage drop of the battery on the port voltage.

[0006] Therefore, there is a need for an interleaved parallel circuit discharge control method that can eliminate the influence of loop voltage drop and accurately determine the discharge endpoint without interrupting the entire discharge process or disturbing the process current. This method would enable multi-channel discharge to maintain process continuity and obtain accurate and consistent discharge endpoint determination, thereby improving the accuracy of capacity measurement and battery safety during the discharge process. Summary of the Invention

[0007] The technical problem to be solved by this application is to provide a discharge efficiency enhancement control method and system for interleaved parallel circuits, which can eliminate the influence of loop voltage drop and accurately determine the discharge in place without interrupting the discharge or disturbing the process current.

[0008] To achieve the above objectives, this application adopts the following technical solution:

[0009] A discharge efficiency enhancement control method for an interleaved parallel circuit is applied to the process of discharging a battery cell using the interleaved parallel circuit. The interleaved parallel circuit includes multiple power phases connected between a discharge port and a DC bus. The discharge port is connected to the battery cell, and each power phase is switched on at an alternate phase difference.

[0010] The method includes: when the port voltage of the discharge port enters a preset low voltage range, controlling each power phase to enter an intermittent conduction mode, so that each power phase has an intermittent idle range in which the inductor current remains zero in each switching cycle.

[0011] Select a switching cycle as the observation period according to the preset observation period, and rearrange the conduction start time of each power phase within the observation period so that the intermittent idle intervals of each power phase overlap with each other at the end of the observation period, forming a full-phase zero-current observation window in which the inductance current of each power phase is zero.

[0012] The port voltage is acquired at the sampling time within the full-phase zero-current observation window, and the acquisition result is used as the zero-current voltage sample value.

[0013] The zero-current voltage sampling values ​​obtained from multiple observations are used to form a zero-current voltage sequence. The zero-current voltage sequence is compared with the templates in the discharge in-place template library to generate a discharge in-place determination result.

[0014] After the observation period ends, the staggered phase difference of each power phase is restored. If the discharge completion determination result is not yet complete, each power phase is controlled to continue discharging. If the discharge completion determination result is complete, each power phase is controlled to stop conducting.

[0015] Optionally, each power phase includes an inductor, a main switch, a freewheeling switch, and an inductor current zero-crossing detection unit; controlling each power phase to enter the intermittent conduction mode includes: detecting the moment when the inductor current of the power phase returns to zero by the inductor current zero-crossing detection unit of the power phase, and turning off the freewheeling switch of the power phase at the moment when the inductor current returns to zero, so that the inductor current of the power phase remains zero before the next conduction of the power phase; the method of selecting the observation period is: selecting one switching period as the observation period at a preset number of switching periods, and in the switching periods not selected as the observation period, each power phase maintains operation according to the interleaved phase difference.

[0016] Optionally, rearranging the conduction start times of each power phase includes: arranging each power phase in a preset order, setting the conduction start time of the power phase that is first in the order to the starting point of the observation frame, and setting the conduction start time of each power phase that follows it to be delayed by a preset arrangement interval relative to the conduction start time of the power phase preceding it, so that the conduction intervals of the main switch and the freewheeling switch in each power phase are concentrated in the front section of the observation frame; taking the latest time of the inductor current returning to zero in each power phase as the starting point of the full-phase zero-current observation window, and taking the end point of the observation frame as the end point of the full-phase zero-current observation window.

[0017] Optionally, the construction process of the discharge in place template library includes: for each historical discharge process, collecting zero-current voltage sampling values ​​according to the observation frame to form a historical zero-current voltage sequence for that historical discharge process; after the historical discharge process stops discharging and is left to stand for a preset standing time, re-measuring the port voltage to obtain the re-measured voltage; when the re-measured voltage falls into the preset in place voltage range, labeling the historical discharge process as in place; otherwise, labeling the historical discharge process as not in place; using the historical zero-current voltage sequence of that historical discharge process as a template feature vector, associating it with the labeled tag, and storing it as a template in the discharge in place template library; comparing the zero-current voltage sequence with the templates in the discharge in place template library includes: calculating the distance metric between the zero-current voltage sequence and the template feature vector of each template, and determining the label associated with the template with the smallest distance metric as the discharge in place determination result.

[0018] Optionally, controlling each power phase to continue discharging when the discharge completion determination result is not yet complete includes: selecting the corresponding total discharge current setting value from a preset current range table according to the voltage range of the zero-current voltage sampling value obtained from the most recently selected observation frame, and controlling each power phase to continue discharging according to the selected total discharge current setting value, wherein the preset current range table stores the correspondence between voltage ranges and total discharge current setting values; controlling each power phase to stop conducting when the discharge completion determination result is complete includes: turning off the main switches and freewheeling switches of all power phases within the full-phase zero-current observation window of the most recently selected observation frame after the discharge completion determination result is generated.

[0019] Optionally, the method further includes: within the observation period, starting from the moment when the inductor current of each power phase returns to zero, acquiring the switching node voltage at the connection node between the inductor and the main switch in that power phase to form a ringing waveform segment of that power phase; extracting ringing features from the ringing waveform segment, the ringing features including oscillation frequency and decay time, the decay time being the time it takes for the oscillation amplitude of the ringing waveform segment to decay to below a preset amplitude threshold; comparing the ringing features of each power phase with the ringing reference template of that power phase, and determining the oscillation frequency between the oscillation frequency and the reference oscillation frequency in the ringing reference template. When the deviation exceeds the preset frequency deviation range, or when the deviation between the attenuation time and the reference attenuation time in the ringing reference template exceeds the preset time deviation range, the path health identifier of the power phase is set to a degraded state; otherwise, the path health identifier of the power phase is set to a normal state. The construction process of the ringing reference template is as follows: in the reference calibration stage after the interleaved parallel circuit is connected to the battery cell, the ringing waveform segment of the power phase is collected and the ringing features are extracted. The extracted oscillation frequency and attenuation time are stored in the ringing reference template of the power phase as the reference oscillation frequency and the reference attenuation time, respectively.

[0020] Optionally, the method further includes: setting the sampling time after the start of the full-phase zero-current observation window, and the interval between the sampling time and the start of the full-phase zero-current observation window is not less than the maximum value of the decay time of each power phase; when each power phase continues to discharge, allocating the total discharge current setting value on which the continued discharge of each power phase is based as the phase current setting value of each power phase, lowering the phase current setting value of the power phase with path health marked as deteriorated by a preset adjustment amount, and evenly distributing the lowered current amount to the phase current setting value of the power phase with path health marked as normal; when the total discharge current setting value is lower than the preset phase reduction threshold, determining the number of power phases to be kept on from the preset reduction level table according to the current range in which the total discharge current setting value is located, and stopping the conduction of the remaining power phases, and preferentially selecting the power phases with path health marked as deteriorated when stopping conduction, wherein the preset reduction level table stores the correspondence between the current range and the number of power phases to be kept on.

[0021] Optionally, the DC bus includes a feedback bus section and a dissipation bus section. The feedback bus section is connected to an energy feedback branch for feeding discharge energy back to the power supply network, and the dissipation bus section is connected to an energy dissipation branch for converting discharge energy into heat. Each power phase is provided with a destination selection switch on its output side. The destination selection switch is used to selectively connect the output of the power phase to either the feedback bus section or the dissipation bus section. The method further includes: collecting the feedback power of the energy feedback branch and the bus voltage of the feedback bus section; generating a switching command when the feedback power is lower than a preset lower limit power or when the bus voltage is higher than a preset upper limit voltage; responding to the switching command, switching at least one destination selection switch of the power phase within the full-phase zero-current observation window of the observation frame selected after the switching command is generated, so that the output of the switched power phase is connected from the feedback bus section to the dissipation bus section.

[0022] Optionally, switching the destination selection switch includes: dividing the multiple power phases into multiple switching groups; in the multiple observation frames selected successively after the switching command is generated, switching only one destination selection switch for each power phase in the switching group within the full-phase zero-current observation window of each observation frame; determining the number of power phases connected to the feedback bus section according to the voltage range of the bus voltage from a preset destination allocation table, wherein the preset destination allocation table stores the correspondence between voltage ranges and the number of power phases connected to the feedback bus section; when the feedback power is higher than the preset feedback lower limit power again, connecting the output of the corresponding power phase from the dissipation bus section to the feedback bus section according to the switching group within the full-phase zero-current observation window of the successively selected observation frames.

[0023] This application also discloses a discharge efficiency enhancement control system for an interleaved parallel circuit to implement the above method, including an interleaved parallel circuit and a system controller;

[0024] The interleaved parallel circuit includes multiple power phases connected between the discharge port and the DC bus. The discharge port is connected to the battery unit and is equipped with a port voltage sampling unit. Each power phase includes an inductor, a main switch, a freewheeling switch, and an inductor current zero-crossing detection unit. The power phases are turned on at staggered start times according to the interleaved phase difference.

[0025] The system controller includes a terminal mode control module, an observation and scheduling module, a conduction reordering module, a zero-current voltage sampling module, a discharge completion determination module, and a discharge execution module.

[0026] The end-stage mode control module is used to control each power phase to enter the intermittent conduction mode when the port voltage collected by the port voltage sampling unit enters the preset low voltage range, so that each power phase has an intermittent idle range in each switching cycle in which the inductor current remains zero.

[0027] The observation scheduling module is used to select a switching cycle as an observation cycle according to a preset observation cycle.

[0028] The conduction rearrangement module is used to rearrange the conduction start times of each power phase within the observation frame, so that the intermittent idle intervals of each power phase overlap with each other at the end of the observation frame, forming a full-phase zero-current observation window in which the inductance current of each power phase is zero, and restoring the staggered phase difference of each power phase after the observation frame ends.

[0029] The zero-current voltage sampling module is used to collect the port voltage at the sampling time within the full-phase zero-current observation window, and the collection result is used as the zero-current voltage sampling value.

[0030] The discharge in place determination module has a built-in discharge in place template library, which is used to form a zero-current voltage sequence by multiple zero-current voltage sampling values ​​obtained from the observation, and compare the zero-current voltage sequence with the template in the discharge in place template library to generate a discharge in place determination result.

[0031] The discharge execution module is used to control each power phase to continue discharging when the discharge completion determination result is not yet complete, and to control each power phase to stop conducting when the discharge completion determination result is complete.

[0032] The beneficial effects of this application are as follows:

[0033] This application solves the problems of port voltage contamination by loop voltage drop and difficulty in accurately determining the discharge completion point by rearranging the conduction start time of each power phase according to the observation beat in intermittent conduction mode, forming a full-phase zero-current observation window and collecting zero-current voltage within the window. Specifically, this application does not measure after stopping the discharge, nor does it identify the loop resistance before compensation. Instead, it controls each power phase to enter intermittent conduction mode when the port voltage enters the preset low voltage range, so that there is an intermittent idle interval with zero inductor current in each switching cycle. Then, the observation beat is selected according to the preset observation cycle. Within the observation beat, the intermittent idle intervals that are normally staggered are rearranged to overlap at the end of the cycle, forming a full-phase zero-current observation window where the inductor current of all power phases is simultaneously zero. At this time, there is no current flowing in the discharge circuit, and the voltage drop on the cables, connectors, and clamps disappears along with the current. The zero-current voltage sample value collected within the window directly reflects the true voltage of the battery cell. This application utilizes the inherent idle intervals in each power phase under intermittent conduction mode, and also leverages the fundamental principle that the ohmic voltage drop is always zero under zero current conditions, enabling voltage drop elimination without relying on any resistor modeling or calibration. The staggered phase difference is immediately restored after the observation period ends, the observation window occupies only a tiny proportion of the discharge time, the discharge process is uninterrupted, and the process current remains undisturbed. The determination result is obtained by comparing the zero-current voltage sequence with a discharge-to-end template library, with the templates constructed from the static retest results of historical discharge processes. This avoids premature termination and continuous over-discharge caused by inconsistent loop voltage drops in different channels, improving the accuracy of capacity measurement and the consistency of discharge depth.

[0034] Meanwhile, this application further solves the problems of sampling timing selection and the inability to sense phase path status online by collecting the ringing waveform segment of the switching node voltage after the inductor current of each power phase returns to zero and extracting the ringing characteristics. The oscillation frequency and decay time of the ringing waveform segment are determined by the parasitic parameters and resistance of the power phase path. Contact degradation and device aging will cause the ringing characteristics to deviate from the reference. This application compares the ringing characteristics with the ringing reference template established in the reference calibration stage to obtain the path health indicator of each power phase. On the one hand, the sampling time is set to be no less than the maximum value of the decay time of each power phase from the start of the full-phase zero-current observation window, ensuring that the zero-current voltage sampling occurs after the ringing decay is completed; on the other hand, the phase current setting value of the power phase with the path health indicator is reduced, and it is also preferentially stopped from conducting during phase clipping, so that the discharge current is concentrated in the healthy path. This application transforms the switching transient signal, which is used as interference filtering in conventional design, into a diagnostic basis, realizing online monitoring of the phase path without adding any power devices, reducing the loss and failure risk of the discharge link.

[0035] This application also solves the problems of low efficiency under light load in the energy feedback branch at the end of the discharge and the impact caused by switching with current by anchoring the energy destination switching within the full-phase zero-current observation window. This application generates a switching command when the feedback power is lower than the preset lower limit power or the bus voltage is higher than the preset upper limit voltage. Then, within the full-phase zero-current observation window of the subsequently selected observation frame, the destination selection switch is switched group by group according to the switching group, ensuring that each switching occurs when the loop current is zero. Therefore, the switching process is free of current impact and arcing. The energy feedback branch always operates within a stable power absorption range, and the recoverable electrical energy is fed back to the power supply network as much as possible. Only the portion exceeding the stable absorption capacity is dissipated, thus improving the recovery rate of discharge energy.

[0036] In summary, this application integrates a full-phase zero-current observation window with ringing health monitoring and zero-current switching into an interleaved parallel circuit for discharge control. This allows voltage measurement, path diagnosis, and energy destination execution to share the same time reference, supporting each other without increasing downtime. Therefore, this application can accurately determine discharge completion, identify path degradation online, and smoothly manage energy destination without interrupting discharge. It is particularly suitable for scenarios with high requirements for discharge continuity and accurate endpoint determination, such as battery formation and capacity testing, battery testing, and secondary utilization screening. Attached Figure Description

[0037] Figure 1 A schematic diagram of the discharge efficiency enhancement control system for the interleaved parallel circuit provided in the embodiments of this application;

[0038] Figure 2 A schematic flowchart illustrating the discharge efficiency enhancement control method for interleaved parallel circuits provided in this application embodiment;

[0039] Figure 3 A timing diagram illustrating the rearrangement of the in-phase conduction start time and the formation of the full-phase zero-current observation window provided in the embodiments of this application;

[0040] Figure 4 A schematic diagram illustrating the ringing waveform segment and ringing feature extraction provided in an embodiment of this application;

[0041] Figure 5 A schematic diagram illustrating the process of constructing and comparing the discharge positioning template library provided in the embodiments of this application;

[0042] Figure 6 A schematic diagram illustrating the flow of the destination selection switch switching control provided in an embodiment of this application;

[0043] Figure 7 A schematic diagram of the system controller provided in an embodiment of this application.

[0044] Figure labeling: 10-Battery unit; 20-Interleaved parallel circuit; 21-Discharge port; 22-Port voltage sampling unit; 30-Power phase; 31-Inductor; 32-Main switch; 33-Freewheeling switch; 34-Inductor current zero-crossing detection unit; 35-Direction selection switch; 40-DC bus; 41-Feedback bus section; 42-Dissipation bus section; 50-Energy feedback branch; 60-Energy dissipation branch; 70-System controller; 71-End-stage mode control module; 72-Observation and scheduling module; 73-Conduction reordering module; 74-Zero-current voltage sampling module; 75-Discharge completion determination module; 7501-Discharge completion template library; 76-Discharge execution module. Detailed Implementation

[0045] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0046] The specific parameter values ​​given in the embodiments of this application are all examples and are used to help understand the scheme. In actual implementation, they can be adjusted according to equipment conditions and process requirements.

[0047] Figure 1 This is a schematic diagram of the discharge efficiency enhancement control system for the interleaved parallel circuit provided in this application embodiment. This system is applied in situations requiring the orderly release of electrical energy from batteries, such as the formation and capacity testing process before lithium batteries leave the factory, the screening for the reuse of retired batteries, and the periodic capacity verification of energy storage power stations. These situations involve large discharge currents, numerous channels, and specific requirements for the accuracy of determining the discharge endpoint. (Refer to...) Figure 1 The battery unit 10 is connected to the interleaved parallel circuit via the discharge port 21. The battery unit 10 can be a single cell or a module composed of several cells, and this embodiment does not limit this. A port voltage sampling unit 22 is configured on the discharge port 21. The port voltage sampling unit 22 continuously collects the port voltage at both ends of the discharge port 21 and sends it to the system controller 70.

[0048] The interleaved parallel circuit includes multiple power phases 30 connected between the discharge port 21 and the DC bus 40. Figure 1Three power phases 30 are illustrated in the diagram, with one power phase 30 shown in its expanded internal structure and the other two represented by simplified boxes. All three have identical internal structures, but in practice, the number of power phases 30 can be four, six, or more. Each power phase 30 includes an inductor 31, a main switch 32, a freewheeling switch 33, and an inductor current zero-crossing detection unit 34. One end of the inductor 31 is connected to the discharge port 21, and the other end is split into two paths via a connection node. One path leads to the output side of the power phase via the freewheeling switch 33, and the other path leads to the common return terminal via the main switch 32. When the main switch 32 is on, the inductor 31 draws power from the battery cell 10 for energy storage. After the main switch 32 is off, the inductor current continues through the freewheeling switch 33 and is released to the DC bus 40. This is the conventional operating mode of the boost discharge converter. The inductor current zero-crossing detection unit 34 is positioned close to the inductor 31 to detect the moment when the inductor current drops to zero.

[0049] Each power phase 30 is switched on at a staggered start time according to the phase difference, and in three-phase operation, the switching cycles of adjacent two phases are staggered by 1 / 3. The staggered operation makes the current ripples of each phase cancel each other out, and the total current flowing into the discharge port 21 and the DC bus 40 is smooth. The filter devices can be made smaller, and the current stress of each phase device is more uniform.

[0050] In this embodiment, the DC bus 40 is divided into two sections: a feedback bus section 41 and a dissipation bus section 42. The feedback bus section 41 connects to the energy feedback branch 50, which converts the discharged energy and feeds it back to the power supply network. The dissipation bus section 42 connects to the energy dissipation branch 60, which converts the discharged energy into heat and dissipates it; it typically consists of a braking resistor and its switch. Each power phase 30 has a destination selection switch 35 on its output side, which selects whether the output of that power phase is connected to the feedback bus section 41 or the dissipation bus section 42. Thus, whether the energy of each phase is recycled or used for heat dissipation can be scheduled phase-by-phase, providing the hardware basis for the energy destination switching described later.

[0051] The system controller 70 is connected to the port voltage sampling unit 22, the zero-crossing detection unit 34 for each inductor current, the switch drive terminal for each power phase 30, and the destination selection switch 35. Figure 1 These control and acquisition signals are shown in dashed lines. The system controller 70 can be implemented using a digital signal processor or an architecture combining a field-programmable logic device (FPGA) and a microcontroller. In the latter architecture, the FPGA is responsible for fine-grained control of the switching timing, while the microcontroller is responsible for non-real-time tasks such as template management.

[0052] Figure 2 This is a flowchart illustrating the discharge efficiency enhancement control method for interleaved parallel circuits provided in this application embodiment. The method is executed by the system controller 70. (Refer to...) Figure 2The process includes steps S101 to S106. In step S101, when the port voltage at the discharge port enters a preset low-voltage range, each power phase is controlled to enter intermittent conduction mode. In step S102, a switching cycle is selected as an observation period according to a preset observation cycle. Within the observation period, the conduction start times of each power phase are rearranged to form a full-phase zero-current observation window. In step S103, the port voltage is collected at the sampling time within the full-phase zero-current observation window, and the collected results are used as zero-current voltage sample values. In step S104, the zero-current voltage sample values ​​obtained from multiple observation periods are used to form a zero-current voltage sequence, which is compared with the template in the discharge completion template library to generate a discharge completion determination result. In step S105, the staggered phase difference of each power phase is restored after the observation period ends. Subsequently, the corresponding branch is executed according to the discharge completion determination result. If the determination result indicates that the discharge is not complete, each power phase is controlled to continue discharging, and the process returns to the next observation period to continue observation. If the determination result indicates that the discharge is complete, step S106 is executed, each power phase is controlled to stop conducting, and the discharge process ends. The following will proceed step by step in this order.

[0053] First, let's look at step S101, which is the switching of the final discharge mode. The final mode control module 71 compares the port voltage collected in real time by the port voltage sampling unit 22 with the preset low voltage range. If the voltage falls into this range, it is determined that the discharge has entered the final stage. Taking the capacity grading process with a module composed of sixteen lithium iron phosphate cells as battery unit 10 and the discharge endpoint being 2.8 volts per cell (44.8 volts for the module) as an example, the preset low voltage range can be 44.8 volts to 51.2 volts, corresponding to 2.8 volts to 3.2 volts per cell, which is a segment where the voltage has not yet reached the endpoint but is close to it. Generally, the lower limit of the preset low voltage range is the discharge endpoint voltage, which is the product of the cell termination voltage and the number of cells in series; the upper limit is the sum of the discharge endpoint voltage and the voltage margin. The voltage margin is the product of the cell voltage margin and the number of cells in series. The cell voltage margin is selected according to the battery chemistry system and can be 0.2 volts to 0.4 volts. The discharge plateau of lithium iron phosphate is flat, but the voltage drop at the end is steep, so the voltage margin of a single cell should be taken from the lower limit. Ternary and lithium cobalt oxide cells have a gentler slope at the end, so the upper limit should be taken. The aforementioned embodiment yields a 6.4V margin based on 16 series cells and a 0.4V single-cell voltage margin. The single-cell voltage margin should also satisfy a constraint: its product with the number of series cells should not be less than twice the product of the maximum discharge current at the end and the upper limit of the loop resistance. With a maximum of 24A and a loop resistance of 50 milliohms, this product is 1.2V, and twice that is 2.4V, which is less than the aforementioned 6.4V, indicating sufficient margin. This setting is based on the consideration that the port voltage is mixed with loop voltage drop when current is present. The margin must include the uncertainty of the voltage drop to ensure that the observation mechanism is activated before the actual battery voltage approaches the endpoint. If the margin is too large, observation will be activated before the end, unnecessarily increasing the control burden and the ripple disturbance caused by the observation beat. Such an interval is drawn because the observation mechanism is only necessary to be activated at the end. Before that, the battery voltage is far from the judgment threshold, and a routine coarse judgment is sufficient.

[0054] After entering the preset low-voltage range, each power phase 30 is controlled to enter intermittent conduction mode. Intermittent conduction mode refers to the operating state in which the inductor current returns to zero and remains at zero for a period of time in each switching cycle. This period of zero current is referred to as the intermittent idle interval in this application. At the end of the discharge, the total current is suppressed by the process curve, and the current of each phase is small. After the main switch 32 is turned off, the inductor 31 quickly releases all the stored energy, and the inductor current naturally returns to zero. Intermittent conduction mode is the natural state of this type of converter under the small current at the end of the discharge. This application explicitly controls it. Specifically, the inductor current zero-crossing detection unit 34 detects the moment when the inductor current of the power phase returns to zero and turns off the freewheeling switch 33 of the power phase at the moment when the inductor current returns to zero, so that the inductor current remains zero before the next conduction of the power phase. If the freewheeling switch 33 is not turned off at the moment of zero return, the inductor current will cross the zero point and flow in the opposite direction, feeding the released energy back into the battery cell 10, and the zero-current window will no longer be established.

[0055] The inductor current zero-crossing detection unit 34 can be implemented using a milliohm-level sampling resistor connected in series in the inductor branch and a high-speed comparator, or it can directly compare the polarity of the on-state voltage drop across the freewheeling switch 33. Synchronous rectifier controllers generally have this type of detection function built in. The detected zero-crossing signal is sent to the switch drive logic to turn off the freewheeling switch 33, and to the system controller 70 for recording, which is used to determine the starting point of the all-phase zero-current observation window.

[0056] Next, let's look at step S102, which is the core action of this application. The observation beat scheduling module 72 selects a switching cycle as the observation beat according to a preset observation period. The observation beat is a switching cycle specifically selected for observation. One is selected at every preset number of switching cycles. During the unselected switching cycles, each power phase 30 maintains an interleaved phase difference. The preset number can be 500 to 5000 switching cycles, but in engineering, 1000 cycles are usually chosen. With a switching frequency of 50 kHz, the switching cycle is 20 microseconds. An interval of 1000 beats is equivalent to an observation every 20 milliseconds. If the interval is too dense, the rearrangement will be too frequent and the proportion of ripple disturbance will increase. If it is too sparse, the sequence update will be slow and the judgment will be lagging. A 20-millisecond beat is more than sufficient for the voltage change rate on the order of millivolts per second in the final stage.

[0057] During the observation frame, the conduction rearrangement module 73 rearranges the conduction start times of each power phase 30, so that the intermittent idle intervals of each phase overlap at the end of the observation frame, forming a full-phase zero-current observation window where the inductance current of each power phase is zero. Figure 3 This is a timing diagram illustrating the rearrangement of the in-phase conduction start time and the formation of the full-phase zero-current observation window, as provided in the embodiments of this application. Figure 3 Draw the inductor current waveforms from power phase 1 to power phase 3 sequentially from top to bottom. The three power phases are labeled power phase 1, power phase 2, and power phase 3 respectively for clarity; in hardware, they are three power phases. (Combined with...) Figure 3 It can be seen that during the normal switching cycle before the observation, the start times of the three-phase conduction are evenly staggered according to the staggered phase difference, and the intermittent idle intervals of each phase are also staggered. Even if there are occasional sections with zero current at the same time, the width is only on the order of sub-microseconds and drifts with the operating conditions. This is insufficient to allow the port voltage to relax completely, and it is also impossible to pre-align the sampling time. Therefore, a reliable zero-current measurement window is out of the question.

[0058] The rearrangement rule within the observation frame is as follows: the power phases are arranged according to a preset arrangement order, with the conduction start time of the first power phase set at the beginning of the observation frame. The conduction start time of each subsequent power phase is delayed by a preset arrangement interval relative to the previous one. The preset arrangement interval is much smaller than the staggered phase difference, for example, 0.5 microseconds to 2 microseconds, typically 1 microsecond. In this way, the conduction intervals of the main switch 32 and the freewheeling switch 33 in each phase are concentrated in the first part of the observation frame. After the inductor currents of each phase successively return to zero, the last part of the observation frame has a period of time when all phases have no current.

[0059] The latest time when the inductor current of each power phase returns to zero is taken as the starting point of the all-phase zero-current observation window, and the end point of the observation period is taken as the end point of the all-phase zero-current observation window. Taking a 20-microsecond switching cycle and a 1-microsecond arrangement interval as an example, the total conduction and freewheeling time of each phase at the lowest current level in the last stage is about 6 to 9 microseconds. The third phase starts at 2 microseconds, and the latest time to return to zero is no later than 11 microseconds. The all-phase zero-current observation window extends from the latest time to zero to the end point of the period at 20 microseconds, with a width of no less than 9 microseconds. The starting point of the window is taken as the latest time to zero because as long as there is still current in one phase, the loop voltage drop has not completely disappeared.

[0060] The reason for daring to break the interleaving within the observation period is that the cost is sufficiently limited. First, the rearrangement only occurs within the selected observation period, which is only one in a thousand switching cycles, accounting for a time fraction of one-thousandth, and its impact on capacity measurement is negligible. Second, the current in each phase at the end is inherently small, and the instantaneous rise in total current ripple caused by concentrated conduction is limited. The preset low-voltage range also ensures that this action only occurs at low current levels. Third, after the observation period ends, the conduction rearrangement module 73 immediately restores the interleaved phase difference of each power phase, such as... Figure 3 As shown in the period following the observation, the three-phase waveforms returned to a uniformly staggered state. The entire discharge process was completed without shutdown, which is a fundamental difference from methods such as stopping the machine and allowing it to stand still for voltage measurement.

[0061] Step S103 completes voltage acquisition within the all-phase zero-current observation window. The zero-current voltage sampling module 74 triggers the port voltage sampling unit 22 to sample during the sampling time within the window, and uses the acquired result as the zero-current voltage sampling value. The zero-current voltage sampling value is the port voltage sampled under all-phase zero-current conditions. When there is current during discharge, the current flows through the cables, connectors, and clamp contact points, generating a voltage drop. The port voltage is equal to the sum of the battery's true voltage and these loop voltage drops. However, the cable lengths and clamp contact conditions vary for each channel, making it impossible to uniformly deduct the voltage drop component. Within the window, the inductor current of all power phases is zero, and no current flows in the discharge circuit. The ohmic voltage drop disappears along with the current. At this time, the port voltage essentially contains no loop voltage drop, directly approximating the true voltage of battery cell 10. The voltage drop is eliminated by the physical fact of zero current, eliminating the need to identify loop resistance or calibrate the compensation model channel by channel.

[0062] Another engineering detail is the voltage settling time. A filter capacitor is typically connected to discharge port 21. Upon entering the window, the port voltage does not jump instantaneously, but relaxes to the battery's true voltage over a time constant determined by the filter capacitor and the loop resistance. To ensure the reliability of the sampled values, the width of the full-phase zero-current observation window is set to be no less than a preset multiple of this time constant. This preset multiple can be 3 to 5 times, typically 5 times. For example, if the port filter capacitor is 10 microfarads, the final loop resistance is 50 milliohms, and the time constant is 0.5 microseconds, then 5 times the time constant is 2.5 microseconds. The aforementioned window width of no less than 9 microseconds provides a margin. It should also be noted that the higher the current level, the later each phase returns to zero, and the narrower the window becomes. If the window width does not meet this condition, the conduction interval of each phase can be appropriately shortened within the observation period. The charge released less within the observation period can be compensated by the adjacent switching cycles. Alternatively, the capacitance level of the port filter capacitor can be reduced; both methods aim to ensure complete relaxation. The specific location of the sampling time within the window is also constrained by ringing attenuation, which is related to the ringing characteristic monitoring discussed later and will be explained in the relevant section.

[0063] Step S104 concatenates the zero-current voltage sampling values ​​obtained from each frame into a sequence and provides a determination. The zero-current voltage sampling values ​​from multiple consecutive observation frames form a zero-current voltage sequence in chronological order. The discharge completion determination module 75 compares this zero-current voltage sequence with the templates in the built-in discharge completion template library 7501 to generate a discharge completion determination result. The battery voltage in the final stage exhibits a slow rebound due to polarization recovery. Two batteries with the same single-point voltage may show different sequence trends, one rising and the other flat, carrying drastically different completion information. Using a sequence rather than a single sampling value for determination is precisely to capture this difference.

[0064] Figure 5 This is a schematic diagram illustrating the process of constructing and comparing the discharge positioning template library provided in an embodiment of this application. (Refer to...) Figure 5The construction of the discharge completion template library 7501 is performed sequentially for each historical discharge process. For each historical discharge process, zero-current voltage sampling values ​​are collected according to the observation time, forming a historical zero-current voltage sequence for that historical discharge process. After the discharge process stops and is left to stand for a preset time, the port voltage is remeasured to obtain the remeasured voltage. If the remeasured voltage falls within the preset completion voltage range, the historical discharge process is labeled as complete; otherwise, it is labeled as incomplete. The historical zero-current voltage sequence of that historical discharge process is used as a template feature vector, associated with the labeled values, and stored as a template in the discharge completion template library 7501. The preset timeout can be from 10 minutes to 60 minutes, typically 30 minutes, allowing the battery polarization to fully recover, so the remeasured voltage can serve as a baseline fact for whether completion has occurred. The preset completion voltage range is set around the discharge endpoint voltage specified by the process; for example, when the discharge endpoint is 44.8 volts for the module, it is set from 44.4 volts to 45.2 volts.

[0065] While static testing is generally considered reliable, it is also recognized as slowing down the production cycle. This application moves it from the online stage of each discharge to the offline stage of template accumulation. Each discharge on the production line no longer requires static testing, and the cost of static testing is only incurred once during the database construction stage.

[0066] During the online comparison phase, the distance metric between the zero-current voltage sequence and the template feature vectors of each template is calculated. The tag associated with the template with the smallest distance metric is determined as the discharge completion judgment result. The distance metric can be the sequence Euclidean distance, i.e., the square root of the sum of the squared differences at each point; when there are time scale differences between sequences, dynamic time warping distance can also be used, and this application embodiment does not impose any restrictions on this. To make the distances comparable, each sequence is of the same length and aligned according to the same rules. The sequence length can be eight to thirty-two beats, and the alignment method is end alignment, i.e., taking sixteen beats backward from the current judgment time as the endpoint. The template feature vectors are truncated according to the same rules when building the database.

[0067] The size of the discharge positioning template library 7501 ranges from hundreds to thousands of entries. A single 16-step template occupies only tens of bytes, and the computational load for retrieval does not burden the microcontroller. The template library is managed by battery model and process file. When a new model is introduced, the corresponding sub-library is activated. When the first batch of discharges for a new model is conducted, the sub-library is empty. In this case, the judgment degenerates to directly comparing the zero-current voltage sampling value with the preset positioning voltage range. At the same time, the templates are statically tested and accumulated according to the aforementioned construction process. Once the number of templates reaches the set lower limit, the system automatically switches back to template comparison mode, thus completing the cold start. The set lower limit can be 30 to 200 templates, with 50 usable values. It is required that the number of templates with positioning tags and those without positioning tags is no less than one-third of the set lower limit. When the initial zero-current voltage sampling value in the final stage is insufficient for the preset sequence length, the direct comparison method is also used. Once the sequence length is reached, the system switches to template comparison. The sub-library is also continuously updated with production. Each time a discharge with static testing is completed, a new template is added. The judgment criteria are updated accordingly when batch characteristics drift.

[0068] The restoration of the interleaved phase difference in step S105 is completed by the conduction rearrangement module 73, which does not depend on the judgment result. It restores the operation first and then digests the judgment to ensure continuous discharge. The discharge execution module 76 acts according to the discharge completion judgment result. If the judgment result indicates that the discharge has not been completed, it selects the corresponding total discharge current setting value from the preset current range table according to the voltage range of the zero-current voltage sampling value obtained from the most recently selected observation frame, and controls each power phase 30 to continue discharging according to the selected total discharge current setting value. The preset current range table stores the correspondence between voltage ranges and total discharge current setting values. For example, when the zero-current voltage sampling value is higher than 48 volts, the total discharge current setting value is 24 amps; when it is between 46 volts and 48 volts, it is 12 amps; and when it is lower than 46 volts, it is 6 amps. The closer the voltage is to the end, the smaller the current, which suppresses the polarization amplitude at the end and makes the zero-current voltage sequence have higher resolution near the end.

[0069] When the judgment result is properly characterized, within the all-phase zero-current observation window of the most recently selected observation frame after the judgment result is generated, the main switch 32 and freewheeling switch 33 of all power phases 30 are turned off. The shutdown action is scheduled to be performed within the window. When the circuit current is turned off, it is already zero. No current is forcibly cut off, so there is no voltage spike or arcing during the shutdown. This is the second purpose of the all-phase zero-current observation window in addition to measurement.

[0070] Here, the shutdown action lags behind the generation of the discharge completion determination result: the determination result is generated when the sampling and comparison of a certain observation period is completed, while the main switch 32 and freewheeling switch 33 that shut off all power phases 30 will not be executed until the full-phase zero-current observation window of the next selected observation period. There is a waiting time between the two, which needs to be clearly explained. The zero-current voltage sequence adopts end alignment, and the last sampled value of the determination basis is taken from the most recent observation period. The sequence length itself does not introduce lag; the lag only comes from the time between the generation of the determination result and the shutdown execution, waiting for the next observation period, which is at most one preset observation period, 20 milliseconds in the example. During the lag period, each power phase 30 neither switches its operating mode nor changes its current level, and continues to discharge in the intermittent conduction mode according to the most recently selected total discharge current setting value. The port voltage continues to decline slightly, and there is no current surge. Regarding discharge accuracy, when the discharge is determined to be complete, the current level is already at its lowest setting, 6 amps in this example. The amount of charge discharged during the lag period is approximately the product of 6 amps and 20 milliseconds, or 0.12 amp-seconds, or 0.033 milliampere-hours. This is less than one millionth of a 50 amp-hour cell, far below the capacity measurement resolution of one-thousandth of a grading process. This is another consideration in this application of linking the current level with the determination result: the closer to the endpoint, the smaller the current, and the over-discharge caused by the lag narrows accordingly, eliminating the need for a separate mechanism to eliminate the lag. In other embodiments, if the process has stricter requirements for endpoint consistency, the preset observation period can be shortened from one thousand switching cycles to one hundred switching cycles when the zero-current voltage sequence approaches within a preset margin of the preset endpoint voltage range. The lag is then compressed to the order of two milliseconds. The cost is that the proportion of observation time in this stage increases from one-thousandth to one-hundredth, but the discharge continuity remains unaffected.

[0071] The core solution has now been completed. Next, we will explain the first auxiliary improvement, namely phase path health monitoring based on ringing characteristics. Figure 4 This is a schematic diagram of the ringing waveform segment and ringing feature extraction provided in an embodiment of this application. After the inductor current of each power phase 30 returns to zero and the freewheeling switch 33 is turned off, the inductor 31 and the parasitic capacitance at the connection node form a resonant circuit, and the voltage at the switching node oscillates with decay around the steady-state level. Figure 4 The waveform shown by the solid line is referred to as the ringing waveform segment in this application. Conventional designs treat ringing as switching noise and try to absorb and suppress it. This application takes the opposite approach and records it for use. Within the observation period, starting from the moment the inductor current of each power phase returns to zero, the switching node voltage at the connection point between inductor 31 and main switch 32 in that power phase is collected, forming the ringing waveform segment of that power phase. The acquisition is only performed within the observation period. The zero-return time of each phase within the observation period has been recorded, and the acquisition window can be precisely aligned. However, ringing sampling requires a megahertz-level high-speed channel, and it is unnecessary to keep it open for each period.

[0072] Ringing features are extracted from the ringing waveform segment, including oscillation frequency and decay time. The oscillation frequency is determined by the inductance and parasitic capacitance of the resonant circuit, and can be obtained by statistically analyzing the time intervals between zero-crossing points of the ringing waveform. Twice the interval between adjacent zero-crossing points constitutes the oscillation period, which is averaged over several periods to suppress noise. The decay time is the time it takes for the oscillation amplitude of the ringing waveform segment to decay to below a preset amplitude threshold. In engineering practice, peak detection is used to extract the envelope, recording the moment when the envelope first remains consistently below the preset amplitude threshold from the zero-crossing point. The preset amplitude threshold is set based on the noise fluctuation band near the steady-state level, and can be 2 to 3 times the noise band width. Figure 4 The figure is shown as a pair of horizontal dotted lines above and below the steady-state level. For example, an inductance of 22 microhenries and a parasitic capacitance of 470 picofarads correspond to an oscillation frequency of approximately 1.5 MHz and a decay time on the order of several microseconds.

[0073] The ringing characteristics of each power phase are compared with the ringing reference template of that power phase. The ringing reference template is an archive of the ringing characteristics of that power phase under healthy conditions. Its construction process is as follows: during the reference calibration stage after the interleaved parallel circuit 20 is connected to the battery cell 10, the ringing waveform segment of that power phase is collected and the ringing characteristics are extracted. The extracted oscillation frequency and decay time are stored in the ringing reference template of that power phase as the reference oscillation frequency and reference decay time, respectively. Figure 4 The waveform corresponding to the ringing reference template is drawn with a dashed line for comparison. What is actually stored is the characteristic value rather than the entire waveform.

[0074] The comparison rule is as follows: when the deviation between the oscillation frequency and the reference oscillation frequency exceeds the preset frequency deviation range, or when the deviation between the decay time and the reference decay time exceeds the preset time deviation range, the path health flag of that power phase is set to a deteriorated state; otherwise, it is set to a normal state. The path health flag is maintained phase-by-phase for subsequent current allocation decisions. The preset frequency deviation range can be ±5% to ±15%, typically ±10%; the preset time deviation range can be ±10% to ±30%, with ±20% being a usable value. Loose contacts or oxidation increase loop resistance, mainly manifested as a shortened decay time; device aging and solder joint fatigue alter parasitic parameters, mainly manifested as oscillation frequency drift. Each of the two features is sensitive to one type of deterioration; exceeding either limit results in a deterioration judgment, avoiding missed alarms. Each phase is compared to its own reference rather than between phases because the parasitic parameters of each phase naturally have individual differences; self-comparison allows manufacturing variations to be excluded from alarm conditions.

[0075] Ringing monitoring directly feeds back to core measurements; this is the adaptive setting of the sampling time. The sampling time is set after the start of the full-phase zero-current observation window, and the interval between the sampling time and the start of the window is not less than the maximum value of the decay time of each power phase. Figure 4Taking the power phase that returns to zero last as an example, this constraint is illustrated. The zero-return time of this phase coincides with the start of the window. Therefore, the starting point of the observation window is indicated by the bracketed position at the time the inductor current returns to zero in the figure. Waiting for the slowest ringing to dissipate is crucial because the zero-current voltage sampling value requires a pure DC level. The ringing residual waves from any phase will introduce millivolt-level jitter, and the final judgment is concerned with millivolt-level differences. The decay time is a quantity measured for each observation phase, so the sampling time adaptively shifts according to the actual state of the equipment, without needing to leave a dead margin for the worst-case scenario. Again, using a window width of approximately 9 microseconds and a maximum decay time of 3 microseconds as an example, the sampling time can be set 5 microseconds after the start of the window, accommodating both the ringing dissipation and voltage relaxation conditions.

[0076] The path health indicator further intervenes in current distribution. As each power phase continues to discharge, the total discharge current setting value used for continued discharge is allocated to the phase current setting value of each power phase. The phase current setting value of the power phase marked as deteriorated in path health is lowered by a preset adjustment amount, and this reduced current is evenly distributed to the phase current setting values ​​of the power phase marked as normal in path health. The preset adjustment amount can be between 10% and 30% of the original allocated value for that phase, and can be 20%. Taking a total discharge current setting of 24 amps, evenly divided into 8 amps per phase across the three phases, as an example, when one phase is marked as deteriorated, that phase is lowered by 1.6 amps to 6.4 amps, and the other two phases are each increased by 0.8 amps to 8.8 amps. The total current remains unchanged, the process curve is unaffected, only the current flow between phases changes. Deteriorated paths generate less heat, thus reducing discharge link losses and thermal risks.

[0077] The total discharge current setting decreases gradually as discharge progresses. When it drops to a certain level, the current in each phase becomes too small, and each phase falls into the degraded region of the efficiency curve. Therefore, when the total discharge current setting is below a preset phase reduction threshold, the number of power phases to remain conducting is determined from a preset reduction level table based on the current range of the total discharge current setting, and the conduction of the remaining power phases is stopped. When stopping conduction, the power phases with a path health flag indicating a degraded state are prioritized. The preset reduction level table stores the correspondence between current ranges and the number of power phases to remain conducting. For example, if the preset phase reduction threshold is 10 amps, two phases are retained when the total discharge current setting is between 6 amps and 10 amps, and one phase is retained when it is below 6 amps. The current of the stopped phase is taken over by the retained phase, which returns to its more efficient current operating point. Prioritizing the shutdown of the degraded phase transforms the reduction action into protection for weak paths.

[0078] The second improvement addresses the issue of where the discharged energy goes. As the feedback power decreases towards the end of the discharge, the efficiency of the energy feedback branch 50 drops sharply after entering the light load region, becoming so low that it cannot even stably connect to the grid. At this point, some or all of the energy should be diverted to the energy dissipation branch 60. However, forcibly switching the direction selection switch 35 while carrying current would cause current interruption and bus voltage spikes, and the final stage is precisely the period when measurement and processes are most vulnerable to disturbances. This application addresses this by anchoring the switching action to the full-phase zero-current observation window, where the loop current is zero, resulting in a shock-free switching process.

[0079] Figure 6 This is a schematic flowchart of the destination selection switch switching control provided in an embodiment of this application, referring to... Figure 6 The process includes steps S201 to S205. In step S201, the feedback power of the energy feedback branch 50 and the bus voltage of the feedback bus section 41 are collected. The feedback power can be obtained by multiplying the bus voltage by the current flowing into the energy feedback branch 50, or by directly reading the power telemetry value reported by the grid-connected converter. Then, it is determined whether the feedback power is lower than the preset feedback lower limit power, or whether the bus voltage is higher than the preset bus voltage upper limit. If neither condition is met, the process returns to step S201 to continue monitoring. If either condition is met, step S202 is executed to generate a switching command.

[0080] The preset lower limit power for feedback is set based on the minimum power at which the energy feedback branch 50 can operate stably. It can be set to 5% to 10% of its rated power, for example, 60 watts for a 1.2 kW rated feedback branch. The preset upper limit for bus voltage is slightly higher than the rated bus voltage, for example, 104 volts for a 96 volt bus. The former condition corresponds to the feedback branch not being fully utilized, and the latter corresponds to the bus voltage rising due to insufficient utilization. Both are signs that the current number of feedback phases cannot be maintained, so they are listed as trigger conditions.

[0081] In step S203, multiple power phases are divided into multiple switching groups. In the multiple observation frames selected sequentially after the switching command is generated, only one power phase's destination selection switch within each switching group is switched within the full-phase zero-current observation window of each observation frame. This allows the output of the switched power phase 30 to be connected from the feedback bus segment 41 to the dissipation bus segment 42. Switching by group window instead of a full switch at once is advantageous because: firstly, each full-phase zero-current observation window is only on the order of 10 microseconds, making the timing of driving all switches within a single window very tight; switching by group window allows for more flexibility. Secondly, switching by group allows the feedback power to decrease in a step-like manner, giving the energy feedback branch 50 time to adjust its operating point. For example, the six power phases can be divided into three groups of two phases each, with an interval of 20 milliseconds between adjacent observation frames. The switching of the three groups is completed within 60 milliseconds, which is still considered fast action for the final stage of the process, which is measured in seconds.

[0082] In step S204, the number of power phases 30 connected to the feedback bus section 41 is determined from a preset destination allocation table based on the voltage range of the bus voltage. The preset destination allocation table stores the correspondence between voltage ranges and the number of power phases connected to the feedback bus section 41. For example, in a 96V bus system, all phases are connected to the feedback bus section 41 when the bus voltage is not higher than 100V, half of the phases are retained in the 100V to 104V range, one phase is retained in the 104V to 108V range, and zero phases are retained when the voltage is higher than 108V. The allocation table first gives the target number of phases, and the group switching in step S203 is performed window by window according to the target. The allocation table determines how many phases are switched, and the grouping determines how they are switched. Thus, the number of phases retained on the feedback bus section 41 is always commensurate with the absorption capacity of the energy feedback branch 50. When the feedback power is lower than the preset feedback lower limit power while the bus voltage is in the normal range, it indicates that the overall discharge power is lower than that required for the stable operation of the energy feedback branch 50. At this time, the target phase number is set to zero, and each switching group is switched out to the dissipation bus section 42 window by window.

[0083] In step S205, when the feedback power exceeds the preset feedback lower limit power again, the output of the corresponding power phase 30 is connected from the dissipation bus section 42 to the feedback bus section 41 in the switching group within the successively selected full-phase zero-current observation window of the observation frame. The same zero-current window and the same grouping window-by-window are restored, symmetrical to the cut-out path. In the scenario of cutting out due to the bus voltage exceeding the limit, the bus voltage drops back to the normal range and is switched back group by group. In the scenario of cutting out all due to insufficient feedback power, the discharge is nearing its end and is usually not switched back. If the process requires the restoration of feedback, a switching group is first tentatively switched back and the feedback power is measured. After confirming that it is higher than the preset feedback lower limit power, the remaining power phases 30 are restored group by group. Thus, the recoverable electrical energy is returned to the power supply network through the energy feedback branch 50 as much as possible. Only the part exceeding its stable absorption capacity is transferred to the energy dissipation branch 60 for heating. The recovery ratio of discharge energy is pushed to the upper limit allowed by the equipment conditions.

[0084] The selection of components for the destination selection switch 35 deserves separate explanation. With a full-phase zero-current observation window width on the order of 10 microseconds, and requiring the switching action to be completed within this window, the destination selection switch 35 can be implemented using a semiconductor switch, such as a bidirectional switch composed of two metal-oxide-semiconductor field-effect transistors connected back-to-back. When directly driven by the drive circuit, the switching time is in the sub-microsecond range, ensuring the action is completed within the window. In other embodiments, the destination selection switch 35 can also use a solid-state relay or an electromechanical relay. Solid-state relays typically have a setup time of tens of microseconds or more, while electromechanical relays have contact actions in the millisecond range. Neither can guarantee completion within the window. In this case, the system controller 70 issues a switching command within the full-phase zero-current observation window and maintains zero current in the relevant power phase by delaying the next conduction until the switching action is completed, thus ensuring contact action under zero-current conditions. The former achieves fast switching and no contact wear, while the latter achieves lower conduction losses and is more cost-effective. The choice in actual implementation depends on the overall cost and lifespan of the system.

[0085] Figure 7 A schematic diagram of the system controller provided in an embodiment of this application. (Refer to...) Figure 7 The system controller 70 includes a final-stage mode control module 71 and an observation and scheduling module 72, as well as a conduction rescheduling module 73, a zero-current voltage sampling module 74, a discharge completion determination module 75, and a discharge execution module 76. The discharge completion determination module 75 has a built-in discharge completion template library 7501. The port voltage collected by the port voltage sampling unit 22 is distributed to the final-stage mode control module 71 and the zero-current voltage sampling module 74. The final-stage mode control module 71 executes the processing of step S101 above, controlling each power phase to enter intermittent conduction mode when the port voltage enters a preset low-voltage range. Figure 7 The diagram shows the discontinuous conduction mode control issued to the interleaved parallel circuit 20. The observation frame scheduling module 72 selects observation frames according to the preset observation period, corresponding to the frame selection action in step S102.

[0086] The conduction rearrangement module 73 rearranges the conduction start times of each power phase within the observation period to form a full-phase zero-current observation window, and restores the staggered phase difference after the observation period ends, corresponding to the rearrangement action in step S102 and step S105. Figure 7 The diagram shows the start time of conduction sent to the interleaved parallel circuit 20. The zero-current voltage sampling module 74 acquires the port voltage at the sampling time within the window to obtain the zero-current voltage sampling value, corresponding to step S103.

[0087] The discharge completion determination module 75 compares the zero-current voltage sequence with the templates in the discharge completion template library 7501 to generate a discharge completion determination result, corresponding to step S104. The discharge execution module 76 controls each power phase to continue discharging or stop conducting based on the determination result, corresponding to step S106 and the incomplete discharge branch. Figure 7 The diagram shows the instruction sent to the interleaved parallel circuit 20 to continue discharging or stop conducting. Each module can be a software module running on the same processor, or it can be implemented on logic devices and microcontrollers according to real-time requirements. The module division expresses the boundary of responsibility rather than the physical boundary.

[0088] The system provided in this application embodiment belongs to the same inventive concept as the aforementioned method. The implementation of the intermittent conduction mode and the details of observation and beat rearrangement, template library construction and cold start, as well as ringing characteristic monitoring and energy destination switching in the method section can all be executed by the corresponding modules of this system. The repeated parts will not be described again.

[0089] The above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Those skilled in the art should understand that modifications can be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features, and such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application.

Claims

1. A discharge efficiency enhancement control method for interleaved parallel circuits, characterized in that, This is applied to the process of discharging a battery cell using an interleaved parallel circuit. The interleaved parallel circuit includes multiple power phases connected between a discharge port and a DC bus. The discharge port is connected to the battery cell, and each power phase is switched on at an alternate phase difference. The method includes: when the port voltage of the discharge port enters a preset low voltage range, controlling each power phase to enter an intermittent conduction mode, so that each power phase has an intermittent idle range in which the inductor current remains zero in each switching cycle. Select a switching cycle as the observation period according to the preset observation period, and rearrange the conduction start time of each power phase within the observation period so that the intermittent idle intervals of each power phase overlap with each other at the end of the observation period, forming a full-phase zero-current observation window in which the inductance current of each power phase is zero. The port voltage is acquired at the sampling time within the full-phase zero-current observation window, and the acquisition result is used as the zero-current voltage sample value. The zero-current voltage sampling values ​​obtained from multiple observations are used to form a zero-current voltage sequence. The zero-current voltage sequence is compared with the templates in the discharge in-place template library to generate a discharge in-place determination result. The process of constructing the discharge arrival template library includes: for each historical discharge process, collecting zero-current voltage sampling values ​​according to the observation frame to form a historical zero-current voltage sequence for that historical discharge process; After the discharge process stops and the port voltage is left to stand for a preset time, the port voltage is remeasured to obtain the remeasured voltage. If the remeasured voltage falls into the preset arrival voltage range, the historical discharge process is marked as in place; otherwise, the historical discharge process is marked as not in place. The historical zero-current voltage sequence of this historical discharge process is used as a template feature vector, and after being associated with the labeled tag, it is stored as a template in the discharge in-place template library; Comparing the zero-current voltage sequence with the templates in the discharge in place template library includes: calculating the distance metric between the zero-current voltage sequence and the template feature vectors of each template, and determining the label associated with the template with the smallest distance metric as the discharge in place determination result; After the observation period ends, the staggered phase difference of each power phase is restored. If the discharge completion determination result is not yet complete, each power phase is controlled to continue discharging. If the discharge completion determination result is complete, each power phase is controlled to stop conducting.

2. The discharge efficiency enhancement control method for interleaved parallel circuits according to claim 1, characterized in that, Each of the power phases includes an inductor, a main switch, a freewheeling switch, and an inductor current zero-crossing detection unit; Controlling each power phase to enter the intermittent conduction mode includes: detecting the moment when the inductor current of the power phase returns to zero by the inductor current zero-crossing detection unit of the power phase, and turning off the freewheeling switch of the power phase at the moment when the inductor current returns to zero, so that the inductor current of the power phase remains zero before the next conduction of the power phase. The observation period is selected as follows: a switching cycle is selected as the observation period at a preset number of switching cycles. During the switching cycles that are not selected as the observation period, each power phase continues to operate according to the staggered phase difference.

3. The discharge efficiency enhancement control method for interleaved parallel circuits according to claim 2, characterized in that, The rearrangement of the conduction start times of each power phase includes: arranging each power phase in a preset arrangement order, setting the conduction start time of the power phase that is first in the arrangement order at the starting point of the observation frame, and setting the conduction start time of each power phase that is later in the arrangement order to be delayed by a preset arrangement interval relative to the conduction start time of the power phase preceding it, so that the conduction interval of the main switch and the freewheeling interval of the freewheeling switch in each power phase are concentrated in the front section of the observation frame; The latest time when the inductor current of each power phase returns to zero is taken as the starting point of the full-phase zero-current observation window, and the end point of the observation frame is taken as the end point of the full-phase zero-current observation window.

4. The discharge efficiency enhancement control method for interleaved parallel circuits according to claim 2, characterized in that, When the discharge completion determination result indicates that the discharge has not been completed, controlling each power phase to continue discharging includes: selecting the corresponding total discharge current setting value from the preset current range table according to the voltage range of the zero-current voltage sampling value obtained from the most recently selected observation frame, and controlling each power phase to continue discharging according to the selected total discharge current setting value. The preset current range table stores the correspondence between voltage ranges and total discharge current setting values. Controlling each power phase to stop conducting when the discharge arrival determination result is in place includes: turning off the main switches and freewheeling switches of all power phases within the full-phase zero-current observation window of the most recently selected observation frame after the discharge arrival determination result is generated.

5. The discharge efficiency enhancement control method for interleaved parallel circuits according to claim 2, characterized in that, The method further includes: within the observation frame, starting from the moment when the inductor current of each power phase returns to zero, collecting the switching node voltage at the connection node between the inductor and the main switch in that power phase to form the ringing waveform segment of that power phase; The ringing features are extracted from the ringing waveform segment, and the ringing features include the oscillation frequency and the decay time. The decay time is the time it takes for the oscillation amplitude of the ringing waveform segment to decay to below a preset amplitude threshold. The ringing characteristics of each power phase are compared with the ringing reference template of that power phase. When the deviation between the oscillation frequency and the reference oscillation frequency in the ringing reference template exceeds the preset frequency deviation range, or when the deviation between the decay time and the reference decay time in the ringing reference template exceeds the preset time deviation range, the path health flag of that power phase is set to a degraded state; otherwise, the path health flag of that power phase is set to a normal state. The construction process of the ringing reference template is as follows: in the reference calibration stage after the battery cell is connected to the interleaved parallel circuit, the ringing waveform segment of the power phase is collected and the ringing characteristics are extracted. The extracted oscillation frequency and decay time are stored as the reference oscillation frequency and the reference decay time, respectively, in the ringing reference template of the power phase.

6. The discharge efficiency enhancement control method for interleaved parallel circuits according to claim 5, characterized in that, The method further includes: setting the sampling time after the start of the full-phase zero-current observation window, and the interval between the sampling time and the start of the full-phase zero-current observation window is not less than the maximum value of the decay time of each power phase; When each power phase continues to discharge, the total discharge current setting value on which each power phase continues to discharge is allocated as the phase current setting value of each power phase. The phase current setting value of the power phase with path health marked as deteriorated is reduced by a preset adjustment amount, and the reduced current amount is evenly distributed to the phase current setting value of the power phase with path health marked as normal. When the total discharge current setting value is lower than the preset phase reduction threshold, the number of power phases to be kept on is determined from the preset reduction level table according to the current range in which the total discharge current setting value is located, and the conduction of the remaining power phases is stopped. When stopping conduction, the power phases with the path health marked as deteriorated are selected first. The preset reduction level table stores the correspondence between the current range and the number of power phases to be kept on.

7. The discharge efficiency enhancement control method for interleaved parallel circuits according to claim 1, characterized in that, The DC bus includes a feedback bus section and a dissipation bus section. The feedback bus section is connected to an energy feedback branch for feeding the discharge energy back to the power supply network. The dissipation bus section is connected to an energy dissipation branch for converting the discharge energy into heat. Each power phase is provided with a destination selection switch on its output side. The destination selection switch is used to select one of the outputs of the power phase to be connected to the feedback bus section or the dissipation bus section. The method further includes: collecting the feedback power of the energy feedback branch and the bus voltage of the feedback bus section, and generating a switching command when the feedback power is lower than the preset lower limit power or when the bus voltage is higher than the preset upper limit voltage. In response to the switching command, at least one of the power phase destination selection switches is switched within the full-phase zero-current observation window of the observation frame selected after the switching command is generated, so that the output of the switched power phase is connected to the dissipation bus section from the feedback bus section.

8. The discharge efficiency enhancement control method for interleaved parallel circuits according to claim 7, characterized in that, Switching the destination selection switch includes: dividing the multiple power phases into multiple switching groups, and in the multiple observation frames selected successively after the switching command is generated, switching only the destination selection switch of each power phase in the switching group within the full-phase zero-current observation window of each observation frame; The number of power phases connected to the feedback bus section is determined from a preset destination allocation table according to the voltage range of the bus voltage. The preset destination allocation table stores the correspondence between voltage ranges and the number of power phases connected to the feedback bus section. When the feedback power is higher than the preset feedback lower limit power again, the output of the corresponding power phase is connected from the dissipation bus section to the feedback bus section according to the switching group within the full-phase zero-current observation window of the successively selected observation frames.

9. A discharge efficiency enhancement control system for implementing the interleaved parallel circuit of claim 1, characterized in that, This includes interleaved parallel circuits and system controllers; The interleaved parallel circuit includes multiple power phases connected between the discharge port and the DC bus. The discharge port is connected to the battery unit and is equipped with a port voltage sampling unit. Each power phase includes an inductor, a main switch, a freewheeling switch, and an inductor current zero-crossing detection unit. The power phases are turned on at staggered start times according to the interleaved phase difference. The system controller includes a terminal mode control module, an observation and scheduling module, a conduction reordering module, a zero-current voltage sampling module, a discharge completion determination module, and a discharge execution module. The end-stage mode control module is used to control each power phase to enter the intermittent conduction mode when the port voltage collected by the port voltage sampling unit enters the preset low voltage range, so that each power phase has an intermittent idle range in each switching cycle in which the inductor current remains zero. The observation scheduling module is used to select a switching cycle as an observation cycle according to a preset observation cycle. The conduction rearrangement module is used to rearrange the conduction start times of each power phase within the observation frame, so that the intermittent idle intervals of each power phase overlap with each other at the end of the observation frame, forming a full-phase zero-current observation window in which the inductance current of each power phase is zero, and restoring the staggered phase difference of each power phase after the observation frame ends. The zero-current voltage sampling module is used to collect the port voltage at the sampling time within the full-phase zero-current observation window, and the collection result is used as the zero-current voltage sampling value. The discharge in place determination module has a built-in discharge in place template library, which is used to form a zero-current voltage sequence by multiple zero-current voltage sampling values ​​obtained from the observation, and compare the zero-current voltage sequence with the template in the discharge in place template library to generate a discharge in place determination result. The discharge execution module is used to control each power phase to continue discharging when the discharge completion determination result is not yet complete, and to control each power phase to stop conducting when the discharge completion determination result is complete.

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