A low temperature coefficient relaxation oscillator for holographic phased array antennas

Abstract

A low temperature drift coefficient relaxation oscillator for holographic phased array antenna belongs to the technical field of integrated circuits, and comprises an oscillator main body, an oscillator output stage comprising a sixth N tube and an eighth P tube connected in series between a power supply and ground, and a seventh N tube and a ninth P tube, the gates of the eighth P tube and the ninth P tube being connected to the drains of the ninth P tube and the eighth P tube respectively, the ninth P tube gate also being connected to the gates of a third P tube and a fifth N tube, and the gates of the eighth P tube and the ninth P tube serving as the oscillator output stage; and a driving matching module is further connected between the gates of the eighth P tube and the ninth P tube. The driving matching module is added to the relaxation oscillator, the oscillator output frequency obtained can be adjusted by adjusting the device parameters to achieve low temperature drift, the driving matching module can also reduce the discharge time of the oscillator, so that the oscillator can reach a higher frequency, and the circuit structure added in the improvement of the oscillator is simple, the number of devices is small, and the adjustment parameters are simple.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit technology and relates to the design of oscillator circuits in integrated circuits. Specifically, it relates to a low-temperature drift coefficient relaxation oscillator for holographic phased array antennas. Background Technology

[0002] Clock signals are the synchronous pulse of integrated circuits, providing a precise timing reference for all digital operations, and are typically generated by oscillators. They coordinate the synchronous operation of billions of transistors within the chip, and their frequency stability directly determines system performance and reliability. Relaxation oscillators generate square or triangular wave outputs through the periodic charging and discharging of energy storage elements such as capacitors and the state switching of switching elements such as transistors. Relaxation oscillators are characterized by a small number of components, low cost, ease of construction, convenient frequency adjustment, and self-oscillation without external clock triggering. However, because the performance of switching devices is easily affected by temperature and power supply voltage, the frequency is prone to fluctuations.

[0003] Beamforming in holographic liquid crystal phased array antennas relies on a TFT backplane to apply precise voltages to a large number of pixel units, achieving subwavelength-level modulation of liquid crystal molecule orientation. This is followed by holographic phase encoding to synthesize the target beam direction, requiring highly precise phase control for beam deflection. In real-world low-Earth orbit (LEO) satellite communication scenarios, terminals face even more severe temperature challenges: rapid acquisition and switching are needed between high-throughput payloads in the space segment and portable / mobile ground-based terminals. Holographic beam scanning algorithms require frequency stability within an ambient temperature range of -40°C to +70°C to ensure phase consistency between FFT phase synthesis and radial waveguide feeding. Existing oscillators rely solely on threshold switching of nonlinear components for oscillation, and their temperature coefficients are insufficient to meet this precision requirement. Therefore, improved temperature compensation designs are urgently needed to adapt to the high-stability frequency requirements of holographic liquid crystal phased array antennas. Summary of the Invention

[0004] The purpose of this invention is to provide a low-temperature drift coefficient relaxation oscillator for holographic phased array antennas, so as to solve the problems mentioned in the background art to a certain extent.

[0005] The low-temperature drift coefficient relaxation oscillator for holographic phased array antennas of the present invention includes an oscillator body, which includes a second P-type transistor and a fourth N-type transistor connected in series between a constant current source transistor and ground, as well as a third P-type transistor and a fifth N-type transistor; a first capacitor is connected between the common terminal of the second P-type transistor and the fourth N-type transistor and ground, and is also connected to the gate of the sixth N-type transistor in the oscillator output stage; a second capacitor is connected between the common terminal of the third P-type transistor and the fifth N-type transistor and ground, and is also connected to the gate of the seventh N-type transistor in the oscillator output stage. The oscillator output stage is characterized by comprising a sixth N-transistor and an eighth P-transistor connected in series between the power supply and ground, as well as a seventh N-transistor and a ninth P-transistor. The gates of the eighth P-transistor and the ninth P-transistor are respectively connected to the drains of the ninth P-transistor and the eighth P-transistor. The gate of the eighth P-transistor is also connected to the gates of the second P-transistor and the fourth N-transistor, and the gate of the ninth P-transistor is also connected to the gates of the third P-transistor and the fifth N-transistor. The gates of the eighth P-transistor and the ninth P-transistor serve as the oscillator output stage. A drive matching module is also connected between the gates of the eighth P-tube and the ninth P-tube. The drive matching module includes a first inverter and a second inverter with opposite directions and connected in parallel between the gates of the eighth P-tube and the ninth P-tube. The first inverter, whose input terminal is connected to the gate of the eighth P-tube, is composed of an eleventh P-tube and a twelfth N-tube. The second inverter, whose input terminal is connected to the gate of the ninth P-tube, is composed of a thirteenth P-tube and a fourteenth N-tube. The constant current source tube is used to output a current that does not change with temperature and power supply voltage; For the sixth N-tube, the eighth P-tube, and the thirteenth P-tube, we have: -G1*P T +N T =0, where G1=(gm8+gm 13 ) / gm6;N T and P T The threshold voltage temperature coefficients of N-type and P-type transistors are gm6, gm8, and gm, respectively. 13 These represent the transconductances of the sixth N-channel MOSFET, the eighth P-channel MOSFET, and the thirteenth P-channel MOSFET, respectively. For the seventh N-tube, the ninth P-tube, and the eleventh P-tube, we have: -G2*P T +N T =0, where G2=(gm9+gm 11 ) / gm7;N T and P T The threshold voltage temperature coefficients of N-channel and P-channel transistors, gm7, gm9, and gm, respectively. 11 These represent the transconductance of the seventh N-tube, the ninth P-tube, and the eleventh P-tube, respectively.

[0006] Preferably, the source of the constant current source transistor is connected to a power supply, and the gate voltage is provided by a constant current source module. The constant current source module includes an operational amplifier. The output terminal of the operational amplifier is connected to the gate of the tenth P transistor. The source and drain of the tenth P transistor are respectively connected to the power supply and the inverting input terminal of the operational amplifier. The inverting input terminal of the operational amplifier is also grounded through a resistor with zero temperature coefficient, and the non-inverting input terminal is connected to an external reference voltage.

[0007] Preferably, it further includes an output adjustment module connected to the gates of the eighth P transistor and the ninth P transistor. The output adjustment module includes an XNOR gate, the gates of the eighth P transistor and the ninth P transistor are respectively connected to the two input terminals of the XNOR gate, the output terminal E of the XNOR gate is connected to the clock terminal of the D flip-flop, the input terminal of the D flip-flop is connected to the inverted output terminal of the D flip-flop, and the non-inverted output terminal of the D flip-flop serves as the output terminal of the output adjustment module.

[0008] Preferably, the gates of the eighth P-tube and the ninth P-tube are respectively connected to a buffer consisting of two inverters IV connected in series, and the output of the buffer serves as a pair of outputs of the oscillator output stage.

[0009] Preferably, the system also includes a power supply module, which includes an operational amplifier. The non-inverting input of the operational amplifier receives an external reference voltage, and the inverting input is connected to the common terminal of a first resistor and a second resistor. The unconnected ends of the first and second resistors are connected to the output of the operational amplifier and ground, respectively.

[0010] Preferably, a capacitor is connected between the output terminal of the operational amplifier and ground.

[0011] This invention adds a drive matching module to an existing relaxation oscillator, allowing the oscillator output frequency to achieve low-temperature drift by adjusting device parameters. The drive matching module can also reduce the oscillator discharge time, enabling the oscillator to reach a higher frequency. Furthermore, the circuit structure added to the oscillator improvement in this invention is simple, requires fewer devices, and is easy to adjust parameters. Attached Figure Description

[0012] Figure 1 This is a schematic diagram of the circuit structure of a specific embodiment of the low-temperature drift coefficient relaxation oscillator for holographic phased array antenna described in this invention; Figure 2 This is a schematic diagram of a specific embodiment of the drive matching module described in this invention; Figure 3 This is a schematic diagram of a specific embodiment of the output adjustment module described in this invention; Figure 4 This is a schematic diagram of a specific embodiment of the power module described in this invention; Figure 5 This is a schematic diagram of a specific embodiment of the constant current source module described in this invention; Figure 6 This is a schematic diagram of a specific input-output waveform of the output adjustment module described in this invention; The image shows: AMP, Operational Amplifier; R1, First Resistor; R2, Second Resistor; R3, Third Resistor; R4, Fourth Resistor; XNOR, XNOR Gate; VCC, Power Supply; VREF, Reference Voltage; VB, Bias Voltage; OUT, Output Terminal; C1, First Capacitor; C2, Second Capacitor; C3, Third Capacitor; M1, Constant Current Source Transistor; M2, Second P-Transistor; M3, Third P-Transistor; M4, Fourth N-Transistor; M5, Fifth N-Transistor; M6, Sixth N-Transistor; M7, Seventh N-Transistor; M8, Eighth P-Transistor; M9, Ninth P-Transistor; M10, Tenth P-Transistor; M11, Eleventh P-Transistor; M12, Twelfth N-Transistor; M13, Thirteenth P-Transistor; M14, Fourteenth N-Transistor. Detailed Implementation

[0013] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments.

[0014] like Figure 1 As shown, the low-temperature drift coefficient relaxation oscillator for holographic phased array antennas of the present invention includes an oscillator body, which includes a second P-type transistor M2 and a fourth N-type transistor M4 connected in series between a constant current source transistor M1 and ground, as well as a third P-type transistor M3 and a fifth N-type transistor M5; a first capacitor C1 is connected between the common terminal of the second P-type transistor M2 and the fourth N-type transistor M4 and ground, and is also connected to the gate of the sixth N-type transistor M6 in the oscillator output stage; a second capacitor is connected between the common terminal of the third P-type transistor and the fifth N-type transistor M5 and ground, and is also connected to the gate of the seventh N-type transistor M7 in the oscillator output stage. The oscillator output stage includes a sixth N-transistor M6 and an eighth P-transistor M8 connected in series between the power supply and ground, as well as a seventh N-transistor M7 and a ninth P-transistor M9. The gates of the eighth P-transistor M8 and the ninth P-transistor M9 are connected to the drains of the ninth P-transistor and the eighth P-transistor, respectively. The gate of the eighth P-transistor M8 is also connected to the gates of the second P-transistor M2 and the fourth N-transistor M4, and the gate of the ninth P-transistor M9 is also connected to the gates of the third P-transistor M3 and the fifth N-transistor M5, serving as a pair of output terminals of the oscillator output stage. A drive matching module DP is also connected between the gates of the eighth P-tube M8 and the ninth P-tube M9. The drive matching module DP includes a first inverter and a second inverter connected in parallel between the gates of the eighth P-tube M8 and the ninth P-tube M9 in opposite directions. The first inverter, whose input terminal is connected to the gate of the eighth P-tube, is composed of the eleventh P-tube M11 and the twelfth N-tube M12. The second inverter, whose input terminal is connected to the gate of the ninth P-tube, is composed of the thirteenth P-tube M13 and the fourteenth N-tube M14. The source of constant current source transistor M1 is connected to the power supply VCC, and the gate voltage is provided by the constant current source module, enabling M1 to continuously output a current that does not change with temperature and power supply voltage. Figure 5 The diagram illustrates a specific implementation of a constant current source module, including an operational amplifier AMP. The output of the operational amplifier is connected to the gate of a tenth P-type transistor M10. The source and drain of the tenth P-type transistor M10 are connected to the power supply VCC and the inverting input of the operational amplifier, respectively. The inverting input of the operational amplifier is also grounded through a resistor. The non-inverting input is connected to an external reference voltage VREF. The resistor can be a series connection of two resistors, a third resistor R3 and a fourth resistor R4, with opposite temperature coefficients. The series connection of R3 and R4 forms a total resistance that does not change with temperature, while the external reference voltage VREF is also temperature-independent. The voltage of the operational amplifier is made equal to the reference voltage VREF through the negative feedback of the operational amplifier and the tenth P transistor. As a result, the current I10 obtained by the tenth P transistor is VREF / (R3+R4). Since the numerator and denominator do not change with temperature, the current I10 obtained by the tenth P transistor also does not change with temperature. The gate voltage of the tenth P transistor is used as the bias voltage VB and output to the gate of the constant current source transistor M1. The gate and source of the constant current source transistor M1 and the tenth P transistor M10 are connected together to form a current mirror. The current obtained by the constant current source transistor M1 also does not change with temperature.

[0015] The oscillator is powered by a power supply module, such as... Figure 4 As shown, the power supply module includes an operational amplifier AMP. The operational amplifier uses a high-voltage external power supply. An external reference voltage is input to the non-inverting input terminal of the operational amplifier. The power supply VCC is generated by dividing the reference voltage VREF, which does not change with temperature, and the first resistor R1 and the second resistor R2. A third capacitor C3 for voltage regulation is connected to the output terminal of the operational amplifier.

[0016] Figure 1 In the specific embodiment shown, in order to enhance the driving capability, the gates of the eighth P-tube and the ninth P-tube are respectively connected to a buffer composed of two inverters IV connected in series. The driving capability is enhanced by the buffer. The output terminal of the buffer serves as a pair of output terminals of the oscillator output stage and is connected to the gates of the second P-tube, the fourth N-tube, the third P-tube and the fifth N-tube.

[0017] The gates of the eighth and ninth P-transistors are defined as points A and B, respectively, and the gates of the fourth and fifth N-transistors are defined as points C and D, respectively. The oscillator operates as follows: The eighth P-transistor M8 and the ninth P-transistor M9 in the oscillator output stage form an interlocking structure; turning one on will cause the other to turn off. Assuming the initial state is that the sixth N-transistor M6 is off and the seventh N-transistor M7 is on, point A is high. At this time, the ninth P-transistor M9 is off, and point B is low. Ignoring buffer delay, points C and D transition to high and low levels, respectively. At this time, the second P-transistor M2 turns on, the fourth N-transistor M4 is off, and the current from the constant current source M1 flows through M2 to the upper plate of the first capacitor C1, charging C1. The third P-transistor M3 turns off, the fifth N-transistor M5 turns on, and the upper and lower plates of the second capacitor C2 are simultaneously grounded, completely discharging any existing charge and causing the seventh N-transistor M7 to gradually turn off. After time T1, the voltage on the upper plate of C1 exceeds the threshold voltage of the sixth N-transistor M6, causing M6 to turn on.

[0018] It should be noted that the upper and lower plates of the second capacitor C2 are grounded at the same time, and any charge that may exist on it is completely discharged, causing the seventh N transistor M7 to gradually turn off. Since the second capacitor C2 is short-circuited to ground, the discharge time is usually shorter than time T1, that is, the seventh N transistor turns off first. However, as long as the sixth N transistor is not conducting, it will not affect the low level of point B before time T1.

[0019] After the sixth N transistor M6 is turned on, it pulls the voltage at point A down to a low level, causing the ninth P transistor M9 to turn on and start charging point B. After time T2, ignoring the buffer delay, the voltages at points B and D are pulled up to a high level. Time T2 is mainly related to the conduction current of the ninth P transistor M9 and the capacitance at point B.

[0020] After the voltages at points B and D become high and the voltages at points A and C become low, the eighth P-transistor M8 is turned off. At this time, the sixth N-transistor M6 is turned on and the seventh N-transistor M7 is turned off. Points A and C are at low levels, and points B and D are at high levels. Therefore, the second P-transistor M2 is turned off, the fourth N-transistor M4 is turned on, and the upper and lower plates of C1 are grounded simultaneously, releasing the charge. The third P-transistor M3 is turned on, and the fifth N-transistor M5 is turned off. The current from the constant current source transistor M1 flows through the third P-transistor M3 to the upper plate of the second capacitor C2, charging the second capacitor C2. After time T3, the voltage of the upper plate of the second capacitor C2 is charged to a level higher than the threshold voltage of the seventh N-transistor M7. The seventh N-transistor M7 is turned on and pulls the voltage at point B down to a low level, causing the eighth P-transistor M8 to turn on.

[0021] After the eighth P transistor M8 is turned on, after time T4, points A and C are pulled up to a high level, ending a complete cycle and starting the process of charging the first capacitor C1 again.

[0022] The entire clock cycle T = T1 + T2 + T3 + T4. Let the voltage across the upper plate of the first capacitor C1 required to flip point A from high to low be denoted as the first flip voltage V1, and the voltage across the upper plate of the second capacitor C2 required to flip point B from high to low be denoted as the second flip voltage V2. Since C1 and C2 have equal capacitance values, and the charging process for C1 and C2 of equal value is the same, T1 = T3, and... T1=C1*V1 / I, T3=C2*V2 / I, T2=T4, T1+T2=T3+T4=T / 2, where I is the current of the constant current source tube.

[0023] When capacitors C1 and C2 are selected as low-temperature drift capacitors such as MIM (metal-insulator-metal) capacitors, their capacitance values ​​are basically unaffected by temperature. The current I of the constant current source tube is also generally unaffected by temperature. If the values ​​of V1 and V2 are also unaffected by temperature, then the clock period T can achieve a good temperature drift coefficient.

[0024] The values ​​of V1 required to flip point A to a low level and V2 required to flip point B to a low level are determined by the combined action of all the devices driving the voltages at points A and B. Taking point A as an example, the devices include the sixth N transistor M6, the eighth P transistor M8, and the fourteenth N transistor M14 and the thirteenth P transistor M13 in the drive matching module DP. When the driving capability of the N transistors is enhanced, a lower V1 voltage can be used to make point A switch from a high level to a low level, and vice versa.

[0025] Without changing the dimensions of each component in the oscillator output stage, V1 and V2 can be fine-tuned by adjusting the dimensions of each component in the drive matching module DP. Under appropriate size ratios, the driving capabilities of the N-tube and P-tube connected to point A change with temperature in almost the same way, thus ensuring that the voltage value of V1 required to flip the voltage at point A from high level to low level remains basically constant at different temperatures.

[0026] Taking point A as an example, when the voltage on the upper plate of C1 rises to V1, due to the increase of the gate-source voltage VGS of the sixth N transistor M6, the N transistor and P transistor compete with each other, and the voltage at point A is pulled down from the high level to an intermediate level, so that both the N transistor and P transistor are in the saturation region. At this time, the voltage at point B has not yet been pulled up from the low level to the high level. The thirteenth P transistor M13 is turned on while the fourteenth N transistor M14 is turned off. The voltage at point A is determined by the sixth N transistor M6, the eighth P transistor M8, and the thirteenth P transistor M13.

[0027] For M6, M8, and M13, the current I = gm * (Vgs - Vth), where gm represents the transconductance of the MOSFET and Vth represents the threshold voltage. The current at point A flows from M8 and M13 into M6, and is calculated as I6 = I8 + I... 13 You can get gm6*(V1-Vthn) = gm8*(VCC-Vthp)+gm 13 *(VCC-Vthp) Among them gm6, gm8, gm 13 Let Vt represent the transconductances of M6, M8, and M13, respectively; Vthn and Vthp represent the threshold voltages of the N-channel and P-channel transistors, respectively; and VCC be the power supply voltage. The voltage value of V1 can be obtained as follows: V1 = G1 * (VCC - Vthp) + Vthn, where G1 = (gm8 + gm) 13 ) / gm6.

[0028] Since the threshold voltage Vth of a MOSFET varies with temperature, the value of V1 will also change with temperature. Let the temperature coefficient of the threshold voltage of an N-channel MOSFET be Nth. T The threshold voltage temperature coefficient of a P-type transistor is Pth. T Since the temperature coefficients of each transconductance are small, they can be considered constants that do not change with temperature. Therefore, the temperature coefficient of V1 can be considered as -G*P. T +N T The transconductance gm is positively correlated with the width-to-length ratio W / L of the MOSFET. Given a fixed integrated circuit manufacturing process, adjusting the width-to-length ratio of the MOSFET can adjust its transconductance.

[0029] By adjusting the width-to-length ratio of M6, M8, and M13, the transconductances gm6, gm8, and gm of the three MOSFETs are adjusted. 13 This makes -G1*P T +N T =0, then the temperature coefficient of V1 is zero, and a good temperature drift coefficient can be obtained in the T1 and T3 time periods of the clock period T.

[0030] Similarly, for the seventh N-tube, the ninth P-tube, and the eleventh P-tube, when -G2*P T +N T When =0, the temperature coefficient of V2 is zero; where G2 = (gm9 + gm) 11 ) / gm7;N T and P T The threshold voltage temperature coefficients of N-channel and P-channel transistors, gm7, gm9, and gm, respectively. 11 These represent the transconductance of the seventh N-tube, the ninth P-tube, and the eleventh P-tube, respectively.

[0031] As the voltage on the upper plate of the capacitor continues to increase, the voltage at point A will drop rapidly, and M6 will enter the linear region, entering the time period T2 and T4.

[0032] In stages T2 and T4, the PMOS mainly pulls the A / B points to a high level, while the NMOS does not play a direct role. Therefore, it is difficult to reduce the temperature coefficient by means of compensation. The only way to reduce the impact on the clock cycle temperature coefficient is to reduce the duration of stages T2 and T4. This is the second purpose of adding the drive matching module DP.

[0033] The working principle of the driver matching module DP is to make the level transition between points A and B a positive feedback process. The driver matching module DP is connected between points A and B. When point A is at a low level, the thirteenth P transistor is turned on and the fourteenth N transistor is turned off, pulling up the voltage at point B. When the voltage at point B increases, the eleventh P transistor is turned off and the twelfth N transistor is turned on, further pulling down the voltage at point A. A similar conclusion can be drawn when point A is at a high level. The driver matching module DP makes the level transition between points A and B a positive feedback process, shortens the high-low level transition time between points A and B, shortens the time length of T2 and T4, and allows the oscillator to reach a higher frequency. At the same time, it increases the proportion of T1 and T3 in the period, and the period can be adjusted more easily by adjusting the capacitance and current.

[0034] To enhance the overall driving capability of the DP driver matching module, two P transistors, namely the eleventh and thirteenth P transistors, are added. For example, P transistors with a larger aspect ratio are selected to shorten the time for points A and B to transition from low to high level, and to shorten the time lengths of T2 and T4, thereby reducing the impact of temperature drift of T2 and T4 on the entire clock cycle.

[0035] By adding the drive matching module DP, the duration of T2+T4 is shortened. This allows T1+T3 to account for over 95% of the total cycle T at higher frequencies, such as 50MHz, with the temperature drift coefficients of T1 and T3 below 1%. T2+T4 accounts for less than 5% of the total cycle, with a temperature drift coefficient below 10%. Therefore, the temperature drift coefficient for the entire cycle T is approximately [value missing].

[0036] Typical relaxation oscillators rely solely on threshold switching of nonlinear components such as MOSFETs to achieve oscillation, and their temperature drift coefficient is often greater than 10%.

[0037] Although the times of T2 and T4 are reduced, at higher frequencies such as 50MHz, the clock period is 20 nanoseconds, and T2+T4 can still reach about 5% of the entire cycle. During this time, the voltages at points C and D remain at low levels. This results in the output waveform having a peak duty cycle of only 47.5% if the signal at point C or D is directly used as the clock signal. If the oscillator frequency is further increased, the peak duty cycle will be even further away from the ideal 50%.

[0038] To address this, an output adjustment module can be introduced into the oscillator. By connecting points C and D to an XNOR gate, a signal can be obtained that is high only during stages T2 and T4, and low for the rest of the time. The output of the XNOR gate is then divided by a D flip-flop, such as... Figure 3 As shown, the output E of the XNOR gate is connected to the clock input CP of the D flip-flop, the input D of the D flip-flop is connected to its inverted output QN, and the non-inverted output Q of the D flip-flop serves as the output of the output adjustment module. The frequency output through the XNOR gate is twice the oscillator's operating frequency, with a peak duty cycle of 5%. Further frequency division of the XNOR gate's output E using the D flip-flop yields a clock signal at the output OUT of the output adjustment module, matching the oscillator's frequency, with a 50% peak duty cycle and low temperature drift. A specific waveform diagram of points C, D, E, and OUT is shown below. Figure 6 As shown.

[0039] This invention adds a drive matching module to an existing relaxation oscillator, allowing the oscillator output frequency to achieve low-temperature drift by adjusting device parameters. The drive matching module can also reduce the oscillator discharge time, enabling the oscillator to reach a higher frequency, thus making it more suitable for high-frequency applications in phased array radar. Moreover, the circuit structure added to the oscillator improvement in this invention is simple, with fewer components and easy parameter adjustment.

[0040] The foregoing descriptions are preferred embodiments of the present invention. Unless there is a clear contradiction between the preferred embodiments or a premise of a particular preferred embodiment, the preferred embodiments can be arbitrarily combined and used. The embodiments and specific parameters described are only for clearly illustrating the inventor's invention verification process and are not intended to limit the scope of protection of the present invention. The scope of protection of the present invention is still determined by its claims. Similarly, any equivalent structural changes made based on the description and drawings of the present invention should also be included within the scope of protection of the present invention.

Claims

1. A low-temperature drift coefficient relaxation oscillator for a holographic phased array antenna, comprising an oscillator body, the oscillator body including a second P-tube (M2) and a fourth N-tube (M4) connected in series between a constant current source tube (M1) and ground, and a third P-tube (M3) and a fifth N-tube (M5); a first capacitor (C1) is connected between the common terminal of the second P-tube (M2) and the fourth N-tube (M4) and ground and is connected to the gate of a sixth N-tube (M6) in the oscillator output stage; a second capacitor (C2) is connected between the common terminal of the third P-tube (M3) and the fifth N-tube (M5) and ground and is connected to the gate of a seventh N-tube (M7) in the oscillator output stage; Its features are, The oscillator output stage includes a sixth N-transistor (M6) and an eighth P-transistor (M8) connected in series between the power supply and ground, as well as a seventh N-transistor (M7) and a ninth P-transistor (M9). The gates of the eighth P-transistor (M8) and the ninth P-transistor (M9) are connected to the drains of the ninth P-transistor (M9) and the eighth P-transistor (M8), respectively. The gate of the eighth P-transistor (M8) is also connected to the gates of the second P-transistor (M2) and the fourth N-transistor (M4), and the gate of the ninth P-transistor (M9) is also connected to the gates of the third P-transistor (M3) and the fifth N-transistor (M5). The gates of the eighth P-transistor (M8) and the ninth P-transistor (M9) serve as the oscillator output stage. A drive matching module is also connected between the gates of the eighth P-tube (M8) and the ninth P-tube (M9). The drive matching module includes a first inverter and a second inverter with opposite directions and connected in parallel between the gates of the eighth P-tube (M8) and the ninth P-tube (M9). The first inverter, whose input terminal is connected to the gate of the eighth P-tube, is composed of an eleventh P-tube (M11) and a twelfth N-tube (M12). The second inverter, whose input terminal is connected to the gate of the ninth P-tube, is composed of a thirteenth P-tube (M13) and a fourteenth N-tube (M14). The constant current source tube is used to output a current that does not change with temperature and power supply voltage; For the sixth N-tube (M6), the eighth P-tube (M8), and the thirteenth P-tube (M13), we have: -G1*P T +N T =0, where G1=(gm8+gm 13 ) / gm6;N T and P T The threshold voltage temperature coefficients of N-type and P-type transistors are gm6, gm8, and gm, respectively. 13 These represent the transconductance of the sixth N-channel transistor (M6), the eighth P-channel transistor (M8), and the thirteenth P-channel transistor (M13), respectively. For the seventh N-tube (M7), the ninth P-tube (M9), and the eleventh P-tube (M11), we have: -G2*P T +N T =0, where G2=(gm9+gm 11 ) / gm7;N T and P T The threshold voltage temperature coefficients of N-channel and P-channel transistors are gm7, gm9, and gm, respectively. 11 These represent the transconductance of the seventh N-tube (M7), the ninth P-tube (M9), and the eleventh P-tube (M11), respectively.

2. The low-temperature drift coefficient relaxation oscillator for a holographic phased array antenna according to claim 1, characterized in that, The source of the constant current source transistor (M1) is connected to the power supply, and the gate voltage is provided by the constant current source module. The constant current source module includes an operational amplifier (AMP). The output of the operational amplifier (AMP) is connected to the gate of the tenth P transistor (M10). The source and drain of the tenth P transistor (M10) are connected to the power supply and the inverting input of the operational amplifier (AMP), respectively. The inverting input of the operational amplifier (AMP) is also grounded through a resistor with zero temperature coefficient, and the non-inverting input is connected to an external reference voltage.

3. The low-temperature drift coefficient relaxation oscillator for a holographic phased array antenna according to claim 1, characterized in that, It also includes an output adjustment module connected to the gate of the eighth P-transistor (M8) and the gate of the ninth P-transistor (M9). The output adjustment module includes an XNOR gate. The gates of the eighth P-transistor (M8) and the ninth P-transistor (M9) are respectively connected to the two input terminals of the XNOR gate. The output terminal of the XNOR gate is connected to the clock terminal of the D flip-flop. The input terminal of the D flip-flop is connected to the inverted output terminal of the D flip-flop. The non-inverted output terminal of the D flip-flop serves as the output terminal of the output adjustment module.

4. The low-temperature drift coefficient relaxation oscillator for a holographic phased array antenna according to claim 1, characterized in that, The gates of the eighth P-tube (M8) and the ninth P-tube (M9) are respectively connected to a buffer consisting of two inverters connected in series. The output of the buffer serves as a pair of output terminals of the oscillator output stage.

5. The low-temperature drift coefficient relaxation oscillator for a holographic phased array antenna according to claim 1, characterized in that, It also includes a power supply module, which includes an operational amplifier (AMP). The non-inverting input of the operational amplifier is connected to an external reference voltage, and the inverting input is connected to the common terminal of a first resistor (R1) and a second resistor (R2). The ends of the first resistor (R1) and the second resistor (R2) that are not connected to each other are respectively connected to the output terminal of the operational amplifier (AMP) and ground.

6. The low-temperature drift coefficient relaxation oscillator for a holographic phased array antenna according to claim 5, characterized in that, A capacitor is connected between the output of the operational amplifier (AMP) and ground.

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