Triple-modular redundant flip-flop and memory cell hardened against radiation

Abstract

The application relates to the technical field of integrated circuit reinforcement design, and provides a three-module redundancy trigger and a storage unit with radiation resistance and reinforcement, wherein a feedback circuit is connected to the output ends of three scan triggers through a self-correction reinforcement design idea, the outputs of the three triggers are internally connected to the three triggers, weak feedback correction is carried out, correct data is written into the trigger with errors in real time under the condition of no clock, other trigger errors are effectively avoided to cause voting failure, and high reliability is achieved. The functional mode and the test mode are integrated in the weak feedback loop of the slave structure, the paths of the structure test and the functional test are effectively separated, and the flexibility is high; compared with a traditional AND gate voter design scheme, the above scheme simplifies the structure design of the circuit, improves the reliability, effectively reduces the number of transistors, and effectively reduces the chip area and power consumption.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit ruggedization design technology, and relates to a radiation-hardened triple-mode redundancy trigger and memory unit. Background Technology

[0002] In environments with high reliability requirements, such as aerospace and nuclear industries, integrated circuits are highly susceptible to the effects of high-energy particle incidents, resulting in single-event effects that can cause data flips or circuit function interruptions. In particular, for sequential logic units, single-event effects can lead to changes in the stored state, i.e., single-event flips, which can then cause system failures.

[0003] Triple mode redundancy (TMR) is one of the most widely used hardening techniques against single-event upsets (SEE). However, traditional TMR flip-flops only correct the logic value at the final output through a voter, without updating the data of the flip-flop where the error occurred. In long-term irradiation environments, if the accumulated errors cause another circuit to malfunction, the voter will be unable to output the correct result, leading to circuit failure. Therefore, traditional TMR hardening designs still have a significant risk of SEE, making the hardening design of TMR flip-flops a pressing technical problem. Summary of the Invention

[0004] To address the problems existing in the above-mentioned traditional technologies, this invention proposes a radiation-hardened triple mode redundancy trigger and storage unit, which can effectively realize the robust design of the triple mode redundancy trigger.

[0005] To achieve the above objectives, the embodiments of the present invention adopt the following technical solutions: On the one hand, a radiation-hardened triple modal redundancy flip-flop is provided, including a first flip-flop, a second flip-flop, a third flip-flop, a feedback circuit, and a 3-to-2 voting device. The clock terminals of each flip-flop are connected to the same clock source, the data input terminals of each flip-flop are connected to the same data source, the output terminals of each flip-flop are respectively connected to the three input terminals of the 3-to-2 voting device, the output terminals of each flip-flop are also respectively connected to the input terminals of the feedback circuit, and the output terminals of the feedback circuit are respectively connected to the input terminals of the inverters connected to the output terminals of each flip-flop. When the scan enable signal connected to each flip-flop and feedback circuit is invalid, each flip-flop operates in functional mode. The feedback circuit is used to perform a two-out-of-three voting based on the output signal of each flip-flop and then send it back to each flip-flop to correct the output signal of the flip-flop that has an error. When the scan enable signal connected to each flip-flop and feedback circuit is valid, each flip-flop operates in test mode and selects to connect the scan chain input signal. The feedback circuit is used to connect each flip-flop in series.

[0006] In one embodiment, each trigger is a D trigger.

[0007] In one embodiment, the feedback circuit includes a pull-up module, an upper scanning branch, an upper voting network, a first switch, a second switch, a lower scanning branch, a lower voting network, and a pull-down module. The control terminal of the pull-up module is used to receive the scan enable signal, the input terminal of the pull-up module is used to connect to the power supply, the output terminal of the pull-up module is connected to the input terminal of the upper voting network, the output terminal of the upper voting network and the output terminal of the upper scanning branch are both connected to the input terminal of the first switch, each control terminal of the upper voting network is connected to the output terminal of each trigger, the input terminal of the upper scanning branch is used to connect to the power supply, the first control terminal of the upper scanning branch is connected to the output terminal of the first trigger, and the second control terminal of the upper scanning branch is used to receive the inverted scan enable signal. The control terminal of the pull-down module is used to receive the inverted scan enable signal. The input terminal of the pull-down module is grounded. The output terminal of the pull-down module is connected to the input terminal of the lower voting network. The output terminal of the lower voting network and the output terminal of the lower scanning branch are both connected to the input terminal of the second switch. Each control terminal of the lower voting network is connected to the output terminal of each flip-flop. The input terminal of the lower scanning branch is grounded. The first control terminal of the lower scanning branch is used to receive the scan enable signal. The second control terminal of the upper scanning branch is connected to the output terminal of the first flip-flop. The output terminals of the first switch and the second switch are connected together and led out as the output terminals of the feedback circuit. The control terminal of the first switch is used to receive the master clock signal, and the control terminal of the second switch is used to receive the inverted master clock signal. When the scan enable signal is invalid, the pull-up module, the upper voting network, the lower voting network and the pull-down module participate in the work. After performing a three-to-two vote based on the output signal of each flip-flop, the vote is sent back to each flip-flop to correct the output signal of the flip-flop that has an error. The upper scan branch and the lower scan branch are disconnected. When the scan enable signal is valid, the pull-up module, the upper voting network, the lower voting network, and the pull-down module are disconnected, and the upper and lower scan branches participate in the operation. The triggers are connected in series for scan testing.

[0008] In one embodiment, the pull-up module is a PMOS transistor, the scanning upper branch includes a pair of PMOS transistors in series, the upper voting network includes three pairs of PMOS transistors in parallel in series, and the first switch is a PMOS transistor. The pull-down module is an NMOS transistor, the scanning lower branch includes a pair of NMOS transistors in series, the lower voting network includes three pairs of NMOS transistors in parallel in series, and the second switch is an NMOS transistor.

[0009] On the other hand, a timing storage unit is also provided, which is hardened using a radiation-hardened tri-mode redundancy flip-flop. The tri-mode redundancy flip-flop includes a 3-to-2 voter, a first flip-flop, a second flip-flop, a third flip-flop, and a feedback circuit. The clock terminals of each flip-flop are connected to the same clock source, the data input terminals of each flip-flop are connected to the same data source, the output terminals of each flip-flop are respectively connected to the three input terminals of the voter, and the output terminals of each flip-flop are also respectively connected to the input terminals of the feedback circuit. The output terminals of the feedback circuit are respectively connected to the input terminals of the inverters connected to the output terminals of each flip-flop. When the scan enable signal connected to each flip-flop and feedback circuit is invalid, each flip-flop operates in functional mode. The feedback circuit is used to perform a two-out-of-three voting based on the output signal of each flip-flop and then send it back to each flip-flop to correct the output signal of the flip-flop that has an error. When the scan enable signal connected to each flip-flop and feedback circuit is valid, each flip-flop operates in test mode and selects to connect the scan chain input signal. The feedback circuit is used to connect each flip-flop in series.

[0010] In one embodiment, the voting device includes an inverter and three voting branches in parallel. Each voting branch includes a pair of PMOS transistors in series and a pair of NMOS transistors in series. The source of one PMOS transistor in the series is connected to the power supply, and the drain of the other PMOS transistor is connected to the input of the inverter. The source of one NMOS transistor in the series is grounded, and the drain of the other NMOS transistor is connected to the input of the inverter. The outputs of each flip-flop are connected in pairs to the gates of each pair of transistors in the three voting branches.

[0011] One of the above technical solutions has the following advantages and beneficial effects: The aforementioned radiation-hardened triple-modular redundancy flip-flops and memory unit employs a self-correcting hardened design. A feedback circuit is connected to the output of each of the three scan flip-flops, internally connecting the outputs of the three flip-flops for weak feedback error correction. This design combines self-correction and scan testing capabilities with minimal area overhead. Even in the absence of a clock (when the clock is low), correct data is written to the erroneous flip-flop in real time for error correction, effectively preventing other flip-flops from malfunctioning and causing voting failure, thus achieving high reliability. The functional mode and test mode are integrated into the weak feedback loop of the slave structure, effectively separating the paths for structural and functional testing, resulting in high flexibility. Compared to traditional AND / OR gate voting designs, this solution simplifies the circuit structure, improving reliability while effectively reducing the number of transistors, thus reducing chip area and power consumption. Attached Figure Description

[0012] To more clearly illustrate the technical solutions in the embodiments of the present invention or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0013] Figure 1 This is a schematic diagram of a radiation-hardened triple-mode redundancy trigger in one embodiment; Figure 2 This is a schematic diagram of the structure of any one of the triggers in one embodiment; Figure 3 This is a schematic diagram of the structure of the feedback circuit in one embodiment; Figure 4 This is a schematic diagram of a specific structure of the feedback circuit in one embodiment; Figure 5 This is a schematic diagram of the circuit structure of a three-to-two voting device in one embodiment. Detailed Implementation

[0014] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the invention.

[0015] It should be noted that, in this document, the reference to "embodiment" means that a specific feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of the invention. The presentation of this phrase in various locations throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. Those skilled in the art will understand that the embodiments described herein can be combined with other embodiments.

[0016] The embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0017] In one embodiment, such as Figure 1As shown, a radiation-hardened triple modulo redundant flip-flop is provided, including a first flip-flop, a second flip-flop, a third flip-flop, a feedback circuit, and a 3-to-2 voting converter. The clock terminals of each flip-flop are connected to the same clock source, the data input terminals of each flip-flop are connected to the same data source, the output terminals of each flip-flop are respectively connected to the three input terminals of the 3-to-2 voting converter, and the output terminals of each flip-flop are also respectively connected to the input terminals of the feedback circuit. The output terminal X of the feedback circuit is respectively connected to the input terminal of the inverter connected to the output terminals of each flip-flop.

[0018] When the scan enable signal connected to each flip-flop and feedback circuit is invalid, each flip-flop operates in functional mode. The feedback circuit performs a two-out-of-three voting based on the output signal of each flip-flop and then sends the result back to each flip-flop to correct the output signal of the flip-flop that has an error. When the scan enable signal connected to each flip-flop and feedback circuit is valid, each flip-flop operates in test mode and selects the scan chain input signal. The feedback circuit connects each flip-flop in series.

[0019] It is understood that the feedback circuit in this embodiment integrates a functional mode and a test mode, allowing for free switching between modes. In functional mode, data undergoes weak feedback error correction via an integrated voter; in test mode, after the voter is turned off, the three flip-flops are connected in series for scanning testing. Furthermore, the flip-flops can be enhanced versions based on D flip-flops, with a commonly used structure as follows... Figure 2 As shown.

[0020] Specifically, there are three triggers (which can be denoted as trigger A, trigger B, and trigger C). Figure 1 The outputs of three flip-flops (represented as Q_A, Q_B, and Q_C) are connected to the three inputs of the voter, as follows: Figure 1 As shown, the voting device uses a 3-to-2 voting output. The output of the flip-flop is connected to the output of the feedback circuit. The outputs of the three flip-flops are respectively fed back to the slave structure of the three flip-flops through the feedback circuit integrated into the slave structure, as shown. Figure 2 As shown, the clock inputs Clk of the three flip-flops are connected to the same clock source, and the data inputs D of the three flip-flops are connected to the same data source, forming a triple modulo redundant flip-flop.

[0021] In functional mode, the scan enable signal SE is invalid (e.g., low level). When the outputs of the three flip-flops are consistent (i.e., the levels of outputs Q_A, Q_B, and Q_C are the same), the three-mode output Q of the voter outputs a stable level. The output signals of outputs Q_A, Q_B, and Q_C are fed back to the slave structure of the flip-flops via a feedback circuit, thus achieving normal feedback functionality.

[0022] When a single particle strikes a flip-flop, causing it to flip (e.g., an erroneous level flip occurs at output Q_A), but the outputs of the other two flip-flops are normal (i.e., the levels at outputs Q_B and Q_C are correct), the voting circuit performs a 3-to-2 selection, resulting in a 3-modulus output Q = Q_B = Q_C. The level state of the 3-modulus output Q is correct. The correct level states of outputs Q_B and Q_C are also selected by a 3-to-2 voting process via feedback circuit. The purpose of this voting is to refresh the final voted value (i.e., the level state of the 3-modulus output Q) onto output Q_A, achieving self-correction for erroneous outputs Q_A. This ensures that the stored states of the three flip-flops are consistent and correct during periods when the main clock signal is invalid (e.g., CK=0), preventing two flip-flops from having their stored values ​​consecutively flipped, and ensuring that the 3-modulus output Q does not produce an erroneous vote (i.e., two incorrect values ​​overwrite one correct value).

[0023] In test mode, the scan enable signal SE is active (e.g., high level). Each flip-flop operates in test mode and selects to connect to the scan chain input signal SI. The feedback circuit connects the flip-flops in series, that is, the output terminal (Q_A) of flip-flop A is connected to the input terminal SI of flip-flop B, the output terminal (Q_B) of flip-flop B is connected to the input terminal SI of flip-flop C, and the output terminal of flip-flop C is still Q_C. This series connection can be used to perform scan tests and realize the correctness test of flip-flop function.

[0024] The aforementioned radiation-hardened tri-mode redundant triggers employ a self-correcting hardening design. A feedback circuit is connected to the outputs of the three scan triggers, internally connecting the outputs of each trigger for weak feedback error correction. This design combines self-correction and scan-test functionality, while reducing the area overhead of the voting unit. Even in the absence of a clock (when the clock is low), correct data is written to the erroneous trigger in real-time for error correction, effectively preventing other triggers from malfunctioning and causing voting failure. This effectively resists multi-bit single-event upsets, improving the tri-mode hardening effect and achieving high reliability. The functional mode and test mode are integrated into the weak feedback loop of the slave structure, effectively separating the structural and functional test paths and providing high flexibility.

[0025] In one embodiment, such as Figure 3As shown, the feedback circuit includes a pull-up module, an upper scanning branch, an upper voting network, a first switch, a second switch, a lower scanning branch, a lower voting network, and a pull-down module. The control terminal of the pull-up module is used to connect to the scan enable signal SE. The input terminal of the pull-up module is connected to the power supply Vdd. The output terminal of the pull-up module is connected to the input terminal of the upper voting network. The output terminals of the upper voting network and the upper scanning branch are both connected to the input terminal of the first switch. Each control terminal of the upper voting network is connected to the output terminal of each flip-flop (i.e., Q_A, Q_B, and Q_C). The input terminal of the upper scanning branch is connected to the power supply Vdd. The first control terminal of the upper scanning branch is connected to the output terminal Q_A of the first flip-flop. The second control terminal of the upper scanning branch is used to connect to the inverted scan enable signal NSE.

[0026] The control terminal of the pull-down module is used to connect to the inverted scan enable signal NSE. The input terminal of the pull-down module is grounded gnd. The output terminal of the pull-down module is connected to the input terminal of the lower voting network. The output terminal of the lower voting network and the output terminal of the lower scanning branch are both connected to the input terminal of the second switch. Each control terminal of the lower voting network is connected to the output terminal of each flip-flop. The input terminal of the lower scanning branch is grounded gnd. The first control terminal of the lower scanning branch is used to connect to the scan enable signal SE. The second control terminal of the upper scanning branch is connected to the output terminal Q_A of the first flip-flop.

[0027] The output terminals of the first switch and the second switch are connected together and led out as the output terminal X of the feedback circuit. The control terminal of the first switch is used to connect the master clock signal CK, and the control terminal of the second switch is used to connect the inverted master clock signal NCK.

[0028] When the scan enable signal SE is invalid, the pull-up module, upper voting network, lower voting network, and pull-down module all operate. Based on the output signals of each flip-flop, a 2-out-of-3 vote is performed, and the results are fed back to each flip-flop to correct the output signal of any erroneous flip-flop. The upper and lower scan branches are then disconnected. When the scan enable signal SE is valid, the pull-up module, upper voting network, lower voting network, and pull-down module are disconnected. The upper and lower scan branches operate, and the flip-flops are connected in series for scan testing.

[0029] It is understood that this embodiment is designed with the following features: Figure 3The feedback circuit shown uses pull-up and pull-down modules that operate only in the functional mode (e.g., SE=0). They precharge the common node to a high level. When the master clock signal CK is active, the first switch opens, allowing the upper voting network to perform a two-out-of-three vote based on the levels of Q_A, Q_B, and Q_C, and then output to the X terminal. For example, if at least two of Q_A, Q_B, and Q_C are high, the output to X is also high; if fewer than two are high, the output to X is low. The circuit output is determined by majority rule. Similarly, the lower voting network and pull-down modules output to X when the inverted master clock signal NCK is active.

[0030] In test mode (e.g., SE=1), the pull-up and pull-down modules do not participate in operation, the precharge path is disconnected, both the upper and lower voting networks exit the three-input majority voting logic, and the upper and lower scanning branches are enabled. As part of the scanning path, test data is transmitted through the Q_A signal to verify the connectivity and logical correctness of the internal nodes of the flip-flop, thus realizing Design for Test (DFT). For example, by switching between function mode and test mode through the SE signal, the internal nodes of the flip-flop can be scanned for testing, improving the fault coverage of the circuit.

[0031] Pull-up modules, scanning upper branches, upper voting networks, first switches, second switches, scanning lower branches, lower voting networks, and pull-down modules can all be constructed using MOS transistors, as long as they can provide the required functions.

[0032] In one embodiment, such as Figure 4 As shown, the pull-up module is a PMOS transistor, and the upper scanning branch includes a pair of PMOS transistors connected in series. The upper voting network includes three pairs of PMOS transistors connected in parallel. The first switch is a PMOS transistor. The pull-down module is an NMOS transistor. The lower scanning branch includes a pair of NMOS transistors connected in series. The lower voting network includes three pairs of NMOS transistors connected in parallel. The second switch is an NMOS transistor.

[0033] It is understood that this embodiment provides one of the more sophisticated feedback circuit designs, such as... Figure 4As shown, the PMOS transistors of the pull-up module and the NMOS transistors of the pull-down module operate in functional mode (e.g., SE=0). They precharge the common node to a high level. When the main clock signal CK is active, the PMOS transistor of the first switch turns on, allowing the upper voting network to perform a two-out-of-three vote based on the levels of Q_A, Q_B, and Q_C, and output to the X terminal. For example, if at least two of Q_A, Q_B, and Q_C are high, the output to X terminal is also high; if fewer than two of Q_A, Q_B, and Q_C are high, the output to X terminal is low. The circuit output is determined by majority rule. Similarly, when the inverted main clock signal NCK is active, the NMOS transistor of the pull-down module pulls the common node low. When the main clock signal CK is inactive, the NMOS transistor of the second switch turns on, allowing the three branches of the lower voting network to perform a two-out-of-three vote based on the levels of Q_A, Q_B, and Q_C, and output to the X terminal.

[0034] In test mode (e.g., SE=1), pull-up and pull-down modules are not active, the precharge path is disconnected, and both the upper and lower voting networks exit the three-input majority voting logic. A pair of series-connected PMOS transistors in the upper scan branch and a pair of series-connected NMOS transistors in the lower scan branch are enabled as part of the scan path. Test data is transmitted via the Q_A signal to verify the connectivity and logical correctness of the internal nodes of the flip-flops, achieving testability design. In test mode, the required circuit connections are pre-connected in the circuit design. The SI input of flip-flop A is connected to the scan chain input data, the Q_A output of flip-flop A is connected to the SI input of flip-flop B, and the Q_B output of flip-flop B is connected to the SI input of flip-flop C. Therefore, when SE=high, data is input from the SI input of flip-flop A, moving sequentially with the CK edge, instead of continuing to input from the D input. This allows for the series connection of flip-flops A, B, and C in test mode.

[0035] Here, PMOS transistors refer to P-channel MOS transistors (the transistors with arrows pointing to the right), and NMOS transistors refer to N-channel MOS transistors (the transistors with arrows pointing to the left). By designing and using the above feedback circuit structure, the hardening effect of a triple-mode redundant flip-flop can be achieved with only 20 transistors, efficiently integrating functional modes and test modes.

[0036] Furthermore, compared to traditional AND / OR gate voting circuit designs, the aforementioned ruggedized design can simplify the ruggedized structure of the voting circuit and optimize it to 14 transistors, such as... Figure 5 As shown, compared to the traditional voting unit consisting of 26 gates composed of AND and OR gates, it can achieve the same function, thus effectively reducing the voting unit area.

[0037] It should be noted that, Figures 2 to 4 In this configuration, SE is the scan enable signal, used for mode selection control; SI is the scan chain input signal; and NSE is the inverted scan enable signal, which is the complementary signal to SE. CK is the master clock signal, and NCK is the inverted master clock signal, which is the complementary signal to CK. For example, SE=0 is the normal operating mode, where the flip-flop samples the data signal at the data input terminal D and performs normal register functions. SE=1 is the test mode, where the flip-flop selects the SI signal and enters the shift register mode for scan chain testing.

[0038] In one embodiment, a timing storage unit is also provided, which is hardened using a radiation-hardened triple modulo redundant trigger, wherein, as... Figure 1 , Figure 2 and Figure 3 As shown, the triple-modulus redundant flip-flop includes a 3-to-2 voting unit, a first flip-flop, a second flip-flop, a third flip-flop, and a feedback circuit. The clock terminals of each flip-flop are connected to the same clock source. The data input terminals of each flip-flop are connected to the same data source. The output terminals of each flip-flop are connected to the three input terminals of the voting unit, and the output terminals of each flip-flop are also connected to the input terminals of the feedback circuit. The output terminal of the feedback circuit is connected to the input terminals of the inverters to which the output terminals of each flip-flop are connected.

[0039] When the scan enable signal connected to each flip-flop and feedback circuit is invalid, each flip-flop operates in functional mode. The feedback circuit performs a two-out-of-three voting based on the output signal of each flip-flop and then sends the result back to each flip-flop to correct the output signal of the flip-flop that has an error. When the scan enable signal connected to each flip-flop and feedback circuit is valid, each flip-flop operates in test mode and selects the scan chain input signal. The feedback circuit connects each flip-flop in series.

[0040] The aforementioned sequential memory unit, by applying the radiation-hardened triple modulo redundancy triggers (TMRs), for example by directly replacing the original register with the aforementioned TMRs, achieves single-event upset (SOME) protection for the hardened register, effectively improving the SOME protection capability of the sequential memory unit and thus enhancing the reliability of the memory unit under high-energy particle radiation environments. The sequential memory unit can be, but is not limited to, a register in a radiation-hardened FPGA (Field-Programmable Gate Array), a register in a radiation-hardened microcontroller (MCU), or a register in a space-grade digital signal processor (DSP).

[0041] In one embodiment, each trigger is a D trigger.

[0042] In one embodiment, the feedback circuit includes a pull-up module, an upper scanning branch, an upper voting network, a first switch, a second switch, a lower scanning branch, a lower voting network, and a pull-down module. The control terminal of the pull-up module is used to receive a scan enable signal; the input terminal of the pull-up module is used to connect to a power supply; the output terminal of the pull-up module is connected to the input terminal of the upper voting network; the output terminals of the upper voting network and the upper scanning branch are both connected to the input terminal of the first switch; each control terminal of the upper voting network is connected to the output terminal of each flip-flop; the input terminal of the upper scanning branch is used to connect to a power supply; the first control terminal of the upper scanning branch is connected to the output terminal of the first flip-flop; and the second control terminal of the upper scanning branch is used to receive an inverted scan enable signal.

[0043] The control terminal of the pull-down module is used to receive the inverted scan enable signal. The input terminal of the pull-down module is grounded. The output terminal of the pull-down module is connected to the input terminal of the lower voting network. The output terminal of the lower voting network and the output terminal of the lower scanning branch are both connected to the input terminal of the second switch. Each control terminal of the lower voting network is connected to the output terminal of each flip-flop. The input terminal of the lower scanning branch is grounded. The first control terminal of the lower scanning branch is used to receive the scan enable signal. The second control terminal of the upper scanning branch is connected to the output terminal of the first flip-flop.

[0044] The output terminals of the first and second switches are connected together and led out as the output terminals of the feedback circuit. The control terminal of the first switch is used to input the master clock signal, and the control terminal of the second switch is used to input the inverted master clock signal. When the scan enable signal is invalid, the pull-up module, the upper voting network, the lower voting network, and the pull-down module participate in the operation. Based on the output signals of each flip-flop, a 2-out-of-3 vote is performed and the results are fed back to each flip-flop to correct the output signal of the erroneous flip-flop. The upper and lower scan branches are then disconnected. When the scan enable signal is valid, the pull-up module, the upper voting network, the lower voting network, and the pull-down module are disconnected. The upper and lower scan branches participate in the operation, and the flip-flops are connected in series for scan testing.

[0045] In one embodiment, the pull-up module is a PMOS transistor. The scan upper branch includes a pair of PMOS transistors connected in series. The upper voting network includes three pairs of PMOS transistors connected in parallel. The first switch is a PMOS transistor. The pull-down module is an NMOS transistor. The scan lower branch includes a pair of NMOS transistors connected in series. The lower voting network includes three pairs of NMOS transistors connected in parallel. The second switch is an NMOS transistor.

[0046] In one embodiment, the scan enable signal is active when it is high and inactive when it is low.

[0047] In one embodiment, such as Figure 5As shown, the voting unit includes an inverter and three voting branches connected in parallel. Each voting branch includes a pair of PMOS transistors and a pair of NMOS transistors connected in series. In the series PMOS transistors, the source of one PMOS transistor is connected to the power supply, and the drain of the other PMOS transistor is connected to the input of the inverter. In the series NMOS transistors, the source of one NMOS transistor is grounded, and the drain of the other NMOS transistor is connected to the input of the inverter. The outputs of each flip-flop are connected in pairs to the gates of the respective pairs of transistors in the three voting branches.

[0048] like Figure 5 As shown, this embodiment can directly implement the voting circuit structure using 14 transistors, eliminating the need for the traditional 26-transistor voting circuit design. This significantly reduces the number of transistors and achieves low hardware overhead. The inverter at the Q terminal can be implemented using a classic inverter structure consisting of a PMOS transistor and an NMOS transistor. The PMOS transistor has its source connected to Vdd, its drain connected to the output, and its gate connected to the input. The NMOS transistor has its source connected to Gnd, its drain connected to the output, and its gate connected to the input. The gates of the two transistors are connected together as the input, and the drains of the two transistors are connected together as the output.

[0049] It is understood that the explanations of the features in the above-mentioned sequential storage unit embodiments can be understood by referring to the explanations of the corresponding features in the above-mentioned radiation-hardened tri-mode redundancy trigger embodiments, and will not be repeated here.

[0050] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0051] The above embodiments merely illustrate several implementation methods of the present invention, and their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of protection of the invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and all such modifications and improvements fall within the scope of protection of the present invention.

Claims

1. A radiation-hardened triple modulo redundant trigger, characterized in that, It includes a first flip-flop, a second flip-flop, a third flip-flop, a feedback circuit, and a 3-to-2 voting device. The clock terminals of each flip-flop are connected to the same clock source, the data input terminals of each flip-flop are connected to the same data source, the output terminals of each flip-flop are respectively connected to the three input terminals of the 3-to-2 voting device, the output terminals of each flip-flop are also respectively connected to the input terminals of the feedback circuit, and the output terminals of the feedback circuit are respectively connected to the input terminals of the inverters connected to the output terminals of each flip-flop. When the scan enable signal connected to each flip-flop and feedback circuit is invalid, each flip-flop operates in functional mode. The feedback circuit is used to perform a two-out-of-three voting based on the output signal of each flip-flop and then send it back to each flip-flop to correct the output signal of the flip-flop that has an error. When the scan enable signal connected to each flip-flop and feedback circuit is valid, each flip-flop operates in test mode and selects to connect the scan chain input signal, thus connecting the flip-flops in series. The feedback circuit includes a pull-up module, an upper scanning branch, an upper voting network, a first switch, a second switch, a lower scanning branch, a lower voting network, and a pull-down module; The control terminal of the pull-up module is used to receive the scan enable signal, the input terminal of the pull-up module is used to connect to the power supply, the output terminal of the pull-up module is connected to the input terminal of the upper voting network, the output terminal of the upper voting network and the output terminal of the upper scanning branch are both connected to the input terminal of the first switch, each control terminal of the upper voting network is connected to the output terminal of each trigger, the input terminal of the upper scanning branch is used to connect to the power supply, the first control terminal of the upper scanning branch is connected to the output terminal of the first trigger, and the second control terminal of the upper scanning branch is used to receive the inverted scan enable signal. The control terminal of the pull-down module is used to receive the inverted scan enable signal. The input terminal of the pull-down module is grounded. The output terminal of the pull-down module is connected to the input terminal of the lower voting network. The output terminal of the lower voting network and the output terminal of the lower scanning branch are both connected to the input terminal of the second switch. Each control terminal of the lower voting network is connected to the output terminal of each flip-flop. The input terminal of the lower scanning branch is grounded. The first control terminal of the lower scanning branch is used to receive the scan enable signal. The second control terminal of the upper scanning branch is connected to the output terminal of the first flip-flop. The output terminals of the first switch and the second switch are connected together and led out as the output terminals of the feedback circuit. The control terminal of the first switch is used to receive the master clock signal, and the control terminal of the second switch is used to receive the inverted master clock signal. When the scan enable signal is invalid, the pull-up module, the upper voting network, the lower voting network and the pull-down module participate in the work. After performing a three-to-two vote based on the output signal of each flip-flop, the vote is sent back to each flip-flop to correct the output signal of the flip-flop that has an error. The upper scan branch and the lower scan branch are disconnected. When the scan enable signal is valid, the pull-up module, the upper voting network, the lower voting network, and the pull-down module are disconnected, and the upper and lower scan branches participate in the operation. The triggers are connected in series for scan testing.

2. The radiation-hardened triple-mode redundancy trigger according to claim 1, characterized in that, All flip-flops are D flip-flops.

3. The radiation-hardened triple-mode redundancy trigger according to claim 1, characterized in that, The pull-up module is a PMOS transistor, the scanning upper branch includes a pair of PMOS transistors in series, the upper voting network includes three pairs of PMOS transistors in parallel in series, and the first switch is a PMOS transistor. The pull-down module is an NMOS transistor, the scanning lower branch includes a pair of NMOS transistors in series, the lower voting network includes three pairs of NMOS transistors in parallel in series, and the second switch is an NMOS transistor.

4. A sequential storage unit, characterized in that, The registers in the sequential storage unit are hardened using radiation-hardened triple modulo redundant flip-flops. The triple modulo redundant flip-flops include a 3-to-2 voting unit, a first flip-flop, a second flip-flop, a third flip-flop, and a feedback circuit. The clock terminals of each flip-flop are connected to the same clock source, the data input terminals of each flip-flop are connected to the same data source, the output terminals of each flip-flop are connected to the three input terminals of the voting unit, and the output terminals of each flip-flop are also connected to the input terminals of the feedback circuit. The output terminals of the feedback circuit are connected to the input terminals of the inverters connected to the output terminals of each flip-flop. When the scan enable signal connected to each flip-flop and feedback circuit is invalid, each flip-flop operates in functional mode. The feedback circuit is used to perform a two-out-of-three voting based on the output signal of each flip-flop and then send it back to each flip-flop to correct the output signal of the flip-flop that has an error. When the scan enable signal connected to each flip-flop and feedback circuit is valid, each flip-flop operates in test mode and selects to connect the scan chain input signal, thus connecting the flip-flops in series. The feedback circuit includes a pull-up module, an upper scanning branch, an upper voting network, a first switch, a second switch, a lower scanning branch, a lower voting network, and a pull-down module; The control terminal of the pull-up module is used to receive the scan enable signal, the input terminal of the pull-up module is used to connect to the power supply, the output terminal of the pull-up module is connected to the input terminal of the upper voting network, the output terminal of the upper voting network and the output terminal of the upper scanning branch are both connected to the input terminal of the first switch, each control terminal of the upper voting network is connected to the output terminal of each trigger, the input terminal of the upper scanning branch is used to connect to the power supply, the first control terminal of the upper scanning branch is connected to the output terminal of the first trigger, and the second control terminal of the upper scanning branch is used to receive the inverted scan enable signal. The control terminal of the pull-down module is used to receive the inverted scan enable signal. The input terminal of the pull-down module is grounded. The output terminal of the pull-down module is connected to the input terminal of the lower voting network. The output terminal of the lower voting network and the output terminal of the lower scanning branch are both connected to the input terminal of the second switch. Each control terminal of the lower voting network is connected to the output terminal of each flip-flop. The input terminal of the lower scanning branch is grounded. The first control terminal of the lower scanning branch is used to receive the scan enable signal. The second control terminal of the upper scanning branch is connected to the output terminal of the first flip-flop. The output terminals of the first switch and the second switch are connected together and led out as the output terminals of the feedback circuit. The control terminal of the first switch is used to receive the master clock signal, and the control terminal of the second switch is used to receive the inverted master clock signal. When the scan enable signal is invalid, the pull-up module, the upper voting network, the lower voting network and the pull-down module participate in the work. After performing a three-to-two vote based on the output signal of each flip-flop, the vote is sent back to each flip-flop to correct the output signal of the flip-flop that has an error. The upper scan branch and the lower scan branch are disconnected. When the scan enable signal is valid, the pull-up module, the upper voting network, the lower voting network, and the pull-down module are disconnected, and the upper and lower scan branches participate in the operation. The triggers are connected in series for scan testing.

5. The timing storage unit according to claim 4, characterized in that, All flip-flops are D flip-flops.

6. The timing storage unit according to claim 4, characterized in that, The pull-up module is a PMOS transistor, the scanning upper branch includes a pair of PMOS transistors in series, the upper voting network includes three pairs of PMOS transistors in parallel in series, and the first switch is a PMOS transistor. The pull-down module is an NMOS transistor, the scanning lower branch includes a pair of NMOS transistors in series, the lower voting network includes three pairs of NMOS transistors in parallel in series, and the second switch is an NMOS transistor.

7. The timing storage unit according to claim 4, characterized in that, The scan enable signal is valid when it is high and invalid when it is low.

8. The timing storage unit according to claim 4, characterized in that, The voting device includes an inverter and three voting branches in parallel. Each voting branch includes a pair of PMOS transistors in series and a pair of NMOS transistors in series. The source of one PMOS transistor in the series is connected to the power supply, and the drain of the other PMOS transistor is connected to the input of the inverter. The source of one NMOS transistor in the series is grounded, and the drain of the other NMOS transistor is connected to the input of the inverter. The outputs of each flip-flop are connected in pairs to the gates of each pair of transistors in the three voting branches.

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