A clock single edge detection circuit

Abstract

The application provides a clock single-edge detection circuit, which comprises a logic circuit group, a clock detection module, an operational transconductance amplifier, a DLL circuit, an NMOS tube and a VDTC circuit; a first logic circuit and a second logic circuit are connected with a first frequency mixer, a third logic circuit and a fourth logic circuit are connected with a second frequency mixer; an output end of the first frequency mixer is connected with a negative input end of the operational transconductance amplifier, and an output end of the second frequency mixer is connected with a positive input end of the operational transconductance amplifier; an output end of the operational transconductance amplifier is connected with a gate of the NMOS tube, a source of the NMOS tube is grounded, and a drain of the NMOS tube is connected with the DLL circuit; an output end of the DLL circuit is connected with an input end of the VDTC circuit, and an output end of the VDTC circuit is connected with an input end of the logic circuit group; and the double-edge detection circuit is changed into a single-edge detection circuit through the logic circuit; and only the single edge of the clock signal can be detected in the duty cycle mismatch.

Description

Technical Field

[0001] This invention relates to the field of integrated circuits, and in particular to a clock single-edge detection circuit. Background Technology

[0002] In digital and mixed-signal circuit systems, the clock signal is the "commander" that coordinates the timing of all modules and ensures stable data transmission and processing. Its signal quality directly determines the circuit's operational accuracy and reliability. The clock detection circuit is the core monitoring unit that ensures the clock signal functions correctly. Existing clock detection circuits use dual-edge detection. To reduce flicker noise, compared to active mixers, an NMOS passive mixer is used to extract the delay error of the delay line. This is combined with resistor R... D It can filter out second harmonics and improve the isolation of clock signals. If used in the clock generation module of a time-interleaved analog-to-digital converter, it is necessary to ensure that the falling edges are orthogonal and reduce timing skew. However, using a dual-edge detection circuit will extract the phase error between the two edges of the clock signal. The duty cycle of each clock signal output in the clock generation circuit may not be exactly the same, resulting in a duty cycle mismatch. This mismatch will directly affect the performance of the detection circuit. Even if the falling edges are orthogonal, due to the duty cycle mismatch, the rising edges are not orthogonal, and a phase error voltage will still be output, thus requiring adjustment towards a worse falling edge orthogonality. Summary of the Invention

[0003] To address the problems existing in the prior art, this invention proposes a single-edge clock detection circuit. The circuit structure includes: a logic circuit group, a clock detection module, an operational transconductance amplifier, a DLL circuit, an NMOS transistor, and a VDTC circuit. The logic circuit group consists of four logic circuits, each composed of an inverter, an AND gate, and two XOR gates. The clock detection module consists of two mixers. The first and second logic circuits are connected to the first mixer, and the third and fourth logic circuits are connected to the second mixer. The output of the first mixer is connected to the negative input of the operational transconductance amplifier, and the output of the second mixer is connected to the positive input of the operational transconductance amplifier. The output of the operational transconductance amplifier is connected to the gate of the NMOS transistor, the source of the NMOS transistor is grounded, and the drain of the NMOS transistor is connected to the DLL circuit. The output of the DLL circuit is connected to the input of the VDTC circuit, and the output of the VDTC circuit is connected to the input of the logic circuit group.

[0004] The beneficial effects of this invention are:

[0005] This invention transforms a double-edge detection circuit into a single-edge detection circuit using logic circuitry. By setting control signals, the rising or falling edge of the clock can be selected for detection. This allows for the detection of only one edge of the clock signal even in cases of duty cycle mismatch. Even if the other edge is not strictly orthogonal, the differential signal voltage of the mixer is essentially zero, which significantly reduces timing skew. This is particularly important for high-speed, high-precision converter applications. Attached Figure Description

[0006] Figure 1 This is a circuit diagram of the mixer of the present invention;

[0007] Figure 2 This invention relates to a four-channel clock orthogonal differential detection unit;

[0008] Figure 3 This is a structural diagram of the four-channel clock quadrature differential detection unit;

[0009] Figure 4 This is a structural diagram of the clock single-edge detection circuit of the present invention;

[0010] Figure 5 This is a simulation result diagram of the four-channel clock orthogonal differential detection unit of the present invention;

[0011] Figure 6 This is a diagram showing the output of the clock single-edge detection circuit of the present invention. Detailed Implementation

[0012] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0013] A single-edge clock detection circuit, such as Figure 3As shown, the circuit structure includes: a logic circuit group, a clock detection module, an operational transconductance amplifier, a DLL circuit, an NMOS transistor, and a VDTC circuit. The logic circuit group consists of four logic circuits, each composed of an inverter, an AND gate, and two XOR gates. The clock detection module consists of two mixers. The first and second logic circuits are connected to the first mixer, and the third and fourth logic circuits are connected to the second mixer. The output of the first mixer is connected to the negative input of the operational transconductance amplifier, and the output of the second mixer is connected to the positive input of the operational transconductance amplifier. The output of the operational transconductance amplifier is connected to the gate of the NMOS transistor, the source of the NMOS transistor is grounded, and the drain of the NMOS transistor is connected to the DLL circuit. The output of the DLL circuit is connected to the input of the VDTC circuit, and the output of the VDTC circuit is connected to the input of the logic circuit group.

[0014] In this embodiment, the connection relationships of the devices in the logic circuit group are as follows: the output of the first XOR gate is connected to the input of the first inverter, the output of the first inverter is connected to the first input of the first AND gate circuit, and the output of the second XOR gate is connected to the second input of the first AND gate circuit; the output of the third XOR gate is connected to the input of the second inverter, the output of the second inverter is connected to the first input of the second AND gate circuit, the output of the fourth XOR gate is connected to the second input of the second AND gate circuit, and the outputs of the first and second AND gate circuits are connected to the input of the first mixer; the outputs of the first and second AND gate circuits are connected to the input of the first mixer; the output of the fifth XOR gate... The output terminal is connected to the input terminal of the third inverter, the output terminal of the third inverter is connected to the first input terminal of the third AND gate circuit, and the output terminal of the sixth XOR gate is connected to the second input terminal of the third AND gate circuit. The output terminal of the seventh XOR gate is connected to the input terminal of the fourth inverter, the output terminal of the fourth inverter is connected to the first input terminal of the fourth AND gate circuit, and the output terminal of the eighth XOR gate is connected to the second input terminal of the fourth AND gate circuit. The output terminals of the third AND gate circuit and the fourth AND gate circuit are connected to the input terminal of the second mixer. The input terminals of the first XOR gate, second XOR gate, third XOR gate, fourth XOR gate, fifth XOR gate, sixth XOR gate, seventh XOR gate, and eighth XOR gate are connected to the output terminal of the VDTC circuit.

[0015] In this embodiment, the VDTC circuit includes three capacitors C1~C3, five NMOS transistors MN1~MN5, and one inverting output Schmitt trigger. The gate of MN1 is connected to the gate of MN2 and then to the output of the inverting output Schmitt trigger. The source of MN1 is connected to the power supply voltage. The drain of MN1 is connected to the positive terminals of capacitors C1, C2, and C3, the drain of MN2, and the input of the inverting output Schmitt trigger. The source of MN2 is grounded. The negative terminal of C1 is connected to the drain of MN3, and the source of MN3 is grounded. The negative terminal of C2 is connected to the drain of MN4, and the source of MN4 is grounded. The negative terminal of C3 is connected to the drain of MN5, and the source of MN5 is grounded. The gates of MN3, MN4, and MN5 output clock signals.

[0016] In this embodiment, the input ports of the first mixer from top to bottom are CLK_0, CLK_90, CLK_180, and CLK_270, with CLK_270 being grounded.

[0017] The connection between the first AND gate circuit and the second AND gate circuit and the first mixer includes: the output terminal of the first AND gate circuit is connected to the CLK_0 port and the CLK_90 port of the first mixer, respectively, and the output terminal of the second AND gate circuit is connected to the CLK_180 port of the first mixer.

[0018] In this embodiment, the input ports of the first mixer from top to bottom are CLK_0, CLK_270, CLK_180, and CLK_90, with CLK_90 being grounded.

[0019] The connection between the third and fourth AND gate circuits and the second mixer includes: the output of the third AND gate circuit is connected to the CLK_0 port and the CLK_270 port of the second mixer, respectively, and the output of the fourth AND gate circuit is connected to the CLK_180 port of the second mixer.

[0020] In this embodiment, as Figure 1 and Figure 2As shown, the mixer includes four resistors and four NMOS transistors; one end of the first resistor is connected to the CLK_0 terminal and the gate of the second NMOS transistor, and the other end of the first resistor is connected to the drain of the first NMOS transistor; one end of the second resistor is connected to the CLK_90 terminal and the gate of the first NMOS transistor, and the other end of the second resistor is connected to the drain of the second NMOS transistor; one end of the third resistor is connected to the CLK_180 terminal and the gate of the fourth NMOS transistor, and the other end of the third resistor is connected to the drain of the third NMOS transistor; one end of the fourth resistor is connected to the CLK_270 terminal and the gate of the third NMOS transistor, and the other end of the fourth resistor is connected to the drain of the fourth NMOS transistor; the sources of the first, second, third, and fourth NMOS transistors are interconnected and serve as the output terminals of the mixer.

[0021] This invention provides a novel single-edge detection circuit, which solves the problem that traditional double-edge detection circuits cannot accurately identify single-sided phase errors when duty cycle mismatch occurs. This is achieved by adding logic circuitry to a traditional clock detection module. The structure diagram of the proposed four-channel clock differential detection unit is shown below. Figure 4 As shown, it consists of an inverter, an AND gate, and a mixer, where the inverter and the AND gate together form a logic circuit.

[0022] Input (CK) (i=1,2,3,4) are clocks with phases of 0 degrees, 90 degrees, 180 degrees, and 270 degrees respectively. These clocks are generated by the clock module and are not necessarily strictly orthogonal phases. The clock signal CK<1:4> is XORed with the SET control signal to generate C<1:4>. The SET control signal determines whether to detect the rising or falling edge of the clock. When the SET control signal is set to 0, the XOR gate outputs C<1:4>. With CK In phase, i.e., CK Its own signal, when the SET control signal is set to 1, the XOR gate outputs CK. The inverted signal. Clock signal C <1> Through an inverter and clock signal C <2> The AND operation generates signal A, and similarly signals B, C, and D can be obtained. Signals A and C are input to the CLK_0 and CLK_90 ports of the mixer Symbol; signals B and D are input to the CLK_180 port of the mixer Symbol; and the CLK_270 port of the mixer Symbol is connected to GND.

[0023] The proposed four-channel clock DLL circuit is an extension of the aforementioned quadrature differential detection unit. It consists of a delay line circuit, a VDTC variable delay time controller, logic circuitry, a mixer, and an operational amplifier. The working principle is as follows: a differential clock CLK_P and CLK_N are input to the delay line circuit. The delay line then outputs four coarse-phase clocks CLK<1:4> with approximately quadrature phase errors. This clock is then processed by a quadrature phase error detection unit composed of logic circuitry and a mixer to determine if it is quadrature. If a phase error exists, two voltages are output. These two voltages are fed back by an operational amplifier to offset the common-mode voltage, Vctrl. Otherwise, the feedback voltage outputs the common-mode voltage. This feedback voltage Vctrl further controls the NMOS transistor, thereby controlling the delay line output to continuously approach the quadrature four-phase clock, eventually stabilizing at a near-quadrature four-phase clock output.

[0024] The variable delay time controller consists of an inverter, a capacitor array with three binary capacitor values, and a hysteresis inverter. The input signal is CLK. The output delay signal CK is generated by the variable delay time controller. The digital control signal DEL<2:0> controls the NMOS transistor as a switch to control whether the capacitor is connected, thereby controlling the delay time.

[0025] The proposed detection circuit was simulated and verified. For comparison, the four falling edges of the input were paired orthogonal in phase, and phase misalignment caused the rising edges to be paired non-orthogonal. The output of the four clock inputs after entering the traditional four-channel clock quadrature differential detection unit is as follows. Figure 5 As shown, even though the falling edges of the output VOP and VON are orthogonal to each other, there is still a phase difference voltage in the output due to duty cycle mismatch. This causes the phase of the four clocks to be adjusted through feedback, so that the four falling edges are no longer orthogonal.

[0026] In this embodiment, the four falling edges of the input are pairwise orthogonal, and phase misalignment causes the rising edges to be pairwise non-orthogonal. The output of the proposed four-channel clock orthogonal differential detection unit after the four clock inputs are as follows: Figure 6 As shown, when the falling edges of the output VOP and VON are already orthogonal to each other, there is no phase difference voltage at the output even if there is a duty cycle mismatch. This avoids adjusting the phase of the four clocks through feedback, ensuring that the four falling edges are orthogonal to each other.

[0027] Specifically, the entire circuit of this invention is a closed-loop feedback system. For example, in a four-channel clock detection system, when four orthogonal clocks with phase errors pass through the detection unit, the clock phase error is converted into a voltage difference between the two inputs of the operational amplifier. These two voltages are fed back to the operational amplifier output as a common-mode voltage offset by a feedback voltage Vctrl; otherwise, the feedback voltage outputs a common-mode voltage. This feedback voltage Vctrl continues to control the NMOS transistor, thereby controlling the delay line output to continuously approach the orthogonal four-phase clocks, eventually stabilizing at an output close to orthogonal four-phase clocks. Therefore, this system can adjust the phase error through feedback, ensuring that the four-phase clocks are as orthogonal as possible.

[0028] The above-described embodiments further illustrate the purpose, technical solution, and advantages of the present invention. It should be understood that the above-described embodiments are merely preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made to the present invention within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A clock single-edge detection circuit, characterized in that, The system includes a logic circuit group, a clock detection module, an operational transconductance amplifier, a DLL circuit, an NMOS transistor, and a VDTC circuit. The logic circuit group consists of four logic circuits, each composed of an inverter, an AND gate, and two XOR gates. The clock detection module consists of two mixers. The first and second logic circuits are connected to the first mixer, and the third and fourth logic circuits are connected to the second mixer. The output of the first mixer is connected to the negative input of the operational transconductance amplifier, and the output of the second mixer is connected to the positive input of the operational transconductance amplifier. The output of the operational transconductance amplifier is connected to the gate of the NMOS transistor, the source of the NMOS transistor is grounded, and the drain of the NMOS transistor is connected to the DLL circuit. The output of the DLL circuit is connected to the input of the VDTC circuit, and the output of the VDTC circuit is connected to the input of the logic circuit group.

2. The clock single-edge detection circuit according to claim 1, characterized in that, The connection relationships of the devices in the logic circuit group are as follows: the output of the first XOR gate is connected to the input of the first inverter, the output of the first inverter is connected to the first input of the first AND gate, and the output of the second XOR gate is connected to the second input of the first AND gate. The output of the third XOR gate is connected to the input of the second inverter, the output of the second inverter is connected to the first input of the second AND gate, the output of the fourth XOR gate is connected to the second input of the second AND gate, and the outputs of the first and second AND gates are connected to the input of the first mixer. The outputs of the first and second AND gates are connected to the input of the first mixer. The output of the fifth XOR gate is connected to... The input terminal of the third inverter is connected to the input terminal of the third AND gate circuit, and the output terminal of the sixth XOR gate is connected to the second input terminal of the third AND gate circuit. The output terminal of the seventh XOR gate is connected to the input terminal of the fourth inverter, and the output terminal of the fourth inverter is connected to the first input terminal of the fourth AND gate circuit. The output terminal of the eighth XOR gate is connected to the second input terminal of the fourth AND gate circuit. The output terminals of the third and fourth AND gate circuits are connected to the input terminals of the second mixer. The input terminals of the first, second, third, fourth, fifth, sixth, seventh, and eighth XOR gates are connected to the output terminals of the VDTC circuit.

3. A clock single-edge detection circuit according to claim 1, characterized in that, The input ports of the first mixer, from top to bottom, are CLK_0, CLK_90, CLK_180, and CLK_270, with CLK_270 being grounded.

4. A clock single-edge detection circuit according to claim 3, characterized in that, The connection between the first AND gate circuit and the second AND gate circuit and the first mixer includes: the output terminal of the first AND gate circuit is connected to the CLK_0 port and the CLK_90 port of the first mixer, respectively, and the output terminal of the second AND gate circuit is connected to the CLK_180 port of the first mixer.

5. A clock single-edge detection circuit according to claim 1, characterized in that, The input ports of the first mixer, from top to bottom, are CLK_0, CLK_270, CLK_180, and CLK_90, with CLK_90 being grounded.

6. A clock single-edge detection circuit according to claim 5, characterized in that, The connection between the third and fourth AND gate circuits and the second mixer includes: the output of the third AND gate circuit is connected to the CLK_0 port and the CLK_270 port of the second mixer, respectively, and the output of the fourth AND gate circuit is connected to the CLK_180 port of the second mixer.

7. A clock single-edge detection circuit according to claim 1, characterized in that, Clock C has phases of 0 degrees, 90 degrees, 180 degrees, and 270 degrees. <1> ~C <4> Clock signal C <1> Through an inverter and clock signal C <2> The AND operation produces signal A, and similarly signals B, C, and D can be obtained.

8. A clock single-edge detection circuit according to claim 1, characterized in that, The mixer includes four resistors and four NMOS transistors. One end of the first resistor is connected to the CLK_0 terminal and the gate of the second NMOS transistor, and the other end of the first resistor is connected to the drain of the first NMOS transistor. One end of the second resistor is connected to the CLK_90 terminal and the gate of the first NMOS transistor, and the other end of the second resistor is connected to the drain of the second NMOS transistor. One end of the third resistor is connected to the CLK_180 terminal and the gate of the fourth NMOS transistor, and the other end of the third resistor is connected to the drain of the third NMOS transistor. One end of the fourth resistor is connected to the CLK_270 terminal and the gate of the third NMOS transistor, and the other end of the fourth resistor is connected to the drain of the fourth NMOS transistor. The sources of the first, second, third, and fourth NMOS transistors are interconnected and serve as the output terminals of the mixer.

9. A clock single-edge detection circuit according to claim 8, characterized in that, The four resistors are of the same value.

10. A clock single-edge detection circuit according to claim 1, characterized in that, The VDTC circuit includes three capacitors C1-C3, five NMOS transistors MN1-MN5, and one inverting output Schmitt trigger. The gate of MN1 is connected to the gate of MN2 and then to the output of the inverting output Schmitt trigger. The source of MN1 is connected to the power supply voltage. The drain of MN1 is connected to the positive terminals of capacitors C1, C2, and C3, the drain of MN2, and the input of the inverting output Schmitt trigger. The source of MN2 is grounded. The negative terminal of C1 is connected to the drain of MN3, and the source of MN3 is grounded. The negative terminal of C2 is connected to the drain of MN4, and the source of MN4 is grounded. The negative terminal of C3 is connected to the drain of MN5, and the source of MN5 is grounded. The gates of MN3, MN4, and MN5 output clock signals.

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