Repetitive data signal pulse refreshing circuit and method

Abstract

The application provides a repeated data signal pulse refresh circuit and method, and relates to the technical field of integrated circuits. A pulse generation module in the circuit is used for receiving a repeated detection signal and controlling an output transient pulse signal based on a received clock signal. A pulse processing module is used for delaying the transient pulse signal to obtain a delayed pulse signal, and performing logical operation on the two pulse signals to output a direction pulse signal. A signal integration module is used for performing logical operation on the direction pulse signal and a current bit data signal to output a final pulse signal. When the current bit data signal is the same as a previous bit data signal, the repeated detection signal is high, and the final pulse signal is finally controlled to be opposite in polarity to the current bit data signal. The above circuit effectively distinguishes each independent bit data, avoids misjudgment, keeps signal jumping in the case of a long string of the same bit, avoids losing synchronization at the receiving end, has a simple structure, low cost, and strong applicability.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a repetitive data signal pulse refresh circuit and method. Background Technology

[0002] In a single-wire transmission system, signals typically represent data in two states: a high level indicates that the transmitted data is "1" and a low level indicates that the transmitted data is "0". When the transmitted bit data changes, such as from data "0" to data "1" or from data "1" to data "0", the register itself relies on edge detection, so it is easy to distinguish the data change and thus perform accurate decoding.

[0003] However, when transmitting the same bit data consecutively, such as three consecutive "1"s or two consecutive "0"s, the receiving end cannot distinguish these consecutive identical bit data by relying solely on level changes, and therefore cannot accurately determine the number of consecutive identical bit data.

[0004] Therefore, a circuit capable of accurately distinguishing multiple consecutive identical bit data is urgently needed for research. Summary of the Invention

[0005] To address the shortcomings of the existing technology, the present invention provides a repetitive data signal pulse refresh circuit and method, which solves the technical problem of accurately distinguishing multiple consecutive identical bit data in the prior art.

[0006] The present invention provides a repetitive data signal pulse refresh circuit, comprising: a pulse generation module, a pulse processing module, and a signal integration module;

[0007] The pulse generation module is used to receive the repeated detection signal and, based on the received clock signal, control the output of the transient pulse signal.

[0008] The pulse processing module is used to receive the transient pulse signal, perform delay processing on the transient pulse signal to obtain a delayed pulse signal, and perform logical operations on the transient pulse signal and the delayed pulse signal to output a direction pulse signal;

[0009] The signal integration module is used to receive the direction pulse signal and the current position data signal, perform logical operations on the direction pulse signal and the current position data signal, and output the final pulse signal;

[0010] When the current bit data signal is the same as the previous bit data signal, the repeat detection signal is high, controlling the transient pulse signal to be an inverted transient pulse signal, and making the direction pulse signal a positive pulse signal, ultimately controlling the final pulse signal to have the opposite polarity to the current bit data signal.

[0011] Optionally, the pulse generation module includes a register; the control terminal of the register is used to receive the clock signal, and the output terminal of the register is controlled based on the clock signal to output a transient pulse signal; the input terminal of the register is used to receive a control signal generated based on the repetitive detection signal, and when the repetitive detection signal is high, the control signal controls the transient pulse signal to invert and output an inverted transient pulse signal.

[0012] Optionally, the pulse generation module further includes a selector; the output terminal of the register is connected to the first input terminal of the selector, and the first input terminal of the selector is used to receive the transient pulse signal; the output terminal of the register is connected to the second input terminal of the selector through an inverter, and is used to receive the inverted signal of the transient pulse signal; the control terminal of the selector is used to receive the repetitive detection signal, and the output terminal of the selector outputs a control signal based on the repetitive detection signal, wherein the control signal is used to control the phase of the transient pulse signal.

[0013] Optionally, the pulse processing module includes a delay unit and a logic operation unit; the output of the pulse generation module is connected to the first input of the logic operation unit on one branch through the delay unit, the delay unit is used to delay the transient pulse signal and output the resulting delayed pulse signal to the logic operation unit; the output of the pulse generation module is connected to the second input of the logic operation unit on another branch to output the transient pulse signal to the logic operation unit; the logic operation unit is used to perform logical operations on the transient pulse signal and the delayed pulse signal to output a directional pulse signal.

[0014] Optionally, the logic operation unit includes a first XOR gate; the first XOR gate is used to perform an XOR operation on the transient pulse signal and the delayed pulse signal to obtain a direction pulse signal, wherein the direction pulse signal is a positive phase pulse signal.

[0015] Optionally, the signal integration module includes a second XOR gate; the first input terminal of the second XOR gate is used to receive the direction pulse signal, the second input terminal of the second XOR gate is used to receive the current bit data signal, and the second XOR gate is used to perform an XOR operation on the direction pulse signal and the current bit data signal to output a final pulse signal.

[0016] Optionally, the circuit further includes a signal detection unit; the signal detection unit is used to compare the current bit data signal and the previous pulse data signal; when the current bit data signal and the previous pulse data signal are the same, the signal detection unit generates a repetition detection signal and outputs the repetition detection signal to the pulse generation module, wherein the repetition detection signal is at a high level.

[0017] Optionally, the circuit further includes a receiver; the receiver is connected to the output of the signal integration module and is used to receive the final pulse signal; when the current bit data signal is the same as the previous bit data signal, the final pulse signal has the opposite polarity to both the current bit data signal and the previous bit data signal, and the final pulse signal appears between the current bit data signal and the previous bit data signal, so that the receiver can identify the final pulse signal through edge detection to distinguish between the current bit data signal and the previous bit data signal.

[0018] Another aspect of the present invention provides a method for refreshing repetitive data signal pulses, the method being implemented based on the repetitive data signal pulse refresh circuit described in any one of the above-mentioned methods, the method comprising:

[0019] When the current bit data signal is the same as the previous bit data signal, the pulse generation module receives the repetition detection signal and controls the output of the transient pulse signal based on the received clock signal. The repetition detection signal is high level and the transient pulse is an inverted transient pulse signal.

[0020] The pulse processing module performs delay processing on the transient pulse signal to obtain a delayed pulse signal, and performs logical operations on the transient pulse signal and the delayed pulse signal to output a directional pulse signal, wherein the directional pulse signal is a positive phase pulse signal;

[0021] The signal integration module receives the direction pulse signal and the current bit data signal, performs logical operations on the direction pulse signal and the current bit data signal, and outputs a final pulse signal, wherein the final pulse signal has the opposite polarity to the current bit data signal.

[0022] Optionally, after performing logical operations on the direction pulse signal and the current bit data signal to output a final pulse signal, the method further includes: using the receiver to receive the final pulse signal output by the signal integration module, and identifying the final pulse signal by edge detection to distinguish the current bit data signal from the previous bit data signal.

[0023] The repetitive data signal pulse refresh circuit and method provided by this invention are specifically applied in single-line transmission systems. When transmitting multiple consecutive identical bit data, traditional level changes cannot effectively distinguish them. However, based on the control of the repetition detection signal, a final pulse signal with the opposite polarity to the current bit data signal is generated and inserted between the current bit data signal and the previous pulse data signal. This effectively distinguishes each independent bit data and avoids misjudgment. Furthermore, in possible application scenarios, it helps maintain sufficient signal transitions in the case of long strings of identical bits, preventing the receiving end from losing synchronization. The entire circuit structure is simple, low-cost, and the control logic is clear and easy to understand. By adjusting the pulse signal generation mechanism, it can adapt to different needs and has strong applicability.

[0024] Other features and advantages of the invention will be set forth in the description which follows, and will be apparent in part from the description, or may be learned by practicing the invention. The objects and other advantages of the invention may be realized and obtained by means of the structures particularly pointed out in the written description, claims, and drawings.

[0025] The technical solution of the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0026] The accompanying drawings are provided to further illustrate the invention and form part of the specification. They are used in conjunction with embodiments of the invention to explain the invention and do not constitute a limitation thereof. In the drawings:

[0027] Figure 1 A schematic diagram of the structure of the repetitive data signal pulse refresh circuit in one embodiment of this application;

[0028] Figure 2 A circuit diagram of a repetitive data signal pulse refresh circuit provided in one embodiment of this application;

[0029] Figure 3 A comparison diagram of the output signals of the repetitive data signal pulse refresh circuit in one embodiment of this application;

[0030] Figure 4 This is a flowchart illustrating a repetitive data signal pulse refresh method in one embodiment of this application.

[0031] In the picture:

[0032] repeat, repeat detection signal; tx_clk, clock signal; spike, transient pulse signal; data, current bit data signal;

[0033] D1, Delay Unit. Detailed Implementation

[0034] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," and "counterclockwise," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0035] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0036] In this invention, unless otherwise explicitly specified and limited, the terms "installation," "connection," "linking," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0037] This application provides a repetitive data signal pulse refresh circuit, such as... Figure 1 As shown, the system includes a pulse generation module, a pulse processing module, and a signal integration module. The pulse generation module receives the repeat detection signal `repeat` and, based on the received clock signal `tx_clk`, outputs a transient pulse signal `spike`. The pulse processing module delays the transient pulse signal `spike` to obtain a delayed pulse signal, and performs logical operations on the transient pulse signal `spike` and the delayed pulse signal to output a direction pulse signal. The signal integration module receives the direction pulse signal and the current bit data signal `data`, performs logical operations on the direction pulse signal and the current bit data signal `data`, and outputs a final pulse signal. When the current bit data signal `data` is the same as the previous bit data signal, the repeat detection signal `repeat` is high, controlling the transient pulse signal `spike` to be an inverted transient pulse signal, and making the direction pulse signal a positive pulse signal, ultimately controlling the final pulse signal to have the opposite polarity to the current bit data signal `data`.

[0038] The repeating data signal pulse refresh circuit provided in this application is specifically applied in a single-line transmission system. When transmitting multiple consecutive identical bit data, traditional level changes cannot effectively distinguish them. However, based on the control of the repeat detection signal (repeat), a final pulse signal with the opposite polarity to the current bit data signal (data) is generated and inserted between the current bit data signal (data) and the previous data signal. This effectively distinguishes each independent bit data and avoids misjudgment. Furthermore, in potential application scenarios, it helps maintain sufficient signal transitions in the case of long strings of identical bits, preventing the receiving end from losing synchronization. The entire circuit has a simple structure, low cost, and clear and easy-to-understand control logic. By adjusting the pulse signal generation mechanism, it can adapt to different needs and has strong applicability.

[0039] Specifically, in the above embodiments, the pulse generation module includes a register; the control terminal of the register is used to receive a clock signal tx_clk, and the output terminal of the register is controlled based on the clock signal tx_clk to output a transient pulse signal spike; the input terminal of the register is used to receive a control signal generated based on a repeat detection signal repeat, and when the repeat detection signal repeat is high, the control signal controls the transient pulse signal spike to invert and outputs an inverted transient pulse signal.

[0040] Specifically, when the current bit data signal (data) is detected to be the same as the previous bit data signal, the repeat detection signal (repeat) goes high, thereby triggering the register to generate an inverted transient pulse signal; the clock signal (tx_clk) is used to provide a synchronization signal to ensure that the register updates its state at the correct time; the transient pulse signal (spike) represents a short pulse signal used to identify repeated data bits, that is, when the repeat detection signal (repeat) goes high, the control signal inverts the transient pulse signal (spike) to generate an inverted transient pulse signal.

[0041] In this embodiment, the synchronous control of the clock signal tx_clk ensures that the generation and output of the pulse signal occur at the correct time, thereby improving the stability and reliability of the system.

[0042] Furthermore, the pulse generation module also includes a selector; the output of the register is connected to the first input of the selector, which is used to receive the transient pulse signal spike; the output of the register is connected to the second input of the selector through an inverter, which is used to receive the inverted signal of the transient pulse signal spike; the control terminal of the selector is used to receive the repeat detection signal repeat, and the output of the selector outputs a control signal based on the repeat detection signal repeat, wherein the control signal is used to control the phase of the transient pulse signal spike.

[0043] The register has a selector connected to its input. The first input of the selector is connected to the output of the register to receive the transient pulse signal spike. The second input of the selector is connected to the output of the register via an inverter to receive the inverted signal of the transient pulse signal spike. The control terminal of the selector receives the repeat detection signal repeat and determines which input signal to use as the output. The output of the selector selects the transient pulse signal spike or its inverted signal based on the repeat detection signal repeat and generates a control signal.

[0044] In this embodiment, when the repeat detection signal repeat is high, at the clock edge of the clock signal tx_clk, the selector connected to the register input will select the inverted signal of the transient pulse signal spike output by the register. Specifically, the register is preferably a D flip-flop, whose input is controlled by a selector. The two inputs of the selector are the current transient pulse signal spike and the inverted signal spike. When the repeat detection signal repeat is high, the inverted signal spike is selected as the input of the register, and then at the next clock edge, the phase of the transient pulse signal spike will flip.

[0045] Specifically, in the above embodiments, the pulse processing module includes a delay unit D1 and a logic operation unit; the output terminal of the pulse generation module is connected to the first input terminal of the logic operation unit on one branch through the delay unit D1, the delay unit D1 is used to delay the transient pulse signal spike and output the resulting delayed pulse signal to the logic operation unit; the output terminal of the pulse generation module is connected to the second input terminal of the logic operation unit on another branch to output the transient pulse signal spike to the logic operation unit; the logic operation unit is used to perform logical operations on the transient pulse signal spike and the delayed pulse signal to output a direction pulse signal.

[0046] In this embodiment, the delay unit D1 delays the input transient pulse signal spike to generate a delayed pulse signal for subsequent logic operations. The logic operation unit performs logic operations on the transient pulse signal spike and the delayed pulse signal to generate a direction pulse signal, ensuring that the output signal can correctly identify repeated data bits.

[0047] Furthermore, the logic operation unit includes a first XOR gate; the first XOR gate is used to perform an XOR operation on the transient pulse signal spike and the delayed pulse signal to obtain a direction pulse signal, wherein the direction pulse signal is a positive phase pulse signal.

[0048] In this embodiment, in the preceding steps, after the transient pulse signal spike flips, an inverted transient pulse signal is generated, and a delayed pulse signal is obtained by passing through the delay unit D1 in a branch. Then, the inverted transient pulse signal and the delayed pulse signal are XORed to generate a directional pulse signal, which is specifically a positive pulse signal with a width equal to the delay time.

[0049] Specifically, in the above embodiments, the signal integration module includes a second XOR gate; the first input terminal of the second XOR gate is used to receive a direction pulse signal, the second input terminal of the second XOR gate is used to receive a current bit data signal data, and the second XOR gate is used to perform an XOR operation on the direction pulse signal and the current bit data signal data to output a final pulse signal.

[0050] In this embodiment, the positive pulse signal is XORed with the current bit data signal data to generate a final pulse signal with opposite polarity to the current bit data signal data on the transmission line. Specifically, in the case of multiple consecutive identical data signals, this pulse with opposite polarity is used to make the receiving end detect the edge, thereby correctly reading the data.

[0051] Specifically, in the above embodiment, the circuit further includes a signal detection unit; the signal detection unit is used to compare the current bit data signal data with the previous pulse data signal; when the current bit data signal data and the previous pulse data signal are the same, the signal detection unit generates a repeat detection signal repeat and outputs the repeat detection signal repeat to the pulse generation module, wherein the repeat detection signal repeat is at a high level.

[0052] In this embodiment, the signal detection unit compares the current bit data signal (data) with the previous data signal. If the current bit data signal (data) is the same as the previous data signal, the signal detection unit generates a high-level repeat detection signal (repeat). The generated repeat detection signal (repeat) is transmitted to the pulse generation module to control the behavior of the pulse generation module. Based on this, the signal detection unit serves as the starting point of the entire circuit, outputting the core control signal, namely the repeat detection signal (repeat). The generation of subsequent signals all depends on the high-level repeat detection signal (repeat) to effectively distinguish each independent bit data signal and avoid misjudgment.

[0053] Specifically, in the above embodiments, the circuit further includes a receiver; the receiver is connected to the output terminal of the signal integration module and is used to receive the final pulse signal; when the current bit data signal data is the same as the previous pulse data signal, the final pulse signal has the opposite polarity to the current bit data signal data and the previous pulse data signal, and the final pulse signal appears between the current bit data signal data and the previous pulse data signal, so that the receiver can identify the final pulse signal through edge detection to distinguish the current bit data signal data and the previous pulse data signal.

[0054] In this embodiment, the receiver receives the final pulse signal from the signal integration module and identifies the final pulse signal through an edge detection mechanism, thereby distinguishing the current bit data signal (data) from the previous pulse data signal. If the current bit data signal (data) is the same as the previous pulse data signal, the final pulse signal has the opposite polarity to these two signals and appears between the current bit data signal (data) and the previous pulse data signal, so that the receiver can accurately distinguish the current bit data signal (data) from the previous pulse data signal.

[0055] The specific application scenarios and working process of the repetitive data signal pulse refresh circuit provided in this application are as follows:

[0056] like Figure 2 As shown, assuming the current bit data signal `data` and the previous bit data signal are both "0", the generated repeat detection signal `repeat` is high. At the rising edge of the clock signal `tx_clk`, the selector selects to maintain the transient pulse signal `spike`. Assuming the transient pulse signal `spike` is "0", based on the repeat detection signal `repeat` control, the transient pulse signal `spike` output by the register is an inverted transient pulse signal, i.e., "1". During the process of the transient pulse signal `spike` changing from "0" to "1", after the delay processing of the delay unit `D1`, the delayed pulse signal is still "0" for a period of time, and the first XOR gate outputs "1". When the delayed pulse signal becomes "1" after a certain delay time, the first XOR gate outputs "0". The final output direction pulse signal is a positive pulse signal. The transmission line at this time is the current bit data signal `data` "0" XORed with the positive pulse signal. That is, when the direction pulse signal is "1", the transmission line outputs "1", otherwise it is "0". Therefore, while the current bit data signal data remains "0", a positive pulse is generated every clock cycle, causing the transmission line to produce a final pulse signal. The receiving end detects this change and thus knows that the current bit data signal data is still "0", but synchronization needs to be maintained.

[0057] like Figure 3The diagram shows the pulse signal received by the receiver. The upper part of the diagram shows the case when multiple identical bit data are received consecutively in the prior art. The lower part of the diagram, based on the circuit provided in this application, generates the final pulse signal, which generates two negative pulses when three consecutive "1" signals are received, one negative pulse when two consecutive "0" signals are received, and two negative pulses when three consecutive "0" signals are received, thereby effectively distinguishing multiple identical signals.

[0058] This application also provides a method for refreshing repetitive data signal pulses, which is implemented based on the repetitive data signal pulse refresh circuit described in any of the above claims, such as... Figure 4 As shown, the method includes: First, when the current bit data signal data is the same as the previous bit data signal, the pulse generation module receives the repeat detection signal repeat and controls the output of the transient pulse signal spike based on the received clock signal tx_clk. The repeat detection signal repeat is high level, and the transient pulse is an inverted transient pulse signal. Then, the pulse processing module delays the transient pulse signal spike to obtain a delayed pulse signal. The transient pulse signal spike and the delayed pulse signal are then logically operated on to output a direction pulse signal, which is a positive pulse signal. Finally, the signal integration module receives the direction pulse signal and the current bit data signal data, and performs logical operations on the direction pulse signal and the current bit data signal data to output a final pulse signal, which has the opposite polarity to the current bit data signal data.

[0059] The repeating data signal pulse refresh method provided in this application generates a final pulse signal with opposite polarity to the current bit data signal (data) based on the control of the repeat detection signal (repeat). The final pulse signal is inserted between the current bit data signal (data) and the previous pulse data signal, which can effectively distinguish each independent bit data and avoid misjudgment. Furthermore, in possible application scenarios, it helps to maintain sufficient signal transitions in the case of long strings of identical bits, and avoids the receiving end losing synchronization.

[0060] Furthermore, after performing logical operations on the direction pulse signal and the current bit data signal data to output the final pulse signal, the method also includes: using a receiver to receive the final pulse signal output by the signal integration module, and identifying the final pulse signal through edge detection to distinguish the current bit data signal data from the previous pulse data signal.

[0061] In this embodiment, after the final pulse signal is output, the receiver receives the final pulse signal and identifies it through an edge detection mechanism, thereby distinguishing the current bit data signal (data) from the previous bit data signal. When the current bit data signal (data) and the previous bit data signal are the same, the final pulse signal has the opposite polarity to these two signals and appears between the current bit data signal (data) and the previous bit data signal. The receiver can accurately distinguish the current bit data signal (data) from the previous bit data signal.

[0062] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this invention and their equivalents, this invention also intends to include these modifications and variations.

Claims

1. A repetitive data signal pulse refresh circuit, characterized in that, include: Pulse generation module, pulse processing module, and signal integration module; The pulse generation module is used to receive the repeated detection signal and, based on the received clock signal, control the output of the transient pulse signal. The pulse processing module is used to receive the transient pulse signal, perform delay processing on the transient pulse signal to obtain a delayed pulse signal, and perform logical operations on the transient pulse signal and the delayed pulse signal to output a direction pulse signal; The signal integration module is used to receive the direction pulse signal and the current position data signal, perform logical operations on the direction pulse signal and the current position data signal, and output the final pulse signal; When the current bit data signal is the same as the previous bit data signal, the repeat detection signal is high, controlling the transient pulse signal to be an inverted transient pulse signal, and making the direction pulse signal a positive pulse signal, ultimately controlling the final pulse signal to have the opposite polarity to the current bit data signal.

2. The repetitive data signal pulse refresh circuit according to claim 1, characterized in that, The pulse generation module includes a register; The control terminal of the register is used to receive the clock signal, and the output terminal of the register is controlled based on the clock signal to output a transient pulse signal; The input terminal of the register is used to receive a control signal generated based on the repeated detection signal. When the repeated detection signal is high, the control signal controls the transient pulse signal to invert and outputs an inverted transient pulse signal.

3. The repetitive data signal pulse refresh circuit according to claim 2, characterized in that, The pulse generation module also includes a selector; The output of the register is connected to the first input of the selector, and the first input of the selector is used to receive the transient pulse signal. The output of the register is connected to the second input of the selector via an inverter, and is used to receive the inverted signal of the transient pulse signal; The control terminal of the selector is used to receive the repeated detection signal, and the output terminal of the selector outputs a control signal based on the repeated detection signal, wherein the control signal is used to control the phase of the transient pulse signal.

4. The repetitive data signal pulse refresh circuit according to claim 1, characterized in that, The pulse processing module includes a delay unit and a logic operation unit; The output of the pulse generation module is connected to the first input of the logic operation unit through the delay unit on a branch. The delay unit is used to delay the transient pulse signal and output the resulting delayed pulse signal to the logic operation unit. The output of the pulse generation module is connected to the second input of the logic operation unit on another branch to output the transient pulse signal to the logic operation unit; The logic operation unit is used to perform logic operations on the transient pulse signal and the delayed pulse signal to output a direction pulse signal.

5. The repetitive data signal pulse refresh circuit according to claim 4, characterized in that, The logic operation unit includes a first XOR gate; The first XOR gate is used to perform an XOR operation on the transient pulse signal and the delayed pulse signal to obtain a directional pulse signal, wherein the directional pulse signal is a positive phase pulse signal.

6. The repetitive data signal pulse refresh circuit according to claim 1, characterized in that, The signal integration module includes a second XOR gate; The first input terminal of the second XOR gate is used to receive the direction pulse signal, the second input terminal of the second XOR gate is used to receive the current bit data signal, and the second XOR gate is used to perform an XOR operation on the direction pulse signal and the current bit data signal to output the final pulse signal.

7. The repetitive data signal pulse refresh circuit according to claim 1, characterized in that, The circuit also includes a signal detection unit; The signal detection unit is used to compare the current bit data signal with the previous bit data signal; When the current bit data signal is the same as the previous bit data signal, the signal detection unit generates a repetition detection signal and outputs the repetition detection signal to the pulse generation module, wherein the repetition detection signal is at a high level.

8. The repetitive data signal pulse refresh circuit according to claim 1, characterized in that, The circuit also includes a receiver; The receiver is connected to the output of the signal integration module and is used to receive the final pulse signal; When the current bit data signal is the same as the previous bit data signal, the final pulse signal has the opposite polarity to both the current bit data signal and the previous bit data signal, and the final pulse signal appears between the current bit data signal and the previous bit data signal, so that the receiver can identify the final pulse signal through edge detection to distinguish between the current bit data signal and the previous bit data signal.

9. A method for refreshing repetitive data signal pulses, characterized in that, The method is implemented based on the repetitive data signal pulse refresh circuit according to any one of claims 1 to 8, and the method includes: When the current bit data signal is the same as the previous bit data signal, the pulse generation module receives the repetition detection signal and controls the output of the transient pulse signal based on the received clock signal. The repetition detection signal is high level and the transient pulse is an inverted transient pulse signal. The pulse processing module performs delay processing on the transient pulse signal to obtain a delayed pulse signal, and performs logical operations on the transient pulse signal and the delayed pulse signal to output a directional pulse signal, wherein the directional pulse signal is a positive phase pulse signal; The signal integration module receives the direction pulse signal and the current bit data signal, performs logical operations on the direction pulse signal and the current bit data signal, and outputs a final pulse signal, wherein the final pulse signal has the opposite polarity to the current bit data signal.

10. The method according to claim 9, characterized in that, After performing logical operations on the direction pulse signal and the current bit data signal to output the final pulse signal, the method further includes: The receiver receives the final pulse signal output by the signal integration module and identifies the final pulse signal by edge detection to distinguish the current bit data signal from the previous bit data signal.

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