Triangular wave signal generation method, device, chip and electronic equipment

Abstract

The application provides a triangular wave signal generation method and device, a chip and an electronic equipment, and relates to the technical field of electronics. The method can be applied to PWM carrier generation of a power electronic converter, carrier phase shift of a multi-path interleaved control system and the like. The application converts the non-integer problem of the number of clock cycles waiting for each amplitude step required for generating a triangular wave into an integer remainder distribution problem in the Bresenham algorithm, that is, by setting a 16-bit integer error accumulator to accumulate and track the remainder, it is dynamically determined whether the current amplitude step continues for the number of basic clocks (short step) or the number of basic clocks + 1 (long step), so that optimal uniform distribution is realized in the integer domain, and zero-overhead preset of arbitrary phase offset is realized in cooperation with the segmented mapping rule. The application can improve the frequency accuracy of multi-path triangular wave signals, ensure the fixed phase difference of multi-path triangular waves, and has low requirements for hardware resources.

Description

Technical Field

[0001] This application relates to the field of circuit technology, specifically to a method, apparatus, chip, and electronic device for generating a triangular wave signal. Background Technology

[0002] Digital triangular wave signals (referred to as triangular wave signals) are widely used in power electronic converters (such as multiphase interleaved DC-DC converters or multilevel inverters), industrial motor drives, and measuring instruments. The most typical application of triangular wave signals is as carrier signals in pulse width modulation (PWM) comparators. In this scenario, the controller compares the modulated wave with the triangular wave signal used as the carrier wave point by point in each comparison cycle and outputs drive pulses (i.e., switching drive pulses) to drive the power switching transistors. The frequency accuracy and phase relationship between the triangular wave signals directly determine the system's harmonic spectrum and electromagnetic interference characteristics. For example, in a multi-phase interleaved control topology (e.g., N-phase interleaved DC-DC), the triangular carrier waves of each phase need to have an equal phase difference (e.g., ...). The input / output current ripples are interleaved to cancel each other out, thereby reducing the size and cost of the passive filter. Based on this, the digital triangular wave signal generation device is required to have the following core capabilities: (1) Settable initial phase: Each generator should start from the preset phase point when it starts up, instead of starting from zero point uniformly; (2) Precise frequency control: The carrier frequency is usually obtained by dividing the master clock, but when the ratio of the two is not an integer, an effective error dispersion mechanism is required to avoid the introduction of harmonic components by step cycle jitter; (3) Multi-channel deterministic synchronization: The multi-channel generator must atomically lock the phase at the same time to ensure that the phase difference between each channel reaches the design value at the moment of activation, and the accuracy requirement reaches the single clock cycle level.

[0003] Currently, existing field programmable gate array (FPGA) digital triangular wave signal generation schemes include schemes based on read-only memory (ROM) lookup tables or dedicated direct digital synthesis (DDS) chips, as well as ROM-free schemes based on counters or phase accumulators.

[0004] One approach, based on a ROM lookup table or a dedicated DDS chip, involves pre-storing waveform sample values ​​in on-chip block random access memory (BRAM) or an external DDS chip, and then sequentially addressing and outputting them through a phase accumulator. This approach yields high-quality triangular wave signals, but it requires BRAM resources, and the initial phase preset needs to be written to the ROM start address, making it difficult to implement on resource-constrained small FPGA devices.

[0005] Among them, the ROM-free scheme based on counters or phase accumulators gradually increases or decreases the amplitude value by counting the clock and determining the direction. This scheme is simple to implement, but when the ratio of the waveform period to the clock period is not an integer (which is a common case in engineering), the step timing jitters between two values ​​that differ by one clock cycle. The duration of each step of the output triangular wave is not optimally uniformly distributed, which has a certain impact on the carrier purity. Phase preset usually relies on software calculation and then writing to the register. This method has the problem that the phase synchronization of each channel cannot guarantee the alignment accuracy of a single clock cycle, which leads to a significant reduction in the ripple cancellation effect, a significant increase in input / output current ripple, and the inability to cancel each other out, thereby increasing the size and cost of the passive filter.

[0006] In summary, existing technologies suffer from problems such as high hardware resource requirements, asynchronous frequencies of multiple triangular wave signals, and inconsistent phase differences among multiple triangular wave signals. Summary of the Invention

[0007] This application provides a method, apparatus, chip, and electronic device for generating triangular wave signals, which can improve the frequency accuracy of multiple triangular wave signals, ensure the phase difference of multiple triangular wave signals is fixed, and have low requirements for hardware resources.

[0008] In a first aspect, this application provides a method for generating a triangular wave signal, and a triangular wave signal generating apparatus for generating a system clock and an enable signal, comprising: During the compilation phase, compilation parameters are determined, including the total number of clock cycles, the total number of amplitude steps, the short step duration, and the number of long steps. The total number of clock cycles is determined based on the triangular wave output frequency and the system clock frequency. The total number of amplitude steps is determined based on the peak amplitude of the triangular wave. The short step duration is equal to the integer part of the quotient of the total number of clock cycles and the total number of amplitude steps. The number of long steps is equal to the difference between the total number of clock cycles and the product of the short step duration and the total number of amplitude steps. In response to the detection of the rising edge of the enable signal, an initialization operation is performed, which includes: clearing the in-step counter and the error accumulator to zero, and mapping the first phase signal based on a preset segmented mapping rule to obtain the initial amplitude and initial direction; the first phase signal is a signal obtained based on the phase bias signal and synchronized with the system clock. During the operation phase, at least one round of iterative processing is performed to generate a triangular wave signal, wherein the i-th round of iterative processing in the at least one round of iterative processing includes: The validity of the i-th step trigger pulse is determined based on the comparison threshold and the total number of system clocks corresponding to the i-th amplitude step stored in the in-step counter. The in-step counter is used to increment by 1 for each system clock cycle within the i-th amplitude step. The comparison threshold is determined based on the i-th amplitude step and the short step duration. i is a positive integer. In response to the detection of a valid i-th step trigger pulse, the error accumulator and step size flag register are updated based on the Bresenham algorithm rules, and the in-step counter is cleared. The updated error accumulator is used to store the i-th accumulated error value, and the updated step size flag register is used to store the step size type of the (i+1)-th amplitude step. When i=1, the i-th accumulated error value is equal to 0. When i is a positive integer greater than 1, the i-th accumulated error value is determined based on the (i-1)-th accumulated error value and the number of long steps. In response to the detection of a valid trigger pulse for the i-th step, the output amplitude and step direction of the i-th amplitude step are updated based on the flip threshold, amplitude threshold, step direction of the i-th amplitude step, and output amplitude of the i-th amplitude step. Wherein, when i=1, the step direction of the i-th amplitude step is the initial direction, and the output amplitude of the i-th amplitude step is the initial amplitude; when i is a positive integer greater than 1, the step direction of the i-th amplitude step is the step direction of the (i-1)-th amplitude step, and the output amplitude of the i-th amplitude step is the output amplitude of the (i-1)-th amplitude step.

[0009] In some implementations, the stopping condition for at least one round of iteration is that the enable signal is low or the device exits the operation phase.

[0010] In some implementations, after performing the i-th iteration, the result of the i-th iteration includes: the updated output amplitude of the i-th amplitude step, and the updated step direction of the i-th amplitude step.

[0011] In some implementations, i is a positive integer greater than 1, and the (i-1)th summation result is the sum of the (i-1)th error accumulation value in the error accumulator and the number of long steps; and, in response to detecting that the i-th step trigger pulse is valid, the error accumulator and the step size flag register are updated based on the Bresenham algorithm rules, including: If the sum of the (i-1)th step is greater than or equal to the total number of amplitude steps, then the (i-1)th error accumulation value is updated to the difference between the (i-1)th error accumulation value and the total number of amplitude steps; the step size flag in the step size flag register is updated to a short step, where the step size type of the (i+1)th amplitude step is the short step indicated by the step size flag. If the sum of the (i-1)th step is less than the total number of amplitude steps, then the (i-1)th error accumulation value is updated to the sum of the (i-1)th step; the step size flag in the step size flag register is updated to long step, where the step size type of the (i+1)th amplitude step is the long step indicated by the step size flag.

[0012] In some implementations, the flip threshold is equal to the difference between the peak amplitude of the triangular wave and 1, and the amplitude threshold is the peak amplitude of the triangular wave; and, based on the flip threshold, the amplitude threshold, the step direction of the i-th amplitude step, and the output amplitude of the i-th amplitude step, the output amplitude and the step direction of the i-th amplitude step are updated, including: When the step direction of the i-th amplitude step is downward and the output amplitude of the i-th amplitude step is less than or equal to the negative of the flip threshold, the step direction of the i-th amplitude step is updated to upward. When the step direction of the i-th amplitude step is upward and the output amplitude of the i-th amplitude step is greater than or equal to the flip threshold, the step direction of the i-th amplitude step is updated to downward. When the step direction of the i-th amplitude step is downward and the output amplitude of the i-th amplitude step is greater than the negative of the amplitude threshold, the output amplitude of the i-th amplitude step is reduced by 1. When the step direction of the i-th amplitude step is upward and the output amplitude of the i-th amplitude step is greater than or equal to the flip threshold, the output amplitude of the i-th amplitude step is incremented by 1.

[0013] In some implementations, the initial amplitude and initial direction are obtained by mapping the first phase signal based on a preset segmented mapping rule, including: When the amplitude of the first phase signal is less than or equal to the peak amplitude of the triangular wave, the initial amplitude is equal to the negative of the amplitude of the first phase signal, and the initial direction is the upward direction. When the amplitude of the first phase signal is greater than the peak amplitude of the triangular wave, the initial amplitude is equal to the difference between the amplitude of the first phase signal and twice the peak amplitude of the triangular wave, and the initial direction is the downward direction.

[0014] In some implementations, in response to the detection of a rising edge of the enable signal, an initialization operation is performed, including: In response to the detection of the rising edge of the enable signal, the enable signal is delayed by one clock cycle to obtain the first pulse signal; In response to the detection of a first pulse signal, an initialization operation is performed, wherein the first phase signal is a signal obtained based on a phase bias signal in response to the detection of the first pulse signal and is synchronized with the system clock.

[0015] In some implementations, the total number of amplitude steps is Q times the peak amplitude of the triangular wave, where Q is a positive integer greater than 1; the total number of clock beats is equal to the result obtained by rounding down the quotient of the triangular wave output frequency and the system clock frequency.

[0016] In some implementations, when the i-th amplitude step is a short step, the comparison threshold is equal to the difference between the short step duration and 1; when the i-th amplitude step is a long step, the comparison threshold is equal to the short step duration.

[0017] Secondly, this application provides a triangular wave signal generating apparatus for performing the method in any possible implementation of the first aspect described above.

[0018] Thirdly, this application provides a chip that includes the triangular wave signal generating device described in the second aspect above.

[0019] Fourthly, this application provides an electronic device that includes the triangular wave signal generating device of the second aspect above, or the chip of the third aspect above.

[0020] Fifthly, this application provides a computer program product comprising: a computer program (also referred to as code or instructions) that, when executed, causes a computer to perform the method in any of the possible implementations of the first aspect described above.

[0021] In a sixth aspect, this application provides a computer-readable storage medium storing a computer program (also referred to as code or instructions) that, when run on a computer, causes the computer to perform the method in any of the possible implementations of the first aspect described above.

[0022] Based on the technical solution provided in this application, the non-integer problem of "the number of clock cycles to wait for each amplitude step" required to generate a triangular wave is transformed into an integer remainder allocation problem in the Bresenham linear algorithm (referred to as the Bresenham algorithm). Specifically, a 16-bit integer error accumulator is used to track and accumulate the remainder, dynamically determining whether the current amplitude step (i.e., the i-th amplitude step) continues with the "base clock number" (i.e., short step) or the "base clock number + 1" (i.e., long step), thus achieving optimal uniform allocation in the integer domain. Simultaneously, piecewise mapping enables zero-overhead preset of arbitrary phase offsets. This application can improve the frequency accuracy of multi-channel triangular wave signals, ensure a fixed phase difference between multiple triangular wave signals, and has low hardware resource requirements. It is applicable to scenarios such as PWM carrier generation in power electronic converters and carrier phase shifting in multi-channel interleaved control systems. Attached Figure Description

[0023] Figure 1 This is a schematic diagram of a triangular wave signal generating device 100 provided in an embodiment of this application.

[0024] Figure 2This is a schematic diagram of an electronic device 200 provided in an embodiment of this application.

[0025] Figure 3 This is a schematic diagram of a triangular wave signal generation method provided in an embodiment of this application.

[0026] Figure 4 Is to execute the above Figure 3 A schematic diagram of S330 in the provided method.

[0027] Figure 5 This is a schematic diagram of another triangular wave signal generation method provided in the embodiments of this application. Detailed Implementation

[0028] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0029] It should be understood that, when used in this specification and the appended claims, the term "comprising" indicates the presence of the described features, integrals, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or collections thereof. The terms "comprising," "including," "having," and variations thereof all mean "including but not limited to," unless otherwise specifically emphasized.

[0030] It should be understood that, in order to clearly describe the technical solution of this application, the terms "first" and "second" are used to distinguish identical or similar items with substantially the same function and effect. Those skilled in the art will understand that the terms "first" and "second" do not limit the quantity or execution order, and that the terms "first" and "second" do not necessarily imply that they are different.

[0031] The technical solution provided in this application will now be described in detail.

[0032] This application provides a method, apparatus, chip, and electronic device for generating triangular wave signals, which can improve the frequency accuracy of multiple triangular wave signals, ensure the phase difference of multiple triangular wave signals is fixed, and have low requirements for hardware resources.

[0033] First, with reference to the accompanying drawings, we will introduce the triangular wave signal generation device to which the triangular wave signal generation method provided in this application is applicable.

[0034] For example, Figure 1This is a schematic diagram of a triangular wave signal generating device 100 provided in an embodiment of this application.

[0035] like Figure 1 As shown, the triangular wave signal generation device 100 may include: an input signal module 101, a phase offset analysis module 102, a compiler parameter module 103, an enable rising edge detection module 104, an in-step counter 105, a step timing control module 106, and a waveform output module 107. Each module is described below.

[0036] The input signal module 101 is used to generate an enable signal, a system clock, and a phase bias signal. Optionally, the input signal module 101 is also used to generate a reset signal.

[0037] Phase offset parsing module 102: This module processes the phase offset signal (e.g., a 32-bit signed phase offset signal) obtained from input signal module 101 through a pipelined register to obtain a first phase signal. It also maps the first phase signal based on a preset segmented mapping rule to obtain the initial amplitude and initial direction. It should be understood that phase offset parsing module 102 has no multiplier; all operations are addition, subtraction, and comparison.

[0038] Compiler Parameter Module 103: Used to determine compiler parameters during the compilation phase. These parameters include the total number of clock cycles, the total number of amplitude steps, the short step duration, and the number of long steps. The total number of clock cycles is determined based on the triangular wave output frequency and the system clock frequency. The total number of amplitude steps is determined based on the peak amplitude of the triangular wave. The short step duration is the integer part of the quotient of the total number of clock cycles and the total number of amplitude steps. The number of long steps is the difference between the total number of clock cycles and the product of the short step duration and the total number of amplitude steps. It should be understood that all compiler parameters exist as register constants; that is, during runtime, compiler parameters do not consume any computational resources.

[0039] Enable rising edge detection module 104: In response to the detection of a rising edge of the enable signal, the enable signal is delayed by one clock cycle to obtain a first pulse signal, wherein the first pulse signal is used to trigger a global synchronization initialization operation.

[0040] In-step counter 105: The in-step counter is used to increment by 1 for each system clock cycle within the i-th amplitude step. It should be understood that in the event of a reset of the i-th step trigger pulse, the first pulse signal, or the triangular wave signal generating device 100, the in-step counter 105 needs to be cleared.

[0041] The step timing control module 106, also known as the Bresenham step timing control module 106, may include an error accumulator 106a and a step size flag register 106b.

[0042] In response to the detection of a valid i-th step trigger pulse, the error accumulator 106a updates the accumulated error value based on the Bresenham algorithm, and the step size flag register 106b updates the step size flag. It should be understood that the step timing control module 106 is also used to control the comparison threshold of the in-step counter to switch between short step duration and long step duration, ensuring that the duration of long steps is one clock cycle longer than the other steps, and that the remainder error is evenly distributed.

[0043] The waveform output module 107 includes a direction register 107a and an amplitude register 107b (also known as a waveform amplitude register).

[0044] The direction register 107a is used to store the step direction of the i-th amplitude step. In some implementations, when the value of the direction register 107a is 1, it indicates that the step direction of the i-th amplitude step is downward; when the value of the direction register 107a is 0, it indicates that the step direction of the i-th amplitude step is upward.

[0045] The direction register 107a is also used to: load an initial direction on the rising edge of a reset or enable signal; and, in response to detecting that the i-th step trigger pulse is valid, perform the following steps: when the step direction of the i-th amplitude step is a downward direction and the output amplitude of the i-th amplitude step is less than or equal to the negative of a flip threshold, update the step direction of the i-th amplitude step to an upward direction; when the step direction of the i-th amplitude step is an upward direction and the output amplitude of the i-th amplitude step is greater than or equal to a flip threshold, update the step direction of the i-th amplitude step to a downward direction.

[0046] Amplitude register 107b is used to output 0 when reset or disabled; when the rising edge of the enable signal is detected, the initial amplitude is loaded; in response to the detection of the valid i-th step trigger pulse, the following steps are performed: when the step direction of the i-th amplitude step is the downward direction and the output amplitude of the i-th amplitude step is greater than the negative of the amplitude threshold, the output amplitude of the i-th amplitude step is decremented by 1; when the step direction of the i-th amplitude step is the upward direction and the output amplitude of the i-th amplitude step is greater than or equal to the toggle threshold, the output amplitude of the i-th amplitude step is incremented by 1.

[0047] It should be understood that Figure 1 The triangular wave signal generating device 100 shown is for illustrative purposes only and does not constitute any limitation on the triangular wave signal generating device applicable to the triangular wave signal generation provided in the embodiments of this application.

[0048] For example, Figure 2 This is a schematic diagram of an electronic device 200 provided in an embodiment of this application. Figure 2 As shown, the electronic device 200 may include the above-mentioned Figure 1The diagram shows a triangular wave signal generating device 100. The type of electronic device 200 is not limited and can be configured according to actual needs. Optionally, the electronic device 200 may also include other devices besides the triangular wave signal generating device 100.

[0049] The method for generating triangular wave signals provided in this application will be described in detail below. It should be understood that the triangular wave signal generation method shown below is for illustrative purposes only and does not constitute any limitation on the triangular wave signal generation method provided in this application.

[0050] Example 1 For example, Figure 3 This is a schematic diagram of a triangular wave signal generation method provided in an embodiment of this application. The following is a description of... Figure 3 The steps shown are described in detail below: In S310, during the compilation phase, compilation parameters are determined. These parameters include the total number of clock cycles, the total number of amplitude steps, the short step duration, and the number of long steps. The total number of clock cycles is determined based on the triangular wave output frequency and the system clock frequency. The total number of amplitude steps is determined based on the peak amplitude of the triangular wave. The short step duration is equal to the integer part of the quotient of the total number of clock cycles and the total number of amplitude steps. The number of long steps is equal to the difference between the total number of clock cycles and the product of the short step duration and the total number of amplitude steps.

[0051] In some implementations, the total number of amplitude steps is Q times the peak amplitude of the triangular wave, where Q is a positive integer greater than 1. For example, the value of Q can be, but is not limited to, 4.

[0052] In some implementations, the total number of clock beats is equal to the result obtained by rounding down the quotient of the triangular wave output frequency and the system clock frequency.

[0053] There are no limitations on the peak amplitude of the triangular wave, the output frequency of the triangular wave, and the frequency of the system clock; these can be set according to actual conditions.

[0054] In S320, in response to the detection of the rising edge of the enable signal, an initialization operation is performed, wherein the initialization operation includes: clearing the in-step counter and the error accumulator to zero, and mapping the first phase signal based on a preset segmented mapping rule to obtain the initial amplitude and initial direction; the first phase signal is a signal obtained based on the phase bias signal and synchronized with the system clock.

[0055] In some implementations, the phase bias signal is a 32-bit signed phase bias.

[0056] In some implementations, the error accumulator is a 16-bit error accumulator.

[0057] In some implementations, the first phase signal is mapped to obtain the initial amplitude and initial direction based on a preset segmented mapping rule, including: when the first phase signal is less than or equal to the peak amplitude of the triangular wave, the initial amplitude is equal to the negative of the amplitude of the first phase signal, and the initial direction is the upward direction; when the first phase signal is greater than the peak amplitude of the triangular wave, the initial amplitude is equal to the difference between the amplitude of the first phase signal and twice the peak amplitude of the triangular wave, and the initial direction is the downward direction.

[0058] In some implementations, in response to the detection of a rising edge of the enable signal, an initialization operation is performed, including: in response to the detection of a rising edge of the enable signal, performing a one-beat delay on the enable signal to obtain a first pulse signal; in response to the detection of the first pulse signal, performing an initialization operation, wherein the first phase signal is a signal obtained based on a phase bias signal in response to the detection of the first pulse signal and is synchronized with the system clock.

[0059] In S330, during the running phase, at least one round of iterative processing is performed to generate a triangular wave signal.

[0060] For details of at least one round of iterative processing, please refer to [link / reference]. Figure 4 S330-1, S330-2, and S330-3 are shown. The following section discusses... Figure 4 S330-1, S330-2 and S330-3 are shown and introduced.

[0061] In S330-1, the validity of the i-th step trigger pulse is determined based on the comparison threshold and the total number of system clocks corresponding to the i-th amplitude step stored in the in-step counter. The in-step counter is used to increment by 1 for each system clock cycle within the i-th amplitude step. The comparison threshold is determined based on the i-th amplitude step and the short step duration. i is a positive integer.

[0062] In some implementations, when the i-th amplitude step is a short step, the comparison threshold is equal to the difference between the short step duration and 1; when the i-th amplitude step is a long step, the comparison threshold is equal to the short step duration.

[0063] In S330-2, in response to the detection of a valid i-th step trigger pulse, the error accumulator and step size flag register are updated based on the Bresenham algorithm rules, and the in-step counter is cleared. The updated error accumulator is used to store the i-th error accumulation value, and the updated step size flag register is used to store the step size type of the (i+1)-th amplitude step. When i=1, the i-th error accumulation value is equal to 0. When i is a positive integer greater than 1, the i-th error accumulation value is determined based on the (i-1)-th error accumulation value and the number of long steps.

[0064] In some implementations, i is a positive integer greater than 1, and the (i-1)th summation result is the sum of the (i-1)th error accumulation value in the error accumulator and the number of long steps; and, in response to detecting that the i-th step trigger pulse is valid, the error accumulator and the step size flag register are updated based on the Bresenham algorithm rules, including: if the (i-1)th summation result is greater than or equal to the total number of amplitude steps, then the (i-1)th error accumulation value is updated to the difference between the (i-1)th error accumulation value and the total number of amplitude steps; the step size flag in the step size flag register is updated to a short step, wherein the step size type of the (i+1)th amplitude step is the short step indicated by the step size flag; if the (i-1)th summation result is less than the total number of amplitude steps, then the (i-1)th error accumulation value is updated to the (i-1)th summation result; the step size flag in the step size flag register is updated to a long step, wherein the step size type of the (i+1)th amplitude step is the long step indicated by the step size flag.

[0065] In S330-3, in response to detecting that the i-th step trigger pulse is valid, the output amplitude and step direction of the i-th amplitude step are updated according to the flip threshold, amplitude threshold, step direction of the i-th amplitude step, and output amplitude of the i-th amplitude step (i.e., output amplitude value of the i-th amplitude step); where, when i=1, the step direction of the i-th amplitude step is the initial direction, and the output amplitude of the i-th amplitude step is the initial amplitude; when i is a positive integer greater than 1, the step direction of the i-th amplitude step is the step direction of the (i-1)-th amplitude step, and the output amplitude of the i-th amplitude step is the output amplitude of the (i-1)-th amplitude step.

[0066] It should be understood that after the system performs the i-th iteration, the output of the i-th iteration includes: the updated output amplitude of the i-th amplitude step obtained by performing the above S330-3, and the updated step direction of the i-th amplitude step.

[0067] In some implementations, the flip threshold is equal to the difference between the peak amplitude of the triangular wave and 1, and the amplitude threshold is the peak amplitude of the triangular wave; and, based on the flip threshold, amplitude threshold, step direction of the i-th amplitude step, and output amplitude of the i-th amplitude step, the output amplitude and step direction of the i-th amplitude step are updated, including: when the step direction of the i-th amplitude step is a downward direction and the output amplitude of the i-th amplitude step is less than or equal to the negative of the flip threshold, the step direction of the i-th amplitude step is updated to an upward direction; when the step direction of the i-th amplitude step is an upward direction and the output amplitude of the i-th amplitude step is greater than or equal to the flip threshold, the step direction of the i-th amplitude step is updated to a downward direction; when the step direction of the i-th amplitude step is a downward direction and the output amplitude of the i-th amplitude step is greater than the negative of the amplitude threshold, the output amplitude of the i-th amplitude step is decremented by 1; when the step direction of the i-th amplitude step is an upward direction and the output amplitude of the i-th amplitude step is greater than or equal to the flip threshold, the output amplitude of the i-th amplitude step is incremented by 1.

[0068] In some implementations, the stopping condition for at least one round of iterative processing is that the enable signal is low or the device exits the operation phase.

[0069] It should be understood that a triangular wave is also called a triangular wave signal, and this application does not limit it.

[0070] It should be noted that the working principle of S310 described above is the same as that described below. Figure 5 The working principle of S502 is the same as that of S320 mentioned above; the working principle of S320 mentioned above is the same as that of S502 mentioned below. Figure 5 The working principles of S505 and S506 are the same; the working principle of S330 mentioned above is the same as that described below. Figure 5 The operating principles of the shown operational phases (i.e., S507 to S519) are the same; for the sake of brevity, details not elaborated here will be provided below. Figure 5 The description of the relevant steps in the provided triangular wave signal generation method.

[0071] It should be understood that Figure 3 The illustrated method for generating triangular wave signals is merely illustrative and does not constitute any limitation on the triangular wave signal generation method provided in the embodiments of this application. For example, the above... Figure 3 The illustrated method for generating a triangular wave signal may also include steps other than S310 to S330; for details, please refer to [link to relevant documentation]. Figure 5 The method for generating the triangular wave signal provided will not be elaborated here for the sake of simplicity.

[0072] In this embodiment, the non-integer problem of "the number of clock cycles to wait for each amplitude step" required to generate a triangular wave is transformed into an integer remainder allocation problem in the Bresenham linear algorithm (referred to as the Bresenham algorithm). Specifically, a 16-bit integer error accumulator is used to track and accumulate the remainders, dynamically determining whether the current amplitude step (i.e., the i-th amplitude step) continues with "the base clock number" (i.e., a short step) or "the base clock number + 1" (i.e., a long step). This achieves optimal uniform allocation in the integer domain, while simultaneously enabling zero-overhead preset of arbitrary phase offsets through piecewise mapping. This application can improve the frequency accuracy of multi-channel triangular wave signals, ensure a fixed phase difference between multiple triangular wave signals, and has low hardware resource requirements. It is applicable to scenarios such as PWM carrier generation in power electronic converters and carrier phase shifting in multi-channel interleaved control systems.

[0073] Example 2 For example, Figure 5 This is a schematic diagram of another triangular wave signal generation method provided in an embodiment of this application. The triangular wave signal generation method provided in this embodiment can be applied to... Figure 1 The triangular wave signal generating device 100 shown, such as the system described below, can be, but is not limited to, [a system that generates triangular waves]. Figure 1The triangular wave signal generating device 100 is shown below. The following is a description of... Figure 5 The steps shown are described in detail below: In S501, the system can be automatically reset upon power-on or manually reset externally.

[0074] The purpose of executing S501 is to reset the system by clearing the values ​​of all registers in the system. This can be done by setting the system to automatically reset upon power-on, or by manually resetting the system during operation (e.g., by pressing a button or using the chip's reset pin) during system operation (e.g., when a system malfunction occurs).

[0075] The system's registers include: an in-step counter (used to store the accumulated clock count of the current Bresenham step, continuously timing across cycles), and a 16-bit error accumulator (used to store the Bresenham iteration remainder). The value is updated only when step_trigger=1, and the error state is maintained for multiple cycles. It is used to allocate long steps or short steps. The step size flag register is used to store the threshold for whether to use long steps or short steps in the next round of counting. ), Direction register (used to store the current waveform rise and fall direction dir), waveform output register (used to store the final waveform amplitude value data_out), phase offset synchronization register (phase_offset_reg), enable delay register (used to delay the stored enable signal output_en by 1 system clock cycle to generate a single clock width rising edge pulse output_en_d1).

[0076] In S502, during the compilation phase: the compile-time module adjusts according to the system clock frequency. Triangular wave output frequency Triangular wave peak amplitude and the total amplitude steps per waveform period Determine the initial value of the baseline error in the Bresenham algorithm. Bresenham molecule and Bresenham denominator .

[0077] The compile-time module executes S502 above, that is, during system compilation, the compile-time module performs the following mapping operation: The total number of clock cycles (i.e., the total number of clock beats) corresponding to each waveform period. The total number of amplitude steps per waveform period (i.e., the total number of amplitude steps). The integer part of the quotient is mapped to the initial value of the baseline error in the Bresenham algorithm. ,in, System clock frequency With the triangular wave output frequency The integer part of the quotient; the total amplitude steps per waveform period. Equal to the peak amplitude of the triangular wave Q times, where Q is a positive integer greater than 1; The total amplitude steps for each waveform period (i.e., amplified by Q times the peak amplitude of the triangular wave) ), mapped to the Bresenham denominator in the Bresenham algorithm. ; and, the total number of clock cycles corresponding to each waveform period. ,and and The difference of the products is mapped to the Bresenham numerator in the Bresenham algorithm. .

[0078] The total number of clock cycles corresponding to each waveform period mentioned above Also known as the total system clock count per single waveform period, it refers to the total number of system clock cycles required to output a complete triangular waveform.

[0079] The total amplitude steps for each waveform period mentioned above This represents the total number of ±1 amplitude changes in `data_out` within a complete triangular wave cycle, i.e., the total number of times `step_trigger=1` (each trigger changes the amplitude by 1 unit) will occur during one round of rising and falling. It also represents the total number of amplitude steps per waveform cycle. Equal to the peak amplitude of the triangular wave 4 times.

[0080] The initial value of the reference error obtained by the above mapping , is the base clock cycle number per amplitude step, i.e., the short step duration in a triangular wave signal. The total number of short steps in a triangular wave signal is equal to the total number of amplitude steps per waveform period. Compared with the total number of long steps in the triangular wave signal (i.e. The difference between the two values. Wherein, the initial value of the reference error is... It can be stored in a 16-bit error accumulator.

[0081] The Bresenham molecule obtained from the above mapping , is the total number of long steps in the triangular wave signal. The duration of the long steps in the triangular wave signal is equal to the duration of the short steps (i.e., ...). Add 1, meaning the long step duration is maintained for one more clock cycle than the short step duration.

[0082] In the above implementation, since the total number of clock cycles corresponding to each waveform period is... When dividing the remainder equally among all steps, a remainder that is not divisible will occur. Therefore, a long and short step approach is introduced to distribute the remainder, ensuring that the total clock of a complete waveform cycle is strictly equal to the remainder. Based on this setting, frequency jitter can be eliminated. Furthermore, since the error accumulation recursive formula of the Bresenham algorithm depends on the denominator (Bresenham denominator),... Therefore, the above implementation method involves setting the total amplitude step number for each waveform period to perform remainder allocation. (i.e., amplified by Q times the peak amplitude of the triangular wave) ), mapped to the Bresenham denominator in the Bresenham algorithm. It can improve waveform amplitude resolution and simultaneously amplify the number of steps.

[0083] For example, the above , and They can be expressed by the following formulas respectively:

[0084] In the above formula, This indicates rounding down to the nearest integer. This represents the total number of clock cycles corresponding to each waveform period, and is a dimensionless positive integer. It should be understood that... , and It is a dimensionless positive integer. Dimensionless, and .

[0085] The above This can be expressed by the following formula:

[0086] In the above formula, This indicates rounding down to the nearest integer. and The value of can be a positive integer. And the unit can be Hz.

[0087] In the above formula This can be expressed by the following formula:

[0088] In the above formula, It is a dimensionless integer greater than 0.

[0089] For example, with , , Taking 512 as an example, then = =100000; = =195, meaning the short step duration is 195 clock cycles, and the number of short steps = =512-160=352; 100000-195 512 = 160 long steps, each lasting 195 + 1 = 196 clock cycles. In this example, all short steps are evenly distributed across 512. 195 = 99840 clock cycles. 99840 clock cycles is 160 clock cycles less than the total of 100000 clock cycles. Therefore, by adding 1 to each of the 160 short steps to fill in the remainder (160 clock cycles), the total number of clock cycles for a complete waveform round is precisely matched (equal to...). This will prevent the frequency jitter problem of inconsistent cycle length.

[0090] In this embodiment of the application, the above-mentioned initial value of the reference error Bresenham molecule , Bresenham denominator and the total amplitude steps per waveform period It is a set of fixed constants, namely the initial values ​​of the aforementioned reference error. Bresenham molecule , Bresenham denominator and the total amplitude steps per waveform period All of these exist in the form of register constants. Therefore, during system operation, this set of fixed constants existing in the form of register constants can be directly called, thus initializing the reference error. Bresenham molecule , Bresenham denominator and the total amplitude steps per waveform period None of them consume computing resources during any runtime phase (e.g., there are no real-time multiplication, division, or rounding operations during system runtime).

[0091] In S503, it is determined whether a rising edge of the enable signal has been detected.

[0092] Execute the above S503, that is, determine whether the instant when the value of the enable signal (symbol denoted as output_en) is updated from 0 to 1 is detected.

[0093] After executing S503 above, if a rising edge of the enable signal is detected, then continue executing S505, which corresponds to... Figure 5 Case 1: If no rising edge of the enable signal is detected, then S504 continues to be executed, i.e., corresponding to... Figure 5 Case 2. In this case, the absence of a rising edge of the enable signal should be interpreted as the enable signal being detected as 0 (i.e., low level).

[0094] In S504, the waveform output module outputs a waveform amplitude of 0 and clears the waveform output service register.

[0095] Executing S504 above, when the detected enable signal is 0 (i.e., low level), the waveform output module outputs a waveform amplitude of 0, meaning the waveform output module stops generating the triangular wave. Simultaneously, the waveform output service register also needs to be cleared. It should be understood that the waveform output service register refers to the register related to the service status of waveform generation. The waveform output service register includes: waveform output register (data_out), in-step counter (cnt), 16-bit error accumulator, and step size flag register (…). ) and direction register (dir).

[0096] In the above implementation, when the enable signal is low, only the waveform output service register is cleared, and the synchronization timing register (i.e., the enable delay register and the phase bias synchronization register) are not cleared. In this way, when the rising edge of the enable signal is detected again, the segmented mapping logic can directly read the initial direction and initial amplitude value (i.e., the initial amplitude) after stable synchronization without additional waiting, and the phase switching is without delay. In addition, since the enable delay register always saves the actual level of the enable signal of the previous clock cycle, the rising edge can be accurately identified at any time.

[0097] It should be understood that after executing S504, it is possible to return to executing S503 again.

[0098] In the S505, the enable rising edge detection module delays the enable signal output_en by one clock cycle to generate a single-clock-cycle pulse signal output_en_pos=1.

[0099] Executing S505 above, that is, when a rising edge of the enable signal is detected, the enable rising edge detection module delays the enable signal output_en by one clock cycle, generating a single-clock-cycle pulse signal output_en_pos=1 (i.e., high level). In other words, output_en_pos=1 only after executing S505 in the current clock cycle when output_en=1 and output_en=0 in the previous clock cycle, and output_en_pos=1 will only be maintained for one system clock cycle, immediately returning to 0 in the next clock cycle.

[0100] For example, the above enable signal could be Figure 3 The enable signal in the provided method, the aforementioned single-clock-cycle pulse signal can be... Figure 3 The first pulse signal in the provided method.

[0101] In S506, a global synchronization initialization operation is triggered in response to the detection of a single clock cycle pulse signal output_en_pos=1.

[0102] Executing S506 above, that is, executing S503 and S505 in sequence, yields a single clock pulse output_en_pos by delaying the enable signal with a rising edge by one clock cycle. This pulse only takes effect on the first clock cycle after the enable signal output_en is turned on, requiring only one global synchronization initialization operation. This avoids repeated execution of the global synchronization initialization operation due to output_en being high for a long time, which helps to further reduce the system's computational overhead.

[0103] The global synchronization initialization operation can include the following operations: Clear the 16-bit error accumulator (symbolized as bres_acc); Clear the in-step counter (denoted as cnt); The received 32-bit signed phase bias input is synchronized by a first-stage pipelined register and then compared in segments (based on the peak amplitude of the triangular wave). (as the dividing point), mapping the bias value to the initial amplitude value. and initial direction ; Set the value of the direction register to the initial direction. ;as well as, Set the value of the waveform output register (denoted as data_out) as the initial amplitude value. .

[0104] Among them, the phase offset segmented mapping (i.e., the above-mentioned segmented comparison (based on the peak amplitude of the triangular wave) (as the dividing point), mapping the bias value to the initial amplitude value. and initial direction This can be expressed by the following formula: when When (i.e., the phase bias is within the rising phase range), (Upward direction); when When (i.e., the phase bias is within the rising phase range), (Descending direction).

[0105] In the above formula, This indicates a 32-bit signed phase bias, which is dimensionless and ; Dimensionless; The value can be 0 or 1.

[0106] In the aforementioned global synchronization initialization operation, the received 32-bit signed phase bias input is synchronized by a first-stage pipelined register and then compared in segments (based on the peak amplitude of the triangular wave). (as the dividing point), mapping the bias value to the initial amplitude value. and initial direction marker The external 32-bit phase bias first passes through a primary register to synchronously eliminate asynchronous glitches. Then, segmented interval comparisons and simple addition and subtraction conversions are performed with the peak amplitude A as the boundary. This process does not use a multiplier. Finally, the initial amplitude value and initial direction for waveform startup are output. The initial amplitude value and initial direction are synchronously loaded at the moment of enable, realizing arbitrary phase startup of the triangular wave.

[0107] In the above implementation, since it is triggered by the rising edge of the same clock control signal (i.e., output_en_pos), the initialization of all status registers (i.e., the assignment of values ​​to the 16-bit error accumulator, in-step counter, direction register, and waveform output register) is completed atomically within one clock cycle, ensuring that the phase difference between multiple triangular wave instances is strictly equal to the difference of their respective preset offsets, with an accuracy of 0 clock cycles, thus achieving the purpose of multi-channel phase synchronization preset.

[0108] For example, the above It can be the above Figure 3 The first phase signal in the provided method.

[0109] It should be understood that after executing S506 above, the following steps will continue. Figure 5 The diagram shows steps S507 to S519, which represent the steady-state operation phase. This phase is a cyclical (iterative) steady-state triangular wave signal generation process. The generation of the triangular wave signal can be performed repeatedly from S507 to S519 until the cycle termination condition is met, at which point the triangular wave signal generation process stops, resulting in the final output triangular wave signal. Steps S507 to S519 will be further described below. It should be understood that S507 to S519 constitute one cycle (i.e., one iteration, as described above). Figure 3 (The flow of the i-th iteration processing in the provided method).

[0110] In S507, within the current amplitude step, the value of the step counter is incremented by 1.

[0111] The in-step counter (cnt) is used to record the total number of system clock cycles for the current amplitude step (i.e., each amplitude step corresponding to each loop process). In other words, the in-step counter is used to record the number of system clock cycles that the current amplitude step has been waiting for.

[0112] Executing S507 above means that within the current amplitude step, the value of the in-step counter (cnt) will be incremented by 1 when each rising edge of the system clock arrives.

[0113] For example, the current amplitude step mentioned above could be the above. Figure 3 The i-th amplitude step in the provided method.

[0114] In S508, the current amplitude step timer is determined based on the value of the step trigger signal (step_trigger). The value of the step trigger signal is determined by comparing the threshold value with the value of the in-step counter.

[0115] In some implementations, the step size flag (symbolized as...) The value equals 1 (meaning the current amplitude step is a long step), and the comparison threshold is the long step threshold. Execute the above S508, and determine whether the current amplitude step timing is completed based on the value of the step trigger signal (step_trigger). For example, this may include the following steps: if the value of the in-step counter is greater than or equal to the long step threshold ( If the step trigger signal (step_trigger) is set to 1, then the current amplitude step timer is determined to be complete, and S509 is executed again; if the value of the in-step counter is less than the long step threshold ( If the step trigger signal (step_trigger) is set to 0, then the value of the step trigger signal (step_trigger) is set to 0. In response to the detection that the value of the step trigger signal (step_trigger) is 0, it is determined that the current amplitude step is not completed, and then the execution of S507 is returned.

[0116] In other implementations, the step size flag (symbolized as...) The value equals 0 (meaning the current amplitude step is a short step), and the comparison threshold is the short step threshold. -1), execute the above S508, and determine whether the current amplitude step timing is completed based on the value of the step trigger signal (step_trigger). For example, this may include the following steps: if the value of the in-step counter is greater than or equal to the short step threshold ( If the value of the step trigger signal (step_trigger) is less than 1, then the value of the step trigger signal (step_trigger) is set to 1; in response to the detection that the value of the step trigger signal (step_trigger) is equal to 1, it is determined that the current amplitude step is completed, and then S509 continues to be executed; if the value of the in-step counter is less than the short step threshold ( If -1), the value of the step trigger signal (step_trigger) is equal to 0; in response to the detection that the value of the step trigger signal (step_trigger) is equal to 0, it is determined that the current amplitude step time is not completed, and then the execution returns to S507.

[0117] In the above implementation, when the in-step counter has not yet reached the target, the step trigger signal (step_trigger) is set to 0, and the output triangular wave signal remains unchanged, only the in-step counter is incremented. When the in-step counter has reached the target, the step trigger signal (step_trigger) is set to 1, thereby triggering the update of the Bresenham algorithm parameters (i.e., the 16-bit error accumulator and step size flag), the waveform direction of the triangular wave signal, and the output amplitude of the triangular wave signal, as described below. At the same time, the in-step counter is reset to start the next round of timing.

[0118] For example, the aforementioned step trigger signal can be the aforementioned Figure 3 The i-th step trigger signal in the provided method.

[0119] In S509, in response to the detection that the step trigger signal (step_trigger) is equal to 1, the value of the 16-bit error accumulator is updated according to the Bresenham algorithm rules, the step size flag is updated, and the value of the in-step counter is cleared to zero.

[0120] Executing S509 above means that the clock count of the current amplitude step (e.g., long step or short step) has reached the comparison threshold (e.g., long step threshold or short step threshold), and the waiting period ends, allowing a complete waveform step update to be performed. Therefore, it is necessary to update the 16-bit error accumulator and the step size flag (i.e. the step size flag for the next round).

[0121] In this embodiment, the value of the 16-bit error accumulator (i.e., the accumulated error value) is updated according to the Bresenham algorithm. ), and update the step size flag, which may include the following steps: like Then Updated to And update the step size flag to long step (i.e., ); like Then Updated to And update the step size flag to short step (i.e., );in, The accumulated error value is stored in the 16-bit error accumulator. Dimensionless, and .

[0122] In the above methods, This can be understood as, for Take the modulo operation and retain the remainder after overflow.

[0123] like Then Updated to And update the step size flag to long step (i.e., This can be understood as follows: if the accumulated error value plus the increment is greater than or equal to the total step denominator, there is an overflow. Therefore, the next round of in-step counting uses the long step threshold (the number of clock beats per step equals (...)). +1 beat, one more beat than the short step, used to distribute the remainder).

[0124] like Then Updated to And update the step size flag to short step (i.e., This can be understood as follows: the accumulated error value plus the increment is less than the total step denominator, there is no overflow, the error is fully preserved, and the next round of in-step counting uses the short-step threshold (the number of clock beats per step equals the number of basic beats). shoot).

[0125] In the above implementation, by employing the Bresenham remainder allocation mechanism, it is possible to guarantee... A long step and The short steps alternate evenly within a complete triangular wave cycle, the duration difference between any two adjacent amplitude steps does not exceed one clock cycle, and the long steps are distributed as evenly as possible.

[0126] For example, the 16-bit error accumulator mentioned above can be the one described above. Figure 3 The error accumulator in the provided method, the value of the aforementioned 16-bit error accumulator (i.e., the accumulated error value) ) can be Figure 3 The i-th accumulated error value in the provided method, as mentioned above ( )for Figure 3 The step size flag in the (i-1)th summation result provided in the method can be... Figure 3 The step size flag is stored in the step size flag register in the provided method.

[0127] In S510, in response to detecting that the step trigger signal (step_trigger) is equal to 1, it is determined whether the direction of the current amplitude step is downward and whether the waveform output amplitude ( () less than or equal to the flip threshold #1.

[0128] The flip threshold #1 is the flip threshold corresponding to the downward direction of the amplitude step (i.e., the step direction of the amplitude step). The value of the flip threshold #1 is equal to -(A-1). Wherein, the flip threshold #1 and the stop threshold #1 (i.e., the peak amplitude of the triangular wave in the downward direction -A-1) are equal. The 1-unit margin between the boundary conditions can prevent boundary race conditions.

[0129] For example, the aforementioned flip threshold #1 could be the above Figure 3A specific example of the flip threshold in the provided method.

[0130] In some implementations, when the process of the running phase shown in S507 to S519 executed by the system is the first process executed by the system after power-on or reset, the direction of the current amplitude step in S510 is the initial direction in S502 (i.e., the direction shown in S502). Figure 3 The initial direction in the provided method), and the waveform output amplitude in 510 is the initial amplitude value in S502 (i.e., the above). Figure 3 (Initial amplitude in the provided method).

[0131] In some implementations, when the system executes the operation phase shown in S507 to S519, which is the second or subsequent execution of the process after power-on or reset, the direction of the current amplitude step in S510 is the direction corresponding to the waveform output amplitude after the system executed S507 to S519 in the previous round (i.e., the direction shown in S510). Figure 3 The step direction of the (i-1)th amplitude step in the provided method), and the waveform output amplitude in 510 above is the waveform output amplitude output by the system after executing S507 to S519 in the previous round (i.e., the above). Figure 3 The output amplitude of the (i-1)th amplitude step in the provided method.

[0132] In this embodiment of the application, when the value of the direction register (i.e. When the value equals 1, it can be understood that the direction of the current amplitude step is downward. In this method, S510 is executed, which determines whether the conditions shown in the following formula are met: and

[0133] After executing S510, if it is determined that the direction of the current amplitude step is downward and the waveform output amplitude is less than or equal to the flip threshold #1, then continue executing S511; if it is determined that the direction of the current amplitude step is not downward and the waveform output amplitude is less than or equal to the flip threshold #1, then continue executing S512. The condition that S512 continues even when the current amplitude step is not satisfied can be understood as: if the direction of the current amplitude step is upward, then continue executing S512.

[0134] The above implementation does not require multiplication and division operations. It only requires calling the corresponding parameter values ​​obtained at compile time and performing comparison operations on the corresponding parameter values. It is simple to implement and can reduce the computational overhead and improve the processing efficiency during the runtime phase.

[0135] In this embodiment, the execution order of S510 and S509 is not limited. For example, S510 can be executed first, followed by S509.

[0136] In S511, the direction of the current amplitude step is updated to the upward direction.

[0137] Execute the above S511, that is, when the direction of the current amplitude step is downward and the current triangular wave amplitude has reached the negative flip threshold (i.e., flip threshold #1), the direction of the current amplitude step needs to be updated to the upward direction.

[0138] In this embodiment of the application, updating the direction of the current amplitude step to the upward direction is, for example, including: updating the value of the direction register to 0, so as to update the direction of the current amplitude step to the upward direction.

[0139] In S512, it is determined whether the current amplitude step direction is upward and whether the waveform output amplitude is greater than or equal to the flip threshold #2.

[0140] Flip threshold #2 is the flip threshold corresponding to an upward amplitude step. The value of flip threshold #2 is equal to... Among them, the flip threshold #2 and the stop threshold #2 (i.e., the peak amplitude of the triangular wave in the upward direction) The 1-unit margin between the boundary conditions can prevent boundary race conditions.

[0141] For example, the aforementioned flip threshold #2 could be the above Figure 3 A specific example of the flip threshold in the provided method.

[0142] In some implementations, when the process of the running phase shown in S507 to S519 executed by the system is the process executed for the first time after the system is powered on or reset, the direction of the current amplitude step in S512 is the initial direction in S502, and the waveform output amplitude in S512 is the initial amplitude value in S502.

[0143] In some implementations, when the system executes the operation phase shown in S507 to S519, which is the second or subsequent execution of the process after power-on or reset, the direction of the current amplitude step in S512 is the direction corresponding to the waveform output amplitude after the system executed S507 to S519 in the previous round (i.e., the direction shown in S512). Figure 3 The step direction of the (i-1)th amplitude step in the provided method), and the waveform output amplitude in S512 above is the waveform output amplitude output by the system after executing S507 to S519 in the previous round (i.e., the above). Figure 3 The output amplitude of the (i-1)th amplitude step in the provided method.

[0144] In this embodiment, when the value of the direction register is equal to 0, it can be understood that the direction of the current amplitude step is upward. In this method, S510 is executed, that is, it is determined whether the condition shown in the following formula is met: and

[0145] After executing S512, if it is determined that the direction of the current amplitude step is the upward direction and the waveform output amplitude is greater than the flip threshold #2, then continue to execute S513; if it is determined that the direction of the current amplitude step is not the upward direction and the waveform output amplitude is less than or equal to the flip threshold #2, then continue to execute S514.

[0146] If the following conditions are not met, S514 will continue to be executed. This can be understood as continuing to execute S514 when the direction register is 0 and the waveform output amplitude is greater than the flip threshold #2.

[0147] In this embodiment, the execution order of S510 and S512 is not limited. For example, S512 can be executed first, followed by S510.

[0148] In S513, the direction of the current amplitude step is updated to the downward direction.

[0149] Execute the above S513, that is, when the direction of the current amplitude step is upward and the current triangular wave amplitude has reached the positive flip threshold (i.e., flip threshold #2), the direction of the current amplitude step needs to be updated to the downward direction.

[0150] In this embodiment of the application, updating the direction of the current amplitude step to the downward direction is, for example, including: updating the value of the direction register to 1, so as to update the direction of the current amplitude step to the downward direction.

[0151] It should be understood that the flip threshold #2 and the flip threshold #1 are opposites of each other.

[0152] In S514, the direction of the current amplitude step is not updated.

[0153] Executing S514 above means that if the direction of the current amplitude step is either upward or downward, and the current triangular wave amplitude has reached the flip threshold, there is no need to modify the value of the direction register, and the direction of the current amplitude step remains unchanged.

[0154] In S515, it is determined whether the current amplitude step direction is downward and whether the waveform output amplitude is greater than the limit threshold #1 (i.e., - ).

[0155] It should be understood that the direction of the current amplitude step in S515 above is the step direction of the current amplitude obtained after executing S511, S513 or S514 above.

[0156] In some implementations, when the process of the operation phase shown in S507 to S519 executed by the system is the first process executed by the system after power-on or reset, the waveform output amplitude in S515 is the initial amplitude value in S502.

[0157] In some implementations, when the process of the running phase shown in S507 to S519 executed by the system is the process executed for the second or more times after the system is powered on or reset, the waveform output amplitude in S515 is the waveform output amplitude output by the system after the previous round of execution of S507 to S519.

[0158] In this embodiment, when the value of the direction register is equal to 1, it means that the direction of the current amplitude step is downward. Therefore, S515 is executed, that is, it is determined whether the following condition is met: and .

[0159] After executing S515 above, if it is determined that the direction of the current amplitude step is downward and the waveform output amplitude is greater than the limit threshold #1, then continue to execute S516; if it is determined that the current amplitude step is not downward and the waveform output amplitude is greater than the limit threshold #1, then continue to execute S517.

[0160] For example, the aforementioned limit threshold #1 could be the above Figure 3 A specific example of the amplitude threshold in the provided method.

[0161] In S516, the waveform output amplitude is reduced by 1.

[0162] Executing S516 above will subtract 1 from the waveform output amplitude of the previous amplitude step (i.e., the waveform output amplitude after executing S507 to S519 in the previous round) to obtain the waveform output amplitude of the current amplitude step.

[0163] The above implementation does not require multiplication and division operations. It only requires calling the corresponding parameter values ​​obtained at compile time and performing subtraction operations on the corresponding parameter values. It is simple to implement and can reduce the computational overhead and improve the processing efficiency during the runtime phase.

[0164] In S517, it is determined whether the current amplitude step direction is upward and whether the waveform output amplitude is less than the limit threshold #2 (i.e., ).

[0165] It should be understood that the direction of the current amplitude step in S517 above is the step direction obtained after executing S511, S513 or S514 above. That is, the direction of the current amplitude step in S517 above is the same as the direction of the current amplitude step in S515 above.

[0166] In some implementations, when the process of the operation phase shown in S507 to S519 executed by the system is the first process executed by the system after power-on or reset, the waveform output amplitude in 517 is the initial amplitude value in S502.

[0167] In some implementations, when the process of the running phase shown in S507 to S519 executed by the system is the process executed for the second or more times after the system is powered on or reset, the waveform output amplitude in S517 is the waveform output amplitude output by the system after the previous round of execution of S507 to S519.

[0168] It should be understood that the waveform output amplitude in S517 above is the same as the waveform output amplitude in S515 above.

[0169] In this embodiment, when the value of the direction register is equal to 0, the direction of the current amplitude step is upward. Therefore, S517 is executed, that is, it is determined whether the following condition is met: and .

[0170] After executing S517 above, if it is determined that the direction of the current amplitude step is upward and the waveform output amplitude is less than the limit threshold #2, then continue to execute S518; if it is determined that the following conditions are not met: the direction of the current amplitude step is upward and the waveform output amplitude is less than the limit threshold #2, then continue to execute S519.

[0171] If it is determined that the following conditions are not met: the direction of the current amplitude step is upward, and the waveform output amplitude is less than the limit threshold #2, then S519 continues to be executed, including: If it is determined that the direction of the current amplitude step is upward and the waveform output amplitude is greater than or equal to the limit threshold #2, then continue to execute S519. That is, if the waveform output amplitude is greater than or equal to the limit threshold #2 when the direction of the current amplitude step is upward, then keep the waveform output amplitude unchanged. If it is determined that the current amplitude step direction is downward and the waveform output amplitude is less than or equal to the limit threshold #1, then continue to execute S519. That is, if the current amplitude step direction is downward and the waveform output amplitude is less than or equal to the limit threshold #1, then keep the waveform output amplitude unchanged.

[0172] For example, the aforementioned limit threshold #2 could be the above Figure 3 A specific example of the amplitude threshold in the provided method.

[0173] The above implementation does not require multiplication and division operations. It only requires calling the corresponding parameter values ​​obtained at compile time and performing comparison operations on the corresponding parameter values. It is simple to implement and can reduce the computational overhead and improve the processing efficiency during the runtime phase.

[0174] It should be understood that the limit threshold #2 and the limit threshold #1 are opposites of each other.

[0175] In S518, the waveform output amplitude is incremented by 1.

[0176] In S519, the current waveform output amplitude remains unchanged.

[0177] Executing S519 as described above, for example, includes: if the current amplitude step direction is upward, and the waveform output amplitude is equal to the limit threshold #2, then the waveform output amplitude value remains unchanged, that is, the waveform output amplitude output by the waveform output module is equal to the limit threshold #2; if the current amplitude step direction is downward, and the waveform output amplitude is equal to the limit threshold #1, then the waveform output module keeps the value unchanged, that is, the waveform output amplitude output by the waveform output module is equal to the limit threshold #1.

[0178] In the above implementation, by setting limit thresholds (i.e., limit threshold #2 and limit threshold #1), it is possible to prevent the waveform output amplitude of the waveform output module from exceeding the set peak value and avoid waveform output amplitude overflow.

[0179] It should be understood that the waveform output amplitude values ​​in S517 to S519 above can be the above... Figure 3 The output amplitude of the i-th amplitude step.

[0180] It should be understood that since S507 to S519 constitute a cyclic process (i.e., an iterative process), the system will stop executing this cyclic process when the cyclic stopping condition (i.e., the iteration stopping condition) is met. The cyclic stopping condition is not limited and can be set according to the actual situation. For example, the cyclic stopping condition can be, but is not limited to, the enable signal being low, or the system exiting the running phase, etc.

[0181] It should be understood that Figure 5The methods shown are for illustrative purposes only and do not constitute any limitation on the methods provided in the embodiments of this application. For example, in the above text, a value of 1 in the direction register indicates that the direction of the current amplitude step is downward; and a value of 0 in the direction register indicates that the direction of the current amplitude step is upward. Optionally, it can also be replaced by the following scheme: a value of 0 in the direction register indicates that the direction of the current amplitude step is downward; and a value of 1 in the direction register indicates that the direction of the current amplitude step is upward.

[0182] It should be understood that the above Figures 1 to 5 This is for illustrative purposes only and is not intended to limit the embodiments of this application to the examples shown in the figures. In fact, those skilled in the art can understand this based on... Figures 1 to 5 The examples in the document can be transformed into equivalent ways to obtain more implementations.

[0183] According to the method provided in the embodiments of this application, this application also provides a chip, which includes one or more processors for calling and executing instructions stored in memory, thereby causing the method described in the embodiments of this application to be executed. This chip system may be composed of a chip, or it may include chips and other discrete devices.

[0184] The chip system may include input circuits or interfaces for transmitting information or data, and output circuits or interfaces for receiving information or data.

[0185] According to the method provided in the embodiments of this application, this application also provides a computer program product, which includes: computer program code, which, when run on a computer, causes the computer to execute the triangular wave signal generation method in any of the foregoing method embodiments.

[0186] According to the method provided in the embodiments of this application, this application also provides a computer-readable storage medium storing program code, which, when run on a computer, causes the computer to execute the triangular wave signal generation method in any of the foregoing method embodiments.

[0187] The computer-readable storage medium may be the aforementioned volatile memory or non-volatile memory, or it may include both volatile memory and non-volatile memory.

[0188] In the embodiments of this application, the terms and English abbreviations are exemplary examples given for ease of description and should not be construed as limiting the application in any way. This application does not preclude the possibility of defining other terms that can achieve the same or similar functions in existing or future agreements.

[0189] In the above embodiments, implementation can be achieved, in whole or in part, through software, hardware, firmware, or any combination thereof. When implemented in software, it can be implemented, in whole or in part, as a computer program product. The computer program product includes one or more computer instructions. When these computer instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of this application are generated.

[0190] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0191] It should be understood that in the various embodiments of this application, the sequence number of each process does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0192] In summary, the above description is merely a preferred embodiment of the technical solution of this application and is not intended to limit the scope of protection of this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A method for generating a triangular wave signal, characterized in that, A triangular wave signal generating device used to generate system clock and enable signals includes: During the compilation phase, compilation parameters are determined, including the total number of clock beats, the total number of amplitude steps, the short step duration, and the number of long steps. The total number of clock beats is determined based on the triangular wave output frequency and the system clock frequency. The total number of amplitude steps is determined based on the peak amplitude of the triangular wave. The short step duration is equal to the integer part of the quotient of the total number of clock beats and the total number of amplitude steps. The number of long steps is equal to the difference between the total number of clock beats and the product of the short step duration and the total number of amplitude steps. In response to the detection of the rising edge of the enable signal, an initialization operation is performed, wherein the initialization operation includes: clearing the in-step counter and the error accumulator to zero, and mapping the first phase signal based on a preset segmented mapping rule to obtain an initial amplitude and an initial direction; the first phase signal is a signal obtained based on a phase bias signal and synchronized with the system clock; During the operation phase, at least one round of iterative processing is performed to generate a triangular wave signal, wherein the i-th round of iterative processing in the at least one round of iterative processing includes: The validity of the i-th step trigger pulse is determined based on the comparison threshold and the total number of system clocks corresponding to the i-th amplitude step stored in the in-step counter, wherein the in-step counter is used to increment by 1 for each system clock step within the i-th amplitude step; the comparison threshold is determined based on the i-th amplitude step and the short step duration; i is a positive integer; In response to the detection that the i-th step trigger pulse is valid, based on the Bresenham algorithm rules, the error accumulator and the step size flag register are updated, and the in-step counter is cleared. The updated error accumulator stores the i-th accumulated error value, and the updated step size flag register stores the step size type of the (i+1)-th amplitude step. When i=1, the i-th accumulated error value is equal to 0. When i is a positive integer greater than 1, the i-th accumulated error value is determined based on the (i-1)-th accumulated error value and the number of long steps. In response to the detection that the i-th step trigger pulse is valid, the output amplitude and the step direction of the i-th amplitude step are updated according to the flip threshold, the amplitude threshold, the step direction of the i-th amplitude step, and the output amplitude of the i-th amplitude step; wherein, when i=1, the step direction of the i-th amplitude step is the initial direction, and the output amplitude of the i-th amplitude step is the initial amplitude; when i is a positive integer greater than 1, the step direction of the i-th amplitude step is the step direction of the (i-1)-th amplitude step, and the output amplitude of the i-th amplitude step is the output amplitude of the (i-1)-th amplitude step.

2. The method according to claim 1, characterized in that, i is a positive integer greater than 1, and the (i-1)th summation result is the sum of the (i-1)th error accumulation value in the error accumulator and the number of long steps; and, in response to detecting that the i-th step trigger pulse is valid, updating the error accumulator and the step size flag register based on the Bresenham algorithm rules includes: If the (i-1)th summation result is greater than or equal to the total number of amplitude steps, then the (i-1)th error accumulation value is updated to the difference between the (i-1)th error accumulation value and the total number of amplitude steps; the step size flag in the step size flag register is updated to a short step, wherein the step size type of the (i+1)th amplitude step is the short step indicated by the step size flag. If the (i-1)th summation result is less than the total number of amplitude steps, then the (i-1)th error accumulation value is updated to the (i-1)th summation result; the step size flag in the step size flag register is updated to long step, wherein the step size type of the (i+1)th amplitude step is the long step indicated by the step size flag.

3. The method according to claim 1 or 2, characterized in that, The flip threshold is equal to the difference between the peak amplitude of the triangular wave and 1, and the amplitude threshold is the peak amplitude of the triangular wave; and the stepping of the i-th amplitude step and the stepping of the i-th amplitude step are updated based on the flip threshold, the amplitude threshold, the stepping direction of the i-th amplitude step, and the output amplitude of the i-th amplitude step, including: When the step direction of the i-th amplitude step is downward and the output amplitude of the i-th amplitude step is less than or equal to the negative of the flip threshold, the step direction of the i-th amplitude step is updated to upward. When the step direction of the i-th amplitude step is upward and the output amplitude of the i-th amplitude step is greater than or equal to the flip threshold, the step direction of the i-th amplitude step is updated to downward. When the step direction of the i-th amplitude step is a downward direction, and the output amplitude of the i-th amplitude step is greater than the negative of the amplitude threshold, the output amplitude of the i-th amplitude step is reduced by 1; When the step direction of the i-th amplitude step is upward and the output amplitude of the i-th amplitude step is greater than or equal to the flip threshold, the output amplitude of the i-th amplitude step is incremented by 1.

4. The method according to claim 1 or 2, characterized in that, The process of mapping the first phase signal based on a preset segmented mapping rule to obtain the initial amplitude and initial direction includes: When the first phase signal is less than or equal to the peak amplitude of the triangular wave, the initial amplitude is equal to the negative of the amplitude of the first phase signal, and the initial direction is the upward direction; When the first phase signal is greater than the peak amplitude of the triangular wave, the initial amplitude is equal to the difference between the amplitude of the first phase signal and twice the peak amplitude of the triangular wave, and the initial direction is the downward direction.

5. The method according to claim 1 or 2, characterized in that, The initialization operation performed in response to detecting the rising edge of the enable signal includes: In response to the detection of the rising edge of the enable signal, the enable signal is delayed by one clock cycle to obtain the first pulse signal; In response to the detection of the first pulse signal, the initialization operation is performed, wherein the first phase signal is a signal obtained based on the phase bias signal in response to the detection of the first pulse signal and is synchronized with the system clock.

6. The method according to claim 1 or 2, characterized in that, The total number of amplitude steps is Q times the peak amplitude of the triangular wave, where Q is a positive integer greater than 1; The total number of clock beats is equal to the result obtained by rounding down the quotient of the triangular wave output frequency and the frequency of the system clock.

7. The method according to claim 1 or 2, characterized in that, When the i-th amplitude step is a short step, the comparison threshold is equal to the difference between the short step duration and 1; When the i-th amplitude step is a long step, the comparison threshold is equal to the short step duration.

8. A triangular wave signal generating device, characterized in that, The triangular wave signal generating device is used to perform the method according to any one of claims 1 to 7.

9. A chip, characterized in that, Includes the triangular wave signal generating device as described in claim 8.

10. An electronic device, characterized in that, It includes the triangular wave signal generating device of claim 8 or the chip of claim 9.

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